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| 32-Bit TX System RISC TX19 Family TMP1941AF MIPS16, application Specific Extensions and R3000A are a trademark of MIPS Technologies, Inc. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. The products described in this document contain components made in the United States and subject to export control of the U.S. authorities. Diversion contrary to the U.S. law is prohibited. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The Toshiba products listed in this document are intended for usage in general electronics applications ( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. The products described in this document may include products subject to the foreign exchange and foreign trade laws. (c) 2003 TOSHIBA CORPORATION All Rights Reserved Preface Toshiba offers a broad range of microcontrollers targeted for both commercial and industrial applications. The TX System RISC TX19 Family manual contains the detailed specifications of the TX1941, including the architecture, programming, capabilities, operation, electrical characteristics, packaging and so forth. The TX1941 is a high-performance RISC processor based on the R3000A architecture and the MIPS16 Application Specific Extension pioneered by MIPS Technologies, Inc. Recently, with the ever-growing market for lightweight portable devices, manufacturers of electronic systems have been seeking cost-effective, single-chip solutions to processor-based applications. Toshiba has designed the TX1941 to help customers achieve the best cost performance for their products. TMP1941AF Contents Handling Precaution TMP1941AF 1. 2. 2.1 2.2 3. 3.1 4. 5. Features ................................................................................................................................................................... 1 Signal Descriptions ................................................................................................................................................. 5 Pin Assignment .................................................................................................................................................. 5 Pin Usage Information ....................................................................................................................................... 6 Core Processor ........................................................................................................................................................ 9 Reset Operation ................................................................................................................................................. 9 Memory Map......................................................................................................................................................... 10 Clock/Standby Control .......................................................................................................................................... 11 5.1 Clock Generation............................................................................................................................................. 12 5.1.1 Main System Clock ................................................................................................................................. 12 5.1.2 Subsystem Clock..................................................................................................................................... 12 5.1.3 Clock Source Block Diagrams ................................................................................................................ 13 5.2 Clock Generator (CG) Registers...................................................................................................................... 14 5.2.1 System Clock Control Registers.............................................................................................................. 14 5.2.2 ADC Conversion Clock .......................................................................................................................... 16 5.2.3 STOP/SLEEP Wake-up Interrupt Control Registers (INTCG Registers) ............................................... 16 5.2.4 Interrupt Request Clear Register ............................................................................................................. 18 5.3 System Clock Control Section ......................................................................................................................... 19 5.3.1 Oscillation Stabilization Time When Switching Between NORMAL and SLOW Modes...................... 19 5.3.2 System Clock Output .............................................................................................................................. 20 5.3.3 Reducing the Oscillator Clock Drive Capability..................................................................................... 20 5.4 Prescalar Clock Control Section ...................................................................................................................... 21 5.5 Clock Frequency Multiplication Section (PLL)............................................................................................... 21 5.6 Standby Control Section .................................................................................................................................. 22 5.6.1 TMP1941AF Operation in NORMAL and Standby Modes.................................................................... 23 5.6.2 CG Operation in NORMAL and Standby Modes ................................................................................... 23 5.6.3 Processor and Peripheral Block Operation in Standby Modes................................................................ 23 5.6.4 Wake-up Signaling.................................................................................................................................. 24 5.6.5 STOP Mode ............................................................................................................................................ 26 5.6.6 Returning from a Standby Mode............................................................................................................. 26 Interrupts ............................................................................................................................................................... 29 6.1 Overview ......................................................................................................................................................... 29 6.2 Interrupt Sources.............................................................................................................................................. 31 6.3 Interrupt Detection........................................................................................................................................... 33 6.4 Resolving Interrupt Priority ............................................................................................................................. 33 6.5 Register Description ........................................................................................................................................ 34 6.5.1 Interrupt Vector Register (IVR) .............................................................................................................. 34 6.5.2 Interrupt Mode Control Registers (IMCF-IMC0) .................................................................................. 35 6.5.3 Interrupt Request Clear Register (INTCLR) ........................................................................................... 35 7.1 7.2 7.3 7.4 7.5 7.6 I/O Ports ................................................................................................................................................................ 36 Address/Data Bus Bits 0-7 (AD0-AD7)......................................................................................................... 40 Address/Data Bus Bits 8-15 (AD8-AD15) / Address Bus Bits 8-15 (A8-A15) ............................................ 40 Address Bus Bits 16-23 (A16-A23) ............................................................................................................... 41 RD , WR , HWR , WAIT , BUSRQ , BUSAK , R / W ..................................................................................... 41 Port 37 ............................................................................................................................................................. 43 Port 4 (P40-P44) ............................................................................................................................................. 44 6. 7. i TMP1941AF 7.7 7.8 7.9 7.10 7.11 7.12 8. Port 5 (P50-P57) ............................................................................................................................................. 47 Port 7 (P70-P77) ............................................................................................................................................. 48 Port 8 (P80-P87) ............................................................................................................................................. 52 Port 9 (P90-P97) ............................................................................................................................................. 55 Port A (PA0-PA7) ........................................................................................................................................... 60 Open-Drain Output Control ............................................................................................................................. 65 External Bus Interface........................................................................................................................................... 66 8.1 Address and Data Buses .................................................................................................................................. 67 8.1.1 Supported Configurations ....................................................................................................................... 67 8.1.2 States of the Address Bus During On-Chip Address Accesses ............................................................... 67 8.2 External Bus Operation.................................................................................................................................... 68 8.2.1 Basic Bus Operation ............................................................................................................................... 68 8.2.2 Wait Timing............................................................................................................................................ 69 8.2.3 ALE Pulse Width .................................................................................................................................... 71 8.2.4 Read Recovery Time............................................................................................................................... 72 8.3 Bus Arbitration ................................................................................................................................................ 73 8.3.1 Bus Access Control................................................................................................................................. 73 8.3.2 Bus Arbitration Flow .............................................................................................................................. 73 8.3.3 Relinquishing the bus.............................................................................................................................. 74 Chip Select/Wait Controller .................................................................................................................................. 75 9.1 Programming Chip Select Ranges ................................................................................................................... 75 9.1.1 Base/Mask Address Registers (BMA0-BMA3) ..................................................................................... 75 9.1.2 Base Address and Address Mask Value Calculations ............................................................................. 78 9.2 Chip Select/Wait Control Registers ................................................................................................................. 81 9.3 Application Example ....................................................................................................................................... 83 9. 10. DMA Controller (DMAC)..................................................................................................................................... 84 10.1 Features............................................................................................................................................................ 84 10.2 Implementation ................................................................................................................................................ 85 10.2.1 On-Chip DMAC Interface....................................................................................................................... 85 10.2.2 DMAC Block.......................................................................................................................................... 86 10.2.3 Bus Snooping.......................................................................................................................................... 86 10.3 Register Description ........................................................................................................................................ 87 10.3.1 DMA Control Register (DCR) ................................................................................................................ 88 10.3.2 Channel Control Registers (CCRn)......................................................................................................... 89 10.3.3 Channel Status Registers (CSRn)............................................................................................................ 91 10.3.4 Source Address Registers (SARn) .......................................................................................................... 92 10.3.5 Destination Address Registers (DARn) .................................................................................................. 93 10.3.6 Byte Count Registers (BCRn) ................................................................................................................. 94 10.3.7 DMA Transfer Control Registers (DTCRn)............................................................................................ 95 10.3.8 Data Holding Register (DHR)................................................................................................................. 96 10.4 Operation ......................................................................................................................................................... 97 10.4.1 Overview................................................................................................................................................. 97 10.4.2 Transfer Request Generation ................................................................................................................ 100 10.4.3 DMA Address Modes ........................................................................................................................... 101 10.4.4 DMA Channel Operation ...................................................................................................................... 102 10.4.5 DMA Channel Priority.......................................................................................................................... 104 10.4.6 Interrupts............................................................................................................................................... 104 10.4.7 Data Packing and Unpacking ................................................................................................................ 105 10.5 DMA Transfer Timing................................................................................................................................... 106 10.5.1 Dual-Address Mode .............................................................................................................................. 106 10.6 Programming Example .................................................................................................................................. 108 11. 8-Bit Timers (TMRAs)........................................................................................................................................ 109 11.1 Block Diagrams ............................................................................................................................................. 110 11.2 Timer Components ........................................................................................................................................ 112 ii TMP1941AF 11.2.1 Prescaler................................................................................................................................................ 112 11.2.2 Up-Counters (UC0 and UC1) ............................................................................................................... 113 11.2.3 Timer Registers (TA0REG and TA1REG) ........................................................................................... 113 11.2.4 Comparators (CP0 and CP1)................................................................................................................. 114 11.2.5 Timer Flip-Flop (TA1FF) ..................................................................................................................... 114 11.3 Register Description ...................................................................................................................................... 115 11.4 Operating Modes ........................................................................................................................................... 120 11.4.1 8-Bit Interval Timer Mode.................................................................................................................... 120 11.4.2 16-Bit Interval Timer Mode.................................................................................................................. 122 11.4.3 8-Bit Programmable Pulse Generation (PPG) Mode ............................................................................ 123 11.4.4 8-Bit PWM Generation Mode............................................................................................................... 125 11.4.5 Operating Mode Summary.................................................................................................................... 128 12. 16-Bit Timer/Event Counters (TMRBs).............................................................................................................. 129 12.1 Block Diagrams ............................................................................................................................................. 130 12.2 Timer Components ........................................................................................................................................ 134 12.2.1 Prescaler................................................................................................................................................ 134 12.2.2 Up-Counter (UC0) ................................................................................................................................ 135 12.2.3 Timer Registers (TB0RG0H/L and TB0RG1H/L)................................................................................ 135 12.2.4 Capture Registers (TB0CP0H/L and TB0CP1H/L) .............................................................................. 136 12.2.5 Capture Control Logic .......................................................................................................................... 137 12.2.6 Comparators (CP0 and CP1)................................................................................................................. 138 12.2.7 Timer Flip-Flop (TB0FF0).................................................................................................................... 138 12.3 Register Description ...................................................................................................................................... 139 12.4 Operating Modes ........................................................................................................................................... 149 12.4.1 16-Bit Interval Timer Mode .................................................................................................................. 149 12.4.2 16-Bit Event Counter Mode.................................................................................................................. 149 12.4.3 16-Bit Programmable Pulse Generation (PPG) Mode .......................................................................... 150 12.4.4 Timing and Measurement Functions Using the Capture Capability...................................................... 152 13. Serial I/O (SIO) ................................................................................................................................................... 157 13.1 Block Diagrams ............................................................................................................................................. 159 13.2 SIO Components............................................................................................................................................ 163 13.2.1 Prescaler................................................................................................................................................ 163 13.2.2 Baud Rate Generator............................................................................................................................. 164 13.2.3 Serial Clock Generator.......................................................................................................................... 167 13.2.4 Receive Counter.................................................................................................................................... 167 13.2.5 Receive Controller ................................................................................................................................ 167 13.2.6 Receive Buffer ...................................................................................................................................... 167 13.2.7 Transmit Counter .................................................................................................................................. 168 13.2.8 Transmit Controller............................................................................................................................... 168 13.2.9 Transmit Buffer..................................................................................................................................... 170 13.2.10 Parity Controller ................................................................................................................................... 170 13.2.11 Error Flags (UART mode only) ............................................................................................................ 170 13.2.12 Signal Generation Timing ..................................................................................................................... 171 13.3 Register Description ...................................................................................................................................... 172 13.4 Operating Modes ........................................................................................................................................... 186 13.4.1 Mode 0 (I/O Interface Mode)................................................................................................................ 186 13.4.2 Mode 1 (7-Bit UART Mode) ................................................................................................................ 189 13.4.3 Mode 2 (8-Bit UART Mode) ................................................................................................................ 190 13.4.4 Mode 3 (9-Bit UART Mode) ................................................................................................................ 190 14. Serial Bus Interface (SBI) ................................................................................................................................... 193 14.1 Block Diagram............................................................................................................................................... 193 14.2 Registers ........................................................................................................................................................ 194 14.3 I2C Bus Mode Data Formats.......................................................................................................................... 194 14.4 Description of the Registers Used in I2C Bus Mode...................................................................................... 195 14.5 I2C Bus Mode Configuration ......................................................................................................................... 199 iii TMP1941AF 14.5.1 Acknowledgment Mode ........................................................................................................................ 199 14.5.2 Number of Bits Per Transfer................................................................................................................. 199 14.5.3 Serial Clock........................................................................................................................................... 199 14.5.4 Slave Addressing and Address Recognition Mode ............................................................................... 200 14.5.5 Configuring the SBI as a Master or a Slave .......................................................................................... 200 14.5.6 Configuring the SBI as a Transmitter or a Receiver ............................................................................. 201 14.5.7 Generating START and STOP Conditions ........................................................................................... 201 14.5.8 Asserting and Deasserting Interrupt Requests....................................................................................... 202 14.5.9 SBI Operating Modes ........................................................................................................................... 202 14.5.10 Lost-Arbitration Detection Monitor ...................................................................................................... 202 14.5.11 Slave Address Match Monitor .............................................................................................................. 203 14.5.12 General-Call Detection Monitor ........................................................................................................... 203 14.5.13 Last Received Bit Monitor.................................................................................................................... 203 14.5.14 Software Reset ...................................................................................................................................... 204 14.5.15 Serial Bus Interface Data Buffer Register (SBI0DBR)......................................................................... 204 14.5.16 I2C Bus Address Register (I2C0AR)..................................................................................................... 204 14.5.17 Baud Rate Register 1 (SBI0DBR1) ...................................................................................................... 204 14.5.18 Baud Rate Register 0 (SBI0BR0) ......................................................................................................... 204 14.6 Programming Sequences in I2C Bus Mode.................................................................................................... 205 14.6.1 SBI Initialization................................................................................................................................... 205 14.6.2 Generating a START Condition and a Slave Address .......................................................................... 205 14.6.3 Transferring a Data Word ..................................................................................................................... 206 14.6.4 Generating a STOP Condition .............................................................................................................. 210 14.6.5 Repeated START Condition ................................................................................................................. 211 14.7 Description of Registers Used in Clock-Synchronous 8-Bit SIO Mode ........................................................ 212 14.8 Clock-Synchronous 8-Bit SIO Mode Operation ............................................................................................ 214 14.8.1 Serial Clock........................................................................................................................................... 214 14.8.2 SIO Transfer Modes.............................................................................................................................. 216 15. Analog-to-Digital Converter (ADC).................................................................................................................... 221 15.1 Register Description ...................................................................................................................................... 222 15.2 Operation ....................................................................................................................................................... 227 15.2.1 Analog Reference Voltages................................................................................................................... 227 15.2.2 Selecting an Analog Input Channel (s).................................................................................................. 227 15.2.3 Starting an A/D Conversion .................................................................................................................. 227 15.2.4 Conversion Modes and Conversion-Done Interrupts ............................................................................ 228 15.2.5 Conversion Time................................................................................................................................... 229 15.2.6 Storing and Reading the A/D Conversion Result.................................................................................. 229 15.3 Programming Examples................................................................................................................................. 231 16. Watchdog Timer (WDT) ..................................................................................................................................... 232 16.1 Implementation .............................................................................................................................................. 232 16.2 Register Description ...................................................................................................................................... 234 16.2.1 Watchdog Timer Mode Register (WDMOD) ....................................................................................... 234 16.2.2 Watchdog Timer Control Register (WDCR) ........................................................................................ 234 16.3 Operation ....................................................................................................................................................... 236 17. Real-Time Clock (RTC) ...................................................................................................................................... 237 17.1 Implemention................................................................................................................................................. 237 18. Electrical Characteristics..................................................................................................................................... 239 18.1 Maximum Ratings.......................................................................................................................................... 239 18.2 DC Electrical Characteristics (1/2) ................................................................................................................ 240 18.3 DC Electrical Characteristics (2/2) ................................................................................................................ 241 18.4 AC Electrical Characteristics......................................................................................................................... 242 18.5 ADC Electrical Characteristics ...................................................................................................................... 248 18.6 SIO Timing .................................................................................................................................................... 249 18.6.1 I/O Interface Mode................................................................................................................................ 249 iv TMP1941AF 18.7 SBI Timing .................................................................................................................................................... 250 18.7.1 I2C Mode............................................................................................................................................... 250 18.7.2 Clock-Synchronous 8-Bit SIO Mode .................................................................................................... 251 18.8 Event Counters (TA0IN, TA2IN, TB0IN0, TB0IN1, TB2IN0)..................................................................... 252 18.9 Timer Capture (TB0IN0, TB0IN1, TB1IN0, TB1IN1, TB2IN0, TB2IN1) .................................................. 252 18.10 General Interrupts .......................................................................................................................................... 252 18.11 NMI and STOP/SLEEP Wake-up Interrupts ................................................................................................ 252 18.12 SCOUT Pin.................................................................................................................................................... 252 18.13 Bus Request and Bus Acknowledge Signals.................................................................................................. 253 19. I/O Register Summary......................................................................................................................................... 254 19.1 I/O Ports ........................................................................................................................................................ 260 19.2 Interrupt Controller........................................................................................................................................ 262 19.3 Chip Select/Wait Controller .......................................................................................................................... 274 19.4 Clock Generator (CG) ................................................................................................................................... 278 19.5 DMA Controller (DMAC) ............................................................................................................................. 280 19.6 8-Bit Timers (TMRAs) .................................................................................................................................. 296 19.7 16-Bit Timer/Event Counters (TMRBs) ........................................................................................................ 297 19.8 Serial I/O (SIO) ............................................................................................................................................. 299 19.9 Serial Bus Interface (SBI).............................................................................................................................. 302 19.10 A/D Converter (ADC) ................................................................................................................................... 303 19.11 Watchdog Timer (WDT) ............................................................................................................................... 304 19.12 Real-Time Clock (RTC) ................................................................................................................................ 304 20. I/O Port Equivalent-Circuit Diagrams................................................................................................................. 305 21. Notations, Precautions and Restrictions .............................................................................................................. 308 21.1 Notations and Terms...................................................................................................................................... 308 21.2 Precautions and Restrictions.......................................................................................................................... 308 v TMP1941AF vi Handling Precautions 1 Using Toshiba Semiconductors Safely 1. Using Toshiba Semiconductors Safely TOSHIBA are continually working to improve the quality and the reliability of their products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. 1 2 Safety Precautions 2. Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions. [Explanation of labels] Indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which if not avoided, may result in minor injury or moderate injury. [Explanation of graphic symbol] Graphic symbol Meaning Indicates that caution is required (laser beam is dangerous to eyes). 2 2 Safety Precautions 2.1 General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. Do not insert devices in the wrong orientation. Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode and resulting in injury. When power to a device is on, do not touch the device's heat sink. Heat sinks become hot, so you may burn your hand. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment's electrodes or probes to the pins of the device under test before powering it on. Otherwise, you may receive an electric shock causing injury. Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it. Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock. Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes. 3 2 Safety Precautions 2.2 2.2.1 Precautions Specific to Each Product Group Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and in the worst case may cause blindness. If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate type of laser protective glasses as stipulated by IEC standard IEC825-1. Ensure that the current flowing in an LED device does not exceed the device's maximum rated current. This is particularly important for resin-packaged LED devices, as excessive current may cause the package resin to blow up, scattering resin fragments and causing injury. When testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the photocoupler. If you detect a leakage current of more than 100 A, use the testing equipment to shut off the photocoupler's supply voltage; otherwise a large short-circuit current will flow continuously, and the device may break down or burst into flames, resulting in fire or injury. When incorporating a visible semiconductor laser into a design, use the device's internal photodetector or a separate photodetector to stabilize the laser's radiant power so as to ensure that laser beams exceeding the laser's rated radiant power cannot be emitted. If this stabilizing mechanism does not work and the rated radiant power is exceeded, the device may break down or the excessively powerful laser beams may cause injury. 2.2.2 Power devices Never touch a power device while it is powered on. Also, after turning off a power device, do not touch it until it has thoroughly discharged all remaining electrical charge. Touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or serious injury. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment's electrodes or probes to the device under test before powering it on. When you have finished, discharge any electrical charge remaining in the device. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. 4 2 Safety Precautions Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or explode, resulting in fire or injury. Use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs. If the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device to catch fire or explode, resulting in fire or injury. When designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device catching fire or exploding. Flying shrapnel can cause injury. When conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the device. Otherwise you may sustain injury caused by the device catching fire or exploding. Make sure that all metal casings in your design are grounded to earth. Even in modules where a device's electrodes and metal casing are insulated, capacitance in the module may cause the electrostatic potential in the casing to rise. Dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching it. When designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the device's forward and reverse losses into account. The leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is used in an extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur. This may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user. A design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate while electricity is conducted to control circuits, so that the main circuit will become inactive. Malfunction of the device may cause serious accidents or injuries. When conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has cooled properly before handling it. Devices become hot when they are operated. Even after the power has been turned off, the device will retain residual heat which may cause a burn to anyone touching it. 2.2.3 Bipolar ICs (for use in automobiles) If your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to prevent negative current from flowing in. The load current generated by powering the device on and off may cause it to function erratically or to break down, which could in turn cause injury. Ensure that the power supply to any device which incorporates protective functions is stable. If the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly. If protective functions fail, the device may break down causing injury to the user. 5 3 General Safety Precautions and Usage Considerations 3. General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 3.1.1 From Incoming to Shipping Electrostatic discharge (ESD) When handling individual devices (which are not yet mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects which come into direct contact with devices should be made of anti-static materials and should be grounded to earth via an 0.5- to 1.0-M protective resistor. Please follow the precautions described below; this is particularly important for devices which are marked "Be careful of static.". (1) Work environment * When humidity in the working environment decreases, the human body and other insulators can easily become charged with static electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment, while also taking into account the fact that moisture-proof-packed products may absorb moisture after unpacking. * Be sure that all equipment, jigs and tools in the working area are grounded to earth. * Place a conductive mat over the floor of the work area, or take other appropriate measures, so that the floor surface is protected against static electricity and is grounded to earth. The surface resistivity should be 104 to 108 /sq and the resistance between surface and ground, 7.5 x 105 to 108 108 /sq, for a resistance between surface and ground of 7.5 x 105 to 108 ) . The purpose of this is to disperse static electricity on the surface (through resistive components) and ground it to earth. Workbench surfaces must not be constructed of low-resistance metallic materials that allow rapid static discharge when a charged device touches them directly. * Cover the workbench surface also with a conductive mat (with a surface resistivity of 104 to * Pay attention to the following points when using automatic equipment in your workplace: (a) When picking up ICs with a vacuum unit, use a conductive rubber fitting on the end of the pick-up wand to protect against electrostatic charge. (b) Minimize friction on IC package surfaces. If some rubbing is unavoidable due to the device's mechanical structure, minimize the friction plane or use material with a small friction coefficient and low electrical resistance. Also, consider the use of an ionizer. (c) In sections which come into contact with device lead terminals, use a material which dissipates static electricity. (d) Ensure that no statically charged bodies (such as work clothes or the human body) touch the devices. 6 3 General Safety Precautions and Usage Considerations (e) Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not touch devices. (g) In processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions. * Make sure that CRT displays in the working area are protected against static charge, for example by a VDT filter. As much as possible, avoid turning displays on and off. Doing so can cause electrostatic induction in devices. * Keep track of charged potential in the working area by taking periodic measurements. * Ensure that work chairs are protected by an anti-static textile cover and are grounded to the floor surface by a grounding chain. (Suggested resistance between the seat surface and grounding chain is 7.5 x 105 to 1012.) /sq; suggested resistance between surface and ground is 7.5 x 105 to 108 .) * Install anti-static mats on storage shelf surfaces. (Suggested surface resistivity is 104 to 108 * For transport and temporary storage of devices, use containers (boxes, jigs or bags) that are made of anti-static materials or materials which dissipate electrostatic charge. * Make sure that cart surfaces which come into contact with device packaging are made of materials which will conduct static electricity, and verify that they are grounded to the floor surface via a grounding chain. * In any location where the level of static electricity is to be closely controlled, the ground resistance level should be Class 3 or above. Use different ground wires for all items of equipment which may come into physical contact with devices. (2) Operating environment * Operators must wear anti-static clothing and conductive shoes (or a leg or heel strap). * Operators must wear a wrist strap grounded to earth via a resistor of about 1 M. * Soldering irons must be grounded from iron tip to earth, and must be used only at low voltages (6 V to 24 V). * If the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in particular avoid metallic tweezers. If a charged device touches a low-resistance tool, rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pat to the tip, and connect it to a dedicated ground used especially for anti-static purposes (suggested resistance value: 104 to 108 ). CRT). * Do not place devices or their containers near sources of strong electrical fields (such as above a 7 3 General Safety Precautions and Usage Considerations * When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another. * Ensure, if possible, that any articles (such as clipboards) which are brought to any location where the level of static electricity must be closely controlled are constructed of anti-static materials. * In cases where the human body comes into direct contact with a device, be sure to wear antistatic finger covers or gloves (suggested resistance value: 108 or less). * Equipment safety covers installed near devices should have resistance ratings of 109 or less. * If a wrist strap cannot be used for some reason, and there is a possibility of imparting friction to devices, use an ionizer. * The transport film used in TCP products is manufactured from materials in which static charges tend to build up. When using these products, install an ionizer to prevent the film from being charged with static electricity. Also, ensure that no static electricity will be applied to the product's copper foils by taking measures to prevent static occuring in the peripheral equipment. 3.1.2 Vibration, impact and stress Handle devices and packaging materials with care. To avoid damage to devices, do not toss or drop packages. Ensure that devices are not subjected to mechanical vibration or shock during transportation. Ceramic package devices and devices in canister-type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends. Vibration Plastic molded devices, on the other hand, have a relatively high level of resistance to vibration and mechanical shock because their bonding wires are enveloped and fixed in resin. However, when any device or package type is installed in target equipment, it is to some extent susceptible to wiring disconnections and other damage from vibration, shock and stressed solder junctions. Therefore when devices are incorporated into the design of equipment which will be subject to vibration, the structural design of the equipment must be thought out carefully. If a device is subjected to especially strong vibration, mechanical shock or stress, the package or the chip itself may crack. In products such as CCDs which incorporate window glass, this could cause surface flaws in the glass or cause the connection between the glass and the ceramic to separate. Furthermore, it is known that stress applied to a semiconductor device through the package changes the resistance characteristics of the chip because of piezoelectric effects. In analog circuit design attention must be paid to the problem of package stress as well as to the dangers of vibration and shock as described above. 8 3 General Safety Precautions and Usage Considerations 3.2 3.2.1 Storage General storage * Avoid storage locations where devices will be exposed to moisture or direct sunlight. * Follow the instructions printed on the device cartons regarding transportation and storage. * The storage area temperature should be kept within a Humidity: Temperature: temperature range of 5C to 35C, and relative humidity should be maintained at between 45% and 75%. * Do not store devices in the presence of harmful (especially corrosive) gases, or in dusty conditions. @@ * Use storage areas where there is minimal temperature fluctuation. Rapid temperature changes can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. As a result, the solderability of the leads will be degraded. * When repacking devices, use anti-static containers. * Do not allow external forces or loads to be applied to devices while they are in storage. * If devices have been stored for more than two years, their electrical characteristics should be tested and their leads should be tested for ease of soldering before they are used. 3.2.2 Moisture-proof packing Moisture-proof packing should be handled with care. The handling procedure specified for each packing type should be followed scrupulously. If the proper procedures are not followed, the quality and reliability of devices may be degraded. This section describes general precautions for handling moisture-proof packing. Since the details may differ from device to device, refer also to the relevant individual datasheets or databook. (1) General precautions Follow the instructions printed on the device cartons regarding transportation and storage. * Do not drop or toss device packing. The laminated aluminum material in it can be rendered ineffective by rough handling. * The storage area temperature should be kept within a temperature range of 5C to 30C, and relative humidity should be maintained at 90% (max). Use devices within 12 months of the date marked on the package seal. 9 3 General Safety Precautions and Usage Considerations * If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture. Please refer to the table below. After the pack has been opened, use the devices in a 5C to 30C. 60% RH environment and within the effective usage period listed on the moisture-proof package. If the effective usage period has expired, or if the packing has been stored in a high-humidity environment, bake the devices at high temperature. Packing Tray Tube Tape Moisture removal If the packing bears the "Heatproof" marking or indicates the maximum temperature which it can withstand, bake at 125C for 20 hours. (Some devices require a different procedure.) Transfer devices to trays bearing the "Heatproof" marking or indicating the temperature which they can withstand, or to aluminum tubes before baking at 125C for 20 hours. Deviced packed on tape cannot be baked and must be used within the effective usage period after unpacking, as specified on the packing. * When baking devices, protect the devices from static electricity. * Moisture indicators can detect the approximate humidity level at a standard temperature of 25C. 6-point indicators and 3-point indicators are currently in use, but eventually all indicators will be 3-point indicators. HUMIDITY INDICATOR 60% 50% DANGER IF PINK CHANGE DESICCANT 40% HUMIDITY INDICATOR 30% 40 DANGER IF PINK 20% 30 10% READ AT LAVENDER BETWEEN PINK & BLUE (a) 6-point indicator 20 READ AT LAVENDER BETWEEN PINK & BLUE (b) 3-point indicator Figure 1 Humidity indicator 10 3 General Safety Precautions and Usage Considerations 3.3 Design Care must be exercised in the design of electronic equipment to achieve the desired reliability. It is important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions, it is also important to consider the overall environment in which equipment will be used, including factors such as the ambient temperature, transient noise and voltage and current surges, as well as mounting conditions which affect device reliability. This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature) will be exceeded. A device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Although absolute maximum ratings differ from product to product, they essentially concern the voltage and current at each pin, the allowable power dissipation, and the junction and storage temperatures. If the voltage or current on any pin exceeds the absolute maximum rating, the device's internal circuitry can become degraded. In the worst case, heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down. If storage or operating temperatures exceed rated values, the package seal can deteriorate or the wires can become disconnected due to the differences between the thermal expansion coefficients of the materials from which the device is constructed. 3.3.2 Recommended operating conditions The recommended operating conditions for each device are those necessary to guarantee that the device will operate as specified in the datasheet. If greater reliability is required, derate the device's absolute maximum ratings for voltage, current, power and temperature before using it. 3.3.3 Derating When incorporating a device into your design, reduce its rated absolute maximum voltage, current, power dissipation and operating temperature in order to ensure high reliability. Since derating differs from application to application, refer to the technical datasheets available for the various devices used in your design. 3.3.4 Unused pins If unused pins are left open, some devices can exhibit input instability problems, resulting in malfunctions such as abrupt increase in current flow. Similarly, if the unused output pins on a device are connected to the power supply pin, the ground pin or to other output pins, the IC may malfunction or break down. Since the details regarding the handling of unused pins differ from device to device and from pin 11 3 General Safety Precautions and Usage Considerations to pin, please follow the instructions given in the relevant individual datasheets or databook. CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted supply current to flow. Therefore, ensure that the unused input pins of a device are connected to the power supply (Vcc) pin or ground (GND) pin of the same device. For details of what to do with the pins of heat sinks, refer to the relevant technical datasheet and databook. 3.3.5 Latch-up Latch-up is an abnormal condition inherent in CMOS devices, in which Vcc gets shorted to ground. This happens when a parasitic PN-PN junction (thyristor structure) internal to the CMOS chip is turned on, causing a large current of the order of several hundred mA or more to flow between Vcc and GND, eventually causing the device to break down. Latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the internal chip, or when the voltage on the Vcc (Vdd) pin exceeds its rated value, forcing the internal chip into a breakdown condition. Once the chip falls into the latch-up state, even though the excess voltage may have been applied only for an instant, the large current continues to flow between Vcc (Vdd) and GND (Vss). This causes the device to heat up and, in extreme cases, to emit gas fumes as well. To avoid this problem, observe the following precautions: (1) Do not allow voltage levels on the input and output pins either to rise above Vcc (Vdd) or to fall below GND (Vss). Also, follow any prescribed power-on sequence, so that power is applied gradually or in steps rather than abruptly. (2) Do not allow any abnormal noise signals to be applied to the device. (3) Set the voltage levels of unused input pins to Vcc (Vdd) or GND (Vss). (4) Do not connect output pins to one another. 3.3.6 Input/Output protection Wired-AND configurations, in which outputs are connected together, cannot be used, since this short-circuits the outputs. Outputs should, of course, never be connected to Vcc (Vdd) or GND (Vss). Furthermore, ICs with tri-state outputs can undergo performance degradation if a shorted output current is allowed to flow for an extended period of time. Therefore, when designing circuits, make sure that tri-state outputs will not be enabled simultaneously. 3.3.7 Load capacitance Some devices display increased delay times if the load capacitance is large. Also, large charging and discharging currents will flow in the device, causing noise. Furthermore, since outputs are shorted for a relatively long time, wiring can become fused. Consult the technical information for the device being used to determine the recommended load capacitance. 12 3 General Safety Precautions and Usage Considerations 3.3.8 Thermal design The failure rate of semiconductor devices is greatly increased as operating temperatures increase. As shown in Figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due to power dissipation in the device. Therefore, to achieve optimum reliability, observe the following precautions concerning thermal design: (1) Keep the ambient temperature (Ta) as low as possible. (2) If the device's dynamic power dissipation is relatively large, select the most appropriate circuit board material, and consider the use of heat sinks or of forced air cooling. Such measures will help lower the thermal resistance of the package. (3) Derate the device's absolute maximum ratings to minimize thermal stress from power dissipation. ja = jc + ca ja = (Tj-Ta) / P jc = (Tj-Tc) / P ca = (Tc-Ta) / P in which ja = thermal resistance between junction and surrounding air (C/W) jc = thermal resistance between junction and package surface, or internal thermal resistance (C/W) ca = thermal resistance between package surface and surrounding air, or external thermal resistance (C/W) Tj = junction temperature or chip temperature (C) Tc = package surface temperature or case temperature (C) Ta = ambient temperature (C) P = power dissipation (W) Ta ca Tc jc Tj Figure 2 Thermal resistance of package 3.3.9 Interfacing When connecting inputs and outputs between devices, make sure input voltage (VIL/VIH) and output voltage (VOL/VOH) levels are matched. Otherwise, the devices may malfunction. When connecting devices operating at different supply voltages, such as in a dual-power-supply system, be aware that erroneous power-on and power-off sequences can result in device breakdown. For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor. 13 3 General Safety Precautions and Usage Considerations 3.3.10 Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 to 100 .) For this reason, the impedance of power supply lines with respect to high frequencies must be kept low. This can be accomplished by using thick and short wiring for the Vcc (Vdd) and GND (Vss) lines and by installing decoupling capacitors (of approximately 0.01 F to 1 F capacitance) as high-frequency filters between Vcc (Vdd) and GND (Vss) at strategic locations on the printed circuit board. For low-frequency filtering, it is a good idea to install a 10- to 100-F capacitor on the printed circuit board (one capacitor will suffice). If the capacitance is excessively large, however, (e.g. several thousand F) latch-up can be a problem. Be sure to choose an appropriate capacitance value. An important point about wiring is that, in the case of high-speed logic ICs, noise is caused mainly by reflection and crosstalk, or by the power supply impedance. Reflections cause increased signal delay, ringing, overshoot and undershoot, thereby reducing the device's safety margins with respect to noise. To prevent reflections, reduce the wiring length by increasing the device mounting density so as to lower the inductance (L) and capacitance (C) in the wiring. Extreme care must be taken, however, when taking this corrective measure, since it tends to cause crosstalk between the wires. In practice, there must be a trade-off between these two factors. 3.3.11 External noise Printed circuit boards with long I/O or signal pattern lines are vulnerable to induced noise or surges from outside sources. Consequently, malfunctions or breakdowns can result from overcurrent or overvoltage, depending on the types of device used. To protect against noise, lower the impedance of the pattern line or insert a noise-canceling circuit. Protective measures must also be taken against surges. Input/Output Signals For details of the appropriate protective measures for a particular device, consult the relevant databook. 3.3.12 Electromagnetic interference Widespread use of electrical and electronic equipment in recent years has brought with it radio and TV reception problems due to electromagnetic interference. To use the radio spectrum effectively and to maintain radio communications quality, each country has formulated regulations limiting the amount of electromagnetic interference which can be generated by individual products. Electromagnetic interference includes conduction noise propagated through power supply and telephone lines, and noise from direct electromagnetic waves radiated by equipment. Different measurement methods and corrective measures are used to assess and counteract each specific type of noise. Difficulties in controlling electromagnetic interference derive from the fact that there is no method available which allows designers to calculate, at the design stage, the strength of the electromagnetic waves which will emanate from each component in a piece of equipment. For this reason, it is only after the prototype equipment has been completed that the designer can take measurements using a dedicated instrument to determine the strength of electromagnetic interference waves. Yet it is possible during system design to incorporate some measures for the 14 3 General Safety Precautions and Usage Considerations prevention of electromagnetic interference, which can facilitate taking corrective measures once the design has been completed. These include installing shields and noise filters, and increasing the thickness of the power supply wiring patterns on the printed circuit board. One effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed. 3.3.13 Peripheral circuits In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device's specifications. The following factors must be taken into account. (1) Inappropriate voltages or currents applied to a device's input pins may cause it to operate erratically. Some devices contain pull-up or pull-down resistors. When designing your system, remember to take the effect of this on the voltage and current levels into account. (2) The output pins on a device have a predetermined external circuit drive capability. If this drive capability is greater than that required, either incorporate a compensating circuit into your design or carefully select suitable components for use in external circuits. 3.3.14 Safety standards Each country has safety standards which must be observed. These safety standards include requirements for quality assurance systems and design of device insulation. Such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards. 3.3.15 Other precautions (1) When designing a system, be sure to incorporate fail-safe and other appropriate measures according to the intended purpose of your system. Also, be sure to debug your system under actual board-mounted conditions. (2) If a plastic-package device is placed in a strong electric field, surface leakage may occur due to the charge-up phenomenon, resulting in device malfunction. In such cases take appropriate measures to prevent this problem, for example by protecting the package surface with a conductive shield. (3) With some microcomputers and MOS memory devices, caution is required when powering on or resetting the device. To ensure that your design does not violate device specifications, consult the relevant databook for each constituent device. (4) Ensure that no conductive material or object (such as a metal pin) can drop onto and short the leads of a device mounted on a printed circuit board. 3.4 3.4.1 Inspection, Testing and Evaluation Grounding Ground all measuring instruments, jigs, tools and soldering irons to earth. Electrical leakage may cause a device to break down or may result in electric shock. 15 3 General Safety Precautions and Usage Considerations 3.4.2 Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user. When conducting any kind of evaluation, inspection or testing using AC power with a peak voltage of 42.4 V or DC power exceeding 60 V, be sure to connect the electrodes or probes of the testing equipment to the device under test before powering it on. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. (1) Apply voltage to the test jig only after inserting the device securely into it. When applying or removing power, observe the relevant precautions, if any. (2) Make sure that the voltage applied to the device is off before removing the device from the test jig. Otherwise, the device may undergo performance degradation or be destroyed. (3) Make sure that no surge voltages from the measuring equipment are applied to the device. (4) The chips housed in tape carrier packages (TCPs) are bare chips and are therefore exposed. During inspection take care not to crack the chip or cause any flaws in it. Electrical contact may also cause a chip to become faulty. Therefore make sure that nothing comes into electrical contact with the chip. 3.5 Mounting There are essentially two main types of semiconductor device package: lead insertion and surface mount. During mounting on printed circuit boards, devices can become contaminated by flux or damaged by thermal stress from the soldering process. With surface-mount devices in particular, the most significant problem is thermal stress from solder reflow, when the entire package is subjected to heat. This section describes a recommended temperature profile for each mounting method, as well as general precautions which you should take when mounting devices on printed circuit boards. Note, however, that even for devices with the same package type, the appropriate mounting method varies according to the size of the chip and the size and shape of the lead frame. Therefore, please consult the relevant technical datasheet and databook. 3.5.1 Lead forming Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. Semiconductor devices must undergo a process in which the leads are cut and formed before the devices can be mounted on a printed circuit board. If undue stress is applied to the interior of a device during this process, mechanical breakdown or performance degradation can result. This is attributable primarily to differences between the stress on the device's external leads and the stress on the internal leads. If the relative difference is great enough, the device's internal leads, adhesive properties or sealant can be damaged. Observe these precautions during the leadforming process (this does not apply to surface-mount devices): 16 3 General Safety Precautions and Usage Considerations (1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) For the minimum clearance specification between a device and a printed circuit board, refer to the relevant device's datasheet and databook. If necessary, achieve the required clearance by forming the device's leads appropriately. Do not use the spacers which are used to raise devices above the surface of the printed circuit board during soldering to achieve clearance. These spacers normally continue to expand due to heat, even after the solder has begun to solidify; this applies severe stress to the device. (4) Observe the following precautions when forming the leads of a device prior to mounting. * Use a tool or jig to secure the lead at its base (where the lead meets the device package) while bending so as to avoid mechanical stress to the device. Also avoid bending or stretching device leads repeatedly. * Be careful not to damage the lead during lead forming. * Follow any other precautions described in the individual datasheets and databooks for each device and package type. 3.5.2 Socket mounting (1) When socket mounting devices on a printed circuit board, use sockets which match the inserted device's package. (2) Use sockets whose contacts have the appropriate contact pressure. If the contact pressure is insufficient, the socket may not make a perfect contact when the device is repeatedly inserted and removed; if the pressure is excessively high, the device leads may be bent or damaged when they are inserted into or removed from the socket. (3) When soldering sockets to the printed circuit board, use sockets whose construction prevents flux from penetrating into the contacts or which allows flux to be completely cleaned off. (4) Make sure the coating agent applied to the printed circuit board for moisture-proofing purposes does not stick to the socket contacts. (5) If the device leads are severely bent by a socket as it is inserted or removed and you wish to repair the leads so as to continue using the device, make sure that this lead correction is only performed once. Do not use devices whose leads have been corrected more than once. (6) If the printed circuit board with the devices mounted on it will be subjected to vibration from external sources, use sockets which have a strong contact pressure so as to prevent the sockets and devices from vibrating relative to one another. 3.5.3 Soldering temperature profile The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used. 17 3 General Safety Precautions and Usage Considerations (1) Using a soldering iron Complete soldering within ten seconds for lead temperatures of up to 260C, or within three seconds for lead temperatures of up to 350C. (2) Using medium infrared ray reflow * Heating top and bottom with long or medium infrared rays is recommended (see Figure 3). Medium infrared ray heater (reflow) Product flow Long infrared ray heater (preheating) Figure 3 Heating top and bottom with long or medium infrared rays * Complete the infrared ray reflow process within 30 seconds at a package surface temperature of between 210C and 240C. * Refer to Figure 4 for an example of a good temperature profile for infrared or hot air reflow. (C) 240 Package surface temperature 210 160 140 60-120 seconds 30 seconds or less Time (in seconds) Figure 4 Sample temperature profile for infrared or hot air reflow (3) Using hot air reflow * Complete hot air reflow within 30 seconds at a package surface temperature of between 210C and 240C. * For an example of a recommended temperature profile, refer to Figure 4 above. (4) Using solder flow * Apply preheating for 60 to 120 seconds at a temperature of 150C. * For lead insertion-type packages, complete solder flow within 10 seconds with the temperature at the stopper (or, if there is no stopper, at a location more than 1.5 mm from the body) which does not exceed 260C. * For surface-mount packages, complete soldering within 5 seconds at a temperature of 250C or 18 3 General Safety Precautions and Usage Considerations less in order to prevent thermal stress in the device. * Figure 5 shows an example of a recommended temperature profile for surface-mount packages using solder flow. (C) 250 Package surface temperature 160 140 60-120 seconds 5 seconds or less Time (in seconds) Figure 5 Sample temperature profile for solder flow 3.5.4 Flux cleaning and ultrasonic cleaning (1) When cleaning circuit boards to remove flux, make sure that no residual reactive ions such as Na or Cl remain. Note that organic solvents react with water to generate hydrogen chloride and other corrosive gases which can degrade device performance. (2) Washing devices with water will not cause any problems. However, make sure that no reactive ions such as sodium and chlorine are left as a residue. Also, be sure to dry devices sufficiently after washing. (3) Do not rub device markings with a brush or with your hand during cleaning or while the devices are still wet from the cleaning agent. Doing so can rub off the markings. (4) The dip cleaning, shower cleaning and steam cleaning processes all involve the chemical action of a solvent. Use only recommended solvents for these cleaning methods. When immersing devices in a solvent or steam bath, make sure that the temperature of the liquid is 50C or below, and that the circuit board is removed from the bath within one minute. (5) Ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a leadless chip carrier (LCC), pin grid array (PGA) or charge-coupled device (CCD), because the bonding wires can become disconnected due to resonance during the cleaning process. Even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion between the mold resin and the frame material. The following ultrasonic cleaning conditions are recommended: Frequency: 27 kHz 29 kHz Ultrasonic output power: 300 W or less (0.25 W/cm2 or less) Cleaning time: 30 seconds or less Suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that the ultrasonic vibrator does not come into direct contact with the circuit board or the device. 19 3 General Safety Precautions and Usage Considerations 3.5.5 No cleaning If analog devices or high-speed devices are used without being cleaned, flux residues may cause minute amounts of leakage between pins. Similarly, dew condensation, which occurs in environments containing residual chlorine when power to the device is on, may cause betweenlead leakage or migration. Therefore, Toshiba recommends that these devices be cleaned. However, if the flux used contains only a small amount of halogen (0.05W% or less), the devices may be used without cleaning without any problems. 3.5.6 Mounting tape carrier packages (TCPs) (1) When tape carrier packages (TCPs) are mounted, measures must be taken to prevent electrostatic breakdown of the devices. (2) If devices are being picked up from tape, or outer lead bonding (OLB) mounting is being carried out, consult the manufacturer of the insertion machine which is being used, in order to establish the optimum mounting conditions in advance and to avoid any possible hazards. (3) The base film, which is made of polyimide, is hard and thin. Be careful not to cut or scratch your hands or any objects while handling the tape. (4) When punching tape, try not to scatter broken pieces of tape too much. (5) Treat the extra film, reels and spacers left after punching as industrial waste, taking care not to destroy or pollute the environment. (6) Chips housed in tape carrier packages (TCPs) are bare chips and therefore have their reverse side exposed. To ensure that the chip will not be cracked during mounting, ensure that no mechanical shock is applied to the reverse side of the chip. Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand. 3.5.7 Mounting chips Devices delivered in chip form tend to degrade or break under external forces much more easily than plastic-packaged devices. Therefore, caution is required when handling this type of device. (1) Mount devices in a properly prepared environment so that chip surfaces will not be exposed to polluted ambient air or other polluted substances. (2) When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). (3) Make sure that PCBs (or any other kind of circuit board) on which chips are being mounted do not have any chemical residues on them (such as the chemicals which were used for etching the PCBs). (4) When mounting chips on a board, use the method of assembly that is most suitable for maintaining the appropriate electrical, thermal and mechanical properties of the semiconductor devices used. * For details of devices in chip form, refer to the relevant device's individual datasheets. 20 3 General Safety Precautions and Usage Considerations 3.5.8 Circuit board coating When devices are to be used in equipment requiring a high degree of reliability or in extreme environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for protection. However, before doing so, you must carefully consider the possible stress and contamination effects that may result and then choose the coating resin which results in the minimum level of stress to the device. 3.5.9 Heat sinks (1) When attaching a heat sink to a device, be careful not to apply excessive force to the device in the process. (2) When attaching a device to a heat sink by fixing it at two or more locations, evenly tighten all the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely tightened). Finally, fully tighten all the screws up to the specified torque. (3) Drill holes for screws in the heat sink exactly as specified. Smooth the surface by removing burrs and protrusions or indentations which might interfere with the installation of any part of the device. (4) A coating of silicone compound can be applied between the heat sink and the device to improve heat conductivity. Be sure to apply the coating thinly and evenly; do not use too much. Also, be sure to use a non-volatile compound, as volatile compounds can crack after a time, causing the heat radiation properties of the heat sink to deteriorate. (5) If the device is housed in a plastic package, use caution when selecting the type of silicone compound to be applied between the heat sink and the device. With some types, the base oil separates and penetrates the plastic package, significantly reducing the useful life of the device. Two recommended silicone compounds in which base oil separation is not a problem are YG6260 from Toshiba Silicone. (6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you may sustain a burn. 3.5.10 Tightening torque (1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch devices. 3.5.11 Repeated device mounting and usage Do not remount or re-use devices which fall into the categories listed below; these devices may cause significant problems relating to performance and reliability. (1) Devices which have been removed from the board after soldering (2) Devices which have been inserted in the wrong orientation or which have had reverse current applied (3) Devices which have undergone lead forming more than once 21 3 General Safety Precautions and Usage Considerations 3.6 3.6.1 Protecting Devices in the Field Temperature Semiconductor devices are generally more sensitive to temperature than are other electronic components. The various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. It is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design. Note also that if a device is used above its maximum temperature rating, device deterioration is more rapid and it will reach the end of its usable life sooner than expected. 3.6.2 Humidity Resin-molded devices are sometimes improperly sealed. When these devices are used for an extended period of time in a high-humidity environment, moisture can penetrate into the device and cause chip degradation or malfunction. Furthermore, when devices are mounted on a regular printed circuit board, the impedance between wiring components can decrease under highhumidity conditions. In systems which require a high signal-source impedance, circuit board leakage or leakage between device lead pins can cause malfunctions. The application of a moisture-proof treatment to the device surface should be considered in this case. On the other hand, operation under low-humidity conditions can damage a device due to the occurrence of electrostatic discharge. Unless damp-proofing measures have been specifically taken, use devices only in environments with appropriate ambient moisture levels (i.e. within a relative humidity range of 40% to 60%). 3.6.3 Corrosive gases Corrosive gases can cause chemical reactions in devices, degrading device characteristics. For example, sulphur-bearing corrosive gases emanating from rubber placed near a device (accompanied by condensation under high-humidity conditions) can corrode a device's leads. The resulting chemical reaction between leads forms foreign particles which can cause electrical leakage. 3.6.4 Radioactive and cosmic rays Most industrial and consumer semiconductor devices are not designed with protection against radioactive and cosmic rays. Devices used in aerospace equipment or in radioactive environments must therefore be shielded. 3.6.5 Strong electrical and magnetic fields Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. Failures have been reported in LSIs mounted near malfunctioning deflection yokes in TV sets. In such cases the device's installation location must be changed or the device must be shielded against the electrical or magnetic field. Shielding against magnetism is especially necessary for devices used in an alternating magnetic field because of the electromotive forces generated in this type of environment. 22 3 General Safety Precautions and Usage Considerations 3.6.6 Interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps) Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases the device can malfunction. This is especially true for devices in which the internal chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. This problem is not limited to optical semiconductors and EPROMs. All types of device can be affected by light. 3.6.7 Dust and oil Just like corrosive gases, dust and oil can cause chemical reactions in devices, which will adversely affect a device's electrical characteristics. To avoid this problem, do not use devices in dusty or oily environments. This is especially important for optical devices because dust and oil can affect a device's optical characteristics as well as its physical integrity and the electrical performance factors mentioned above. 3.6.8 Fire Semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently. When this happens, some devices may generate poisonous gases. Devices should therefore never be used in close proximity to an open flame or a heat-generating body, or near flammable or combustible materials. 3.7 Disposal of Devices and Packing Materials When discarding unused devices and packing materials, follow all procedures specified by local regulations in order to protect the environment against contamination. 23 4 Precautions and Usage Considerations Specific to Each Product Group 4. Precautions and Usage Considerations Specific to Each Product Group This section describes matters specific to each product group which need to be taken into consideration when using devices. If the same item is described in Sections 3 and 4, the description in Section 4 takes precedence. 4.1 4.1.1 Microcontrollers Design (1) Using resonators which are not specifically recommended for use Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application. (2) Undefined functions In some microcontrollers certain instruction code values do not constitute valid processor instructions. Also, it is possible that the values of bits in registers will become undefined. Take care in your applications not to use invalid instructions or to let register bit values become undefined. (3) Scratch and puncture wounds by the point of a probe The tips of probes and adaptors used in development tools are individually designed to be compatible with particular devices. Probes for some devices have sharp points. When you handle them bare-handed, take care not to suffer a scratch or puncture wound. 24 4 Precautions and Usage Considerations Specific to Each Product Group 4.1.2 Reliability predictions for microcontroller devices For microcontroller devices, the following junction temperature range is used for reliability predictions: Tj = 0C 85C An estimation of the chip junction temperature, Tj, can be obtained from the equation: Tj = Ta + Q xja where: ambient temperature (C) The assumption is that the ambient temperature is not affected by any heat transfers from the device. Q = chip's average power dissipation (W) ja = package thermal resistance (C/W) Ta = Note 1: If you use a microcontroller device outside the 0 to 85C range for long periods of time, contact your nearest Toshiba office or authorized Toshiba dealer. Note 2: For the ja value, contact your nearest Toshiba office or authorized Toshiba dealer. 25 4 Precautions and Usage Considerations Specific to Each Product Group 26 TMP1941AF TMP1941AF 32-Bit RISC Microprocessor TX19 Family TMP1941AF 1. Features The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000ATM architecture. Additionally, the TX19 supports the MIPS16 Application-Specific Extensions (ASE) for improved code density. The TMP1941 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1941 is suitable for low-voltage, low-power applications. Features of the TMP1941 include the following: (1) TX19 core processor 1) Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed * * 2) The 16-bit ISA is object-code compatible with the code-efficient MIPS16 ASE. The 32-bit ISA is object-code compatible with the high-performance TX39 family. Combines high performance with low power consumption. -- High performance * * * * * Single clock cycle execution for most instructions 3-operand computational instructions for high instruction throughput 5-stage pipeline On-chip high-speed memory DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single clock cycle. -- Low power consumption * * 3) * * * Optimized design using a low-power cell library Programmable standby modes in which processor clocks are stopped Fast interrupt response suitable for real-time control Distinct starting locations for each interrupt service routine Automatically generated vectors for each interrupt source Automatic updates of the interrupt mask level 980508EBA1 * TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. * The products described in this document are subject to foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. TMP1941AF-1 2003-03-27 TMP1941AF (2) 10-Kbyte on-chip RAM No on-chip ROM (3) External memory expansion * * * 16-Mbyte off-chip address space for code and data External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (4) 4-channel DMA controller Interrupt- or software-triggered (5) 4-channel 8-bit timer (6) 4-channel 16-bit timer (7) 1-channel real-time counter (RTC) (8) 4-channel general-purpose serial interface Two channels support both UART and synchronous transfer modes and the other two channels are solely for UART. (9) 1-channel serial bus interface Either I2C bus mode or clock-synchronous mode can be selected. (10) 8-channel 10-bit A/D converter (with internal sample/hold) Conversion time: 8.6 s @40 MHz (11) Watchdog timer (12) 4-channel chip select/wait controller (13) Interrupt sources * * * 4 CPU interrupts: 32 internal interrupts: 11 external interrupts: software interrupt instruction 7 priority levels, with the exception of the watchdog timer interrupt 7 priority levels, with the exception of the NMI interrupt (14) 46-pin input/output ports (15) Four standby modes * * * * * IDLE (HALT, DOZE), SLEEP, STOP (16) Dual clocks Clock for low-power operation: Low-speed clock (32.768 kHz) RTC clock: Low-speed clock (32.768 kHz) (17) Clock generator On-chip PLL (x4) Clock gear: Divides the operating speed of the CPU by 1/2, 1/4 or 1/8 (18) Little-endian Higher address 31 11 7 Lower address 3 24 23 10 6 2 16 15 9 5 1 87 8 4 0 0 Word address 8 4 0 * * Byte 0 is the lowest-order byte (bits 7-0). The address of a word data item is the address of its lowest-order byte (byte 0). TMP1941AF-2 2003-03-27 TMP1941AF (19) Operating voltage range: 2.7 to 3.6 V (20) Operating frequency * * * 40 MHz (Vcc 3.0 V) 28 MHz (Vcc 2.7 V) (21) Package 100-pin QFP (14 x 14 x 1.4 (t) mm, 0.5-mm pitch) TMP1941AF-3 2003-03-27 TMP1941AF TX19 Processor Core TX19 CPU MAC 10-Kbyte RAM ( ): Initial pin function after reset DMAC (4ch) X1 G-Bus X2 XT1 (P96) CG XT2 (P97) SCOUT (P44) PLLOFF NMI INT0 (P77) INT1-4 (PA0-3) INT5-A, (P74-5, P80-1, P83-4) INTC ADTRG (P53) I/O Bus I/F 10-Bit ADC RESET (P50-P57) AN0-AN7 AVCC, AVSS VREFH, VREFL TXD0 (P90) RXD0 (P91) (P92) SCLK0/ CTS0 TXD1 (P93) RXD1 (P94) (P95) SCLK1/ CTS1 SCK (PA5) SO/SDA (PA6) SI/SCL (PA7) TA0IN (P70) TA1OUT (P71) TA2IN (P72) TA3OUT (P73) TB0IN0/INT5 (P74) TB0IN1/INT6 (P75) TB0OUT (P76) TB1IN0/INT7 (P80) TB1IN1/INT8 (P81) TB1OUT (P82) TB2IN0/INT9 (P83) TB2IN1/INTA (P84) TB2OUT (P85) TB3OUT (P86) AD0-AD7 AD8/A8-AD15/A15 SIO0 A0/A16-A7/A23 EBIF SIO1 RD WR HWR WAIT Serial Bus I/F (SBI) PORT3 BUSRQ BUSAK R/ W 8-Bit TMRA0/1 P37 (P40-P43) CS0 - CS3 AM0/1 8-Bit TMRA2/3 PORT4 16-Bit TMRB0 WDT 16-Bit TMRB1 Real-Time Counter (RTC) TXD3 (P70) 16-Bit TMRB2 SIO3 RXD3 (P71) TXD4 (P72) RXD4 (P73) 16-Bit TMRB3 SIO4 Figure 1.1 TMP1941AF Block Diagram TMP1941AF-4 2003-03-27 TMP1941AF 2. Signal Descriptions This section contains pin assignments for the TMP1941AF as well as brief descriptions of the TMP1941AF input and output signals. 2.1 Pin Assignment The following illustrates the TMP1941AF pin assignment. 88 P44/SCOUT DVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3/ADTRG P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC P70/TA0IN/TXD3 P71/TA1OUT/RXD3 P72/TA2IN/TXD4 P73/TA3OUT/RXD4 P74/TB0IN0/INT5 P75/TB0IN1/INT6 P76/TB0OUT P77/INT0 P80/TB1IN0/INT7 P81/TB1IN1/INT8 P82/TB1OUT P83/TB2IN0/INT9 P84/TB2IN1/INTA P85/TB2OUT P86/TB3OUT/INTLV P87 P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RXD1 P95/SCLK1/CTS1 AM0 CVCC X2 CVSS X1 AM1 RESET P96/XT1 P97/XT2 PLLOFF FVCC TEST FVSS PA0/INT1 89 90 91 92 93 94 95 96 97 98 99 100 87 DVCC 86 P43/CS3 85 P42/CS2 84 P41/CS1 83 P40/CS0 82 P37/DSU 81 R/W 80 BUSAK 79 BUSRQ 78 WAIT 77 HWR 76 WR 75 RD 74 A7/A23 73 A6/A22 72 A5/A21 71 A4/A20 70 A3/A19 69 A2/A18 68 A1/A17 67 A0/A16 66 AD15/A15 65 AD14/A14 64 DVCC 63 NMI 62 DVSS 61 AD13/A13 60 AD12/A12 59 AD11/A11 58 AD10/A10 57 AD9/A9 56 AD8/A8 55 AD7 54 AD6 53 AD5 52 AD4 51 AD3 50 AD2 49 AD1 48 AD0 47 DVCC 46 ALE 45 DVSS 44 PA7/SI/SCL 43 PA6/SO/SDA 42 PA5/SCK 41 PA4/SDAO 40 PA3/INT4 39 PA2/INT3 38 PA1/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Figure 2.1 100-Pin LQFP Pin Assignment TMP1941AF-5 2003-03-27 TMP1941AF 2.2 Pin Usage Information Table 2.1 lists the input and output pins of the TMP1941AF, including alternate pin names and functions for multi-function pins. Table 2.1 Pin Names and Functions Pin Name AD0-AD7 AD8-AD15 A8-A15 A0-A7 A16-A23 RD WR HWR WAIT BUSRQ BUSAK # of Pins 8 8 8 1 1 1 1 1 1 1 1 Type Input/output Input/output Output Output Output Output Output Output Input Input Output Output Input/output Input Function Address (Lower): Bits 0-7 of the address/data bus Address/Data (Upper): Bits 8-15 of the address/data bus Address: Bits 8-15 of the address bus Address: Bits 0-7 of the address bus Address: Bits 16-23 of the address bus Read Strobe: Asserted during a read operation from an external memory device Write Strobe: Asserted during a write operation on D0-D7 Higher Write Strobe: Asserted during a write operation on D8-D15 Wait: Causes the CPU to suspend external bus activity Bus Request: Asserted by an external bus master to request bus mastership Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to BUSRQ . Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle Port 37: Programmable as input or output (with internal pull-up resister) DSU Enable: If this pin is sampled low at the rising edge of RESET , the TMP1941AF enters DSU mode for software debugging using an external real-time debug system. If this pin is sampled as high at the rising edge of RESET , the TMP1941AF enters NORMAL mode. Port 40: Programmable as input or output (with internal pull-up resister) Chip Select 0: Asserted low to enable external devices at programmed addresses Port 41: Programmable as input or output (with internal pull-up resister) Chip Select 1: Asserted low to enable external devices at programmed addresses Port 42: Programmable as input or output (with internal pull-up resister) Chip Select 2: Asserted low to enable external devices at programmed addresses Port 43: Programmable as input or output (with internal pull-up resister) Chip Select 3: Asserted low to enable external devices at programmed addresses Port 44: Programmable as input or output System Clock Output: Drives out a clock signal at the same frequency as the CPU clock (high-speed or low-speed) Port 5: Input-only Analog Input: Input to the on-chip A/D Converter A/D Trigger: Starts an A/D conversion (multiplexed with P53) Port 70: Programmable as input or output 8-Bit Timer 0 Input: Input to Timer 0 Serial Transmit Data 3: Programmable as a push-pull or open-drain output Port 71: Programmable as input or output 8-Bit Timer 1 Output: Output from either Timer 0 or Timer 1 Serial Receive Data 3 Port 72: Programmable as input or output 8-Bit Timer 2 Input: Input to Timer 2 Serial Transmit Data 4: Programmable as a push-pull or open-drain output Port 73: Programmable as input or output 8-Bit Timer 3 Output: Output from either Timer 2 or Timer 3 Serial Receive Data 4 Port 74: Programmable as input or output 16-Bit Timer 0 Input 0: Count/capture trigger input to 16-bit Timer 0 Interrupt Request 5: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive R/W P37 DSU P40 CS0 1 1 1 1 1 Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input Input Input Input/output Input Output Input/output Output Input Input/output Input Output Input/output Output Input Input/output Input Input P41 CS1 P42 CS2 P43 CS3 P44 SCOUT P50-P57 AN0-AN7 ADTRG P70 TA0IN TXD3 P71 TA1OUT RXD3 P72 TA2IN TXD4 P73 TA3OUT RXD4 P74 TB0IN0 INT5 8 1 1 1 1 1 TMP1941AF-6 2003-03-27 TMP1941AF Pin Name P75 TB0IN1 INT6 P76 TB0OUT P77 INT0 P80 TB1IN0 INT7 P81 TB1IN1 INT8 P82 TB1OUT P83 TB2IN0 INT9 P84 TB2IN1 INTA P85 TB2OUT P86 TB3OUT P87 # of Pins 1 Type Input/output Input Input Input/output Output Input/output Input Input/output Input Input Input/output Input Input Input/output Output Input/output Input Input Input/output Input Input Input/output Output Input/output Output Input/output Function Port 75: Programmable as input or output 16-Bit Timer 0 Input 1: Capture trigger input to 16-bit Timer 0 Interrupt Request 6: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive Port 76: Programmable as input or output 16-Bit Timer 0 Output: Output from 16-bit Timer 0 Port 77: Programmable as input or output Interrupt Request 0: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive Port 80: Programmable as input or output 16-Bit Timer 1 Input 0: Count/capture trigger input to 16-bit Timer 1 Interrupt Request 7: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive Port 81: Programmable as input or output 16-Bit Timer 1 Input 1: Capture trigger input to 16-bit Timer 1 Interrupt Request 8: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive Port 82: Programmable as input or output 16-Bit Timer 1 Output: Output from 16-bit Timer 1 Port 83: Programmable as input or output 16-Bit Timer 2 Input 0: Count/capture trigger input to 16-bit Timer 2 Interrupt Request 9: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive Port 84: Programmable as input or output 16-Bit Timer 2 Input 1: Capture trigger input to 16-bit Timer 2 Interrupt Request A: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive Port 85: Programmable as input or output 16-Bit Timer 2 Output: Output from 16-bit Timer 2 Port 86: Programmable as input or output 16-Bit Timer 3 Output: Output from 16-bit Timer 3 Port 87: Programmable as input or output This pin is used to select the operating mode during reset. This pin should be pulled down to a logic 0 during a reset sequence. Port 90: Programmable as input or output Serial Transmit Data 0: Programmable as a push-pull or open-drain output Port 91: Programmable as input or output Serial Receive Data 0 Port 92: Programmable as input or output Serial Clock Input/Output 0 Serial Clear-to-Send 0 Port 93: Programmable as input or output Start Serial Transmit Data 1: Programmable as a push-pull or open-drain output Port 94: Programmable as input or output Serial Receive Data 1 Port 95: Programmable as input or output Serial Clock Input/Output 1 Serial Clear-to-Send 1 Port 96: Programmable as input or open-drain output Connection pin for a low-speed crystal Port 97: Programmable as input or open-drain output Connection pin for a low-speed crystal Ports A0-A3: Individually programmable as input or output Interrupt Request 1-4: Individually programmable to be high-level, low-level, risingedge or falling-edge sensitive Port A4: Programmable as input or output Port A5: Programmable as input or output Clock input/output pin when the Serial Bus Interface is in SIO mode 1 1 1 1 1 1 1 1 1 1 P90 TXD0 P91 RXD0 P92 SCLK0 CTS0 P93 TXD1 P94 RXD1 P95 SCLK1 CTS1 P96 XT1 P97 XT2 PA0-PA3 INT1-INT4 PA4 PA5 SCK 1 1 1 1 1 1 1 1 4 Input/output Output Input/output Input Input/output Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Input Input/output Output Input/output Input Input/output Input/output Input/output 1 1 TMP1941AF-7 2003-03-27 TMP1941AF Pin Name PA6 SO SDA PA7 SI SCL ALE # of Pins 1 Type Input/output Output Input/output Input/output Input Input/output Output Input Input Input Input Input Input Input Input Input/output Function Port A6: Programmable as input or output Data transmit pin when the Serial Bus Interface is in SIO mode Data transmit/receive pin when the Serial Bus Interface is in I2C mode; programmable as a push-pull or open-drain output Port A7: Programmable as input or output Data receive pin when the Serial Bus Interface is in SIO mode Clock input/output pin when the Serial Bus Interface is in I2C mode; as an output, programmable as a push-pull or open-drain output Address Latch Enable (This signal is driven out only when external memory is accessed.) Nonmaskable Interrupt Request: Causes an NMI interrupt on the falling edge AM1 should be tied to logic 0. AM0 should be tied to logic 0 when configuring a 16-bit or mixed 8-/16-bit bus. AM0 should be tied to logic 1 when configuring a 8-bit bus. Test pin: This pin should be left open or tied to ground. This pin should be tied to logic 1 when the frequency multiplied clock from the PLL is used; otherwise, it should be tied to logic 0. Reset (with internal pull-up resister): Initializes the whole TMP1941AF. Input pin for high reference voltage for the A/D Converter. This pin should be connected to the AVCC pin when the A/D Converter is not used. Input pin for low reference voltage for the A/D Converter. This pin should be connected to the AVSS pin when the A/D Converter is not used. Power supply pin for the A/D Converter. This pin should always be connected to power supply even when the A/D Converter is not used. Ground pin for the A/D Converter. This pin should always be connected to ground even when the A/D Converter is not used. Connection pins for a high-speed crystal Power supply pins Ground pins (0 V) 1 1 1 1 1 1 1 1 1 1 1 1 2 5 5 NMI AM1 AM0 TEST PLLOFF RESET VREFH VREFL AVCC AVSS X1/X2 DVCC, CVCC DVSS, CVSS Note 1: Note 2: When a DSU ICE is used, P37 and A0-A7 function as debug interface signals. P37 and P87 should be held at the prescribed logic states for one system clock cycle before and after the rising edge of RESET , with the RESET signal being stable in either logic state. The following shows the DSU interface signals. Figure 2.2 DSU Interface Signals DSU Debug Interface If the DSU pin is sampled low at the rising edge of RESET , the Port A pins are configured as interface signals for an external real-time debug system. The DSU pin has an internal pullup resistor. DRESET (PA7) I O I O O O I O DCLK (PA0) DBGE (PA5) PCST[2] (PA1) PCST[1] (PA2) PCST[0] (PA3) SDI/ DINT (PA6) SDAO/TPC (PA4) Debug Reset DRESET signal for an external real-time debug system Debug Clock DCLK signal for an external real-time debug system Debugger Enable DBGE signal for an external real-time debug system PC Trace Status [2] PCTS[2] signal for an external real-time debug system PC Trace Status [1] PCST[1] signal for an external real-time debug system PC Trace Status [0] PCTS[0] signal for an external real-time debug system Serial Data Input / Debug Interrupt SDI/ DINT signal for an external real-time debug system Serial Data and Address Output / Target PC SDAO/TPC signal for an external real-time debug system TMP1941AF-8 2003-03-27 TMP1941AF 3. Core Processor The TMP1941AF contains a high-performance 32-bit core processor called the TX19. For a detailed description of the core processor, refer to the 32-Bit TX System RISC TX19 Core Architecture manual. Be sure to read Section 21, Notations, Precautions and Restrictions, before using this product. Functions unique to the TMP1941AF, which are not covered in the architecture manual, are described below. 3.1 Reset Operation To reset the TMP1941AF, RESET must be asserted for at least 12 system clock periods after the power supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 2.4 s at 40 MHz when the on-chip PLL is utilized, and 4.8 s otherwise. After a reset, either the PLL-multiplied clock or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected clock is geared down to 1/8 for internal operation. The following occurs as a result of a reset: * * The System Control Coprocessor (CP0) registers within the TX19 core processor are initialized. For details, refer to the 32-Bit TX System RISC TX19 Core Architecture manual. The Reset exception is taken. Program control is transferred to the exception handler at a predefined address. This predefined location is called exception vector, which directly indicates the start of the actual exception handler routine. The Reset exception is always vectored to virtual address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt exception). All on-chip I/O peripheral registers are initialized. All port pins, including those multiplexed with on-chip peripheral functions, are configured as either general-purpose inputs or general-purpose outputs. * * Note: A reset operation does not affect the contents of the on-chip RAM. TMP1941AF-9 2003-03-27 TMP1941AF 4. Memory Map The mapping of virtual addresses to physical addresses is shown below. Virtual Address Physical Address 16 Mbytes Reserved On-Chip Peripherals (Reserved) Kseg2 1 Gbytes On-Chip RAM (10 KB) (Reserved) Reserved for debugging (2 MB) (Reserved) 2 Gbytes 0xFF00_0000 0xFFFF_FFFF 0xFFFF_E000 0xFFFF_BFFF 0xFFFF_9800 0xFFFF_8000 0xFF3F FFFF 0xFF20 FFFF 0xFFFF_FFFF 16 Mbytes Reserved 0xC000_0000 Kseg1 0xA000_0000 Kseg0 0x8000_0000 16 Mbytes Reserved 16 Mbytes Reserved Kuseg Inaccessible 0x4000_0000 0x2000_0000 512 Mbytes 0x0000_0000 0x0000_0000 Figure 4.1 Memory Map Note 1: The on-chip RAM is mapped to the addresses from 0xFFFF_9800 through 0xFFFF_BFFF. Note 2: The TMP1941AF has access to only 16 Mbytes of external physical address space. The 16-Mbyte physical memory can be located anywhere within the CPU's 3.5-Gbyte physical address space through use of programmable chip select signals. However, any address references to the on-chip memory, on-chip peripheral or reserved regions override external memory access. Note 3: No instruction should be placed in the last four words of the physical memory available in the user's system. TMP1941AF-10 2003-03-27 TMP1941AF 5. Clock/Standby Control The TMP1941AF has two clocking modes: Single-Clock mode which operates off of the high-speed clock supplied from the X1/X2 pins, and Dual-Clock mode which operates off of the high-speed clock supplied from the X1/X2 pins and the low-speed clock supplied from the XT1/XT2 pins. Figure 5.1 shows the transitions between clocking modes in Single-Clock mode and Dual-Clock mode. Reset Reset released IDLE Mode (CPU halted) (Selectable peripheral operation) Instruction Interrupt NORMAL Mode (fc / gear_value) Instruction Interrupt STOP Mode (Whole chip halted) (a) Single-Clock Mode Reset Reset released IDLE Mode (CPU halted) (Selectable peripheral operation) Instruction Interrupt Instruction SLEEP Mode (fs only) (Only RTC is active.) Interrupt Instruction Interrupt NORMAL Mode (fc/gear_value) Interrupt Instruction Interrupt Interrupt Instruction STOP Mode (Whole chip halted) SLOW Mode (fs) Note 1: Note 2: Note 3: Before a transition to SLOW or SLEEP mode can occur, the low-speed oscillator (fs) must be oscillating stably. After SLEEP mode is exited, the TMP1941AF returns to the mode it was in before entering SLEEP mode. After STOP mode is exited, the TMP1941AF returns to the mode specified by the System Control Register 0 (SYSCR0). See Section 5.2. (b) Dual-Clock Mode Figure 5.1 Standby Modes Flow Diagram Reset Reset released PLLOFF = 1 PLL used Reset Reset released PLLOFF = 0 PLL not used NORMAL Mode fc = fpll = fosc x 4 fsys = fc / 8 fsys = fosc / 2 fperiph = fsys A. When the PLL clock is used fosc: fs: fpll: fc: fgear: fsys: fperiph: NORMAL Mode fc = fosc / 2 fsys = fc / 8 fsys = fosc / 16 fperiph = fsys B. When the PLL is not used Clock frequency supplied via the X1 and X2 pins Clock frequency supplied via the XT1 and XT2 pins PLL multiplied clock frequency (x4) Clock frequency selected by the PLLOFF pin Clock frequency selected by the GEAR[1:0] bits in the SYSCR1 System clock frequency selected by the SYSCK bit in the SYSCR1 Clock source for the prescalers inside on-chip peripherals Figure 5.2 Default Clock Frequencies in NORMAL Mode TMP1941AF-11 2003-03-27 TMP1941AF 5.1 Clock Generation Main System Clock * * * * A crystal can be connected between X1 and X2, or X1 can be externally driven with a clock. The on-chip PLL can be enabled or disabled (bypassed) during reset by using the PLLOFF pin. When the PLL is enabled, the input clock frequency is multiplied by four. The clock gear can be programmed to divide the clock by 2, 4 or 8. (The default is 1/8 on reset.) Input clock frequency Input Frequency Range PLL ON (For both crystal and external clock) Crystal PLL OFF External clock 4-10 MHz 16-20 MHz 16-20 MHz 20-40 MHz 5.1.1 fmax 40 MHz 20 MHz 20 MHz 20 MHz1 fmin 2 MHz 1 MHz 1 MHz 1.25 MHz Note 1: The DFOSC bit in the SYSCR1 must be cleared to 0. The default is 0 on reset. 5.1.2 Subsystem Clock * * * A 32.768-kHz crystal is connected between XT1 and XT2 (or XT1 can be externally driven with a clock.) SLOW mode: The CPU operates off of the low-speed clock. SLEEP mode: Only the Real-Time Counter (RTC) is operational. TMP1941AF-12 2003-03-27 TMP1941AF 5.1.3 Clock Source Block Diagrams SYSCR0.WUEF SYSCR2.WUPT[1:0] SYSCR3.LUPTM SYSCR1.FPSEL SYSCR0. XTEN XT1 XT2 LowSpeed Oscillator SYSCR0. XEN X1 X2 HighSpeed Oscillator fosc fs Warm-up Timer Lock (PLL) Timer fc fgear fperiph (To on-chip peripherals) fs fpll = fosch x 4 MUX PLL /2 /2 PLLOFF (Default setting pin) fsys /4 /8 SYSCR1.SYSCK SYSCR1.GEAR[1:0] The default is 1/8 on reset. SYSCR1.DFOSC fsys SYSCR0. PRCK[1:0] CPU fadc ROM /2 RAM /4 ADCCK[1:0] DMAC fperiph /2 /4 INTC /2 On-chip peripherals: ADC, TMRA/B, SIO, SBI, PIO, WDT, RTC T0 fs Real-Time Counter (RTC) SYSCR3.SCOSEL On-chip peripherals: TMRA/B, SIO, SBI (prescaler input) SCOUT Note 1: When the clock gear is used to reduce the system clock frequency (fsys), the prescalars within on-chip peripherals must be programmed so that the prescaler output (Tn) satisfies the following relationship: Tn < fsys / 2 Descriptions of each peripheral on the following sections include tables showing legal programming alternatives. Note 2: When the low-speed clock (fs) is used as the system clock, all on-chip peripherals except the Watchdog Timer (WDT) and the Real-Time Counter (RTC) must be disabled. The presclar clock source (Tn) must not be changed while any of the peripherals to which it is supplied are running. Note 3: Figure 5.3 Clock Source Block Diagrams TMP1941AF-13 2003-03-27 TMP1941AF 5.2 Clock Generator (CG) Registers System Clock Control Registers 7 6 5 4 RXTEN 5.2.1 3 2 WUEF 0 Oscillator warm-up period (WUP) timer On writes: 0: Don'tcare 1: Start WUP On reads: 0: Expired 1: Not expired 1 PRCK1 0 PRCK0 SYSCR0 (0xFFFF_EE00) Name XEN XTEN RXEN Read/Write Reset Value 1 0 1 Function High-speed Low-speed High-speed oscillator oscillator oscillator after exiting STOP mode 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable RSYSCK R/W 0 0 Low-speed Clock select after oscillator after exiting exiting STOP STOP mode mode 0: Disable 1: Enable 0: High-speed 1: Low-speed 0 0 Prescaler clock select 00: fperiph/4 01: fperiph/2 10: fperiph 11: Reserved 15 SYSCR1 (0xFFFF_EE01) Name Read/Write Reset Value Function 14 13 SYSCK 0 System clock (fsys) select 0: Highspeed (fgear) 1: Lowspeed (fs) 12 FPSEL R/W 0 fperiph select 11 DFOSC 0 High-speed oscillator frequency divide factor 0: Divide-by-2 1: Divide-by-1 10 9 GEAR1 8 GEAR0 R/W 1 1 High-speed clock (fc) gear select 00: fc 01: fc/2 10: fc/4 11: fc/8 0: fgear 1: fc 23 SYSCR2 (0xFFFF_EE02) 22 21 WUPT1 20 WUPT0 19 STBY1 18 STBY0 17 16 DRVE R/W 0 1: Pins are driven in STOP mode. Name DRVSOCH DRVOSCL Read/Write Reset Value 0 0 Function High-speed Low-speed oscillator oscillator drive drive capability capability 0: High 0: High 1: Low 1: Low R/W 1 0 1 1 Oscillator warm-up time Standby mode select 00: Reserved 01: 28/input frequency 10: 214/input frequency 11: 216/input frequency 00: Reserved 01: STOP mode 10: SLEEP mode 11: IDLE mode 31 SYSCR3 (0xFFFF_EE03) Name Read/Write Reset Value Function 30 SCOSEL R/W 0 SCOUT output select 0: fs 1: fsys 29 28 ALESEL R/W 1 ALE output width select 0: fsys x 0.5 1: fsys x 1.5 27 26 25 LUPFG R 0 PLL lock 0: Locked 1: Unlocked 24 LUPTM R/W 0 PLL lock time select 0: 216/input frequency 1: 212/input frequency TMP1941AF-14 2003-03-27 TMP1941AF Note 1: The Config register in the CP0 has the Doze and Halt bits. Setting the Halt bit puts the TMP1941AF in one of the standby modes, as specified by the STBY1-STBY0 bits in the SYSCR2. Setting the Doze bit puts the TMP1941AF in IDLE mode, irrespective of the settings of the STBY1-STBY0 bits. When the PLL is not used, the LUPTM bit in the SYSCR3 must be set to 1 (212/input frequency). The WUPT1-WUPT0 bits in the SYSCR2 must not be changed during the oscillator warm-up period. The LUPTM bit in the SYSCR3 must not be changed during the PLL lock period. The following considerations relate to consecutive mode changes immediately after a warm-up event (e.g., SLEEP-NORMAL-SLEEP). Hardware warm-up (with no software intervention) (1) After having transitioned from STOP or SLEEP mode to NORMAL mode * When the PLL is used A transition to a next mode can not occur until the PLL locks (SYSCR3.LUPFG=0) and at least five program instructions are executed (including the instruction to check the LUPFG flag). * When the PLL is not used * When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to 01 (28/input frequency) A transition to a next mode can not occur until the PLL locks (SYSCR3.LUPFG=0) and at least five program instructions are executed. * When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to either 10 (214/input frequency) or 11 (216/input frequency) A transition to a next mode can not occur until at least five program instructions are executed. (2) After having transitioned from STOP or SLEEP mode to SLOW mode Once in SLOW mode, a transition to a next mode can occur immediately. Software warm-up (1) After having transitioned from SLOW mode to NORMAL mode * When the PLL is used The NORMAL mode can be entered after the oscillator warm-up period timer has expired (i.e., after the SYSCR2.WUEF bit is cleared). A transition to a next mode can not occur until the PLL locks (SYSCR3.LUPFG=0) and at least five program instructions are executed (including the instruction to check the LUPFG flag). * When the PLL is not used * When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to either 01 (28/input frequency) The NORMAL mode can be entered after the oscillator warm-up period timer has expired (i.e., after the SYSCR2.WUEF bit is cleared). A transition to a next mode can not occur until the PLL locks (SYSCR3.LUPFG=0) and at least five program instructions are executed. * When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to either 10 (214/input frequency) or 11 (216/input frequency) The NORMAL mode can be entered after the oscillator warm-up timer has expired (i.e., after the SYSCR2.WUEF bit is cleared). A transition to a next mode can not occur until at least five program instructions are executed. (2) After having transitioned from NORMAL mode to SLOW mode After the oscillator warm-up timer has expired (SYSCR2.WUEF=0), a transition to a next mode can not occur until at least five program instructions are executed. Note 2: Note 3: Note 4: TMP1941AF-15 2003-03-27 TMP1941AF 5.2.2 ADC Conversion Clock 7 ADCCLK (0xFFFF_EE04) Name Read/Write Reset Value Function 6 5 4 3 2 1 ADCCK1 R/W 0 0 ADCCK0 R/W 0 ADC conversion clock (fadc) select 00: fsys/2 01: fsys/4 10: fsys/8 11: Don't use. Note: A/D conversion is executed using the clock selected by this register. Reduced conversion accuracy occurs unless the conversion time is set to 8.6 s or more. Relationships Between fsys Frequencies and A/D Conversion Times fsys 32 MHz 20 MHz 16 MHz 10 MHz 8 MHz Conversion Clock fsys/2 Don't use. 8.6 s 10.75 s 17.2 s 21.5 s fsys/4 10.75 s 17.2 s 21.5 s 34.4 s 43.0 s fsys/8 21.5 s 34.4 s 43.0 s 68.8 s 86.0 s Note: The conversion clock must not be changed while A/D conversion is in progress. 5.2.3 STOP/SLEEP Wake-up Interrupt Control Registers (INTCG Registers) 7 6 5 4 3 2 1 0 INT0EN R/W 0 INT0 enable 0: Disable 1: Enable IMCGA0 (0xFFFF_EE10) Name Read/Write Reset Value Function EMCG01 EMCG00 R/W 1 0 Wake-up INT0 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 15 IMCGA1 (0xFFFF_EE11) Name Read/Write Reset Value Function 14 13 12 11 10 9 8 INT1EN R/W 0 INT1 enable 0: Disable 1: Enable EMCG11 EMCG10 R/W 1 0 Wake-up INT1 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 23 IMCGA2 (0xFFFF_EE12) Name Read/Write Reset Value Function 22 21 20 19 18 17 16 INT2EN R/W 0 INT2 enable 0: Disable 1: Enable EMCG21 EMCG20 R/W 1 0 Wake-up INT2 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge TMP1941AF-16 2003-03-27 TMP1941AF 31 IMCGA3 (0xFFFF_EE13) Name Read/Write Reset Value Function 30 29 28 27 26 25 24 INT3EN R/W 0 INT3 enable 0: Disable 1: Enable EMCG31 EMCG30 R/W 1 0 Wake-up INT3 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 7 IMCGB0 (0xFFFF_EE14) Name Read/Write Reset Value Function 6 5 4 3 2 1 0 INT4EN R/W 0 INT4 enable 0: Disable 1: Enable EMCG41 EMCG40 R/W 1 0 Wake-up INT4 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 15 IMCGB1 (0xFFFF_EE15) Name Read/Write Reset Value Function 14 13 12 11 10 9 8 0 Must be set to 0. 1 0 Must be set to 10. 23 IMCGB2 (0xFFFF_EE16) Name Read/Write Reset Value Function 22 21 20 19 18 17 16 0 Must be set to 0. 1 0 Must be set to 10. 31 IMCGB3 (0xFFFF_EE17) Name Read/Write Reset Value Function 30 29 28 27 26 25 24 INTRTCEN R/W 0 INTRTC enable 0:Disable 1: Enable EMCG71 EMCG70 R/W 1 0 Wake-up INTRTC sensitivity 00: Don't use. 01: Don't use. 10: Don't use. 11: Rising edge These bits must be set to 11. Note 1: The edge/level sensitivity must be defined for an interrupt pin which is enabled as wake-up signaling to exit STOP/SLEEP mode. Interrupt programming must follow these steps: 1. Configure the pin as an interrupt input, if the pin is multiplexed with a general-purpose port. 2. Set the active state for the interrupt during initialization. 3. Clear any interrupt request. 4. Enable the interrupt. Note 2: Note 3: Note 4: The above steps must be performed with the relevant interrupt pin disabled. The TMP1941AF has six interrupt sources which can be used for wake-up signaling to exit STOP/SLEEP mode: INT0 to INT4 (external interrupts) and INTRTC (internal RTC interrupt). When one of these interrupt sources is used for STOP/SLEEP wake-up signaling, its interrupt sensitivity defined in the CG block overrides the setting in the INTC block. In the INTC block, its senstivity must be set to the high level (which has no effect). Note 5: TMP1941AF-17 2003-03-27 TMP1941AF Example: Enabling the INT0 interrupt IMCGA0.EMCG[01:00] = 10 IMCGA0.INT0EN = 1 IMC0L.EIM[11:10] = 01 IMC0L.IL[12:10] = 101 CG block (Set the INT0 sensitivity to the falling edge) INTC block (Set the interrupt sensitivity to the high level, and the interrupt priority level to 5.) All interrupt sources other than those used for STOP/SLEEP wake-up signaling are controlled by the INTC block. 5.2.4 Interrupt Request Clear Register 7 6 5 4 3 2 ICRCG2 1 0 EICRCG (0xFFFF_EE20) Name Read/Write Reset Value Function ICRCG1 ICRCG0 W Clear interrupt request 000: INT0 100: INT4 001: INT1 101: Reserved 010: INT2 110: Reserved 011: INT3 111: INTRTC Note 1: Clearing the INT0-INT4 and INTRTC interrupt requests, if programmed for STOP/SLEEP wakeup signaling, requires two register settings: first, the EICRCG register in the CG block, and then the INTCLR register in the INTC block. The clearing of other interrupt sources is controlled through the INTCLR register alone. In cases where INT0-INT4 are not used for STOP/SLEEP wake-up signaling, they are controlled by the INTC block in the same way as other interrupt sources. INTRTC is controlled by both the CG and INTC blocks, regardless of whether it is used for wake-up signaling. Note 2: TMP1941AF-18 2003-03-27 TMP1941AF 5.3 System Clock Control Section A system reset initializes the SYSCR0.XEN bit to 1, the SYSCR0.XTEN bit to 0 and the SYSCR1.GEAR[1:0] bits to 00, putting the TMP1941AF in Single-Clock mode. If the on-chip PLL is enabled, the PLL reference clock is always multiplied by four. By default, the system clock frequency (fsys) is geared down to fc/8, where fc = fosc x 4 (fosc is the oscillator frequency). For example, if an 8-MHz crystal is connected between the X1 and X2 pins, the fsys clock operates at 4 MHz (8 x 4 x 1/8). The PLL output clock can be disabled by setting the PLLOFF pin low during reset. Regardless of the logic state of the PLLOFF pin, the fsys frequency is, by default, geared down to fc/8. A reset clears the SYSCR1.DFOSC bit to 0, setting fc to fosc/2. Therefore, for example, if a 20-MHz crystal is connected between the X1 and X2 pins, fsys becomes 20 x 1/2 x 1/8 = 1.25 MHz. Alternatively, the X1 pin can be driven with an external clock. Since the fsys clock must have a 50% duty cycle, it is recommended to use the default DFOSC bit value of 0 (i.e., fc = fosc x 1/2). However, the divideby-2 clock generator may be bypassed by setting the DFOSC bit after reset. This causes fc to be equal to fosc; i.e., fsys becomes double the rate available when a crystal is connected between X1 and X2. 5.3.1 Oscillation Stabilization Time When Switching Between NORMAL and SLOW Modes When a crystal is connected between the X1 and X2 pins and/or the XT1 and XT2 pins, the integrated warm-up period timer is used to assure oscillation stability. The warm-up period can be selected through the WUPT1-WUPT0 bits of the SYSCR2 to suit the crystal used. The warm-up period timer can be started by software writing a 1 to the WUEF bit in the SYSCR0. This bit is self-clearing; it can be read to ascertain that the timer has expired. Table 5.1 shows the warm-up periods required when the clocking is switched between NORMAL and SLOW modes. Note 1: No warm-up is necessary when the TMP1941AF is driven by an external oscillator clock which is already stable. Because the warm-up period timer is clocked by the oscillator clock, any frequency fluctuations will lead to small timer errors. Table 5.1 should be considered as approximate values. Ensure that the PLL lock flag (SYSCR3.LUPFG) is cleared before starting the warm-up period timer. When a low-speed crystal is connected between XT1 (Port 96) and XT2 (Port 97), the following register settings are required to reduce power consumption: When a crystal is connected between XT1 and XT2: P9CR.P96C-P97C = 11 P9.P96-P97 = 00 When XT1 is driven with an external clock: P9CR.P96C-P97C = 11 P9.P96-P97 = 10 Note 2: Note 3: Note 4: Table 5.1 Warm-up Periods Warm-up Period Select SYSCR2.WUPT[1:0] 01 (28/ oscillation frequency) 10 (214/ oscillation frequency) 11 (216/ oscillation frequency) Assumption: fosc = 10 MHz, fs = 32.768 kHz High-Speed Clock (fosc) 25.6 (s) 1.638 (ms) 6.554 (ms) Low-Speed Clock (fs) 7.8 500 (ms) (ms) 2000 (ms) TMP1941AF-19 2003-03-27 TMP1941AF Example: Switching from NORMAL mode to SLOW mode SYSCR2.WUPT[1:0] = xx SYSCR0.XTEN = 1 SYSCR0.WUEF = 1 Check SYSCR0.WUEF. SYSCR1.SYSCK = 1 SYSCR0.XEN = 0 Select warm-up period. Enable low-speed clock (fs) oscillation. Start warm-up period (WUP) timer. Wait until SYSCR0.WUEF is cleared (i.e., the WUP expires.) Switch system clock speed to low speed (fs). Disable high-speed clock (fosc) oscillation. 5.3.2 System Clock Output Either the fsys or fs clock can be driven out from the P44/SCOUT pin. The P44/SCOUT pin is configured as SCOUT (system clock output) by programming the Port 4 registers as follows: P4CR.P44C=1 and P4FC.P44F=1. The output clock is selected through the SYSCR3.SCOSEL bit. Table 5.2 shows the pin states in each clocking mode when the P44/SCOUT pin is configured as SCOUT. Table 5.2 SCOUT Output States SCOUT Select SCOSEL = 0 SCOSEL = 1 NORMAL/ SLOW The fs clock is driven out. The fsys clock is driven out. Standby Modes IDLE SLEEP STOP Held at either 1 or 0. NOTE: The phase difference between the system clock output signal (SCOUT) and the internal clock signal can not be guaranteed. 5.3.3 Reducing the Oscillator Clock Drive Capability When a crystal is connected between the X1 and X2 pins and/or between XT1 and XT2 pins, oscillator noise and power consumption can be reduced through the programming of the SYSCR2. Setting the SYSCR2.DRVOSCH bit reduces the drive capability of the high-speed oscillator. Setting the SYSCR2.DRVOSCL bit reduces the drive capability of the low-speed oscillator clock. A reset clears both the DRVOSCH and DRVOSCL bits to 0, providing a high drive capability at power-up. Both the high-speed and low-speed oscillator clocks must have a high drive capability (i.e., DRVOSCH=0, DRVOSCL=0) when clocking modes are changed. TMP1941AF-20 2003-03-27 TMP1941AF * Drive capability of the high-speed oscillator fOSC C1 X1 Pin Oscillation Enable Crystal C2 X2 Pin SYSCR2.DRVOSCH * Drive capability of the low-speed oscillator C1 XT1 Pin Oscillation Enable Crystal C2 XT2 Pin SYSCR2.DRVOSCL fS Figure 5.4 Oscillator Clock Drive Capabilities 5.4 Prescalar Clock Control Section The TMRA01, TMRA23, TMRB0 to TMRB3, SIO0 to SIO4 (there is no SIO2), and SBI have a clock prescalar. The prescalar clock source (T0) can be selected from fperiph/4, fperiph/2 and fperiph/1 through the PRCK[1:0] bits of the SYSCR0. fperiph can be selected from either fgear or fc through the FPSEL bit of the SYSCR1. The default reset values select fgear as fperiph, and fperiph/4 as T0. 5.5 Clock Frequency Multiplication Section (PLL) The on-chip PLL multiplies the frequency of the high-speed oscillator clock (fosc) by four to generate the fpll clock. At reset, the PLL is disabled. To use the PLL, the PLLOFF pin must be high when RESET is released. Note: If the PLLOFF pin is low when RESET is released, the PLL will be disabled and the oscillator clock will be driven with no frequency multiplication. Being an analog circuit, the PLL requires a certain duration of time (called lock time) to stabilize, like an oscillator. The oscillator warm-up period (WUP) timer is also used as the PLL lock timer. The LUPTM bit in the SYSCR3 must be programmed so that the following relationship is satisfied: PLL lock time Oscillator warm-up time At reset, the default lock-up time is 216 / input frequency. Setting the WUP timer control bit (SYSCR0.WUEF) starts the PLL lock timer. The SYSCR3.LUPTM bit remains set while the PLL is out of lock, and is cleared when the PLL locks. In real-time applications whose software execution time is critical, once the PLL has gone out of lock in a standby mode, software must determine before resuming operation whether the PLL has locked (after the oscillator warm-up period timer has expired) in order to assure clock stability. TMP1941AF-21 2003-03-27 TMP1941AF There is one thing to remember when changing the clock gear value. The clock gear can be changed by the programming of the GEAR[1:0] bits of the SYSCR1. The RF[1:0] bits of the CPU's Config register need not be altered. It takes a few clock cycles for a gear change to take effect. Therefore, one or more instructions following the instruction that changed the clock gear value may be executed using the old clock gear value. If subsequent instructions need be executed with a new clock gear value, a dummy instruction (one that executes a write cycle) should be inserted after the instruction that modifies the clock gear value. When the clock gear is used, the prescalars within on-chip peripherals must be programmed so that the prescaler output (Tn) satisfies the following relationship: Tn < fsys / 2 5.6 Standby Control Section The TMP1941AF provides support for several levels of power reduction. While in NORMAL mode, setting the Halt bit of the Config register within the TX19 core processor causes the TMP1941AF to enter one of the standby modes -- IDLE, SLEEP or STOP -- as specified by the SYSCR2.STBY[1:0] bits. Setting the Doze bit of the Config register causes the TMP1941AF to enter IDLE (Doze) mode, irrespective of the setting of SYSCR2.STBY[1:0]. Prior to a transition to any of the standby modes, all interrupts other than those used for wake-up signaling must be disabled through the Interrupt Controller (INTC). The characteristics of the IDLE, SLEEP and STOP modes are as follows: IDLE: The CPU stops. On-chip peripherals can be selectively enabled and disabled through use of a register bit in a given peripheral, as shown in Table 5.3. Table 5.3 IDLE Mode Register Settings Peripheral TMRA01 TMRA23 TMRB0 TMRB1 TMRB2 TMRB3 SIO0 SIO1 SIO3 SIO4 SBI ADC WDT Note 1: IDLE Mode Bit TA01RUN.I2TA01 TA23RUN.I2TA23 TB0RUN.I2TB0 TB1RUN.I2TB1 TB2RUN.I2TB2 TB3RUN.I2TB3 SC0MOD1.I2S0 SC1MOD1.I2S1 SC3MOD1.I2S3 SC4MOD1.I2S4 SBI0BR1.I2SBI0 ADMOD1.I2AD WDMOD.I2WDT In Halt mode (i.e., a standby mode entered by setting the Halt bit in the Config register), the TMP1941AF freezes the TX19 core processor, preserving the pipeline state. In Halt mode, the TMP1941AF ignores any external bus requests; so it continues to assume bus mastership. In Doze mode (i.e., a standby mode entered by setting the Doze bit in the Config register), the TMP1941AF freezes the TX19 core processor, preserving the pipeline state. In Doze mode, the TMP1941AF recognizes external bus requests. Note 2: SLEEP: Only the internal low-speed oscillator and the RTC are operational. STOP: The whole TMP1941AF stops. TMP1941AF-22 2003-03-27 TMP1941AF 5.6.1 TMP1941AF Operation in NORMAL and Standby Modes Table 5.4 TMP1941AF Operation in NORMAL and Standby Modes Operation Mode NORMAL IDLE (Halt) IDLE (Doze) SLEEP STOP Operating States The TX19 core processor and peripherals operate at frequencies specified in the CG block. The processor and DMAC operations stop; other on-chip peripherals can be selectively disabled. Processor operation stops; the DMAC is operational; other on-chip peripherals can be selectively disabled. Processor operation stops; of the on-chip peripherals, only the RTC is operational (at fs). All processor and peripheral operations stop completely. 5.6.2 CG Operation in NORMAL and Standby Modes Table 5.5 CG States in NORMAL and Standby Modes Clock Source Crystal Mode NORMAL SLOW IDLE (Halt) IDLE (Doze) SLEEP STOP Oscillator On On On On fs only Off Off Off Off Off Off Off PLL On Off On On Off Off On Off On On Off Off Clock Supply to Peripherals Yes Partially supplied (See Note.) Selectable Selectable RTC only No Yes Partially supplied (See Note.) Selectable Selectable RTC only No Clock Supply to CPU Yes Yes No No No No Yes Yes No No No No External Clock NORMAL SLOW IDLE (Halt) IDLE (Doze) SLEEP STOP Note: The INTC, External Bus Interface (EBIF), I/O ports, WDT and RTC can operate in SLOW mode. 5.6.3 Processor and Peripheral Block Operation in Standby Modes Table 5.6 Processor and Peripheral Blocks in Standby Modes Circuit Block Clock Source IDLE (Doze) Off On On On On On IDLE (Halt) Off Off On On On Off SLEEP Off Off Off Off Off Off Off Off Off Off Off On On STOP Off Off Off Off Off Off Off Off Off Off Off Off Off TX19 Core Processor DMAC INTC EBIF External Bus Mastership I/O Ports ADC SIO I2C Timer Counters WDT RTC CG fsys Selectable on a block-by-block basis fs On On On On TMP1941AF-23 2003-03-27 TMP1941AF 5.6.4 Wake-up Signaling There are two ways to exit a standby mode: an interrupt request or reset signal. Availability of wakeup signaling depends on the settings of the Interrupt Mask Level bits, CMask[15:13], of the CP0 Status register and the current standby mode (see Table 5.7). * Wake-up via Interrupt Signaling The operation upon return from a standby mode varies, depending on the interrupt priority level programmed before entering a standby mode. If the interrupt priority level is greater than the processor's interrupt mask level, execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated the standby mode (i.e., the instruction that set the Halt or Doze bit in the Config register). If the interrupt priority level is equal to or less than the processor's interrupt mask level, program execution resumes with the instruction that activated the standby mode. The interrupt is left pending. Nonmaskable interrupts are always serviced upon return from a standby mode, regardless of the current interrupt mask level. * Wake-up via Reset Signaling Reset signaling always brings the TMP1941AF out of any standby mode. A wake-up from STOP mode must allow sufficient time for the oscillator to restart and stabilize (see Table 5.1). A reset does not affect the contents of the on-chip RAM, but initializes everything else, whereas an interrupt preserves all internal states that were in effect before the standby mode was entered. TMP1941AF-24 2003-03-27 TMP1941AF Table 5.7 Wake-up Signaling Sources and Wake-up Operations Interrupt Masking Standby Mode NMI INTWDT INT0-4 Wake-up Signaling Sources INTRTC INT5-A Interrupts INTTA0-3 INTTB00-31 INTTBOF0-3 INTRX0-4 INTTX0-4 INTS2 INTAD INTDMA2 RESET Unmasked Interrupt (request_level > mask_level) IDLE SLEEP (Programmable) - - - - - - - - Masked Interrupt (request_level mask_level) IDLE SLEEP (Programmable) - - - - - - - - STOP 1 - 1 - - - - - - - - STOP 1 - 1 - - - - - - - - : : -: Execution resumes with the interrupt service routine. ( RESET initializes the whole TMP1941AF.) Execution resumes with the instruction that activated the standby mode. The interrupt is left pending. Cannot be used to exit a standby mode. The TMP1941AF exits the standby mode after the warm-up period timer expires. INTDMA is accepted only in IDLE (Doze) mode. If the interrupt request level is greater than the mask level, an interrupt signal which is programmed as levelsensitive must be held active until interrupt processing begins. Otherwise, the interrupt will not be serviced successfully. If interrupts are disabled in the CPU, all interrupts other than those used for wake-up signaling must also be disabled in the Interrupt Controller (INTC) before a standby mode is entered. Otherwise, any interrupt could take the TMP1941AF out of the standby mode. Note 1: Note 2: Note 3: Note 4: TMP1941AF-25 2003-03-27 TMP1941AF 5.6.5 STOP Mode The STOP mode stops the whole TMP1941AF, including the on-chip oscillator. Pin states in STOP mode depend on the setting of the SYSCR2.DRVE bit, as shown in Table 5.8. Upon detection of wakeup signaling, the warm-up period timer should be activated to allow sufficient time for the oscillator to restart and stabilize before exiting STOP mode. After that, the system clock output can restart. On exiting STOP mode, the TMP1941AF enters either NORMAL or SLOW mode, as programmed by the RXEN, RXTEN and RSYSCK bits of the SYSCR0. These register bits must be programmed prior to the instruction that activates a standby mode. The warm-up period is chosen through the SYSCR2.WUPT[1:0] bits. 5.6.6 Returning from a Standby Mode (1) Mode transitions from NORMAL to STOP to NORMAL fsys (High-speed clock) Mode CG (High-speed clock) Warm-up (W-up) Warm-up started When fosc = 10 MHz W-up Time Select SYSCR2.WUPT[1:0] 01 (28/fosc) 10 (214/fosc) 11 (216/fosc) W-up Time (fc) 25.6 s 1.638 ms 6.554 ms Warm-up completed NORMAL System clock stopped STOP NORMAL High-speed clock oscillator started (2) Mode transitions from NORMAL to SLEEP to NORMAL fsys (High-speed clock) Mode CG (High-speed clock) CG (Low-speed clock) Warm-up (W-up) Warm-up started When fosc = 10 MHz W-up Time Select SYSCR2.WUPT[1:0] 01 (28/fosc) 10 (214/fosc) 11 (216/fosc) W-up Time (fc) 25.6 s 1.638 ms 6.554 ms Warm-up completed Low-speed clock (fs) continues oscillation. System clock stopped NORMAL SLEEP NORMAL High-speed clock oscillator started Low-speed clock (fs) continues oscillation. TMP1941AF-26 2003-03-27 TMP1941AF (3) Mode transitions from SLOW to STOP to SLOW fsys (Low-speed clock) Mode CG (Low-speed clock) Warm-up (W-up) Warm-up started When fosc = 32.768 kHz W-up Time Select SYSCR2.WUPT[1:0] 01 (28/fosc) 10 (214/fosc) 11 (216/fosc) Warm-up completed SLOW System clock stopped STOP SLOW Low-speed clock oscillator started W-up Time (fc) 7.8 ms 500 ms 2000 ms (4) Mode transitions from SLOW to SLEEP to SLOW fsys (Low-speed clock) Mode CG (Low-speed clock) Warm-up (W-up) Warm-up started When fosc = 32.768 kHz W-up Time Select SYSCR2.WUPT[1:0] 01 (28/fosc) 10 (214/fosc) 11 (216/fosc) W-up Time (fc) 7.8 ms 500 ms 2000 ms Warm-up completed SLOW SLEEP SLOW Low-speed clock continues oscillation. Note 1: Note 2: Although the fs clock continues oscillation, a warm-up time must be specified. For the TMP1941AF with an on-chip flash, when the RESET signal is used for STOP/ SLEEP wake-up signaling, it must be held active for at least 500 s for the internal system to stabilize. TMP1941AF-27 2003-03-27 TMP1941AF Table 5.8 Pin States in STOP Mode, Depending on the Setting of the SYSCR2.DRVE Bit Pin Name AD0~AD7 AD8~AD15 A0~A7/A16A23 RD , WR WAIT , BUSRQ HWR , BUSAK , R / W P37 P40-43 P44 (SCOUT) P50-57 P70-76 P77 (INT0) Input/Output Input/Output Output Output Input Output Output mode Input mode Output mode Input mode Output mode Input pin Input mode Output mode Input mode Output mode Input mode (INT0) Input mode Output mode Input mode Output mode Input mode Output mode XT1, XT2 Input mode Output mode Input mode (INT1-INT4) Input mode Output mode Input pin Output pin Input pin Input pin Input pin Output pin PU* PU* Input Input Input Output Low Input Input Output High Input Output Input Output Input Output Input Output Input Input Output Input Output Input Output Input Output Input Input Output Input Output Low Input Input Output High Type DRVE = 0 PU* PU* DRVE = 1 Output Output Input Output P80-87 P90-95 P96 (XT1) - P97 (XT2) PA0-PA3 PA4-PA7 NMI ALE RESET AM0, AM1 X1 X2 : Input: Pins configured for input mode and input-only pins are disabled. Pins configured for output mode and output-only pins assume the high-Impedance state. The input gate is active; the input voltage must be held at either the high or low level to keep the input pin from floating. Output: Pin direction is output. PU*: Programmable pull-up. Because the input gate is always disabled, no overlap current flows while in high-impedance state. TMP1941AF-28 2003-03-27 TMP1941AF 6. 6.1 Interrupts Overview Interrupt processing is coordinated bewtween the CP0 Status register, the Interrupt Controller (INTC) and the Clock Generator (CG). The Status register contains the Interrupt Mask Level field (CMask[15:13]) and the Interrupt Enable bit (IEc). For interrupt processing, also refer to the 32-Bit TX System RISC TX19 Core Architecture manual. The TMP1941AF interrupt mechanism includes the following features: * * * * * * 4 CPU internal interrupts (software interrupts) 12 external interrupt pins ( NMI , INT0 through INTA) 32 on-chip peripheral interrupts Vector generation for each interrupt source Programmable priority for each interrupt source (7 levels) DMA trigger on interrupt TX19L Core Processor INTC CG Interrupt Priority Settings Interrupt Request 3 Interrupt Vector Generation 6 Interrupt Detection Block 6 INT0-INT4 INTRTC Interrupt Clear Register Nonmaskable Interrupt Request Priority Resolver 5 INT0-INT4 bypass the CG unless used for STOP/SLEEP wake-up signaling Interrupt Detection Block Interrupt Clear Register Internal interrupt signals (DMAC, Timers, SIO, SBI, ADC) INT5-INTA NMI, INTWDT Note 1: There are interrupt enable and polarity bits in these registers: * Interrupt Mode Control registers (IMCxx) in the INTC * IMCGxx registers in the CG Note 2: The TMP1941AF provides six interrupt sources, INT0-INT4 and INTRTC, that can be used for STOP/SLEEP wake-up signaling. External interrupts INT5-INTA cannot function as wake-up signals. Figure 6.1 General Interrupt Mechanism The Interrupt Detection block monitors interrupt events. Each interrupt source can be individually programmed for active polarity and either level or edge sensitivity. The TMP1941AF interrupts are broadly grouped as follows: * External interrupts INT0-INT4 and INTRTC * When enabled for STOP/SLEEP wake-up signaling The TMP1941AF awakens from STOP or SLEEP mode, if so programmed, when any of the external interrupts INT0-INT4 or INTRTC is asserted. The EMCGxx field in the IMCGxx register TMP1941AF-29 2003-03-27 TMP1941AF defines the interrupt polarity. The INTxEN bit in the IMCGxx register controls whether these interrupt sources are enabled as wake-up signal sources (1=enable). If enabled, the interrupt polarity (EIMxx) field in the INTC's IMCxx register has no effect, but must be set to 01, or high level. The ILxx field in the IMCxx register determines the action taken after exiting STOP/SLEEP mode; i.e., whether execution resumes with an interrupt service routine. * When disabled for STOP/SLEEP wake-up signaling If INT0-INT4 are disabled for STOP/SLEEP wake-up signaling, the INTC alone determines the polarity and enabling of these interrupt sources. INTRTC is programmed through both the CG and INTC, regardless of whether it is used for wake-up signaling. * External interrupts INT5-INTA and internal interrupts except INTRTC These interrupts are programmable through the INTC. The INTC collects interrupt events, prioritizes them and presents the highest-priority request to the TX19 core processor. Hardware interrupts are summarized below. Interrupt INT0-INT4 Programming IMCGxx reg. in CG IMCx reg. in INTC Interrupt Sensing When enabled for STOP/SLEEP wake-up signaling, the polarity field in the INTC has no effect, but must always be set to "highlevel." The actual sensitivity is programmed in the CG. When disabled for STOP/SLEEP wake-up signaling, interrupt sensitivity is programmed in the INTC. In either case, each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. In the INTC, the polarity must always be set to "high-level." The actual sensitivity must be configured as rising-edge triggered in the CG. Configurable as negative or positive polarity, and as edgetriggered or level-sensitive. Falling edge Rising edge INTRTC IMCGxx reg. in CG IMCx reg. in INTC IMCx reg. in INTC INTDMAn Other IMCx reg. in INTC IMCx reg. in INTC INT0-INTA On-Chip Peripherals Here are example register settings required to enable and disable the INT0 interrupt as a source of the STOP/SLEEP wake-up signal (negative-edge triggered). * Enabling the interrupt IMCGA0.EMCG[01:00] = 10 EICRCG.ICRCG[2:0] = 000 IMCGA0.INT0EN = 1 IMC0L.EIM[11:10] = 01 IMC0L.IL[12:10] = 101 : Configure INT0 as negative-edge triggered : Clear INT0 request : Enable INT0 for wake-up signaling : Configure INT0 as high-level sensitive INTC block TX19 core processor : Set INT0 priority level to 5 CG block INTCLR.EICLR[5:0] = 000001 : Clear INT0 request Status.IEc = 1, Status.CMask = xxx * Disabling the interrupt Status.IEc = 0 IMC0L.IL[12:10] = 000 IMCGA0.INT0EN = 0 EICRCG.ICRCG[2:0] = 000 : Disable INT0 interrupt : Disable INT0 for wake-up signaling : Clear INT0 request INTCLR.EICLR[5:0] = 000001 : Clear INT0 request TX19 core processor TMP1941AF-30 2003-03-27 TMP1941AF 6.2 Interrupt Sources The TMP1941AF provides a reset interrupt, nonmaskable interrupts, and maskable interrupts: * Reset and nonmaskable interrupts The RESET pin causes a Reset interrupt. The NMI pin functions as a nonmaskable interrupt. The on-chip Watchdog Timer (WDT) is also capable of being a source of a nonmaskable interrupt (INTWDT). Reset and nonmaskable interrupts are always vectored to virtual address 0xBFC0_0000. * Maskable interrupts The TMP1941AF supports two types of maskable interrupts: software and hardware interrupts. Maskable interrupts are vectored to virtual addresses 0xBFC0_0210 through 0xBFC0_0260, as shown below. Interrupt Source Reset Nonmaskable Maskable Swi0 Software Swi1 Swi2 Swi3 Hardware Note 1: 0xBFC0_0210 0xBFC0_0220 0xBFC0_0230 0xBFC0_0240 0xBFC0_0260 Virtual Vector Address 0xBFC0_0000 The above table shows the vector addresses when the BEV bit in the CP0 Status register is set to 1. When BEV=1, all exception vectors reside in the on-chip ROM space. Software interrupts are posted by setting one of the Sw[3:0] bits in the CP0 Cause register. Software interrupts are distinct from the "Software Set" interrupt which is one of the hardware interrupt sources. A Software Set interrupt is posted from the INTC to the TX19 core processor when the IL0[2:0] field in the INTC's IMC0 register is set to a non-zero value. Note 2: TMP1941AF-31 2003-03-27 TMP1941AF Table 6.1 Hardware Interrupt Sources Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 IVR[9:0] 000 010 020 030 040 050 060 070 080 090 0A0 0B0 0C0 0D0 0E0 0F0 100 110 120 130 140 150 160 170 180 190 1A0 1B0 1C0 1D0 1E0 1F0 200 210 220 230 240 250 260 270 280 290 2A0 2B0 2C0 2D0 2E0 2F0 300 310 320 330 340 350 Interrupt Source Software Set INT0 pin INT1 pin INT2 pin INT3 pin INT4 pin Reserved Reserved Reserved Reserved INT5 pin INT6 pin INT7 pin INT8 pin INT9 pin INTA pin Reserved Reserved Reserved Reserved INTTA0: 8-Bit Timer 0 INTTA1: 8-Bit Timer 1 INTTA2: 8-Bit Timer 2 INTTA3: 8-Bit Timer 3 Reserved Reserved Reserved Reserved INTTB00: 16-Bit Timer 0 (TB0RG0) INTTB01: 16-bit Timer 0 (TB0RG1) INTTB10: 16-bit Timer 1 (TB1RG0) INTTB11: 16-bit Timer 1 (TB1RG1) INTTB20: 16-bit Timer 2 (TB2RG0) INTTB21: 16-bit Timer 2 (TB2RG1) INTTB30: 16-bit Timer 3 (TB3RG0) INTTB31: 16-bit Timer 3 (TB3RG1) Reserved Reserved Reserved Reserved INTTBOF0: 16-Bit Timer 0 (Overflow) INTTBOF1: 16-Bit Timer 1 (Overflow) INTTBOF2: 16-Bit Timer 2 (Overflow) INTTBOF3: 16-Bit Timer 3 (Overflow) Reserved Reserved Reserved Reserved INTRX0: SIO receive (Channel 0) INTTX0: SIO transmit (Channel 0) INTRX1: SIO receive (Channel 1) INTTX1: SIO transmit (Channel 1) INTS2: Serial Bus Interface (SBI) Reserved Interrupt Control Register IMC0L IMC0H IMC1L IMC1H IMC2L IMC2H IMC3L IMC3H IMC4L IMC4H IMC5L IMC5H IMC6L IMC6H IMC7L IMC7H IMC8L IMC8H IMC9L IMC9H IMCAL IMCAH IMCBL IMCBH IMCCL IMCCH IMCDL Address 0xFFFF_E000 0xFFFF_E002 0xFFFF_E004 0xFFFF_E006 0xFFFF_E008 0xFFFF_E00A 0xFFFF_E00C 0xFFFF_E00E 0xFFFF_E010 0xFFFF_E012 0xFFFF_E014 0xFFFF_E016 0xFFFF_E018 0xFFFF_E01A 0xFFFF_E01C 0xFFFF_E01E 0xFFFF_E020 0xFFFF_E022 0xFFFF_E024 0xFFFF_E026 0xFFFF_E028 0xFFFF_E02A 0xFFFF_E02C 0xFFFF_E02E 0xFFFF_E030 0xFFFF_E032 0xFFFF_E034 TMP1941AF-32 2003-03-27 TMP1941AF Interrupt Number 54 55 56 57 58 59 60 61 62 63 IVR[9:0] 360 370 380 390 3A0 3B0 3C0 3D0 3E0 3F0 Interrupt Source INTRX3: SIO receive (Channel 3) INTTX3: SIO transmit (Channel 3) INTRX4: SIO receive (Channel 4) INTTX4: SIO transmit (Channel 4) INTRTC: RTC INTAD: A/D conversion complete INTDMA0: DMA complete (Channel 0) INTDMA1: DMA complete (Channel 1) INTDMA2: DMA complete (Channel 2) INTDMA3: DMA complete (Channel 3) Interrupt Control Register IMCDH IMCEL IMCEH IMCFL IMCFH Address 0xFFFF_E036 0xFFFF_E038 0xFFFF_E03A 0xFFFF_E03C 0xFFFF_E03E 6.3 Interrupt Detection When enabled as a STOP/SLEEP wake-up signal, the polarities of INT0-INT4 are programmed in the EMCGxx field of the IMCGxx register within the CG; in this case, the EIMxx field of the IMCx register within the INTC has no effect; it must be set to "high-level sensitive," though. When disabled as a wake-up singnal, the polarities of INT0-INT4 are programmed in the EIMxx field in the INTC's IMCx register. The polarity of INTRTC is always programmed in both the CG and the INTC. All other interrupts are always programmed in the INTC's IMCx register. Each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. When a selected transition is detected, an interrupt request is issued to the INTC (except for the NMI and INTWDT interrupts, which are directly delivered to the TX19 core processor). It is the responsibility of software (an interrupt handler routine) to determine the cause of an interrupt and to clear the interrupt condition. INTRTC and INT0-INT4 used for STOP/SLEEP wake-up signaling require software access to two registers: the EICRCG register in the CG and the INTCLR register in the INTC. Other interrupts can be cleared by writing its IVR[9:4] value to the INTCLR register located within the INTC. For an external interrupt configured as level-sensitive, software must explicitly address the device in question and clear the interrupt condition. A level-sensitive interrupt signal must be held active until the TX19 core processor reads its interrupt vector from the Interrupt Vector Register (IVR). 6.4 Resolving Interrupt Priority (1) Seven Interrupt Priority Levels The Interrupt Mode Control registers (IMCF-IMC0) contain a 3-bit interrupt priority level (ILx) field for each interrupt source, which ranges from level 0 to level 7, with level 7 being the highest priority. Level 0 indicates that the interrupt is disabled. (2) Interrupt Level Notification When an interrupt event occurs, the INTC sends its priority level to the TX19 core processor. The processor can determine the priority level of an interrupt being requested by reading the IL field in the CP0 Cause register. (3) Interrupt Vector (Interrupt Source Notification) Whenever an interrupt request is made, the INTC automatically sets its vector in the IVR. The TX19 core processor can determine the exact cause of an interrupt by reading the IVR. If multiple interrupt requests occur at the same level, the interrupt with the smallest interrupt number is delivered (see Table 6.1). When no interrupt is pending, the IVR[9:4] field in the IVR contains a value of zero. When the TX19 core processor responds to a request with an interrupt acknowledge cycle, the INTC forwards the interrupt vector for that interrupt request. At this time, the TX19 core processor saves the priority level value in the CMask field of the CP0 Status register. TMP1941AF-33 2003-03-27 TMP1941AF 6.5 Register Description Table 6.2 INTC Register Map Address 0xFFFF_E060 0xFFFF_E040 0xFFFF_E03C 0xFFFF_E038 0xFFFF_E034 0xFFFF_E030 0xFFFF_E02C 0xFFFF_E028 0xFFFF_E024 0xFFFF_E020 0xFFFF_E01C 0xFFFF_E018 0xFFFF_E014 0xFFFF_E010 0xFFFF_E00C 0xFFFF_E008 0xFFFF_E004 0xFFFF_E000 Symbol INTCLR IVR IMCF IMCE IMCD IMCC IMCB IMCA IMC9 IMC8 IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 Register Name Interrupt Request Clear Register Interrupt Vector Register Interrupt Mode Control Register F Interrupt Mode Control Register E Interrupt Mode Control Register D Interrupt Mode Control Register C Interrupt Mode Control Register B Interrupt Mode Control Register A Interrupt Mode Control Register 9 Interrupt Mode Control Register 8 Interrupt Mode Control Register 7 Interrupt Mode Control Register 6 Interrupt Mode Control Register 5 Interrupt Mode Control Register 4 Interrupt Mode Control Register 3 Interrupt Mode Control Register 2 Interrupt Mode Control Register 1 Interrupt Mode Control Register 0 Corresponding Interrupt Number All (63 - 0) All (63 - 0) 63 - 60 59 - 56 55 - 52 51 - 48 47 - 44 43 - 40 39 - 36 35 - 32 31 - 28 27 - 24 23 - 20 19 - 16 15 - 12 11 - 8 7-4 3-0 6.5.1 Interrupt Vector Register (IVR) This register indicates the vector for the interrupt source when there is an interrupt event. 7 6 5 4 R 0 0 0 0 3 2 1 0 IVR (0xFFFF_E040) Name IVRL Read/Write Reset Value 0 0 0 0 Function Interrupt vector for the source of the current interrupt 15 Name Read/Write Reset Value Function 14 13 IVRH R/W 12 11 10 9 IVRL R 8 0 0 0 0 0 0 0 0 Interrupt vector for the source of the current interrupt 23 Name Read/Write Reset Value Function Name Read/Write Reset Value Function 22 21 20 IVRM R/W 19 18 17 16 0 0 0 0 0 0 0 0 31 30 29 28 IVRM R/W 27 26 25 24 0 0 0 0 0 0 0 0 TMP1941AF-34 2003-03-27 TMP1941AF 6.5.2 Interrupt Mode Control Registers (IMCF-IMC0) These registers control the interrupt priority level, active polarity, either level or edge sensitivity, and DMA triggering. 7 IMC0L (0xFFFF_E000) Name Read/Write Reset Value Function 6 5 EIM01 4 EIM00 3 DM0 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL02 1 IL01 0 IL00 0 0 Interrupt sensitivity 00: Low level Must be set to 00. 0 0 0 When DM0 = 0 Interrupt Number 0 (Software Set) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM0 = 1 DMAC channel select 000-011: Channel number (0-3) 100-111: Don't use. 15 Name Read/Write Reset Value Function 14 13 EIM11 12 EIM10 11 DM1 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL12 9 IL11 8 IL10 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 When DM0 = 0 Interrupt Number 1 (INT0 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM0 = 1 DMAC channel select 000-011: Channel number (0-3) 100-111: Don't use. 23 IMC0H (0xFFFF_E002) Name Read/Write Reset Value Function 22 21 EIM21 20 EIM20 19 DM2 18 IL22 17 IL21 16 IL20 0 0 Same as above (INT1) R/W 0 0 0 0 Same as Interrupt Number 2 (INT1 pin) above Same as above (INT1) 31 Name Read/Write Reset Value Function 30 29 EIM31 28 EIM30 27 DM3 26 IL32 25 IL31 24 IL30 0 0 Same as above (INT2) R/W 0 0 0 0 Same as Interrupt Number 3 (INT2 pin) above Same as above (INT2) Note 1: Note 2: Note 3: Interrupt sensitivity must be programmed when interrupts are enabled. For a complete list of the Interrupt Mode Control registers, see Chapter 19. When an interrupt is used to trigger a DMAC channel, that DMAC channel must be put in Ready state after the programming of the INTC. 6.5.3 Interrupt Request Clear Register (INTCLR) Loading the EICLR[5:0] field of this register with the IVRL[9:4] value of the IVR causes the corresponding interrupt to be cleared. 7 6 5 EICLR5 4 EICLR4 3 EICLR3 2 EICLR2 1 EICLR1 0 EICLR0 INTCLR 0xFFFF_E060) Name Read/Write Reset Value Function Note1: Note2: W IVRL[9:4] value for an interrupt to be cleared An interrupt request must not be cleared before the TX19 core processor reads the IVR value. Follow the steps below to disable a particular interrupt with the Interrupt Controller (INTC). 1. Globally disable the acceptance of interrupts by the core processor by clearing the IEc bit of the Status register. 2. Disable a desired interrupt with the INTC by clearing the ILx[2:0] field of the IMCxx register. 3. Execute the SYNC instruction. 4. Enable the acceptance of interrupts by the core processor by setting the IEc bit of the Status register. Example: mtc0 r0, r31 ; _DI ( ) ; sb r0, IMC** ; IMC** = 0 ; sync ; _SYNC ( ) ; mtc0 $sp, r31 ; _EI ( ) ; TMP1941AF-35 2003-03-27 TMP1941AF 7. I/O Ports The TMP1941AF has 46 I/O port pins. All the port pins except a few share pins with alternate functions. They can be individually programmed as general-purpose I/O or dedicated I/O for the on-chip CPU or peripherals. Table 7.1 shows all the I/O port pins available on the TMP1941AF and their shared functions. (There is no Port 6.) Table 7.2 is a summary of register settings used to control the port pins. Table 7.1 Programmable I/O Ports Port Port 3 Pin Name # of Pins P37 P40 P41 P42 P43 P44 P50-P57 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0-PA3 PA4 PA5 PA6 PA7 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 Direction Input/output Input/output Input/output Input/output Input/output Input/output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Pull Resistor Pullup Pullup Pullup Pullup Pullup Direction Programmability Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Fixed Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise CS0 CS1 CS2 CS3 Alternate Functions Port 4 SCOUT AN0-AN7/ ADTRG (P53) TA0IN/TXD3 TA1OUT/RXD3 TA2IN/TXD4 TA3OUT/RXD4 TB0IN0/INT5 TB0IN1/INT6 TB0OUT INT0 TB1IN0/INT7 TB1IN1/INT8 TB1OUT TB2IN0INT9 TB2IN1/INTA TB2OUT (/ BOOT in TMP1940FDBF) TB3OUT/INTLV TXD0 RXD0 SCLK0/ CTS0 TXD1 RXD1 SCLK1/ CTS1 XT1 XT2 INT1-INT4 SCK SO/SDA SI/SCL Port 5 Port 7 Port 8 Port 9 Port A TMP1941AF-36 2003-03-27 TMP1941AF Table 7.2 I/O Port Programmability (1/2) Port Pin Name AD0-AD7 bus AD8-AD15 bus A8-A15 bus A16-A23 bus RD WR HWR (Note 1) WAIT BUSRQ BUSAK Direction / Function Input/output Input/output Output Output Output Output Output Input (with pullup disabled) Input (with pullup enabled) Input (with pullup disabled) Input (with pullup enabled) Output Output Input port (with pullup disabled) Input port (with pullup enabled) Input port (with pullup disabled) Input port (with pullup enabled) Output port CS0 output CS1 output CS2 output CS3 output SCOUT output Input port AN[0:7] inputs (Note 2) ADTRG input (Note 3) Input port Output port TA0IN input TXD3 output TA1OUT output RXD3 input TA2IN input TXD4 output TA3OUT output RXD4 input TB0IN0 input INT5 input TB0IN1 input INT6 input TB0OUT output Wake-up INT0 input (Note 4) INT0 input (no wake-up) I/O Register Settings Pn N/A N/A N/A N/A N/A N/A N/A 0 1 0 1 N/A N/A 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X PnCR N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0 0 0 0 1 1 1 1 1 1 N/A 0 1 0 1 1 0 0 1 1 0 0 0 0 0 1 0 0 PnFC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0 0 0 0 0 1 1 1 1 1 R / W (Note 1) Port 3 P37 P40-P43 (Note 1) P40 P41 P42 P43 P44 P50-P57 P53 P70-P77 P70 P71 P72 P73 Port 7 P74 Port 4 Port 5 P75 P76 P77 0 0 1 1 1 1 1 1 1 1 1 Setting unneeded 1 Setting unneeded 1 1 Setting unneeded TMP1941AF-37 2003-03-27 TMP1941AF Table 7.2 I/O Port Programmability (2/2) Port Pin Name P80-P87 Input port Output port TB1IN0 input P80 P81 INT7 input TB1IN1 input INT8 input Port 8 P82 P83 TB1OUT output TB2IN0 input INT9 input P84 TB2IN1 input INTA input P85 P86 P90-P95 P90 P91 P92 Port 9 P93 P94 P95 P96-P97 TB2OUT output TB3OUT output Input port Output port TXD0 output RXD0 input SCLK0 output CTS0 /SCLK0 input Function / Direction I/O Register Settings Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X PnCR 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 PnFC 0 0 1 Setting unneeded 1 Setting unneeded 1 1 Setting unneeded 1 Setting unneeded 1 1 0 0 1 N/A 1 1 1 N/A 1 1 N/A 0 0 Setting unneeded 1 1 0 1 0 1 TXD1 output RXD1 input SCLK1 output CTS1 /SCLK1 input Input port Output port (Note 5) XT1-XT2 (Note 6) PA0-PA7 PA0-PA3 Input port Output port Wake-up INT1-INT4 inputs (Note 4) INT1-INT4 inputs (no wake-up) Port A PA5 PA6 PA7 SCK input SCK output SDA input SDA output (Note 5)/SO output SI input/SCL input SCL output (Note 7) X: Don't care Pn: Port n Register, PnCR: Port n Control Register, PnFC: Port n Function Register TMP1941AF-38 2003-03-27 TMP1941AF Note 1: HWR , R / W and P40 to P43 have their internal pullup resistors enabled when the corresponding P4FC register bit is set and when the bus is released. When P50-P57 are configured as analog channels of the ADC, the ADCH[2:0] field in A/D Mode Control Register 1 (ADMOD1) is used to select a channel(s). See Section 15.1. When P53 is configured as ADTRG , the ADTRGE bit in the ADMOD1 register is used to enable and disable the external trigger input to the ADC. When INT0-INT4 are enabled for a wake-up from STOP mode with the SYSCR2.DRIVE bit cleared (undriven pins), the corresponding bit in the PnFC must be set. When P96-P97 are configured as output ports, they function as open-drain outputs. When P96-P97 are configured as XT1-XT2, the SYSCR0 register must be programmed to enable oscillation, etc. When PA6 and PA7 are configured as SDA and SCL outputs for the SBI, the ODEA[7:6] field in the Open-Drain Enable (ODE) register can be used to configure them as either push-pull or open-drain ouptuts. Upon reset, the default is push-pull. See Section 7.11. Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: TMP1941AF-39 2003-03-27 TMP1941AF 7.1 Address/Data Bus Bits 0-7 (AD0-AD7) AD0-AD7 function as bits 0-7 of the address/data bus. The address bits 0-7 (A0-A7) and the data bits 0- 7 (D0-D7) are multiplexed onto these pins. Address/Data Outputs Internal Data Bus AD0-AD7 Data Inputs Figure 7.1 Address/Data Bus Bits 0-7 (AD0-AD7) 7.2 Address/Data Bus Bits 8-15 (AD8-AD15) / Address Bus Bits 8-15 (A8-A15) These pins function as either AD[8:15] bits of the address/data bus or the A[8:15] bits of the address bus, depending on the logic state of the AM0 pin. When AM0 is at logic 0 (i.e., 16-bit data bus or mixed 8/16-bit data bus), these pins always function as the AD[8:15] bits of the address/data bus. When AM0 is at logic 1 (i.e., 8-bit data bus), these pins always function as the A[8:15] bits of the address bus. Address/Data Outputs Address Outputs Internal Data Bus AD8-AD15/A8-A15 Data Inputs Figure 7.2 Address/Data Bus Bits 8-15 (AD8-AD15) / Address Bus Bits 8-15 (A8-A15) TMP1941AF-40 2003-03-27 TMP1941AF 7.3 Address Bus Bits 16-23 (A16-A23) These pins always function as A[16:23] bits of the address bus. Internal Data Bus Address Outputs A16-A23 Figure 7.3 Address Bus Bits 16-23 (A16-A23) 7.4 RD , WR , HWR , WAIT , BUSRQ , BUSAK , R/ W These pins always function as bus control signals. Upon reset, the internal pullup resistors of the WAIT and BUSRQ pins are enabled; the pullup resistors can be disabled by clearing the corresponding bits in the P3 register. HWR and R/ W are held at logic 1 while BUSAK =0. Internal Data Bus RD , WR Internal Data Bus P-ch HWR , BUSAK , R/ W Figure 7.4 RD , WR , HWR , BUSAK , R/ W TMP1941AF-41 2003-03-27 TMP1941AF Internal Data Bus Output Latch P-ch (Programmable Pullup Resistor) P3 Write WAIT Input BUSRQ Input WAIT , BUSRQ Figure 7.5 WAIT / BUSRQ Pullup Control Register 7 P3 (0xFFFF_F018) Name Read/Write Reset Value Function R/W 1 1 1 1 (Pullup) 6 5 4 RQPUP R/W 3 WTPUP 1 1 (Pullup) 2 1 0 0: Pullup disabled 1: Pullup enabled Note: The Pullup Control and P3 registers are physically the same register. Bit 7 of this register controls the internal pullup register of Port 37. Figure 7.6 WAIT / BUSRQ Pullup Control Register TMP1941AF-42 2003-03-27 TMP1941AF 7.5 Port 37 Port 37 functions as a general-purpose I/O pin. Port 37 can be configured as an input or an output by programming the P3CR register. Upon reset, the Output Latch P37 is set to 1 and the P37C bit in the P3CR register is cleared, configuring Port37 for input mode with pullup. Reset Direction Control (bitwise) P3CR Write Internal Data Bus P-ch Programmable Pullup Resistor S Output Latch Output Buffer P3 Write P37 P3 Read Figure 7.7 Port 37 Port 3 Register 7 P3 (0xFFFF_F018) Name Read/Write Reset Value Functoin P37 R/W 1 0: Pullup disabled 1: Pullup enabled 6 5 4 R/W 1 3 R/W 1 2 1 0 Note: The P3 and WAIT / BUSRQ Pullup Control registers are physically the same register. Bits 3 and 4 control the internal pullup resistors of WAIT and BUSRQ . Port 3 Control Register 7 P3CR (0xFFFF_F01A) Name Read/Write Reset Value Function 0: IN 1: OUT 6 5 W 4 3 2 1 0 P37 0 Must be written as 1. Must be written as 1. Must be written as 0. Must be written as 0. Must be written as 1. Figure 7.8 Port 37 Registers TMP1941AF-43 2003-03-27 TMP1941AF 7.6 Port 4 (P40-P44) P40-P43 can be individually programmed to function as either discrete general-purpose I/O pins or programmable chip select ( CS0 - CS3 ) pins. P44 can be programmed to function as either a general-purpose I/O pin or a system clock output (SCOUT) pin. The P4CR and P4FC registers select the direction and function of the Port 4 pins. Upon reset, the P4CR and P4FC register bits are cleared, configuring all the Port 4 pins as input port pins; P40-P43 have an internal pullup resistor. Upon reset, the Output Latch (P4) is set to all 1s. Reset Direction Control (bitwise) P4CR Write Function Control (bitwise) Internal Data Bus P4FC Write P-ch Programmable Pullup Resistor S Output Latch A B P4 Write S Output Buffer P40 ( CS0 ) P41 ( CS1 ) P42 ( CS2 ) P43 ( CS3 ) Selector P4 Read CS0 , CS1 , CS2 , CS3 Figure 7.9 Port 4 (P40-P43) TMP1941AF-44 2003-03-27 TMP1941AF Reset Direction Control (bitwise) P4CR Write Function Control (bitwise) Internal Data Bus P4FC Write S Output Latch A S P44 (SCOUT) Selector Y B P4 Write S B A Y Selector P4 Read fsys Clock fs Clock A Selector B S Y SYSCR3.SCOSEL Figure 7.10 Port 4 (P44) TMP1941AF-45 2003-03-27 TMP1941AF Port 4 Register 5 4 1 1 (Pullup) P44 7 P4 (0xFFFF_F01E) Name Read/Write Reset Value 6 3 P43 2 P42 R/W Input mode 1 (Pullup) 1 P41 0 P40 1 (Pullup) 1 (Pullup) 7 P4CR (0xFFFF_F020) Name Read/Write Reset Value Port 4 Control Register 6 5 4 0 P44C 3 P43C 0 0: IN 2 P42C W 1 1 P41C 0 1: OUT 0 P40C 0 7 P4FC (0xFFFF_F021) Name Read/Write Reset Value Function Port 4 Function Register 6 5 4 0 0: Port 1: SCOUT P44F 3 P43F 0 2 P42F W 1 0: Port 1: CS 1 P41F 0 0 P40F 0 0 1 0 1 0 1 0 1 Port (P40) CS0 Port (P41) CS1 Port (P42) CS2 Port (P43) CS3 Figure 7.11 Port 4 Registers TMP1941AF-46 2003-03-27 TMP1941AF 7.7 Port 5 (P50-P57) Eight Port 5 pins are input-only pins shared with the analog input pins of the A/D Converter (ADC). P53 is also shared with the A/D trigger input pin. Internal Data Bus Port 5 P50-P57 (AN0-AN7) Port 5 Read A/D Conversion Result Register AD Read A/D Converter Channel Selector ADTRG (Only P53) Figure 7.12 Port 5 (P50-P57) 7 P5 (0xFFFF_F025) Bit Symbol Read/Write After reset P57 6 P56 Port 5 Register 5 4 P55 P54 R 3 P53 2 P52 1 P51 0 P50 Input mode Figure 7.13 Port 5 Register Note 1: A/D Mode Control Register 1 (ADMOD1) is used to select an A/D converter input channel(s) and to enable the A/D trigger input. See Section 15.1. When P53 is used as the A/D trigger Input ( ADTRG ) pin, P53 (AN3) can not function as an analog input. Note 2: TMP1941AF-47 2003-03-27 TMP1941AF 7.8 Port 7 (P70-P77) Eight Port 7 pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, all Port 7 pins are configured as input port pins. Alternatively, P70 and P72 can each be programmed as either the TXD output from an SIO channel or the clock input (TA0IN or TA2IN) to an 8-bit timer. P71 and P73 can each be programmed as either the RXD input to an SIO channel or the timer output (TA1OUT or TA3OUT) from an 8-bit timer. P74 and P75 can each be programmed as either the clock input (TB0IN0 or TB0IN1) to a 16-bit timer or an external interrupt request pin (INT5 or INT6). P76 can be programmed as the timer flip-flop output (TB0OUT) from a 16-bit timer. P77 can be programmed as an external interrupt request pin (INT0). The P7CR and P7FC registers select the direction and function of the Port 7 pins. A reset sets the Output Latch (P7) to all 1s, and clears the P7CR and P7FC register bits, configuring all Port 7 pins as input port pins. When INT0 is used as a wake-up from STOP mode with the SYSCR2.DRVE bit cleared, the P7FC.P77F bit must be set to 1. Reset Direction Control (bitwise) P7CR Write Function Control (bitwise) Internal Data Bus P7FC Write S Output Latch A S Selector P7 Write TXD3, TXD4 B Configurable as an open-drain output ODE.ODE70 ODE.ODE72 S Selector P7 Read TA0IN TA2IN A P70 (TA0IN/TXD3) P72 (TA2IN/TXD4) B Figure 7.14 Port 7 (P70, P72) TMP1941AF-48 2003-03-27 TMP1941AF Reset Direction Control (bitwise) P7CR Write Function Control (bitwise) Internal Data Bus P7FC Write S Output Latch A S Selector P7 Write Timer Flip-Flop Output TA1OUT: From TMRA01 TA3OUT: From TMRA23 S Selector P7 Read RXD3 RXD4 Reset A B B P71 (TA1OUT/RXD3) P73 (TA3OUT/RXD4) Direction Control (bitwise) P7CR Write Function Control (bitwise) Internal Data Bus P7FC Write S Output Latch P7 Write S Selector P7 Read A B P74 (TB0IN0/INT5) P75 (TB0IN1/INT6) TB0IN0 TB0IN1 INT5 INT6 Figure 7.15 Port 7 (P71, P73, P74, P75) TMP1941AF-49 2003-03-27 TMP1941AF Reset Direction Control (bitwise) P7CR Write Function Control (bitwise) Internal Data Bus P7FC Write S Output Latch A S Selector B P76 (TB0OUT) P7 Write Timer Flip-Flop Output TB0OUT: From TMRB0 S Selector P7 Read Reset B A Direction Control (bitwise) P7CR Write Function Control (bitwise) Internal Data Bus P7FC Write S Output Latch P77 (INT0) P7 Write S Selector P7 Read (Note) INT0 Level/Edge Sensitivity Positive/Negative Polarity A B IMCGA0.EMCG[01:00], IMCGA0.INT0EN IMC0L.EIM1 Figure 7.16 Port 7 (P76, P77) TMP1941AF-50 2003-03-27 TMP1941AF Port 7 Register 5 4 P75 P74 7 P7 (0xFFFF_F02B) Name Read/Write Reset Value P77 6 P76 3 P73 2 P72 1 P71 0 P70 1 1 R/W Input mode (The Output Latch is set to 1.) 1 1 1 1 1 1 7 P7CR (0xFFFF_F02E) Name Read/Write Reset Value Function P77C 0 6 Port 7 Control Register 5 4 P75C 0 0: IN P74C W 0 1: OUT 3 P73C 0 2 P72C 0 1 P71C 0 0 P70C 0 P76C 0 Port 7 Direction Settings 0 Input 1 Output 7 P7FC (0xFFFF_F02F) Port 7 Function Register 6 5 4 P74F W 0 0: Port 1: TB0IN0 3 P73F 2 P72F 1 P71F 0 P70F Name P77F P76F P75F Read/Write Reset Value 0 0 0 Function 0: Port 0: Port 0: Port 1: Wake-up 1: TB0OUT 1: TB0IN1 INT0 INT0 Settings P7FC.P77F P7CR.P77C 0 0 0: Port 0: Port 1: TA3OUT 1: TA2IN 1: RXD4 1: TXD4 0 0 0: Port 0: Port 1: TA1OUT 1: TA0IN 1: RXD3 1: TXD3 1 0 Note: Required to exit STOP mode, with SYSCR2.DRVE cleared. Otherwise, unneeded. TB0OUT Settings P7FC.P76F P7CR.P76C TB0IN1 Settings P7FC.P75F P7CR.P75C TB0IN0 Settings P7FC.P74F P7CR.P74C RXD4 Settings P7FC.P73F P7CR.P73C TA2IN Settings P7FC.P72F P7CR.P72C RXD3 Settings P7FC.P71F P7CR.P71C TA0IN Settings P7FC.P70F P7CR.P70C 1 1 1 0 1 0 TA3OUT Settings P7FC.P73F P7CR.P73C TXD4 Settings P7FC.P72F P7CR.P72C TA1OUT Settings P7FC.P71F P7CR.P71C TXD3 Settings P7FC.P70F P7CR.P70C 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 Figure 7.17 Port 7 Registers TMP1941AF-51 2003-03-27 TMP1941AF 7.9 Port 8 (P80-P87) Eight Port 8 pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, all Port 8 pins are configured as input port pins, and the Output Latch (P8) is set to all 1s. Port 8 pins (except P87) can be programmed as clock inputs to 16-bit timers, timer flip-flop outputs from 16bit timers, or external interrupt request pins (INT7 through INTA). Setting the P8FC register bits configures the Port 8 pins for dedicated functions. A reset clears all the P8CR and P8FC register bits, configuring all Port 8 pins as input port pins. TMP1941AF-52 2003-03-27 TMP1941AF Reset Direction Control (bitwise) P8CR Write Function Control (bitwise) Internal Data Bus P8FC Write S Output Latch P80 (TB1IN0/INT7) P81 (TB1IN1/INT8) P83 (TB2IN0/INT9) P84 (TB2IN1/INTA) P8 Write S Selector P8 Read TB1IN0 TB1IN1 TB2IN0 TB2IN1 INT7 INT8 INT9 INTA Reset A B Direction Control (bitwise) P8CR Write Function Control (bitwise) Internal Data Bus P8FC Write S Output Latch A S Selector B P82 (TB1OUT) P85 (TB2OUT) P86 (TB3OUT) P87 P8 Write Timer Flip-Flop Output TB1OUT: From TMRB1 TB2OUT: From TMRB2 TB3OUT: From TMRB3 S Selector P8 Read B A Figure 7.18 Port 8 (P80~P87) TMP1941AF-53 2003-03-27 TMP1941AF Port 8 Register 5 4 P85 P84 R/W Input mode (The Output Latch is set to 1.) 7 P8 (0xFFFF_F030) Name Read/Write Reset Value P87 6 P86 3 P83 2 P82 1 P81 0 P80 7 P8CR (0xFFFF_F032) Name Read/Write Reset Value Function 0 P87C Port 8 Control Register 6 5 4 P86C 0 P85C 0 P84C W 0 0: IN 3 P83C 0 1: OUT 2 P82C 0 1 P81C 0 0 P80C 0 Port 8 Direction Settings 0 1 Input Output Port 8 Function Register 7 P8FC (0xFFFF_F033) Name Read/Write Reset Value Function Must be written as 0. 0 0 0 0: Port 0: Port 0: Port 1: TB3OUT 1: TB2OUT 1: TB2IN1 6 P86F 5 P85F 4 P84F W 3 P83F 0 0: Port 1: TB2IN0 2 P82F 0 1 P81F 0 0 P80F 0 0: Port 1: TB1IN0 0: Port 0: Port 1: TB1OUT 1: TB1IN1 TB1OUT Settings P8FC.P82F P8CR.P82C TB3OUT Settings P8FC.P86F P8CR.P86C 1 1 TB2OUT Settings P8FC.P85F P8CR.P85C 1 1 1 1 Figure 7.19 Port 8 Registers TMP1941AF-54 2003-03-27 TMP1941AF 7.10 Port 9 (P90-P97) * P90-P95 P90-P95 can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, P90-P95 are configured as input port pins, and the corresponding Output Latch (P9) bits are set to 1. Setting the bits in the P9FC register configures the corresponding pin for SIO input or output pins. A reset clears the relevant P9CR and P9FC bits, configuring P90-P95 as input port pins. * P96-P97 P96 and P97 function as general-purpose I/O pins. As output ports, P96 and P97 are configured as open-drain outputs. Upon reset, the relevant Output Latch (P9) bits are set to 1, and the P9CR register bits are set, causing P96 and P97 to assume the high-impedance state. P96 and P97 can also be used as the XT1 and XT2 pins; in this case, a low-frequency crystal is connected between XT1 and XT2 to provide for Dual-Clock mode, which is controlled through System Clock Control Registers 0 and 1 (SYSCR0 and SYSCR1). (1) P90 (TXD0) and P93 (TXD1) P90 and P93 can be programmed to function as either general-purpose I/O pins or TXD output pins for SIO channels. P90 and P93 are configurable as open-drain outputs. Reset Direction Control (bitwise) P9CR Write Internal Data Bus Function Control (bitwise) P9FC Write S Output Latch A S Selector TXD0, TXD1 P9 Write P90 (TXD0) P93 (TXD1) Configurable as open-drain outputs ODE.ODE90 ODE.ODE93 B S Selector P9 Read B A Figure 7.20 Port 9 (P90, P93) TMP1941AF-55 2003-03-27 TMP1941AF (2) P91 (RXD0) and P94 (RXD1) P91 and P94 can be programmed to function as either general-purpose I/O pins or RXD input pins for SIO channels. Reset Direction Control (bitwise) P9CR Write Internal Data Bus S Output Latch S P9 Write Selector A P9 Read RXD0, RXD1 B P91 (RXD0) P94 (RXD1) Figure 7.21 Port 9 (P91, P94) TMP1941AF-56 2003-03-27 TMP1941AF (3) P92 (SCLK0/ CTS0 ) and P95 (SCLK1/ CTS1 ) P92 and P95 can be programmed to function as general-purpose I/O pins, or SCLK clock input or output pins or CTS input pins for SIO channels. Reset Direction Control (bitwise) P9CR Write Function Control (bitwise) Internal Data Bus P9FC Write S Output Latch A S Selector B P92 (SCLK0/ CTS0 ) P95 (SCLK1/ CTS1) P9 Write SCLK0 and SCLK1 outputs S Selector P9 Read CTS0 , CTS1 SCLK0, SCLK1 B A Figure 7.22 Port 9 (P92, P95) TMP1941AF-57 2003-03-27 TMP1941AF (4) P96 (XT1) and P97 (XT2) P96 and P97 function as general-purpose I/O pins. Alternatively, P96 and P97 can be used as the XT1 and XT2 pins for connecting a low-frequency crystal. Reset S Direction Control (bitwise) Low-Frequency Oscillator Enable P9CR Write S Output Latch Output Buffer (Open-drain) P9 Write P96 (XT1) S B Y Selector Internal Data Bus A P9 Read (Enabled when 1) S Direction Control (bitwise) P9CR Write S Output Latch Output Buffer (Open-Drain) P9 Write Low-Frequency Clock S B Y Selector A P9 Read P97 (XT2) Figure 7.23 Port 9 (P96, P97) TMP1941AF-58 2003-03-27 TMP1941AF Port 9 Register 5 4 P95 P94 R/W Output mode 1 1 1 1 Input mode 1 1 1 1 7 P9 (0xFFFF_F031) Name Read/Write Reset Value P97 6 P96 3 P93 2 P92 1 P91 0 P90 7 P9CR (0xFFFF_F034) Name Read/Write Reset Value Function P97C 1 6 Port 9 Control Register 5 4 P95C 0 0: IN P94C W 0 1: OUT 3 P93C 0 2 P92C 0 1 P91C 0 0 P90C 0 P96C 1 Port 9 Direction Settings 0 Input 1 Output 7 P9FC (0xFFFF_F035) Name Read/Write Reset Value Function Port 9 Function Register 6 5 4 P95F 0 0: Port 1: SCLK1 output or CTS1 / SCLK1 input W 3 P93F 0 0: Port 1: TXD1 2 P92F 0 0: Port 1: SCLK0 output or CTS0 / SCLK0 input 1 0 P90F 0 0: Port 1: TXD0 CTS1 /SCLK1 Input Settings P9FC.P95F 1 P9CR.P95C 0 SCLK1 Output Settings P9FC.P95F 1 P9CR.P95C 1 TXD1 Output Settings P9FC.P93F P9CR.P93C CTS1 /SCLK0 Input Settings P9FC.P92F 1 P9CR.P92C 0 TXD0 Output Settings P9FC.P90F P9CR.P90C 1 1 1 1 SCLK0 Output Settings P9FC.P92F 1 P9CR.P92C 1 Note 1: Setting bit 0 of the Open-Drain Enable (ODE) register configures theTXD0 pin as an open-drain output. Setting bit 1 of the ODE register configures the TXD1 pin as an open-drain output. See Section 7.11. The P91/RXD0 and P94/RXD1 pins do not have bits for selecting pin functions. These pins can be continuously used as shared input port and serial data input pins. Low-speed oscillator consideration When a low-frequency crystal is connected between XT1 (P96) and XT2 (P97), the following register settings are required to reduce power consumption: When a crystal is connected between XT1 and XT2: P9CR.P96C-P97C = 11 P9.P96-P97 = 00 When XT1 is driven with an external clock: P9CR.P96C-P97C = 11 P9.P96-P97 = 10 Note 2: Figure 7.24 Port 9 Registers TMP1941AF-59 2003-03-27 TMP1941AF 7.11 Port A (PA0-PA7) Eight Port A pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, all Port A pins are configured as input port pins. Alternatively, PA0-PA3 can be programmed as external interrupt request pins (INT1-INT4), and PA5- PA7 as the Serial Bus Interface (SBI) pins. Setting the PAFC register bits configures the corresponding Port 8 pins for dedicated functions. A reset clears all the PACR and PAFC register bits, configuring all Port A pins as input port pins. When INT1-INT4 are used as a wake-up from STOP mode with the SYSCR2.DRVE bit cleared, the corresponding bits in the PAFC register must be set to 1. Port A can act as an interface to the DSU ICE. TMP1941AF-60 2003-03-27 TMP1941AF Reset Direction Control (bitwise) PACR Write Function Control (bitwise) Internal Data Bus PAFC Write S Output Latch PA0-PA3 (INT1-INT4) PA Write S Selector B PA Read A (Note) INT1-INT4 Level/Edge Sensitivity Positive/Negative Polarity IMCGAx.EMCGx[1:0], IMCGAx.INTxEN IMCxx.EIMx Reset Direction Control (bitwise) PACR Write Internal Data Bus S Output Latch S PA Write Selector A B PA4 PA Read Figure 7.25 Port A (PA0-PA4) TMP1941AF-61 2003-03-27 TMP1941AF Reset Direction Control (bitwise) PACR Write Function Control (bitwise) Internal Data Bus PAFC Write S Output Latch A S Selector PA Write SCK Output B PA5 (SCK) S Selector PA Read SCK Input B A Reset Direction Control (bitwise) PACR Write Function Control (bitwise) Internal Data Bus PAFC Write S Output Latch A S Selector B Configurable as an open-drain output ODE.ODEA6 PA6 (SO/SDA) PA Write SO Output S Selector PA Read SDA Input B A Figure 7.26 Port A (PA5-PA6) TMP1941AF-62 2003-03-27 TMP1941AF Reset Direction Control (bitwise) PACR Write Function Control (bitwise) Internal Data Bus PAFC Write S Output Latch A S Selector B Configurable as an open-drain output ODE.ODEA7 PA7 (SI/SCL) PA Write SCL Output S Selector PA Read SI Input B A SCL Input Figure 7.27 Port A (PA7) TMP1941AF-63 2003-03-27 TMP1941AF Port A Register 5 4 PA5 PA4 R/W Input mode (The Output Latch set to 1.) 7 PA (0xFFFF_F036) Name Read/Write Reset Value PA7 6 PA6 3 PA3 2 PA2 1 PA1 0 PA0 7 PACR (0xFFFF_F038) Name Read/Write Reset Value Function 0 PA7C Port A Control Register 6 5 4 PA6C 0 PA5C 0 0: IN PA4C W 0 1: OUT 3 PA3C 0 2 PA2C 0 1 PA1C 0 0 PA0C 0 Port A Direction Settings 0 1 Input Output Port A Function Register 7 PAFC (0xFFFF_F039) Name Read/Write Reset Value Function 0 0: Port 1: SCL output 0 0 Must be written as 0. 0: Port 0: Port 0: Port 0: Port 1: Wake-up 1: Wake-up 1: Wake-up 1: Wakeup INT1 INT2 INT3 INT4 input input input input 0: Port 0: Port 1: SDA/SO 1: SCK output output PA7F 6 PA6F 5 PA5F 4 PA4F W 3 PA3F 2 PA2F 1 PA1F 0 PA0F Wake-up INT1-INT4 Input Settings PAFC.PAxF PACR.PAxC 1 0 Note: Required to exit STOP mode, with SYSCR2.DRVE cleared. Otherwise, unneeded. SCK Output Settings PAFC.PA5F PACR.PA5C SDA/SO Output Settings PAFC.PA6F SCL Output Settings PAFC.PA7F PACR.PA7C 1 1 PACR.PA6C 1 1 1 1 Figure 7.28 Port A Registers TMP1941AF-64 2003-03-27 TMP1941AF 7.12 Open-Drain Output Control The TXD output pins (P70, P72, P90 and P93) of the SIO, and the SO/SDA (PA6) and SI/SCL (PA7) pins of the Serial Bus Interface (SBI) can be configured as either push-pull or open-drain outputs. Open-Drain Enable Register 6 5 4 0 P72 0: Pushpull 1: Opendrain 0 P70 0: Pushpull 1: Opendrain 0 PA7 0: Pushpull 1: Opendrain ODE72 ODE70 7 ODE (0xFFFF_F050) Name Read/Write Reset Value Function 3 ODEA7 R/W 2 ODEA6 0 PA6 0: Pushpull 1: Opendrain 1 ODE93 0 P93 0: Pushpull 1: Opendrain 0 ODE90 0 P90 0: Pushpull 1: Opendrain Figure 7.29 Open-Drain Enable Register TMP1941AF-65 2003-03-27 TMP1941AF 8. External Bus Interface The TMP1941AF contains external bus interface logic that handles the transfer of information between the internal busses and the memory or peripherals in the external address space. It consists of the External Bus Interface (EBIF) logic and the Chip Select/Wait Controller. The CS/Wait Controller provides four programmable chip select signals, with variable block sizes. The chip select function supports automatic wait-state generation and data bus sizing (8-bit or 16-bit) for each of the four address blocks and the rest of the external address locations. The EBIF logic controls the timing of the external bus, based on the settings of the CS/Wait Controller. The EBIF logic also performs dynamic bus sizing and bus arbitration. (1) Wait-state generation Individually programmable for each address block * * Automatic insertion of up to seven wait cycles WAIT pin (2) Data bus width Individually programmable (8-bit or 16-bit) for each address block (3) Read recovery cycles Individually programmable (to up to 2 cycles) for each address block. Read recovery cycles are dummy cycles inserted between two consecutive external bus cycles. (4) ALE pulse width Selectable ALE pulse width (0.5 or 1.5 cycles). This setting applies to all the address blocks. (5) Bus arbitration * When AM0 = 0 The TMP1941AF has either a mixed 8/16-bit data bus or the 16-bit data bus. The program memory accessed after reset must be connected with the TMP1941AF with a 16-bit data bus. * When AM1 = 1 The TMP1941AF has a 8-bit data bus. When AM1 is at logic 1, the data bus width settings in the Chip Select/Wait Control registers are ignored. TMP1941AF-66 2003-03-27 TMP1941AF 8.1 Address and Data Buses Supported Configurations For external memory interface, Port 0 (AD0-AD7), Port 1 (AD8-AD15/A8-A15) and Port 2 (A16- A23/A0-A7) pins can be configured as the address and data buses. The TMP1941AF supports the following four bus configurations. When AM1 = 0 and AM0 = 1, the address and data buses are configured as shown in (1) below. When AM1 = 0 and AM0 = 0, the address and data buses are configured as shown in (2) below. (1) Address Lines Data Lines Multiplexed Address/Data Lines Port 0 Pin Functions Port 1 Port 2 A23-8 24 Max (16 Mbytes) 8 8 AD0-AD7 A8-A15 A16-A23 A23-8 A23-16 8.1.1 (2) 24 Max (16 Mbytes) 16 16 AD0-AD7 AD8-AD15 A16-A23 A23-8 AD7-0 Timing Diagram ALE RD A7-0 D7-0 AD15-0 ALE RD A15-0 D15-0 Note 1: Because the data bus is multiplxed with the address bus, even in the C and D configurations, address bits also appear on the AD bus prior to the data being accepted or provided. Upon reset, all of Ports 0-2 are configured as general-purpose input ports; programming is required to use them as address or data bus pins. Address and data bus configurations are selectable through the programming of the P1CR, P1FC, P2CR and P2FC registers. Note 2: Note 3: 8.1.2 States of the Address Bus During On-Chip Address Accesses While an on-chip address is being accessed, the address bus maintains the previous address externally presented. During this time, the address/data bus assumes the high-impedance state. TMP1941AF-67 2003-03-27 TMP1941AF 8.2 External Bus Operation This section describes external bus operations. In the timing diagrams which follow, A23-A16 is the address bus, and AD15-AD0 is the address/data bus. This section only provides a functional description of the bus; refer to Section 18, AC Electrical Characteristics, for detailed timing specifications. 8.2.1 Basic Bus Operation While the TMP1941AF provides a total of three clock cycles to perform a read or write, it also allows the bus cycle to be extended by inserting wait states. Figure 8.1 shows external bus read timing. Figure 8.2 shows external bus write timing. While an onchip address is being accessed, the external address bus maintains the previous value with the ALE pin kept inactive. During this time, the address/data bus assumes the high-impedance state, and bus control signals such as RD and WR remain inactive. tsys A[23:16] AD[15:0] ALE ADR DATA Inactive Inactive No change Hi-Z RD External access Internal access Figure 8.1 Read Cycle Timing tsys A[23:16] AD[15:0] ALE WR No change ADR DATA Hi-Z Inactive Inactive External access Internal access Figure 8.2 Write Cycle Timing Note: tsys is the system clock period. TMP1941AF-68 2003-03-27 TMP1941AF 8.2.2 Wait Timing The CS/Wait Controller provides two ways to insert wait states in a bus cycle. Each address block can be programmed either: * * to insert required number of wait state cycles (up to seven cycles), or to use the WAIT pin to insert wait states dynamically on a cycle basis Following are bus cycle timing diagrams with wait states. tsys A[23:16] Upper Address Wait State Upper Address AD[15:0] ALE ADR DATA ADR DATA RD 0 Wait State 1 Wait State Figure 8.3 Read Cycle Timing (with Zero and One Wait State Cycle) Wait States tsys A[23:16] Upper Address Upper Address AD[15:0] ALE ADR DATA ADR DATA RD WAIT (1 + N Wait States; N = 1) 0 Wait State Figure 8.4 Read Cycle Timing (with 1 + N Wait States; N=1) TMP1941AF-69 2003-03-27 TMP1941AF Wait State tsys A[23:16] Upper Address Upper Address AD[15:0] ADR DATA ADR DATA ALE WR 0 Wait State 1 Wait State Figure 8.5 Write Cycle Timing (with Zero and One Wait State Cycle) Wait States tsys A[23:16] Upper Address Upper Address AD[15:0] ADR DATA ADR DATA ALE WR WAIT 0 Wait State 1 + N Wait States; N=1 Figure 8.6 Write Cycle Timing (with 1 + N Wait State Cycles; N=1) TMP1941AF-70 2003-03-27 TMP1941AF 8.2.3 ALE Pulse Width The ALE pulse width is programmed to 0.5 or 1.5 clock cycles through the ALESEL bit of the SYSCR3 register within the CG. The default is 1.5 cycles. This setting applies to the whole external address space. tsys ALE (ALESEL = 0) 0.5 Clock Cycles AD[15:0] ALE (ALESEL = 1) 1.5 Clock Cycles AD[15:0] Figure 8.7 ALE Pulse Width Figure 8.8 shows read cycle timing, with the ALE width programmed to 0.5 and 1.5 clock cycles. tsys A[23:16] Upper Address Upper Address AD[15:0] ADR DATA ADR DATA ALE RD ALE = 0. 5 Clock Cycles ALE = 1. 5 Clock Cycles Figure 8.8 Read Cycle Timing (ALE = 0.5 and 1.5 Clock Cycles) TMP1941AF-71 2003-03-27 TMP1941AF 8.2.4 Read Recovery Time Following an external bus read cycle, a certain recovery time may be required before initiating the next external bus cycle. To allow for a read recovery time, one or two dummy cycles can be inserted between back-to-back bus cycles. (Dummy cycles can only be inserted immediately after a read.) * * * Between an external read and an external read: Between an external read and an external write: After an external write: Programmable Programmable No dummy cycle Dummy cycle insertion is programmable in the CS/Wait Controller. tsys RD AD[15:0] ALE Read Data Next ADR AD[15:0] Read Data Next ADR ALE Two Dummy Cycles Figure 8.9 Read Recovery Time Dummy cycles insert idle cycles between transfers to enable slow off-chip peripherals to remove data from the data bus before the next transfer begins. This provides a sufficient time after the RD strobe for the previous read is deasserted until the address for the next read or write is placed on the address bus. Figure 8.10 shows bus cycle timing with one and two dummy cycles inserted into bus cycles. Dummy tsys Dummy A[23:16] Upper Address AD[15:0] DATA ADR DATA ADR ALE RD 1 Dummy Cycle 2 Dummy Cycles Figure 8.10 Read Cycle Timing (with Dummy Cycles Inserted) TMP1941AF-72 2003-03-27 TMP1941AF 8.3 Bus Arbitration The TMP1941AF provides support for an external bus master to take control of the external bus. Two bus arbitration control signals, BUSRQ and BUSAK , are used to determine the bus master. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the TMP1941AF internal bus. 8.3.1 Bus Access Control External bus masters can gain control of the external bus, but not the TMP1941AF internal bus (GBus). Thus, external bus masters cannot access the TMP1941AF's on-chip memory and peripherals. The External Bus Interface (EBIF) logic in the TMP1941AF manages the arbitration of the external bus; the CPU and on-chip DMAC do not participate in any way in this bus arbitration. During external bus mastership, the CPU and the on-chip DMAC can access the internal memory (RAM and ROM) and registers. Once an external device assumes bus mastership, the CPU or the on-chip DMAC has no way to regain the bus until the external bus master releases the bus. If the CPU or the on-chip DMAC issues an external memory access request, it is forced to wait until the TMP1941AF regains the bus. Therefore, should BUSRQ be left asserted for a long time, the TMP1941AF might suffer system lockups. 8.3.2 Bus Arbitration Flow External devices capable of becoming bus masters assert BUSRQ to request the bus. The TMP1941AF samples BUSRQ at the end of each external bus cycle, as seen on its internal bus (GBus). When the TMP1941AF has made an internal decision to grant the bus, it asserts BUSAK to indicate to the requesting device that the bus is available. At the same time, the TMP1941AF puts the address bus, the data bus and bus control signals in the high-impedance state. A load or store may require multiple bus cycles, depending on the port size of the addressed device (dynamic bus sizing). In that case, the TMP1941AF does not grant the bus until the entire transfer is complete. The TMP1941AF, if so programmed, automatically inserts dummy cycles between back-to-back bus cycles to allow for sufficient read recovery time. In dummy cycles, the TMP1941AF has already internally initiated a bus cycle on the G-Bus for the next external access. The TMP1941AF can only accept an external bus request at the boundary of an internal G-Bus bus cycle. Therefore, if BUSRQ is asserted during a dummy cycle, the TMP1941AF grants the bus after it completes the next external bus cycle. An external bus master must keep BUSRQ asserted until it is granted the bus. A timing diagram of the bus arbitration sequence is shown in Figure 8.11. TMP1941AF-73 2003-03-27 TMP1941AF 1 Internal clock Internal address External address BUSRQ BUSAK TMP1941AF external access 2 3 TMP1941AF external access External bus master TMP1941AF TMP1941AF Figure 8.11 Bus Arbitration Timing Diagram 1. BUSRQ is sampled high. 2. The TMP1941AF recognizes the assertion of BUSRQ . 3. The TMP1941AF asserts BUSAK at the completion of the current bus cycle. The external bus master recognizes BUSAK and assumes bus mastership to start a bus transfer. 8.3.3 Relinquishing the bus When the external bus master has completed its bus transactions, it deasserts BUSRQ to relinquish the bus to the TMP1941AF. Figure 8.12 shows the timing for an external bus master to relinquish the bus. 1 Internal clock Internal address External address BUSRQ TMP1941AF external access 23 TMP1941AF external access @ A B External bus masters TMP1941AF TMP1941AF BUSAK Figure 8.12 External Bus Master Relinquishing the Bus 1. The external bus master has control of the bus. 2. When the external bus master no longer needs the bus, it deasserts BUSRQ . 3. In response to the deassertion of BUSRQ , the TMP1941AF deasserts BUSAK . TMP1941AF-74 2003-03-27 TMP1941AF 9. Chip Select/Wait Controller The TMP1941AF supports direct connections to ROM and SRAM devices. The TMP1941AF provides four programmable chip select signals. Programmable features include variable block sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back bus cycles. CS0 - CS3 (multiplexed with P40-P43) are the chip select output pins for the CS0-CS3 address ranges. These chip select signals are generated when the CPU or on-chip DMAC issues an address within the programmed ranges. The P40-P43 pins must be configured as CS0 - CS3 by programming the Port A Control (P4CR) register and the Port 4 Function (P4FC) register. Chip select address ranges are defined in terms of a base address and an address mask. There is a Base/Mask Address (BMAn) register for each of the four chip select signals, where n is a number from 0 to 3. There is also a set of three Chip Select/Wait Control registers, B01CS, B23CS and BEXCS, each of which consists of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. External memory devices can also use the WAIT pin to insert wait states and consequently prolong read and write bus cycles. 9.1 Programming Chip Select Ranges Each of the four chip select address ranges is defined in the BMAn register. The basic chip select model allows one of the chip select output signals ( CS0 - CS3 ) to assert when an address on the address bus falls within a particular programmed range. The B01CS register defines specific operations for CS0 and CS1 , and the B23CS register defines specific operations for CS2 and CS3 (see Section 9.2). 9.1.1 Base/Mask Address Registers (BMA0-BMA3) The organizations of the BMAn registers are shown in Figure 9.1 and Figure 9.2. The base address (BAn) field specifies the starting address for a chip select. Any set bit in the address mask field (MAn) masks the corresponding base address bit. The address mask field determines the block size of a particular chip select line. The address is compared on every bus cycle. (1) Base address The base address (BAn) field specifies the upper 16 bits (A31-A16) of the starting address for a chip select. The lower 16 bits (A15-A0) are assumed to be zero. Thus, the base address is any multiple of 64 Kbytes starting at 0x0000_0000. Figure 9.3 shows the relationships between starting addresses and the BMAn values. (2) Address mask The address mask field defines whether any particular bits of the address should be compared or masked. Any set bit masks the corresponding base address bit. The address compare logic uses only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address match. Address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as follows: CS0 and CS1 spaces: CS2 and CS3 spaces: A29-A14 A30-A15 The address mask field defines the block size of a particular chip select line. Note: Use physical addresses in the BMAn registers. TMP1941AF-75 2003-03-27 TMP1941AF 7 BMA0 (0xFFFF_E400) Name Read/Write Reset Value Function 1 1 CS0 block size 1 1 Base/Mask Address Registers 6 5 4 R/W 3 2 1 0 MA0 (A29 - A14) 1 1 1 1 0: The address compare logic uses this address bit. 15 Name Read/Write Reset Value Function 0 14 13 12 R/W 11 10 9 8 MA0 (A29 - A14) 0 0 0 0 0 1 1 Must be written as 0. 23 Name Read/Write Reset Value Function 0 22 21 20 BA0 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address for CS0 31 Name Read/Write Reset Value Function 0 30 29 28 BA0 R/W 27 26 25 24 0 0 0 0 0 0 0 A31-A24 of the starting address for CS0 7 BMA1 (0xFFFF_E404) Name Read/Write Reset Value Function 1 6 5 4 R/W 3 2 1 0 MA1 (A29 - A14) 1 CS1 block size 1 1 1 1 1 1 0: The address compare logic uses this address bit. 15 Name Read/Write Reset Value Function 0 14 13 12 R/W 11 10 9 8 MA1 (A29 - A14) 0 0 0 0 0 1 1 Must be written as 0. 23 Name Read/Write Reset Value Function 0 22 21 20 BA1 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address for CS1 31 Name Read/Write Reset Value Function 0 30 29 28 BA1 R/W 27 26 25 24 0 0 0 0 0 0 0 A31-A24 of the starting address for CS1 Note: Bits 10-15 in the BMA0 and BMA1 must be written as zeros. The CS0 and CS1 block sizes can vary from 16 Kbytes to 1 Gbytes. However, the TMP1941AF supports only 16 Mbytes of external address space. Therefore, bits 10-15 in the BMA0 and BMA1 must be cleared so that A24-A29 of an address will not be masked. Figure 9.1 Base/Mask Address Registers (BMA0 and BMA1) TMP1941AF-76 2003-03-27 TMP1941AF 7 BMA2 (0xFFFF_E408) Name Read/Write Reset Value Function 1 1 CS2 block size 1 1 6 5 4 R/W 3 2 1 0 MA2 (A30 - A15) 1 1 1 1 0: The address compare logic uses this address bit. 15 Name Read/Write Reset Value Function 0 14 13 12 R/W 11 10 9 8 MA2 (A30 - A15) 0 0 0 Must be written as 0. 0 0 0 1 23 Name Read/Write Reset Value Function 0 22 21 20 BA2 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address for CS2 31 Name Read/Write Reset Value Function 0 30 29 28 BA2 R/W 27 26 25 24 0 0 0 0 0 0 0 A31-A24 of the starting address for CS2 7 BMA3 (0xFFFF_E40C) Name Read/Write Reset Value Function 1 6 5 4 R/W 3 2 1 0 MA3 (A30 - A15) 1 CS3 block size 1 1 1 1 1 1 0: The address compare logic uses this address bit. 15 Name Read/Write Reset Value Function 0 14 13 12 R/W 11 10 9 8 MA3 (A30 - A15) 0 0 0 Must be written as 0. 0 0 0 1 23 Name Read/Write Reset Value Function 0 22 21 20 BA3 R/W 19 18 17 16 0 0 0 0 0 0 0 A23-A16 of the starting address for CS3 31 Name Read/Write Reset Value Function 0 30 29 28 BA3 R/W 27 26 25 24 0 0 0 0 0 0 0 A31-A24 of the starting address for CS3 Note: Bits 9-15 in the BMA2 and BMA3 must be written as zeros. The CS2 and CS3 block sizes can vary from 32 Kbytes to 1 Gbytes. However, the TMP1941AF supports only 16 Mbytes of external address space. Therefore, bits 9-15 in the BMA0 and BMA1 must be cleared so that A24-A30 of an address will not be masked. Figure 9.2 Base/Mask Address Registers (BMA2 and BMA3) TMP1941AF-77 2003-03-27 TMP1941AF Address 0xFFFF_FFFF Starting Address 0xFFFF_0000 Base Address Value (BAn) FFFF 0x0006_0000 0x0005_0000 0x0004_0000 0x0003_0000 0x0002_0000 0x0001_0000 0x0000_0000 64 Kbytes 0x0000_0000 0006 0005 0004 0003 0002 0001 0000 Figure 9.3 Relationships Between Starting Addresses and Base Address Register Values 9.1.2 Base Address and Address Mask Value Calculations * Program the BMA0 register as follows to cause CS0 to be asserted in the 64 Kbytes of address space starting at 0xC000_0000. 31 16 15 0 BA0 MA0 11000000000000000000000000000011 C 0 0 0 0 0 0 3 BMA0 Register Value The BA0 field specifies the upper 16 bits of the starting address, or 0xC000. The MA0 field determines whether the A29-A14 bits of the address should be compared or masked. The A31 and A30 bits are always compared. Bits 15-10 of the MA0 field must be cleared so that the A29-A24 bits are always compared. When the BMA0 register is programmed as shown above, the A31-A16 bits of the address are compared to the value of the BA0 field. Consequently, the 64-Kbyte address range between 0xC000_0000 and 0xC000_FFFF is defined as the CS0 space. TMP1941AF-78 2003-03-27 TMP1941AF * Program the BMA2 register as follows to cause CS2 to be asserted in the 512 Kbytes of address space starting at 0x1FC8_0000. 31 16 15 0 BA2 MA2 00011111110010000000000000001111 1 F C 8 0 0 0 F BMA2 Register Value The BA2 field specifies the upper 16 bits of the starting address, or 0x1FC8. The MA2 field determines whether the A30-A15 bits of the address should be compared or masked. The A31 bit is always compared. Bits 15-9 of the MA2 field must be cleared so that the A30-A24 bits are always compared. When the BMA2 register is programmed as shown above, the A31-A19 bits of the address are compared to the value of the BA2 field. Consequently, the 512-Kbyte address range between 0x1FC8_0000 and 0x1FCF_FFFF is defined as the CS2 space. * Program the BMA2 register as follows to cause CS2 to be asserted in the 1 Mbytes of address space starting at 0x1FC8_0000. 31 16 15 0 BA2 MA2 00011111110010000000000000011111 1 F C 8 0 0 1 F BMA2 Register Value The BA2 field specifies the upper 16 bits of the starting address, or 0x1FC8. The MA2 field determines whether the A30-A15 bits of the address should be compared or masked. The A31 bit is always compared. Bits 15-9 of the MA2 field must be cleared so that the A30-A24 bits are always compared. When the BMA2 register is programmed as shown above, the A31-A20 bits of the address are compared to the value of the BA2 field. Note, however, that the 512-Kbyte range between 0x1FC0_0000 and 0x1FC7_FFFF is reserved for the on-chip ROM. Consequently, the 512Kbyte address range between 0x1FC8_0000 and 0x1FCF_FFFF is defined as the CS2 space. Note: The TMP1941AF does not assert any CSn signal in the following address ranges: 0xFFFF_8000 through 0xFFFF_BFFF TMP1941AF-79 2003-03-27 TMP1941AF Table 9.1 shows the programmable block sizes for CS0 to CS3. Even if the user has accidentally programmed more than one chip select line to the same area, only one chip select line is driven because of internal line priorities. CS0 has the highest priority, and CS3 the lowest. Example: The starting address of the CS0 space is progammed as 0xC000_0000 with a size of 16 Kbytes. The starting address of the CS1 space is programmed as 0xC000_0000 with a size of 64 Kbytes. CS0 Space CS1 Space 0xC000_FFFF 0xC000_3FFF 0xC000_0000 0xC000_3FFF 0xC000_0000 When an attempt is made to access the overlapping area, the CS0 area is selected. Table 9.1 Supported Block Sizes CS Space CS0 CS1 CS2 CS3 Size (bytes) 16 K 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M 16 M TMP1941AF-80 2003-03-27 TMP1941AF 9.2 Chip Select/Wait Control Registers The organizations of the Chip Select/Wait Control registers are shown in Figure 9.4 to Figure 9.5. Each of these registers consist of a chip select type field, a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. The B01CS register defines the CS0 and CS1 lines; the B23CS register defines the CS2 and CS3 lines; and the BEXCS register defines the access characteristics for the rest of the address locations. Chip Select/Wait Control Registers 6 5 4 3 B0OM W 0 0 Chip select output waveform 00: ROM/RAM Don't use any other value. 0 Data bus width 0: 16-bit 1: 8-bit 0 B0BUS W 1 0 1 Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 7 B01CS (0xFFFF_E480) Name Read/Write Reset Value Function 2 B0W 1 0 15 Name Read/Write Reset Value Function 14 13 12 11 B0E W 0 CS0 enable 0: Disable 1: Enable 10 9 B0RCV W 0 8 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. 23 Name Read/Write Reset Value Function 0 B1OM W 22 21 20 B1BUS 19 18 B1W W 17 16 0 0 Data bus width 0: 16-bit 1: 8-bit 0 1 0 1 Chip select output waveform 00: ROM/RAM Don't use any other value. Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 31 Name Read/Write Reset Value Function 30 29 28 27 B1E W 0 CS1 enable 0: Disable 1: Enable 26 25 B1RCV W 0 24 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. Figure 9.4 Chip Select/Wait Control Registers TMP1941AF-81 2003-03-27 TMP1941AF 7 B23CS (0xFFFF_E484) Name Read/Write Reset Value Function 0 B2OM W 0 Chip select output waveform 00: ROM/RAM Don't use any other value. 6 5 4 B2BUS 3 2 B2W W 1 0 0 Data bus width 0: 16-bit 1: 8-bit 0 1 0 1 Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 15 Name Read/Write Reset Value Function 14 13 12 11 B2E 1 CS2 enable 0: Disable 1: Enable 10 B2M W 0 9 B2RCV 0 8 0 CS2 space Number of dummy cycles (Read recovery select time) 00: 2 dummy cycles 0: Whole 4-Gbyte 01: 1 dummy cycle space 10: No dummy cycle 1: CS 11: Don't use. space 23 Name Read/Write Reset Value Function B3OM W 0 0 22 21 W 0 20 B3BUS 19 B3W 0 1 18 17 16 0 1 Chip select output waveform 00: ROM/RAM Don't use any other value. Data bus width 0: 16-bit 1: 8-bit Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 31 Name Read/Write Reset Value Function 30 29 28 27 B3E W 0 CS3 enable 0: Disable 1: Enable 26 25 B3RCV W 0 24 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. Figure 9.5 Chip Select/Wait Control Registers TMP1941AF-82 2003-03-27 TMP1941AF 7 BEXCS (0xFFFF_E488) Name Read/Write Reset Value Function BEXOM W 0 0 Chip select output waveform 00: ROM/RAM Don't use any other value. 6 5 W 0 4 BEXBUS 3 BEXW 0 1 2 1 0 0 1 Data bus width 0: 16-bit 1: 8-bit Sets the number of Wait cycles 0000-0111: 0-7 wait states 1111: (1 + N) wait states, as determined by the WAIT pin Don't use any other value. 15 Name Read/Write Reset Value Function 14 13 12 11 10 W 0 9 BEXRCV 0 8 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. Figure 9.6 Chip Select/Wait Control Registers 9.3 Application Example Figure 9.7 shows an example usage of the TMP1941AF programmable chip selects. In this example, 128 Kbytes of ROM and 256 Kbytes of RAM are connected off-chip through a 16-bit data bus. TMP1941AF A16-17 AD8-15 Latch x 16 DQ A16 A1-15 ROM (128 Kbits x 16) A15 A0-14 OE CE RAM (128 Kbits x 8) A15-16 A0-14 OE R/W Upper Byte CE1 RAM (128 Kbits x 8) A15-16 A0-14 OE R/W Lower Byte CE1 D8-15 D0-7 AD0-7 ALE CS2 LE A16-17 A1-15 RD HWR CS1 WR I/O1-8 A16-17 A1-15 I/O1-8 AM1 AM0 Figure 9.7 External Memory Connections (ROM Width = 16 bits, RAM Width = 16 bits) TMP1941AF-83 2003-03-27 TMP1941AF 10. DMA Controller (DMAC) The TMP1941AF contains a four-channel DMA controller. 10.1 Features The TMP1941AF DMAC has the following features: (1) Four independent DMA channels (2) Two types of bus requests, with and without bus snooping (3) Transfer requests: Internal transfer requests: Software initiated External transfer requests: Hardware signals from on-chip peripherals and external interrupt pins (4) Dual-address mode (5) Memory-to-memory, memory-to-I/O, and I/O-to-memory transfers (6) Transfer width: * * Memory: 32-bit (8-bit and 16-bit memory devices are supported through the programming of the CS/Wait Controller.) I/O peripherals: 8-, 16-, and 32-bit (7) Address pointers can increment, decrement or remain constant. The user can program the bit positions at which address incrementation or decrementation occurs. (8) Fixed channel priority TMP1941AF-84 2003-03-27 TMP1941AF 10.2 Implementation 10.2.1 On-Chip DMAC Interface Figure 10.1 shows how the DMAC is internally connected with the TX19 core processor and the Interrupt Controller (INTC). INTDREQ[3:0] TX19 Core Processor DACK[3:0] Interrupt Controller (INTC) External Interrupt Requests On-Chip I/O Peripheral Interrupt Requests Bus Grant DMAC BUSGNT Bus Request Bus Release Request Bus Grant Ackowledge Control Address Data BUSREQ BUSREL HAVEIT Internal signals Figure 10.1 DMAC Connections within the TMP1941AF The DMAC provides four independently programmable channels. With each DMA channel, there are two associated signals: a DMA request (INTDREQn) and a DMA acknowledge ( DACKn ), where n is a channel number from 0 to 3. INTDREQn is an input to the DMAC coming from the INTC, and DACKn is an output signal from the DMAC going to the INTC. Channel priority is fixed. Channel 0 has the highest priority, and Channel 3 has the lowest priority. The TX19 core processor supports bus snooping. When snooping is enabled, the TX19 core processor grants the processor data bus to the DMAC, so that the DMAC can access the on-chip RAM connected to the processor. Snooping can be enabled and disabled under software control. The DMAC bus snooping is discussed in the next subsection in more details. There are two bus request signals from the DMAC going to the TX19 core processor, SREQ and GREQ. GREQ is a bus request without snooping. SREQ is a bus request with snooping. Note: DMA channel priority exists only among those using the same type of bus request signal (SREQ or GREQ). For example, once a given DMA channel has acquired bus mastership using SREQ, no other DMA channel can assume bus mastership using GREQ until the ongoing DMA transaction is completed. TMP1941AF-85 2003-03-27 TMP1941AF 10.2.2 DMAC Block The DMAC block diagram is shown in Figure 10.2. Channel 3 Channel 2 Channel 1 31 Channel 0 0 Source A h OE XR egi er sut 0 31 f X e B l [ V " A h OE X OE X ^ W Source Address (SARn) Register B yt C ount OE W X ^ e Destination Address Register (DARn) l R " [ OE W g Byte at Count Register OE X ^ l St us (BCRn) W Channel Control Register (CCRn) X^ Channel Status Register (CSRn) DMA Transfer Control Register (DTCRn) DMA Control Register (DCR) Data Holding Register (DHR) Figure 10.2 DMAC Block Diagram 10.2.3 Bus Snooping The TX19 core processor supports snoop operations. If snooping is enabled, the TX19 core processor grants the processor data bus to the DMAC. Because the DMAC takes control of the processor data bus, the TX19 stops operating during snoop operations until the DMAC relinquishes the bus to the processor. Snooping allows the DMAC to access the onchip RAM, and thus to use them as a DMA source or destination device. The DMAC allows the enabling and disabling of the snooping function by software. If snooping is disabled, the DMAC can not access the on-chip RAM. However, regardless of whether snooping is enabled or disabled, the DMAC assumes mastership of the TMP1941AF on-chip bus (GBus) during DMA transfers. Therefore, as long as DMA transfers are in progress, the TX19 core processor can not access memory or I/O peripherals via the G-Bus; any attempt to do so causes the processor pipeline to stall. Note: If snooping is disabled, the TX19 core processor does not grant mastership of the processor data bus to the DMAC. Therefore, if the on-chip RAM is specified as a source or destination for DMA transfers, a DMA acknowledge signal will never be returned, causing bus lockup. TMP1941AF-86 2003-03-27 TMP1941AF 10.3 Register Description The DMAC has twenty-six 32-bit registers. The DMAC register map is shown in Table 10.1. Table 10.1 DMAC Registers Address 0xFFFF_E200 0xFFFF_E204 0xFFFF_E208 0xFFFF_E20C 0xFFFF_E210 0xFFFF_E218 0xFFFF_E220 0xFFFF_E224 0xFFFF_E228 0xFFFF_E22C 0xFFFF_E230 0xFFFF_E238 0xFFFF_E240 0xFFFF_E244 0xFFFF_E248 0xFFFF_E24C 0xFFFF_E250 0xFFFF_E258 0xFFFF_E260 0xFFFF_E264 0xFFFF_E268 0xFFFF_E26C 0xFFFF_E270 0xFFFF_E278 0xFFFF_E280 0xFFFF_E28C Symbol CCR0 CSR0 SAR0 DAR0 BCR0 DTCR0 CCR1 CSR1 SAR1 DAR1 BCR1 DTCR1 CCR2 CSR2 SAR2 DAR2 BCR2 DTCR2 CCR3 CSR3 SAR3 DAR3 BCR3 DTCR3 DCR DHR Register Name Channel Control Register (Ch. 0) Channel Status Register (Ch. 0) Source Address Register (Ch. 0) Destination Address Register (Ch. 0) Byte Count Register (Ch. 0) DMA Transfer Control Register (Ch. 0) Channel Control Register (Ch. 1) Channel Status Register (Ch. 1) Source Address Register (Ch. 1) Destination Address Register (Ch. 1) Byte Count Register (Ch. 1) DMA Transfer Control Register (Ch. 1) Channel Control Register (Ch. 2) Channel Status Register (Ch. 2) Source Address Register (Ch. 2) Destination Address Register (Ch. 2) Byte Count Register (Ch. 2) DMA Transfer Control Register (Ch. 2) Channel Control Register (Ch. 3) Channel Status Register (Ch. 3) Source Address Register (Ch. 3) Destination Address Register (ch. 3) Byte Count Register (Ch. 3) DMA Transfer Control Register (Ch. 3) DMA Control Register (All channels) Data Holding Register (All channels) TMP1941AF-87 2003-03-27 TMP1941AF 10.3.1 31 Rst W 30 0 : Read/Write DMA Control Register (DCR) 16 15 0 0 : Read/Write Bits 31 Mnemonic Rst Field Name Reset Description Performs a software reset of the DMAC. When the Rst bit is set to 1, all the DMAC internal registers are initialized to their reset values. Any transfer requests are removed and all the four DMA channels are put in Idle state. 0: Don't-care 1: Resets the DMAC. Note 1: When the snoop request is disabled (CCRn.SReq=0), a software reset of the DMAC must be performed in the following sequence: 1. Disable interrupts. 2. Execute NOP four times. 3. Perform a software reset. 4. Perform a software reset again. 5. Re-enable interrupts. Execute steps 3 and 4 consecutively. Note 2: If the software reset command is written to the DCR register immediately after the completion of the last transfer cycle of a DMA transaction, the DMA-done interrupt will not be cleared. In this case, the software reset only initializes channel registers, etc. Note 3: Don't issue a software reset command to the DCR register via a DMA transfer. Figure 10.3 DMA Control Register (DCR) TMP1941AF-88 2003-03-27 TMP1941AF 10.3.2 31 Str W 30 0 Channel Control Registers (CCRn) 25 24 W 23 NIEn R/W 1 22 AblEn R/W 1 6 DIO R/W 0 21 R/W 1 5 DAC R/W 00 20 R/W 0 4 19 R/W 0 3 TrSiz R/W 00 18 R/W 0 2 17 Big R/W 1 1 DPS R/W 00 : Read/Write : Reset Value 16 R/W : Read/Write 0 0 : Reset Value 15 R/W 0 14 ExR R/W 0 13 PosE R/W 0 12 Lev R/W 0 11 10 9 SIO R/W 0 8 SAC R/W 00 7 Sreq ReIEN R/W 0 R/W 0 Bits 31 Mnemonic Str Field Name Channel Start Description Reset value: Enables a DMA channel. Setting this bit puts the DMA channel in Ready state. DMA transfer starts as soon as a transfer request is received. Only a write of 1 is valid, and a write of 0 has no effect on this bit. A 0 is returned on read. 1: Enables a DMA channel. This bit is reserved and must be written as 0. Reset value = 1 1: Enables an interrupt when the channel finishes a transfer without an error condition. 0: Does not enable an interrupt when the channel finishes a transfer without an error condition. Reset value = 1 1: Enables an interrupt when the channel encounters a transfer error. 0: Does not enable an interrupt when the channel encounters a transfer error. This bit is reserved and must be written as 0. This bit is reserved and must be written as 0. This bit is reserved and must be written as 0. This bit is reserved and must be written as 0. Reset value = 1 1: The DMA channel operates in big-endian mode. 0: The DMA channel operates in little-endian mode. In the TMP1941AF, this bit must be cleared to 0. This bit is reserved and must be written as 0. This bit is reserved and must be written as 0. Reset value = 0 Selects a transfer request mode. 1: External transfer requests (interrupt-driven) 0: Internal transfer requests (software-initiated) Reset value = 0 Defines the polarity of the internal DMA request signal (INTDREQn) for the channel. This bit is valid for external transfer requests (i.e., when ExR=1), and has no effect on internal transfer requests (i.e., when ExR=0). In the TMP1941AF, the PosE bit must be cleared, and the Lev bit must be set. Reset value = 0 Specifies whether external transfer requests are level-senstiive or edge-triggered. This bit is valid for external transfer requests (i.e., when ExR=1), and has no effect on internal transfer requests (i.e., when ExR=0). In the TMP1941AF, this bit must be set. 24 23 NIEn Reserved Normal Completion Interrupt Enable Abnormal Termination Interrupt Enable Reserved Reserved Reserved Reserved Big-Endian 22 AbIEn 21 20 19 18 17 Big 16 15 14 ExR Reserved Reserved External Request Mode 13 PosE Positive Edge 12 Lev Level Mode Figure 10.4 Channel Control Registers (CCRn) (1/2) TMP1941AF-89 2003-03-27 TMP1941AF Bit 11 Mnemonic SReq Field Name Snoop Request Description Reset value = 0 Controls whether or not to request bus mastership with snooping. If set, the TX19 core processor's snoop function becomes valid, allowing the DMAC to use the processor's data bus. If cleared, the snoop function is disabled. 1: The snoop function is enabled (i.e., SREQ is used as a bus request signal). 0: The snoop function is disabled (i.e., GREQ is used as a bus request signal). Reset value = 0 Controls whether or not to respond to the bus release request signal from the TX19 core processor. This bit is valid when the DMAC uses GREQ as a bus request signal. This bit has no meaning or effect when the DMAC uses SREQ as a bus request signal because, in that case, the TX19 core processor does not have the capability to generate a bus release request signal. 1: The DMAC will respond to the bus release request signal from the TX19 core processor, if it has control of the bus. The DMAC will relinquish the bus when the current DMA bus cycle completes. 0: The DMAC will ignore the bus release request signal from the TX19 core processor. Reset value = 0 Specifies the type of the source device. 1: I/O device 0: Memory Reset value = 00 Selects the manner in which the source address changes after each cycle. 1x: Fixed (remains unchanged) 01: Decremented 00: Incremented Reset value = 0 Specifies the type of the destination device. 1: I/O device 0: Memory Reset value = 00 Selects the manner in which the destination address changes after each cycle. 1x: Fixed (remains unchanged) 01: Decremented 00: Incremented Reset value = 00 Specifies the amount of data to be transferred in response to a DMA request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) Reset value = 00 Specifies the port size of a source or destination I/O device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 10 RelEn Bus Release Request Enable 9 SIO I/O Source 8:7 SAC Source Address Count 6 DIO I/O Destination 5:4 DAC Destination Address Count 3:2 TrSiz Transfer Size 1:0 DPS Device Port Size Figure 10.4 Channel Control Registers (CCRn) (2/2) Note 1: Note 2: Note 3: The DPS field has no meaning or effect on memory-to-memory transfers. To access on-chip peripherals, the transfer size (TrSiz) must be equal to the device port size (DPS). The CCRn register must be programmed before placing the DMAC in Ready state. TMP1941AF-90 2003-03-27 TMP1941AF 10.3.3 31 Act R 0 15 0 30 0 Channel Status Registers (CSRn) 24 23 NC R/W 0 22 AbC R/W 0 21 R/W 0 20 BES R 0 19 SED R 0 3 18 Conf R 0 2 R/W 00 0 : Read/Write : Reset Value 17 00 : Read/Write : Reset Value 16 Bit 31 Mnemonic Act Field Name Channel Active Description Reset value = 0 Indicates whether or not the DMA channel is in Ready state. 1: The DMA channel is in Ready state. 0: The DMA channel is not in Ready state. Reset value = 0 If set, the DMA channel has terminated by normal completion. If the NIEn bit in the CCRn is set, an interrupt is generated. The NC bit is cleared by writing a 0 to it. Clearing the NC bit causes the interrupt to be cleared. The NC bit must be cleared prior to starting the next transfer. An attempt to set the Str bit in the CCRn when NC=1 will cause an error. A write of 1 has no effect on this bit. 1: The DMA channel has terminated by normal completion. 0: The DMA channel has not terminated by normal completion. Reset value = 0 If set, the DMA channel has terminated with an error. If the AbIEn bit in the CCRn is set, an interrupt is generated. The AbC bit is cleared by writing a 0 to it. Clearing the AbC bit causes the interrupt to be cleared. The AbC bit must be cleared prior to starting the next transfer. An attempt to set the Str bit in the CCRn when AbC=1 will cause an error. A write of 1 has no effect on this bit. 1: The DMA channel has terminated with an error. 0: The DMA channel has not terminated with an error. This bit is reserved and must be written as 0. Reset value = 0 1: A bus error has occurred during the source read cycle. 0: A bus error has not occurred during the source read cycle. Reset value = 0 1: A bus error has occurred during the destination write cycle. 0: A bus error has not occurred during the destination write cycle. Reset value = 0 1: A configuration error is present. 0: No configuration error is present. These bits are reserved and must be written as 0s. 23 NC Normal Completion 22 AbC Abnormal Completion 21 20 BES Reserved Source Bus Error 19 BED Destination Bus Error Configuration Error Reserved 18 Conf 2:0 Figure 10.5 Channel Status Registers (CSRn) TMP1941AF-91 2003-03-27 TMP1941AF 10.3.4 31 SAddr R/W 0 15 SAddr R/W : Read/Write : Reset Value 0 : Read/Write : Reset Value Source Address Registers (SARn) 16 Bit 31:0 Mnemonic SAddr Field Name Source Address Description Reset value: Contains the physical address of the source device. The address changes as programmed in the SAC and TrSiz fields in the CCRn and the SACM field in the DTCRn. Figure 10.6 Source Address Registers (SARn) TMP1941AF-92 2003-03-27 TMP1941AF 10.3.5 31 DAddr R/W 0 15 DAddr R/W : Read/Write : Reset Value 0 : Read/Write : Reset Value Destination Address Registers (DARn) 16 Bit 31:0 Mnemonic DAddr Field Name Destination Address Description Reset value: Contains the physical address of the destination device. The address changes as programmed in the DAC and TrSiz fields in the CCRn and the DACM field in the DTCRn. Figure 10.7 Destination Address Registers (DARn) TMP1941AF-93 2003-03-27 TMP1941AF 10.3.6 31 0 Byte Count Registers (BCRn) 24 23 BC R/W : Read/Write : Reset Value 0 BC R/W : Read/Write : Reset Value 16 15 Bit 23:0 Mnemonic BC Field Name Byte Count Description Reset value: Contains the number of bytes left to transfer on a DMA channel. The count is decremented by 1, 2 or 4 (as determined by the TrSiz field in the CCRn register) for each successful transfer. Figure 10.8 Byte Count Registers (BCRn) TMP1941AF-94 2003-03-27 TMP1941AF 10.3.7 31 0 : Read/Write : Reset Value 15 0 6 5 DACM R/W 000 3 2 SACM R/W 000 : Read/Write : Reset Value 0 DMA Transfer Control Registers (DTCRn) 16 Bit 5:3 Mnemonic DACM Field Name Destination Address Count Mode Description Selects the manner in which the destination address is incremented or decremented. 000: Counting begins with bit 0 of the DARn. 001: Counting begins with bit 4 of the DARn. 010: Counting begins with bit 8 of the DARn. 011: Counting begins with bit 12 of the DARn. 100: Counting begins with bit 16 of the DARn. 101: Reserved 110: Reserved 111: Reserved Selects the manner in which the source address is incremented or decremented. 000: Counting begins with bit 0 of the SARn. 001: Counting begins with bit 4 of the SARn. 010: Counting begins with bit 8 of the SARn. 011: Counting begins with bit 12 of the SARn. 100: Counting begins with bit 16 of the SARn. 101: Reserved 110: Reserved 111: Reserved 2:0 SACM Source Address Count Mode Figure 10.9 DMA Transfer Control Registers (DTCRn) TMP1941AF-95 2003-03-27 TMP1941AF 10.3.8 31 DOT R/W 15 DOT R/W : Read/Write : Reset Value 0 : Read/Write : Reset Value Data Holding Register (DHR) 16 Bit 31:0 Mnemonic DOT Field Name Data on Transfer Description Reset value: Contains data read from the source address during a dual-address operation. Figure 10.10 Data Holding Register (DHR) TMP1941AF-96 2003-03-27 TMP1941AF 10.4 Operation This section describes the operation of the DMAC. 10.4.1 Overview The DMAC is a high-speed 32-bit DMA controller used to quickly move large blocks of data between I/O peripherals and memory without intervention of the TX19 core processor. (1) Devices Supported for the Source and Destination The DMAC handles data transfers from memory to memory and between memory and I/O peripherals. The device from which data is transferred is referred to as a source device, and the device to which data is transferred is referred to as a destination device. Both memory and I/O peripherals can be a source or destination device. The DMAC supports data transfers from memory to I/O peripherals, from I/O peripherals to memory, and from memory to memory, but not from I/O peripherals to I/O peripherals. DMA protocols for memory and I/O peripherals differ in that when accessing an I/O peripheral, the DMAC asserts the DACKn (n = channel number) signal to indicate that data is being transferred in response to a previous transfer request. Because each DMA channel has only one DACKn signal, the DMAC can not handle data transfers between two I/O peripherals. Interrupt requests can be programmed to be a trigger to initiate a DMA process instead of requesting an interrupt to the TX19 core processor. If so programmed, the Interrupt Controller (INTC) forwards a DMA request to the DMAC (see 10.4.6, Interrupts). The DMA request coming from the INTC is cleared when the INTC receives a DACKn from the DMAC. Consequently, a DMA request for a transfer to/from an I/O peripheral is cleared after each DMA bus cycle (i.e., every time the number of bytes programmed into the CCRn.TrSiz field is transferred). On the other hand, during memory-to-memory transfer, the DACKn signal is not asserted until the byte count register (BCRn) reaches zero. Therefore, memory-to-memory transfer can continuously move large blocks of data in response to a single DMA request. For example, data transfers between the TMP1941AF on-chip peripheral and on- or off-chip memory is discontinued after every DMA bus cycle. Nonetheless, until the BCRn register reaches zero, the DMAC remains in Ready state to wait for the next transfer request. (2) Exchanging Bus Mastership (Bus Arbitration) In response to a DMA request, the DMAC issues a bus request to the TX19 core processor. When the DMAC receives a bus grant signal from the TX19 core processor, it assumes bus mastership to service the DMA request. There are two bus request signals from the DMAC going to the TX19 core processor. One is a bus request without snooping (GREQ), and the other is a bus request with snooping (SREQ). The SReq bit in the CCRn register is used to select a bus request signal to use for each DMA channel. While the DMAC has control of the bus, the TX19 core processor may issue a bus release request to the DMAC. The RelEn bit of the CCRn register controls whether to honor this request on a channel-by-channel basis. This setting has a meaning only when a DMA channel uses GREQ (i.e., a bus request without snooping). It has no meaning or effect when a DMA channel uses SREQ (i.e., a bus request with snooping) because, in this case, the TX19 core processor does not have the capability to generate a bus release request. The DMAC relinquishes the bus to the TX19 core processor when there is no pending DMA request to be serviced. Note 1: The NMI interrupt is left pending while the DMAC has control of the bus. Note 2: Don't place the TMP1941AF in Halt powerdown mode while the DMAC is operating. TMP1941AF-97 2003-03-27 TMP1941AF (3) Transfer Request Generation Each DMA channel supports two types of request generation methods: internal and external. Internal requests are those generated within the DMAC. The DMA channel is started as soon as the Str bit in the CCRn register is set. The channel immediately requests the bus and begins transferring data. If a channel is programmed for external request and the Str bit is set, the transfer request signal (INTDREQn) must be asserted by the Interrupt Controller before the channel requests the bus and begins a transfer. Although INTDREQn can be programmed for level/edge sensitivity, the TMP1941AF requires INTDREQn to be low-level sensitive. (4) Data Transfer Modes The TMP1941AF DMAC supports dual-address transfers, but not single-address transfers. The dual-address mode allows data to be transferred from memory to memory and between memory and an I/O peripheral. In this mode, the DMAC explicitly addresses both the source and destination devices. The DMAC also generates a DACKn signal when accessing an I/O peripheral. In dual-address mode, a transfer takes place in two DMA bus cycles: a source read cycle and a destination write cycle. In the source read cycle, the data being transferred is read from the source address and put into the DMAC internal Data Holding Register (DHR). In the destination write cycle, the DMAC writes data in the DHR to a destination address. (5) DMA Channel Operation The DMAC has four independent DMA channels 0 to 3. Setting the Start (Str) bit in the CCRn (n = 0-3) enables a particular channel and puts it in Ready state. When a DMA request is detected in any of the channels in Ready state, the DMAC arbitrates for the bus and begins a transfer. When no DMA request is pending, the DMAC relinquishes the bus to the TX19 core processor and returns to Ready state. The channel can terminate by normal completion or from an error of a bus cycle. When a channel terminates, that channel is put in Idle state. Interrupts can be generated by error termination or by normal channel termination. Figure 10.11shows a general state transitions of a DMA channel. The DMAC does not have bus mastership. Ready Start Idle The DMAC gives up bus mastership. The DMAC assumes bus mastership. Transfer done Transfer The DMAC has bus mastership. Figure 10.11 DMA Channel State Transitions TMP1941AF-98 2003-03-27 TMP1941AF (6) Summary of Transfer Modes The DMAC can perform data transfers as follows according to the combination of mode settings. Transfer Request Edge/Level Address Mode Internal External Low Level Dual Dual Data Flow Memory-to-memory Memory-to-memory Memory-to-I/O I/O-to-memory (7) Address Change Options Address pointers can increment, decrement or remain constant. The SAC and DAC fields in the CCRn respectively select address change directions for the Source Address Register (SARn) and the Destination Address Register (DARn). While memory addresses can be programmed to increment, decrement or remain constant, I/O addresses must be programmed to remain constant. The SACM and DACM fields in the DTCRn provide options to program bit positions at which the source and destination addresses are incremented or decremented after each transfer. The bit position can be bit 0, 4, 8, 12 or 16. Use of bit 0 is the regular increment/decrement mode in which the address changes by 1, 2 or 4, according to the source or destination size. Two examples of how other increment/decrement modes affect address changes are show below. Example 1: When address bit 0 is selected in the SACM field and address bit 4 is selected in the DACM field SAC: Programmed to increment the source address DAC: Programmed to increment the destination address TrSiz: Programmed to a transfer size of 32 bits Source address: 0xA000_1000 Destination address: 0xB000_0000 SACM: 000 Bit 0 is the source address bit at which address incrementation occurs. DACM: 001 Bit 4 is the destination address bit at which address incrementation occurs. Source 0xA000_1000 0xA000_1004 0xA000_1008 0xA000_100C ... Destination 0xB000_0000 0xB000_0010 0xB000_0020 0xB000_0030 ... 1st transfer 2nd transfer 3rd transfer 4th transfer Example 2: When address bit 8 is selected in the SACM field and address bit 0 is selected in the DACM field SAC: Programmed to decrement the address DAC: Programmed to decrement the address TrSiz: Programmed to a transfer size of 16 bits Source address: 0xA000_1000 Destination address: 0xB000_0000 SACM: 010 Bit 8 is the source address bit at which address decrementation occurs. DACM: 000 Bit 0 is the destination address bit at which address decrementation occurs. Source 0xA000_1000 0x9FFF_FF00 0x9FFF_FE00 0x9FFF_FD00 ... Destination 0xB000_0000 0xAFFF_FFFE 0xAFFF_FFFC 0xAFFF_FFFA ... 1st transfer 2nd transfer 3rd transfer 4th transfer TMP1941AF-99 2003-03-27 TMP1941AF 10.4.2 Transfer Request Generation A DMA request must be issued for the DMAC to initiate a data transfer. Each DMA channel in the DMAC supports two types of request generation method: internal and external. In either request generation mode, once a DMA channel is started, a DMA request causes the DMAC to arbitrate for the bus and begin transferring data. * Internal Request Generation A channel is programmed for internal request by clearing the ExR bit in the CCRn. In internal request generation mode, a transfer request is generated as soon as the Str bit in the CCRn is set. An internally generated request keeps a transfer request pending until the transfer is complete. If no transition to a higher-priority DMA channel or a bus master occurs, the channel will use 100% of the available bus bandwidth to transfer all data continuously. Internally generated requests support only memory-to-memory transfer. * External Request Generation A channel is programmed for external request by setting the ExR bit in the CCRn. In external request generation mode, setting the Str bit in the CCRn puts the channel in Ready state. While in Ready state, assertion of the INTDREQn signal (where n is the channel number) coming from the Interrupt Controller (INTC) causes a transfer request to be generated. Externally generated requests support data transfers from memory to memory and between memory and an I/O peripheral. INTDREQn can be programmed for either edge or level sensitivity through the PosE bit in the CCRn. However, in the TMP1941AF, INTDREQn is an active-low, level-sensitive signal. Therefore, the PosE bit must be cleared to 0. The transfer size, i.e., the amount of data to be transferred in response to a transfer request, is programmed in the TrSize field in the CCRn. The transfer size can be 32 bits, 16 bits or 8 bits. A transfer request is removed by assertion of the DACKn signal (where n is the channel number). DACKn is asserted: 1) when an I/O peripheral bus cycle has completed and 2) when the Byte Count Register (BCRn) has reached zero in memory-to-memory transfer. Consequently, a memory-to-I/O or I/O-to-memory transfer request terminates after one DMA bus cycle completes, whereas memory-to-memory transfer can continuously move large blocks of data in response to a single DMA request. The INTC might clear INTDREQn before the DMAC accepts it and begins a data transfer. It must be noted that, even if that happens, a DMA bus cycle might be executed after the interrupt request has been cleared. TMP1941AF-100 2003-03-27 TMP1941AF 10.4.3 DMA Address Modes The TMP1941AF supports only dual-address mode in which both the source and destination devices are explicitly addressed. In dual-address mode, two bus transfers occur: a read from a source device and a write to the destination device. In the source read cycle, data is read from the source address and placed in the DMAC internal Data Holding Register (DHR). Then, in the destination write cycle, the data held in the DHR is written to the destination address. DMAC Source Device Address Address Bus 1. Source read 2. Desti. write Data Data Bus 2. Desti. write 1. Source read Destination Device Figure 10.12 Dual-Address Transfer Mode The transfer size programmed into the CCRn.TrSiz field determines the amount of data that is transferred from a source device to a destination device in response to a DMA request. The transfer size can be 32 bits, 16 bits or 8 bits. The internal DHR is a 32-bit register that serves as a buffer for the data being transferred from a source device to a destination device during dual-address mode. Memory accesses occur in a manner to fulfill the CCRn.TrSiz setting. Remember that the CS/Wait Controller supports either 16-bit or 8-bit bus accesses for external memory. If the DMA transfer size is programmed to 32 bits in CCRn.TrSiz, DMA read and write cycles each take up to four bus cycles to complete. A 16-bit data bus, as programmed in the CS/Wait Controller, requires two independent bus cycles to complete a 32-bit transfer. Likewise, an 8-bit data bus requires four independent bus cycles to complete a 32-bit transfer. Memory-to-I/O and I/O-to-memory DMA transfers are governed by the setting of the CCRn.DPS field in addition to the setting of CCRn.TrSiz. The DPS field defines the port size of a source or destination I/O peripheral. The I/O port size can be 32 bits, 16 bits or 8 bits. If the transfer size is equal to the I/O port size, an I/O access takes a single read or single write cycle. If the I/O port size is less than the programmed transfer size, the internal 32-bit DHR serves as a buffer for the data being transferred. For example, assume that the transfer size is programmed to 32 bits. If the source I/O port size is 8 bits and the destination memory width is 32 bits, then four 8-bit read cycles occur, followed by a 32-bit write cycle. (If the destination is an external memory with a 16-bit data bus, TMP1941AF-101 2003-03-27 TMP1941AF the write cycle takes two bus cycles.) The 32 bits of data are buffered in the DHR until the destination write cycle occurs. Source and destination addresses can be programmed to increment or decrement after each transfer. The SARn and DARn change, if so programmed, after each data transfer, depending on the transfer size, i.e., the programmed TrSiz value. The BRCn is decremented by TrSiz for each data transfer. It is forbidden to program the device port size (DPS) to a value greater than the DMA transfer size (TrSiz). The relationships between TrSiz and DPS are summarized below. Table 10.2 DMA Transfer Sizes and Device Port Sizes (in Dual-Address Mode) TrSiz 0x (32 bits) 0x (32 bits) 0x (32 bits) 10 (16 bits) 10 (16 bits) 10 (16 bits) 11 (8 bits) 11 (8 bits) 11 (8 bits) DPS 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) # of I/O Bus Cycles 1 2 4 Don't use. 1 2 Don't use. Don't use. 1 Note: The DMAC does not incremnt or decrement the address for I/O peripherals. Therefore, if, for example, TrSiz is programmed to 16 bits and DPS is programmed to 8 bits, both the first and second bus cycles access the lower eight bits of the I/O data bus. 10.4.4 DMA Channel Operation Each DMA channel is started by setting the Str bit in the CCRn to 1. Once started, the DMAC checks the channel setups for configuration errors. If no configuration error is present, the channel enters Ready state. When a DMA request is detected while in Ready state, the DMAC arbitrates for the bus and begins transferring data. The channel can terminate by normal completion or from an error. (1) Channel Startup A DMA channel is started by setting the Str bit in the CCRn. Once started, the DMAC checks the channel setups for configuration errors. If a configuration error is detected, the channel terminates abnormally. If no configuration error is present, the channel enters Ready state. Once a channel enters Ready state, the Act bit in the CSRn is set to 1. If the channel is programmed for internal request, the channel requests the bus and starts transferring data immediately. If the channel is programmed for external request, INTDREQn must be asserted before the channel requests the bus. (2) Channel Termination A DMA channel can terminate by normal completion or from an error. The status of a DMA operation can be determined by reading the CSRn. A channel terminates abnormally when an attempt is made to set the Str bit in the CCRn when the NC or AbC bit in the CSRn is set. TMP1941AF-102 2003-03-27 TMP1941AF Normal Termination A DMA channel terminates by normal completion in the following case. Normal completion always occurs at the boundary of transfers programmed into the CCRn.TrSize field. * Data transfers have terminated, with the BCRn decremented to 0. Abnormal Termination The paragraphs that follow summarize the cases in which a DMA channel terminates from an error. * Configuration errors A configuration error results when the channel initialization contains inconsistencies or errors. A configuration error is reported before any data transfer takes place; therefore, in case of a configuration error, the SARn, DARn and BCRn remain unaltered. When a DMA channel has terminated from a configuration error, the AbC and Conf bits in the CSRn are set. A configuration error occurs for the following cases: - Both the CCRn.SIO and CCRn.DIO bits are set. - The CCRn.Str bit is set when the NC or AbC bit in the CSRn is set. - The BCRn contains a value that is not an integer multiple of the transfer size programmed into the CCRn.TrSiz field. - The SARn or DARn contains a value that is not an integer multiple of the transfer size programmed into the CCRn.TrSiz field. - The CCRn.TrSiz and CCRn.DPS fields contain illegal combinations. - The CCRn.Str bit is set when the the BCRn contains a value of zero. * Bus errors When a DMA channel has terminated from a bus error, the AbC bit and the BES or BED bit in the CSRn is set. - A bus error has been reported during a source read or destination write cycle. Note: The contents of the BCRn, SARn and DARn are not guaranteed when a channel has terminated due to a bus error. Chapter 19 lists the reserved addresses that, if accessed, cause a bus error. TMP1941AF-103 2003-03-27 TMP1941AF 10.4.5 DMA Channel Priority The DMAC provides a fixed priority for the four channels, with channel 0 always having the highest priority and channel 3 the lowest. For example, when transfer requests occur on channels 0 and 1 simultaneously, the channel 0 request is serviced first. The channel 1 request is left pending. So that the channel 1 request is serviced, it must be maintained until data transfer completes on channel 0. Remember that the internally generated request is kept until the servicing of the request is finished. External transfer requests come from the Interrupt Controller (INTC). The INTC can program any interrupts to be used as a DMA trigger instead of as an interrupt request. If such an interrupt is programmed for edge sensitivity, the INTC internally maintains a transfer request. However, a levelsensitive interrupt is not held in the INTC; thus the interrupt request signal must remain asserted until the servicing of the DMA request begins. A higher-priority channel always gets the attention of the DMAC. If a transfer request occurs on channel 0 while a request on channel 1 is being serviced, the servicing of the channel 1 request is suspended temporarily in order to service the channel 0 request first. After the channel 0 request has been serviced, channel 1 resumes the remaining data transfer. Channel transitions take place at the boundary of a transfer size programmed for the current channel being serviced; that is, after all data in the DHR are written to a destination. Note: DMA channel priority exists only among those using the same type of bus request signal (SREQ or GREQ). 10.4.6 Interrupts The DMAC can generate an interrupt request (INTDMAn) to the TX19 core processor on completion of a channel operation: either by normal channel termination or by abnormal termination of a bus cycle. * Normal Completion Interrupt When a channel operation terminates by normal completion, the NC bit in the CSRn is set to 1. At this time, if the NIEn bit in the CCRn is set, an interrupt request is generated to the TX19 core processor. * Abnormal Completion Interrupt When a channel operation terminates abnormally, the AbC bit in the CSRn register is set to 1. At this time, if the AbIEn bit in the CCRn register is set, an interrupt request is generated to the TX19 core processor. TMP1941AF-104 2003-03-27 TMP1941AF 10.4.7 Data Packing and Unpacking In dual-address mode, the internal 32-bit DHR allows the data to be packed and unpacked by the DMAC if the programmed transfer size is not equal to the device port size. For example, if a source I/O peripheral is 8-bits wide and a destination memory device is 32-bits wide, four byte-read cycles occur. The four bytes of data are buffered in the DHR before a destination word-write cycle occurs. The following illustrates the byte ordering for packing and unpacking of data. I/O Device DHR 8 4n + 3 4n + 2 4n + 1 4n + 0 D C B A 0 31 Little-Endian D C B A 0 Figure 10.13 Data Packing and Unpacking TMP1941AF-105 2003-03-27 TMP1941AF 10.5 DMA Transfer Timing All DMAC operations are synchronous to the rising edges of the internal system clock. 10.5.1 Dual-Address Mode * Memory-to-memory transfer Figure 10.14 shows a DMA cycle from one external 16-bit memory to another, with the transfer size programmed to 16 bits. A block of data is transferred until the BCRn register reaches 0. tsys A[23:16] CS0 CS1 RD WR / HWR Addr Data Addr Data AD [15:0] Read Write Figure 10.14 Memory-to-Memory Transfer (Dual-Address Mode) * Memory-to-I/O transfer Figure 10.15 shows a DMA cycle from a 16-bit memory to an 8-bit I/O peripheral, with the transfer size programmed to 16 bits. tsys A[23:16] CS0 CS1 RD WR AD[15:0] Addr Data Addr Data Addr Data Read Write Write Figure 10.15 Memory-to-I/O Transfer (Dual-Address Mode) TMP1941AF-106 2003-03-27 TMP1941AF * I/O-to-memory transfer Figure 10.16 shows a DMA cycle from an 8-bit I/O peripheral to a 16-bit memory, with the transfer size programmed to 16 bits. tsys A[23:16] CS0 CS1 RD WR AD[15:0] Addr Data Addr Data Addr Data Read Read Write Figure 10.16 I/O-to-Memory Transfer (Dual-Address Mode) TMP1941AF-107 2003-03-27 TMP1941AF 10.6 Programming Example The following illustrates the programming required to transfer data from an SIO receive buffer (SCnBUF) to the on-chip RAM. The assumptions are as follows: DMAC Settings: * * * * DMA channel used: Channel 0 Source address: SC1BUF Destination address: 0xFFFF_9800 (physical address) Number of bytes transferred: 256 SIO Settings: * * * Data format: 8 bits, UART SIO channel used: Channel 1 Transfer rate: 9600 bps DMA channel 0 is used for the transfer. The SIO1 receive interrupt is used as a trigger to start the DMA channel. DMA channel 0 settings: DCR 0x8000_0000 15 7 0 xxxx, xxxx, xx10, x100 0x3c 0x0000_0000 0xFFFF_F208 0xFFFF_9800 0x0000_00FF 0x80c0_5b0f 27 23 19 /* Reset DMAC * / /* Bit positions */ /* Interrupt level = 4 (arbitrary) * / /*IVR[9:4]; clear INTDMA0 * / /* DACM = 000 * / /* SACM = 000 * / /* Physical address of SC1BUF */ /* Physical address of destination */ /* 256 (Number of bytes to be transferred) */ IMCFL INTCLR DTCR0 SAR0 DAR0 BCR0 CCR0 (Contents) 31 1000000011000000 15 11 7 3 01011x11x0001111 SIO channel 1 settings: IMCCH 31 16 /* Bit positions */ xxxx, xxxx, xx11, 1000 /* Use INTRX1 as a DMA trigger and select DMA ch. 0 * / /* IVR[9:4]; clear INTRX1 * / /* UART mode, 8-bit data format, baud rate generator * / INTCLR 0x32 SC1MOD0 0x09 SC1CR BR1CR 0x00 0x1d /* @fc = 32 MHz (approx. 9615 bps) */ /* Enable receiver * / SC1MOD0 0x29 TMP1941AF-108 2003-03-27 TMP1941AF 11. 8-Bit Timers (TMRAs) The TMP1941AF has a four-channel 8-bit timer (TMRA0-TMRA3), which is comprised of two modules named TMRA01 and TMRA23. The TMRA01 contains the TMRA0 and the TMRA1, and the TMRA23 contains the TMRA2 and TMRA3. Each timer module has the following operating modes: * * * * 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable pulse generation (PPG) mode (Variable frequency, variable duty cycle) 8-bit pulse width modulated (PWM) signal generation mode (Fixed frequency, variable duty cycle) Figure 11.1 and Figure 11.2 are block diagrams of the TMRA01 and TMRA23 respectively. The main components of a timer channel are an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. Two timer channels share a prescalar and a timer flip-flop. A total of six 8-bit registers provide control over the operating modes and timer flip-flops for the TMRA01 and the TMRA23 each, which can be independently programmed. The TMRA01 and the TMRA23 are functionally equivalent. In the following sections, any references to the TMRA01 also apply to the TMRA23. Table 11.1 gives the pins and registers for the two timer modules. Table 11.1 Pins and Registers for the TMRA01 and the TMRA23 TMRA01 External Pins External clock input Timer flip-flop output Timer Run register Registers (Addresses) Timer registers Timer Mode register Timer Flip-Flop Control register TA0IN (Shared with P70) TA1OUT (Shared with P71) TA01RUN (0xFFFF_F100) TA0REG (0xFFFF_F102) TA1REG (0xFFFF_F103) TA01MOD (0xFFFF_F104) TA1FFCR (0xFFFF_F105) TMRA23 TA2IN (Shared with P72) TA3OUT (Shared with P73) TA23RUN (0xFFFF_F108) TA2REG (0xFFFF_F10A) TA3REG (0xFFFF_F10B) TA23MOD (0xFFFF_F10C) TA3FFCR (0xFFFF_F10D) TMP1941AF-109 2003-03-27 Prescaler 2 4 8 16 32 64 128 256 512 Prescalar Clock Source: T0 TA01RUN.TA01PRUN T1 Timer Flip-Flop TA1FF TA01RUN.TA0RUN Selector T1 T4 T16 8-Bit Up-Counter (UC0) 2n-1 Overflow TA01MOD. PWM[01:00] TA01MOD. TA1CLK[1:0] Match Detect 8-Bit Comparator (CP1) TA01MOD. TA0CLK[1:0] T1 T16 T256 8-Bit Up-Counter (UC1) Selector TA01RUN.TA1RUN TA1FFCR T4 T16 T256 11.1 Block Diagrams Run/Clear Timer Flip-Flop Output: TA1OUT External Clock Input: TA0IN Figure 11.1 TMRA01 Block Diagram TMP1941AF-110 8-Bit Comparator (CP0) TA01MOD. TA01M[1:0] 8-Bit Timer Register TA1REG Match Detect TA0TRG 8-Bit Timer Register TA0REG TA01RUN. TA0RDE Register Buffer 0 Internal Data Bus TMRA0 Interrupt Output: INTTA0 TMRA0 Match Output: TA0TRG Internal Data Bus TMP1941AF TMRA1 Interrupt Output: INTTA1 2003-03-27 Prescaler 2 4 8 16 32 64 128 256 512 Run/Clear Prescalar Clock Source: T0 TA23RUN.TA23PRUN T1 T4 T16 T256 Timer Flip-Flop TA3FF Selector T1 T4 T16 8-Bit Up-Counter (UC2) 2n-1 Overflow TA23MOD. TA23RUN.TA2RUN Selector T1 T16 T25 8-Bit Up-Counter (UC3) TA23RUN.TA3RUN Timer Flip-Flop Output: TA3OUT TA3FFCR External Clock Input: TA2IN TA23MOD. TA2CLK[1:0] TA23MOD. PWM[21:20] TA3CLK[1:0] Figure 11.2 TMRA23 Block Diagram TA2TRG TA23MOD. TMP1941AF-111 8-Bit Comparator (CP2) Match Detect 8-Bit Timer Register TA2REG TA23M[1:0] TA23RUN. TA2RDE Register Buffer 2 Internal Data Bus TMRA2 Interrupt Output: INTTA2 TMRA2 Match Output: TA2TRG 8-Bit Comparator (CP3) Match Detect 8-Bit Timer Register TA3REG TMP1941AF Internal Data Bus TMRA3 Interrupt Output: INTTA3 2003-03-27 TMP1941AF 11.2 Timer Components 11.2.1 Prescaler The TMRA01 has a 9-bit prescalar that slows the rate of a clocking source to the counters. The prescalar clock source (T0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG. The TA01PRUN bit in the TA01RUN register allows the enabling and disabling of the prescalar for the TMRA01. A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the prescalar. Prescalar output taps can be divide-by-2 (1), divide-by-8 (T4), divide-by-32 (T16) and divideby-512 (T256). Table 11.2 shows prescalar output clock resolutions (@fc = 32 MHz). Table 11.2 Prescalar Output Clock Resolutions @fc = 40 MHz Peripheral Clock Select SYSCR1. FPSEL Clock Gear Value SYSCR1. GEAR[1:0] Prescaler Clock Source SYSCR0. PRCK[1:0] 00 (fperiph/4) Prescalar Output Clock Resolution T1 fc/2 (0.2 s) fc/2 (0.1 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.2 s) fc/2 (0.1 s) fc/2 (0.2 s) 5 3 2 3 5 6 4 5 3 4 2 3 T4 fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.8 s) 4 5 3 4 5 3 4 5 6 7 8 5 6 7 4 5 6 3 4 5 T16 fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (12.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 10 9 7 8 9 6 7 8 5 6 7 T256 fc/2 fc/2 11 10 9 (51.2 s) (25.6 s) (102.4 s) (51.2 s) (25.6 s) (204.8 s) (102.4 s) (51.2 s) (409.6 s) (204.8 s) (102.4 s) (51.2 s) (25.6 s) (51.2 s) (25.6 s) (51.2 s) (25.6 s) (51.2 s) (25.6 s) 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (12.8 s) fc/2 12 11 10 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 fc/2 fc/2 fc/2 13 12 11 fc/2 fc/2 (25.6 s) 14 13 12 11 10 9 11 (fc/8) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (12.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) 5 6 7 5 6 7 5 6 7 5 6 7 8 fc/2 fc/2 fc/2 fc/2 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (12.8 s) fc/2 fc/2 11 10 9 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (12.8 s) fc/2 fc/2 11 10 9 fc/2 (12.8 s) fc/2 fc/2 11 10 9 11 (fc/8) 01 (fperiph/2) 10 (fperiph) fc/2 (12.8 s) Note 1: The prescaler's output clock Tn must be selected so that Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the timer is running. Note 3: The -- character means "Don't use." TMP1941AF-112 2003-03-27 TMP1941AF 11.2.2 Up-Counters (UC0 and UC1) The timer module contains two 8-bit binary up-counters, each of which is driven by a clock independently selected by the TA01MOD register. The clock input to the UC0 is either one of three prescalar outputs (1,T4, T16) or the external clock applied to the TA0IN pin. Which clock is to use is programmed into the TA0CLK[1:0] field of the TA01MOD register. Possible clock sources for the UC1 depend on the selected operating mode. In 16-bit interval timer mode, the clock input to the UC1 is always the UC0 overflow output. In other operating modes, the clock input to the UC1 is either one of three prescalar outputs (1,T16, T256) or the TMRA0 comparator match-detect output. The TA0RUN and TA1RUN bits in the TA01RUN register are used to start counting and to stop and clear the counter. Upon reset, the up-counter is set to 00H and the whole timer module is disabled. 11.2.3 Timer Registers (TA0REG and TA1REG) Each timer register is an 8-bit register containing a time constant. When the up-counter reaches the time constant value in the timer register, the comparator block generates a match-detect signal. When the time constant is set to 00H, a match occurs upon a counter overflow. One of the two timer registers, TA0REG, is double-buffered. The double-buffering function can be enabled and disabled through the programming of the TA0RDE bit in the TA01RUN: 0=disable, 1=enable. If double-buffering is enabled, the TA0REG latches a new time constant value from the register buffer. This takes place upon detection of a 2n-1 overflow in PWM mode and upon a match between the UC0 and the TA1REG in PPG mode. Double-buffering must be disabled in interval timer modes. A reset clears the TA01RUN.TA0RDE bit to 0, disabling the double-buffering function. To use this function, the TA01RUN.TA0RDE bit must be set to1 after loading the TA0REG with a time constant. When TA01RUN.TA0RDE=1, the next time constant can be written to the register buffer. Figure 11.13 illustrates the double-buffer structure for the TA0REG. Up-Counter Comparator (CP0) Timer Register 0 (TA0REG) Y Shift Trigger Register Buffer 0 Write Selector B A Write to TA0REG S TA1REG Match in PPG Mode 2n-1 Overflow in PWM Mode TA01RUN.TA0RDE Internal Data Bus Figure 11.3 Timer Register 0 (TA0REG) Structure Note: The timer register and the corresponding register buffer are mapped to the same address. When TA01RUN.TA0RDE=0, a time constant value is written to both of the timer register and the register buffer; when TA01RUN.TA0RDE=1, a time constant value is written only to the register buffer. TMP1941AF-113 2003-03-27 TMP1941AF The addresses of the timer registers are as follows: TA0REG: TA1REG: TA2REG: TA3REG: 0xFFFF_F102 0xFFFF_F103 0xFFFF_F10A 0xFFFF_F10B The timer registers are write-only registers. 11.2.4 Comparators (CP0 and CP1) The comparator compares the output of the 8-bit up-counter with a time constant value in the 8-bit timer register. When a match is detected, an interrupt (INTTA0/INTTA1) is generated and the timer flip-flop is toggled, if so enabled. 11.2.5 Timer Flip-Flop (TA1FF) The timer flip-flop (TA1FF) is toggled, if so enabled, each time the comparator match-detect output is asserted. The toggling of the timer flip-flop can be enabled and disabled through the programming of the TAFF1IE bit in the TA1FFCR. A reset clears the TAFF1IE bit, disabling the toggling of the TA1FF. The TA1FF can be initialized to 1 or 0 by writing 01 or 10 to the TAFF1C[1:0] field in the TA1FFCR. Additionally, a write of 00 by software causes the TA1FF to be toggled to the opposite value. The value of the TA1FF can be driven onto the TA1OUT pin, which is multiplexed with P71. The Port 7 registers (P7CR and P7FC) must be programmed to configure the P71/TA1OUT pin as TA1OUT. TMP1941AF-114 2003-03-27 TMP1941AF 11.3 Register Description TMRA01 Run Register 7 TA01RUN (0xFFFF_F100) Name Read/Write Reset Value TA0RDE R/W 0 Double Buffering 0: Disable 1: Enable 6 5 4 3 I2TA01 0 IDLE 0: Off 1: On 2 TA01PRUN 1 TA1RUN 0 R/W 0 TA0RUN 0 0 Prescalar Run/Stop Control 0: Stop 1: Run Function Timer Run/Stop Control 0: Stop & clear 1: Run I2TA01: Timer on/off in IDLE mode TA01PRUN: Prescaler TA1RUN: TMRA1 TA0RUN: TMRA0 Note: Bits 4, 5 and 6 are read as undefined. TMRA23 Run Register 7 TA23RUN (0xFFFF_F108) Name Read/Write Reset Value TA2RDE R/W 0 Double Buffering 0: Disable 1: Enable 6 5 4 3 I2TA23 0 IDLE 0: Off 1: On 2 TA23PRUN 1 TA3RUN R/W 0 TA2RUN Function 0 Prescalar Run/Stop Control 0: Stop 1: Run 0 0 Timer Run/Stop Control 0: Stop & clear 1: Run I2TA23: Timer on/off in IDLE mode TA23PRUN: Prescaler TA3RUN: TMRA3 TA2RUN: TMRA2 Note: Bits 4, 5 and 6 are read as undefined. Figure 11.4 Timer Run Registers TMP1941AF-115 2003-03-27 TMP1941AF TMRA01 Mode Register 7 TA01MOD Name (0xFFFF_F104) Read/Write Reset Value TA01M1 0 6 TA01M0 0 5 PWM01 0 PWM period 00: Reserved 01: 26-1 10: 27-1 11: 28-1 4 PWM00 0 R/W 3 TA1CLK1 0 2 TA1CLK0 0 1 TA0CLK1 0 0 TA0CLK0 0 Function Operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit PPG 11: 8-bit PWM TMRA1 clock source 00: TA0TRG 01: T1 10: T16 11: T256 TMRA0 clock source 00: TA0IN input 01: T1 10: T4 11: T16 TMRA0 clock source 00 External input (TA0IN) 01 10 11 T1 T4 T16 (Prescaler) (Prescaler) (Prescaler) TMRA1 clock source TA01MOD.TA01M[1:0]01 TA01MOD.TA01M[1:0]=01 00 01 10 11 TMRA0 match output TMRA0 overflow output T1 T16 T256 16-Bit Timer Mode Period select in 8-bit PWM mode 00 Reserved 01 10 11 (26-1) x clock source (27-1) x clock source (28-1) x clock source TMRA01 operating mode 00 Two 8-bit timers 01 10 11 16-bit timer 8-bit PPG 8-bit PWM generation (TMRA0) & 8-bit timer (TMRA1) Figure 11.5 Timer Mode Register TMP1941AF-116 2003-03-27 TMP1941AF TMRA23 Mode Register 7 TA23MOD (0xFFFF_F10C) Name Read/Write Reset Valu 0 0 0 PWM period 00: Reserved 01: 26-1 10: 27-1 11: 28-1 0 Operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit PPG 11: 8-bit PWM TA23M1 6 TA23M0 5 PWM21 4 PWM20 R/W 3 TA3CLK1 0 2 TA3CLK0 0 1 TA2CLK1 0 0 TA2CLK0 0 Function TMRA3 clock source 00: TA2TRG 01: T1 10: T16 11: T256 TMRA2 clock source 00: TA2IN 01: T1 10: T4 11: T16 TMRA2 clock source 00 External input (TA2IN) 01 10 11 T1 T4 T16 (Prescaler) (Prescaler) (Prescaler) TMRA3 clock source TA23MOD.TA23M[1:0]01 TA23MOD.TA23M[1:0]=01 00 01 10 11 TMRA2 match output T1 T16 T256 TMRA2 overflow output 16-Bit Timer Mode Period select in 8-bit PWM mode 00 Reserved 01 10 11 (26-1) x clock source (27-1) x clock source (28-1) x clock source TMRA23 operating mode 00 Two 8-bit timers 01 10 11 16-bit timer 8-bit PPG 8-bit PWM generation (TMRA2) & 8-bit timer (TMRA3) Figure 11.6 Timer Mode Register TMP1941AF-117 2003-03-27 TMP1941AF TMRA01 Timer Flip-Flop Control Register 7 TA1FFCR (0xFFFF_F105) Name Read/Write Reset Value 6 5 4 3 TAFF1C1 1 2 TAFF1C0 1 R/W 1 TAFF1IE 0 TA1FF toggle enable 0: Disable 1: Enable 0 TAFF1IS 0 TA1FF toggle trigger 0: TMRA0 1: TMRA1 Function 00: Toggles TA1FF. (software toggle) 01: Sets TA1FF to 1. 10: Clears TA1FF to 0. 11: Don't-care This field is always read as 11. Selects a signal to toggle Timer Flip-Flop 1 (TA1FF) (Don't-care in other than 8-bit timer mode) 0 1 Toggled by TMRA0 Toggled by TMRA1 Note: Bits 4 to 7 are read as undefined. Figure 11.7 TMRA01 Flip-Flop Control Register TMP1941AF-118 2003-03-27 TMP1941AF TMRA23 Flip-Flop Control Register 7 TA3FFCR (0xFFFF_F10D) Name Read/Write Reset Value 6 5 4 3 TAFF3C1 1 2 TAFF3C0 1 R/W 1 TAFF3IE 0 TA3FF toggle enable 0: Disable 1: Enable 0 TAFF3IS 0 TA3FF trigger 0: TMRA2 1: TMRA3 Function 00: Toggles TA3FF (software toggle). 01: Sets TA3FF to 1 10: Clears TA3FF to 0 11: Don't care This field is always read as 11. Selects a signal to toggle Timer Flip-Flop 3 (TA3FF) (Don't-care in other than 8-bit timer mode) 0 1 Toggled by TMRA2 Toggled by TMRA3 Note: Bits 4 to 7 are read as undefined values. Figure 11.8 TMRA23 Flip-Flop Control Register TMP1941AF-119 2003-03-27 TMP1941AF 11.4 Operating Modes 11.4.1 8-Bit Interval Timer Mode The TMRA0 and the TMRA1 can be independently programmed as 8-bit interval timers. Programming these timers should only be attempted when the timers are not running. (1) Generating Periodic Interrupts In the following example, the TMRA1 is used to accomplish periodic interrupt generation. First, stop the TMRA1 (if it is running). Then, set the operating mode, clock source and interrupt interval in the TA01MOD and TA1REG registers. Then, enable the INTTA1 interrupt and start the TMRA1. Example: Generating the INTTA1 interrupt at a 20-s interval (fc = 32 MHz) Clocking conditions: System clock: High-speed (fc) Prescaler clock: fperiph/4 (fperiph = fsys) MSB LSB TA01RUN TA01MOD 7 - 0 6 - 0 5 X X 4 X X 3 - 1 2 - 0 1 0 X 0 - X TA1REG IMC5LH 0 X 1 X 0 1 1 1 0 0 0 1 0 0 0 1 TA01RUN X = Don't care, - X X X - 1 1 - Stops and clears the TMRA1. Selects 8-bit interval timer mode and T1 as the clock source (which provides a 0.2s resolution @fc = 40 MHz.) Sets the time constant value in the TA1REG. 20 s / T1 = 80 (50H) Enables INTTA1 and sets the interrupt level to 5. INTTA1 must always be programmed to be rising-edge triggered. Starts the TMRA1. - = No change Refer to Table 11.2 when selecting a timer clock source. Note: The clock inputs to the TMRA0 and the TMRA1 can be one of the following: TMRA0: TA0IN input, T1, T4 or T16 TMRA1: Match-detect signal from the TMRA0, T1, T16 or T256 TMP1941AF-120 2003-03-27 TMP1941AF (2) Generating a SquareWave with a 50% Duty Cycle The 8-bit interval timer mode can be used to generate square-wave output. This is accomplished by toggling the timer flip-flop (TA1FF) periodically. The TA1FF state can be driven out to the TA1OUT pin. Both the TMRA0 and the TMRA1 can be used as square-wave generators. The following shows an example using the TMRA1. Example: Generating square-wave output with a 1.2-s period on the TA1OUT pin (fc = 40 MHz) Clocking conditions: System clock: High-speed (fc) High-speed clock gear: 1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) MSB LSB TA01RUN TA01MOD 7 - 0 0 X - - - 6 X 0 5 X X 4 X X 3 - 0 2 - 1 1 0 - 0 - - TA1REG TA1FFCR P7CR P7FC TA01RUN X = Don't care, 0 X - - X 0 X - - X 0 X - - X 0 1 - - - 0 0 - - 1 1 1 1 1 1 1 1 - - - Stops and clears the TMRA1. Selects 8-bit interval timer mode and T1 as the clock source (which provides a 0.2s resolution @fc = 40 MHz). Sets the time constant value in the TA1REG. 1.2 s / T1 / 2 = 3 Clears the TA1FF to 0 and selects the TMRA1 match-detect output as a toggle-trigger signal. Configures P71 as the TA1OUT output pin. Starts the TMRA1. - = No change T1 TA01RUN.TA1RUN Bits 7-2 UpCounter Bit 1 Bit 0 Comparator Timing Comparator Output (Match Detect) INTTA1 Up-Counter Clear 0 1 2 3 0 1 2 3 0 1 2 3 0 TA1FF TA1OUT 0.6 s @fc = 40 MHz Figure 11.9 Square-Wave Generation (50% Duty Cycle) TMP1941AF-121 2003-03-27 TMP1941AF (3) Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1 Set the TMRA01 in 8-bit interval timer mode. Select the TMRA0 comparator match-detect output (TA0TRG) as the clock source for the TMRA1. TMRA0 Comparator Match Output TMRA0 Up-Counter (when TA0REG = 5) TMRA1 Up-Counter (when TA1REG = 2) TMRA1 Match Output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 11.10 Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1 11.4.2 16-Bit Interval Timer Mode The TMRA0 and the TMRA1 are cascadable to form a 16-bit interval timer. The TMRA01 is put in 16-bit interval timer mode by programming the TA01M[1:0] field in the TA01MOD register to 01. In 16-bit interval timer mode, the TMRA1 is clocked by the counter overflow output from the TMRA0. In this mode, the TA1CLK[1:0] bits in the TA01MOD register are don't-cares. The clock input to the TMRA0 can be selected from an external clock and one of three prescalar outputs (see Table 11.2). Write the lower eight bits of a time constant value to the TA0REG and the upper eight bits to the TA1REG. Programming these registers should only be attempted when the timers are not running. Example: Generating the INTTA1 interrupt at a 0.2-second interval (fc = 40 MHz) Clocking conditions: System clock: High-speed (fc) High-speed clock gear: 1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) Under the above conditions, T16 has a period of 3.2 s @ 40 MHz. When T16 is used as the TMRA0 clock source, the required time constant value is calculated as follows: 0.2 s / 3.2 s = 62500 = H424H Thus, the TA1REG is to be set to F4H and the TA0REG to 24H. Every time the up-counter UC0 reaches the value in the TA0REG, the TMRA0 comparator generates a match-detect output, but the TMRA0 continues counting up. A match between the UC0 and the TA0REG does not cause an INTTA0 interrupt. Every time the up-counter UC1 reaches the value in the TA1REG, the TMRA1 comparator generates a match-detect output. When the TMRA0 and TMRA1 match-detect outputs are asserted simultaneously, both the up-counters (UC0 and UC1) are reset to 00H and an interrupt is generated on INTTA1. Also, if so enabled, the timer flip-flop (TA1FF) is toggled. Example: TA1REG = 04H and TA0REG = 80H Up-Counter Values 0000H (UC1/UC0) Match-Detect Signal from the TMRA0 Comparator INTTA1 Interrupt TA1OUT Timer Output Toggled 0080H 0180H 0280H 0380H 0480H Figure 11.11 Timer Output in 16-Bit Interval Timer Mode TMP1941AF-122 2003-03-27 TMP1941AF 11.4.3 8-Bit Programmable Pulse Generation (PPG) Mode The 8-bit PPG mode can be used to generate a square wave with any frequency and duty cycle, as shown below. The pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (TA1FF). This mode is supported by the TMRA0, but not by the TMRA1. The squarewave output is driven to the TA1OUT pin (which is multiplexed with P71). tH tL t Match Between TA0REG and Up-Counter 0 (INTTA0) Match Between TA1REG and Up-Counter 0 (INTTA1) TA1OUT TA0REG TA1REG Figure 11.12 8-Bit PPG Output Waveform In this mode, a square wave is generated by toggling the timer flip-flop (TA1FF). The TA1FF changes state every time a match is detected between the UC0 and the TA0REG and between the UC0 and the TA1REG. The TA0REG must be set to a value less than the TA1REG value. In this mode, the TMRA1 up-counter (UC1) can not be independently used; however, the TMRA1 must be put in a running state by setting the TA1RUN bit in the TA01RUN register to 1. Figure 11.3 shows a functional diagram of 8-bit PPG mode. TA1OUT Selector T1 T4 T16 TA01MOD.TA0CLK[1:0] Comparator Comparator 8-Bit Up-Counter (UC0) TA01RUN.TA0RUN TA1FF TA1FFCR.TAFF1IE Toggle INTTA0 INTTA1 Selector TA0REG-WR TA0REG Shift-Trigger Register Buffer TA1REG TA01RUN.TA0RDE Internal Data Bus Figure 11.13 Functional Diagram of 8-Bit PPG Mode TMP1941AF-123 2003-03-27 TMP1941AF In 8-bit PPG mode, if the double-buffering function is enabled, the TA0REG value can be changed dynamically by writing a new value into the register buffer. Upon a match between the TA1REG and the UC0, the TA0REG latches a new value from the register buffer. The TA0REG can be loaded with a new value upon every match, thus making it easy to generate a square wave with virtually any (and variable) duty cycle. Match Between TA0REG and Up-Counter 0 Match Between TA1REG and Up-Counter TA0REG (compare value) Register Buffer Q1 Q2 (Up-Counter = Q1) (Up-Counter = Q2) Shift-Trigger for Register Buffer Q2 Q3 Write to TA0REG (Register Buffer). Figure 11.14 Register Buffer Operation Example: Generating a 50-kHz square wave with a 25% duty cycle (fc = 40 MHz) 20 s Clocking conditions: System clock: High-speed (fc) High-speed clock gear: 1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) The time constant values to be loaded into the TA0REG and TA1REG are determined as follows: A 50-kHz waveform has a period of 20 s. Under the above clocking conditions, T1 has a 0.2-s resolution (@fc = 40 MHz). When T1 is used as the timer clock source, the TA1REG should be loaded with: 20 s / 0.2 s = 100 (64H) With a 25% duty cycle, the high pulse width is calculated as 20 s x 1/4 = 5 s. Thus, the TA0REG should be loaded with: 5 s / 0.2 s = 25 (19H) MSB LSB TA01RUN TA01MOD TA0REG TA1REG TA1FFCR 7 0 1 0 0 X 6 X 0 0 1 X 5 X X 0 1 X 4 X X 1 0 X 3 - X 1 0 0 2 0 X 0 1 1 1 0 0 0 0 1 0 0 1 1 0 X Stops and clears the TMRA0. Selects 8-bit PPG mode and T1 as the clock source. Writes 19H. Writes 64H. Sets the TA1FF to 1 and enables toggling. If these bits are set to 10, a low-going pulse is generated. P7CR P7FC TA01RUN X = Don't care, - - 1 - - X - - X - - X - - - - - 1 1 1 1 - - 1 Configures P71 as the TA1OUT output pin. Starts the TMRA0 and the TMRA1. - = No change TMP1941AF-124 2003-03-27 TMP1941AF 11.4.4 8-Bit PWM Generation Mode The TMRA0 can be used as a pulse-width modulated (PWM) signal generator with up to 8 bits of resolution. This mode is supported by the TMRA0, but not by the TMRA1. The PWM signal is driven out on the TA1OUT pin (which is multiplexed with P71). While the TMRA01 is in this mode, the TMRA1 is usable as an 8-bit interval timer. However, the TMRA0 match-detect output can not be used as a clock source for the TMRA1, and the timer output is not available for the TMRA1. The timer flip-flop toggles when the up-counter (UC0) reaches the TA0REG value and when a 2n-1 counter overflow occurs, where n is programmable to 6, 7 or 8 through the PWM[01:00] field in the TA01MOD register. The UC0 is reset to 00H upon a 2n-1 overflow. In 8-bit PWM generation mode, the following must be satisfied: (TA0REG value) < (2n-1 counter overflow value) (TA0REG value) 0 Match Between TA0REG and Up-Counter 0 2n-1 Overflow (INTTA0 Interrupt) TA1OUT tPWM (PWM Cycle) Figure11.15 8-Bit PWM Signal Generation Figure 11.16 shows a functional diagram of 8-bit PWM generation mode. TA01RUN.TA0RUN T1 T4 T16 Selector 8-Bit Up-Counter (UC0) Clear 2n-1 Overflow Control Overflow TA1OUT TA1FFCR. TAFF1IE TA1FF Toggle TA01MOD. PWM[01:00] TA01MOD.TA0CLK[1:0] Comparator INTTA0 TA0REG Selector Shift-Trigger Register Buffer TA0REG-WR TA01RUN.TA0RDE Internal Data Bus Figure 11.16 Functional Diagram of 8-Bit PWM Generation Mode TMP1941AF-125 2003-03-27 TMP1941AF In 8-bit PWM generation mode, if the double-buffering function is enabled, the TA0REG value (i.e., the duty cycle) can be changed dynamically by writing a new value into the register buffer. Upon a 2n-1 counter overflow, the TA0REG latches a new value from the register buffer. The TA0REG can be loaded with a new value upon every counter overflow, thus generating a PWM signal with variable duty cycle. Match Between TA0REG and Up-Counter 0 2 -1 Overflow TA0REG (Compare Value) Register Buffer Q1 Q2 n Up-Counter = Q1 Up-Counter = Q2 Shift into TA0REG Q2 Q3 Write to TA0REG (Register Buffer) Figure11.17 Register Buffer Operation Example: Generating a PWM signal as shown below on the TA1OUT pin (fc = 40 MHz) 14 s 25.4 s Clocking conditions: System clock: High-speed (fc) High-speed clock gear: 1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) Under the above conditions, T1 has a 0.2-s period (@fc = 40 MHz). 25.4 s / 0.2 s = 127 which is equal to 27 - 1. 14 s / 0.2 s = 70 = 46H Hence, the time constant value to be programmed into the TA0REG is 48H. MSB LSB TA01RUN TA01MOD TA0REG TA1FFCR P7CR P7FC TA01RUN X = Don't care, 7 - 1 0 X - - 1 6 X 1 1 X - - X 5 X 1 0 X - - X 4 X 0 0 X - - X 3 - - 0 1 - - - 2 - - 1 0 - - 1 1 - 0 1 1 1 1 - 0 0 1 0 X - - 1 Stops and clears the TMRA0. Selects 8-bit PWM mode (period = 27-1) and T1 as the clock source. Writes 46H. Clears the TA1FF to 0 and enables toggling. Configures P71 as the TA1OUT output pin. Starts the TMRA0. - = No change TMP1941AF-126 2003-03-27 TMP1941AF Table 11.3 PWM Period @fc = 40 MHz Prescaler Peripheral Clock Gear Clock Clock Value Source Select SYSCR1. SYSCR0. SYSCR1. GEAR[1:0] PRCK[1:0] FPSEL 00 (fperiph/4) 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 11 (fc/8) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 11 (fc/8) 01 (fperiph/2) 10 (fperiph) PWM Period 2 -1 6 2 -1 7 2 -1 8 T1 12.6 s 6.3 s 25.2 s 12.6 s 50.4 s 25.2 s 50.4 s 12.6 s 6.3 s 12.6 s T4 50.4 s 25.2 s 12.6 s 50.4 s 25.2 s T16 201.6 s 100.8 s 50.4 s 201.6 s 100.8 s T1 25.4 s 12.7 s 50.8 s 25.4 s 50.8 s T4 50.8 s 25.4 s T16 203.2 s 101.6 s T1 51 s 25.5 s 102 s 51 s 204 s 102 s 408 s 204 s 51 s 25.5 s 51 s T4 204 s 102 s 51 s 408 s 204 s 102 s 816 s 408 s 204 s 1632 s 816 s 408 s 204 s 102 s 51 s 204 s 102 s 51 s 204 s 102 s 204 s T16 816 s 408 s 204 s 1632 s 816 s 408 s 3264 s 1632 s 816 s 6528 s 3264 s 1632 s 816 s 408 s 204 s 816 s 408 s 204 s 816 s 408 s 204 s 816 s 408 s 204 s 101.6 s 406.4 s 100.8 s 403.2 s 203.2 s 812.8 s 101.6 s 406.4 s 50.8 s 203.2 s 201.6 s 806.4 s 101.6 s 406.4 s 1626 s 100.8 s 403.2 s 50.4 s 201.6 s 203.2 s 812.8 s 101.6 s 406.4 s 100.8 s 403.2 s 1613 s 203.2 s 812.8 s 3251 s 201.6 s 806.4 s 101.6 s 406.4 s 1626 s 100.8 s 403.2 s 50.4 s 25.2 s 12.6 s 50.4 s 25.2 s 12.6 s 50.4 s 25.2 s 50.4 s 201.6 s 100.8 s 50.4 s 201.6 s 100.8 s 50.4 s 201.6 s 100.8 s 50.4 s 201.6 s 100.8 s 50.4 s 25.4 s 12.7 s 25.4 s 203.2 s 812.8 s 101.6 s 406.4 s 50.8 s 25.4 s 50.8 s 25.4 s 50.8 s 203.2 s 101.6 s 203.2 s 101.6 s 203.2 s 101.6 s 203.2 s 101.6 s 101.6 s 406.4 s 101.6 s 406.4 s 101.6 s 406.4 s Note 1: The prescaler's output clock Tn must be selected so that Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the timer is running. Note 3: The -- character means "Don't use." TMP1941AF-127 2003-03-27 TMP1941AF 11.4.5 Operating Mode Summary Table 11.4 shows the settings for the TMRA01 for each of the operating modes. Table 11.4 Register Settings for Each Operating Mode Register Field Function TA01M[1:0] Interval Timer Mode 00 TA01MOD PWM[01:00] PWM Period TA1CLK[1:0] UC1 Clock Source Match output from UC0 T1, T16, T256 (00, 01, 10, 11) TA1FFCR TA0CLK[1:0] UC0 Clock Source External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) TAFF1IS Timer Flip-Flop Toggle-Trigger 0: UC0 output 1: UC1 output 8-Bit Timer x 2ch 16-Bit Timer Mode 01 8-Bit PPG x 1ch 8-Bit PWM x 1ch 8-Bit Timer x 1ch (Note) - = Don't care Note: 10 26 - 1, 27 - 1, 28 - 1 (01, 10, 11) T1, T16, T256 (01, 10, 11) 11 PWM output In 8-bit PWM generation mode, the UC1 can be used as an 8-bit timer. However, the match-detect output from the UC0 can not be used as a clock source for the UC1, and the timer output is not avaialble for the UC1. TMP1941AF-128 2003-03-27 TMP1941AF 12. 16-Bit Timer/Event Counters (TMRBs) The TMP1941AF has a 16-bit timer/event counter consisting of four identical channels (TMRB0-TMRB3). Each channel has the following three basic operating modes: * * * 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) mode Each channel has the capture capability used to latch the value of the counter. The capture capability allows: * * * Frequency measurement Pulse-width measurement Time difference measurement Figure 12.1 to Figure 12.4 are block diagrams of the TMRB0 to TMRB3. The main components of a TMRBn block are a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two comparators, capture control logic, a timer flip-flop and its associated control logic. Each channel is independently programmable and functionally equivalent except that the TMRB3 has no external clock/capture trigger inputs. Table 12.1 gives the pins and registers for the four channels. In the following sections, any references to the TMRB0 also apply to all the other channels. Table 12.1 Pins and Registers for the Four TMRBn Channels TMRB0 External clock / Capture trigger inputs TB0IN0 (Shared with P74) TB0IN1 (Shared with P75) TB0OUT0 (Shared with P76) TB0RUN (0xFFFF_F180) TB0MOD (0xFFFF_F182) TB0FFCR (0xFFFF_F183) TB0RG0L (0xFFFF_F188) TB0RG0H (0xFFFF_F189) TB0RG1L (0xFFFF_F18A) TB0RG1H (0xFFFF_F18B) TB0CP0L (0xFFFF_F18C) TB0CP0H (0xFFFF_F18D) TB0CP1L (0xFFFF_F18E) TB0CP1H (0xFFFF_F18F) TMRB1 TB1IN0 (Shared with P80) TB1IN1 (Shared with P81) TB1OUT0 (Shared with P82) TB1RUN (0xFFFF_F190) TB1MOD (0xFFFF_F192) TB1FFCR (0xFFFF_F193) TB1RG0L (0xFFFF_F198) TB1RG0H (0xFFFF_F199) TB1RG1L (0xFFFF_F19A) TB1RG1H (0xFFFF_F19B) TB1CP0L (0xFFFF_F19C) TB1CP0H (0xFFFF_F19D) TB1CP1L (0xFFFF_F19E) TB1CP1H (0xFFFF_F19F) TMRB2 TB2IN0 (Shared with P83) TB2IN1 (Shared with P84) TB2OUT (Shared with P85) TB2RUN (0xFFFF_F1A0) TB2MOD (0xFFFF_F1A2) TB2FFCR (0xFFFF_F1A3) TB2RG0L (0xFFFF_F1A8) TB2RG0H (0xFFFF_F1A9) TB2RG1L (0xFFFF_F1AA) TB2RG1H (0xFFFF_F1AB) TB2CP0L (0xFFFF_F1AC) TB2CP0H (0xFFFF_F1AD) TB2CP1L (0xFFFF_F1AE) TB2CP1H (0xFFFF_F1AF) TMRB3 External Pins Timer flip-flop output Timer Run register Timer Mode register Timer Flip-Flop Control register TB3OUT (Shared with P86) TB3RUN (0xFFFF_F1B0) TB3MOD (0xFFFF_F1B2H TB3FFCR (0xFFFF_F1B3) TB3RG0L (0xFFFF_F1B8) TB3RG0H (0xFFFF_F1B9) TB3RG1L (0xFFFF_F1BA) TB3RG1H (0xFFFF_F1BB) TB3CP0L (0xFFFF_F1BC) TB3CP0H (0xFFFF_F1BD) TB3CPIL (0xFFFF_FIBE) TB3CPIH (0xFFFF_FIBF) Registers (Addresses) Timer registers Capture registers TMP1941AF-129 2003-03-27 Internal Data Bus Run/ Clear TB0RUN. TB0PRUN Capture Register 0 TB0CP0H/L TB0MOD. TB0CP0 TB0RUN.TB0RUN TB0MOD.TB0CLE Counter Clock 16-Bit Up-Counter (UC0) Timer FlipFlop Control Capture Register 1 TB0CP1H/L Internal Data Bus Interrupt Output Register 0 Register 1 INTTB00 INTTB01 12.1 Block Diagrams Prescaler Clock Source: T0 2 T1 T4 T16 4 8 16 32 Timer Flip-Flop TB0FF0 TA1OUT (From TMRA01) TB0IN0 TB0IN1 TB0MOD. T1 TB0CPM[1:0] T4 T16 TB0MOD.TB0CLK[1:0] Selector Capture & External Interrupt Control Timer FlipFlop Output TB0OUT Figure 12.1 TMRB0 Block Diagram TMP1941AF-130 16-Bit Comparator (CP0) Match Detect 16-Bit Timer Register TB0RG0H/L TB0RUN. TB0RDE Register Buffer 0 Internal Data Bus Overflow Interrupt INTTBOF0 Match Detect 16-Bit Comparator (CP1) 16-Bit Timer Register TB0RG1H/L TMP1941AF Internal Data Bus 2003-03-27 Internal Data Bus Internal Data Bus Interrupt Output Register 0 Register 1 INTTB10 INTTB11 Prescalar Clock Source: T0 2 T1 Capture Register 0 TB1CP0H/L Capture & External Interrupt Control Selector TB1MOD. T1 TB1CPM[1:0] T4 T16 16-Bit Up-Counter (UC1) TB1MOD.TB1CLK[1:0] Match Detect Match Detect 16-Bit Comparator (CP1) Count Clock TB1RUN.TB1RUN TB1MOD.TB1CLE TB1MOD. TB1CP0 Timer FlipFlop Control Capture Register 1 TB1CP1H/L T4 T16 4 Run/ Clear TB1RUN. 8 16 32 TB1PRUN TA1OUT (From TMRA01) TB1IN0 TB1IN1 Timer Timer FlipFlip-Flop Flop Output TB1OUT TB1FF0 Figure 12.2 TMRB1 Block Diagram TMP1941AF-131 16-Bit Comparator (CP0) 16-Bit Timer Register TB1RG0H/L TB1RUN. TB1RDE Register Buffer 0 Internal Data Bus Overflow Interrupt INTTBOF1 16-Bit Timer Register TB1RG1H/L TMP1941AF Internal Data Bus 2003-03-27 Internal Data Bus Internal Data Bus Interrupt Output Register 0 Register 1 INTTB20 INTTB21 Prescalar Clock Source: T0 2 T1 Capture Register 0 TB2CP0H/L Capture & External Interrupt Control Selector Count Clock 16-Bit Up-Counter (UC2) TB2RUN.TB2RUN TB2MOD.TB2CLE TB2MOD. T1 TB2CPM[1:0] T4 T16 TB2MOD.TB2CLK[1:0] Match Detect TB2MOD. TB2CP0 Timer FlipFlop Control Capture Register 1 TB2CP1H/L T4 T16 4 Run/ Clear TB2RUN. 8 16 32 TB2PRUN TA1OUT (From TMRA01) TB2IN0 TB2IN1 Timer Timer FlipFlip-Flop Flop Output TB2OUT TB2FF0 Figure 12.3 TMRB2 Block Diagram TMP1941AF-132 16-Bit Comparator (CP0) 16-Bit Timer Register TB2RG0H/L TB2RUN. TB2RDE Register Buffer 0 Internal Data Bus Overflow Interrupt INTTBOF2 16-Bit Comparator (CP1) Match Detect 16-Bit Timer Register TB2RG1H/L TMP1941AF 2003-03-27 Internal Data Bus Internal Data Bus Internal Data Bus Interrupt Output Register 0 Register 1 INTTB30 INTTB31 Prescalar Clock Source: T0 2 T1 Capture Register 0 TB3CP0H/L TB3MOD. TB3CP0 TB3RUN.TB3RUN TB3MOD.TB3CLE Count Clock 16-Bit Up-Counter (UC3) Timer FlipFlop Control Capture Register 1 TB3CP1H/L T4 T16 4 Run/ Clear TB3RUN. 8 16 32 TB3PRUN TA1OUT (From TMRA01) Capture & External Interrupt Control TB3MOD. T1 TB3CPM[1:0] T4 T16 TB3MOD.TB3CLK[1:0] Match Detect Selector Timer Timer FlipFlip-Flop Flop Output TB3OUT TB3FF0 Figure 12.4 TMRB3 Block Diagram TMP1941AF-133 16-Bit Comparator (CP0) 16-Bit Timer Register TB3RG0H/L TB3RUN. TB3RDE Register Buffer 0 Internal Data Bus Overflow Interrupt INTTBOF3 16-Bit Comparator (CP1) Match Detect 16-Bit Timer Register TB3RG1H/L TMP1941AF Internal Data Bus 2003-03-27 TMP1941AF 12.2 Timer Components 12.2.1 Prescaler The TMRB0 has a 5-bit prescalar that slows the rate of a clocking source to the counter. The prescalar clock source (T0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG. The TB0RUN bit in the TB0RUN register allows the enabling and disabling of the TMRB0 prescalar. A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the prescalar. Prescalar output taps can be divide-by-2 (T1), divide-by-8 (T4) and divide-by-32 (T16). Table 12.2 shows prescalar output clock resolutions (@fc = 32 MHz). Table 12.2 Prescaler Output Clock Resolutions @fc = 40 MHz Peripheral Clock Select SYSCR1.FPSEL Clock Gear Value SYSCR1.GEAR[1:0] Prescaler Clock Source SYSCR0.PRCK[1:0] 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) Prescaler Output Clock Resolution T1 fc/2 (0.2 s) fc/2 (0.1 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.2 s) fc/2 (0.1 s) fc/2 (0.2 s) 5 3 3 T4 fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.8 s) 4 5 3 5 3 5 6 7 8 5 6 7 5 6 3 5 T16 fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (12.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 10 9 7 8 9 6 7 8 5 6 7 3 00 (fc) 2 4 4 01 (fc/2) 0 (gear) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 4 5 4 6 (25.6 s) 11 (fc/8) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 5 fc/2 (12.8 s) fc/2 (6.4 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) 5 6 7 5 6 7 5 6 7 5 6 7 8 3 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 2 4 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 4 11 (fc/8) 01 (fperiph/2) 10 (fperiph) Note 1: The prescaler's output clock Tn must be selected so that the relationship Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the timer is running. Note 3: The -- character means "Don't use." TMP1941AF-134 2003-03-27 TMP1941AF 12.2.2 Up-Counter (UC0) The TMRB0 contains a 16-bit binary up-counter, which is driven by a clock selected by the TB0CLK[1:0] field in the TB0MOD register. The clock input to the UC0 is either one of three prescalar outputs (1,T4, T16) or the external clock applied to the TB0IN0 pin. The clock input can be selected through the programming of the TB0CLK[1:0] field in the TB0MOD register. The TB0RUN bit in the TB0RUN register is used to start the UC0 and to stop and clear the UC0. The UC0 is cleared to 0000H, if so enabled, when it reaches the value in the TB0RG1H/L register. The TB0CLE bit in the TB0MOD register allows the user to enable and disable this clearing. If it is disabled, the UC0 acts as a free-running counter. An overflow interrupt (INTTBOF0) is generated upon a counter overflow. Note: Programming the TB0CLK[1:0] and TB0CLE bits in the TB0MOD register should only be attempted when the timer is not running. 12.2.3 Timer Registers (TB0RG0H/L and TB0RG1H/L) Each timer channel has two 16-bit timer registers containing a time constant. When the up-counter reaches the time constant value in each timer register, the associated comparator block generates a match-detect signal. Each of the timer registers (TB0RG0H/L, TB0RG1H/L) can be written with either a halfword-store instruction or a series of two byte-store instructions. When byte-store instructions are used, the loworder byte must be stored first, followed by the high-order byte. The 16-bit timer registers are often simply referred to as TB0RG0 and TB0RG1 without the H and L suffix. One of the two timer registers, TB0RG0, is double-buffered. The double-buffering function can be enabled and disabled through the programming of the TB0RDE bit in the TB0RUN: 0=disable, 1=enable. If double-buffering is enabled, the TB0RG0 latches a new time constant value from the register buffer. This takes place when a match is detected between the UC0 and the TB0RG1. Upon reset, the contents of the TB0RG0 and TB0RG1 are undefined; thus, they must be loaded with valid values before the timer can be used. A reset clears the TB0RUN.TB0RDE bit to 0, disabling the double-buffering function. To use this function, the TB0RUN.TB0RDE bit must be set to 1 after loading the TB0RG0 and TB0RG1 with time constants. When TB0RUN.TB0RDE=1, the next time constant can be written to the register buffer. Note 1: The TB0RG0 and the corresponding register buffer are mapped to the same address (0xFFFF_F188 thru 0xFFFF_F189). When TB0RUN.TB0RDE=0, a time constant value is written to both the TB0RG0 and the register buffer; when TB0RUN.TB0RDE=1, a time constant value is written only to the register buffer. Therefore, the double-buffering function should be disabled when writing an initial time constant to the timer register. Note 2: Programming the TB0RDE bit should only be attempted when the timer is not running. The following diagram shows the addresses of each timer register. TMP1941AF-135 2003-03-27 TMP1941AF TMRB0 TB0RG0 8 high-order bits 0xFFFF_F189 8 low-order bits 0xFFFF_F188 TB0RG1 8 high-order bits 0xFFFF_F18B 8 low-order bits 0xFFFF_F18A TMRB1 TB1RG0 8 high-order bits 0xFFFF_F199 8 low-order bits 0xFFFF_F198 TB1RG1 8 high-order bits 0xFFFF_F19B 8 low-order bits 0xFFFF_F19A TMRB2 TB2RG0 8 high-order bits 0xFFFF_F1A9 8 low-order bits 0xFFFF_F1A8 TB2RG1 8 high-order bits 0xFFFF_F1AB 8 low-order bits 0xFFFF_F1AA TMRB3 TB3RG0 8 high-order bits 0xFFFF_F1B9 8 low-order bits 0xFFFF_F1B8 TB3RG1 8 high-order bits 0xFFFF_F1BB 8 low-order bits 0xFFFF_F1BA The Timer registers are write-only registers and cannot be read. 12.2.4 Capture Registers (TB0CP0H/L and TB0CP1H/L) The capture registers are 16-bit registers used to latch the value of the up-counter (UC0). Each of the capture registers can be read with either a halfword-load instruction or a series of two byte-load instructions. When byte-load instructions are used, the low-order byte must be read first, followed by the high-order byte. The 16-bit capture registers are often simply referred to as TBnCP and TBnCP1 without the H and L suffix. The following diagram shows the addresses of each capture register. TMP1941AF-136 2003-03-27 TMP1941AF TMRB0 TB0CP0 8 high-order bits 0xFFFF_F18D 8 low-order bits 0xFFFF_F18C TB0CP1 8 high-order bits 0xFFFF_F18F 8 low-order bits 0xFFFF_F18E TMRB1 TB1CP0 8 high-order bits 0xFFFF_F19D 8 low-order bits 0xFFFF_F19C TB1CP1 8 high-order bits 0xFFFF_F19F 8 low-order bits 0xFFFF_F19E TMRB2 TB2CP0 8 high-order bits 0xFFFF_F1AD 8 low-order bits 0xFFFF_F1AC TB2CP1 8 high-order bits 0xFFFF_F1AF 8 low-order bits 0xFFFF_F1AE TMRB3 TB3CP0 8 high-order bits 0xFFFF_F1BD 8 low-order bits 0xFFFF_F1BC TB3CP1 8 high-order bits 0xFFFF_F1BF 8 low-order bits 0xFFFF_F1BE The Capture registers are read-only registers and cannot be written by software. 12.2.5 Capture Control Logic The capture control logic controls the capture of an up-counter (UC0) value into the capture registers (TB0CP0 and TB0CP1). The TB0CPM[1:0] field in the TB0MOD register selects a capture trigger input to be sensed by the capture control logic. Futhermore, a counter value can be captured under software control; a write of 0 to the TB0MOD.TB0CP0 bit causes the current UC0 value to be latched into the TB0CP0. To use the capture capability, the prescalar must be running (i.e., TB0RUN.TB0PRUN=1). Note 1: Reading the eight low-order bits of a capture register disables the capture capability. Reading the eight high-order bits thereafter re-enables the capture capability. The reading of a whole capture register should be completed during an interval between active transitions on the defined capture trigger input. Note 2: Don't stop the timer after only reading the eight low-order bits of a capture register. If this is done, the capture capability continues to remain in the disabled state even after the timer is restarted. Note 3: When the TB0IN0 pin is selected as a capture trigger input, it can not function as a timer clock source. TMP1941AF-137 2003-03-27 TMP1941AF 12.2.6 Comparators (CP0 and CP1) The TMRB0 contains two 16-bit comparators. The CP0 block compares the output of the up-counter (UC0) with a time constant value in the TB0RG0. The CP1 block compares the output of the UC0 with a time constant value in the TB0RG1. When a match is detected, an interrupt (INTTB00/INTTB01) is generated. 12.2.7 Timer Flip-Flop (TB0FF0) The timer flip-flop (TB0FF0) is toggled, if so enabled, upon assertion of match-detect signals from the comparators and latch signals from the capture control logic. The toggling of the TB0FF0 can be enabled and disabled through the programming of the TB0C1T1, TB0C0T1, TB0E1T1 and TB0E0T1 bits in the TB0FFCR register. Upon reset, the TB0FF0 assumes an undefined state. The TB0FF0 can be initialized to 1 or 0 by writing 01 or 10 to the TB0FF0C[1:0] field in the TB0FFCR. A write of 01 to this field sets the TB0FF0; a write of 10 to this field clears the TB0FF0. Additionally, a write of 00 causes the TB0FF0 to be toggled to the opposite value. The value of the TB0FF0 can be driven onto the TB0OUT pin, which is multiplxed with P76. The Port 7 registers (P7CR and P7FC) must be programmed to configure the P76/TB0OUT pin as TB0OUT. Note: Programming the TB0FF0C[1:0] field should only be attempted when the timer is not running. TMP1941AF-138 2003-03-27 TMP1941AF 12.3 Register Description TMRB0 Run register 7 Name TB0RUN (0xFFFF_F180) Read/Write Reset Value TB0RDE R/W 0 Double Buffering 0: Disable 1: Enable 6 R/W 0 Must be written as 0. 5 4 3 I2TB0 R/W 0 IDLE 0: Off 1: On 2 TB0PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run 1 0 TB0RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run Function I2TB0: Timer on/off in IDLE mode TB0PRUN: Prescaler TB0RUN: TMRB0 Note: Bits 1, 4 and 5 are read as undefined. TMRB1 Run register 7 TB1RUN (0xFFFF_F190) Name Read/Write Reset Value TB1RDE R/W 0 Double Buffering 0: Disable 1: Enable 6 R/W 0 Must be written as 0. 5 4 3 I2TB1 R/W 0 IDLE 0: Off 1: On 2 TB1PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run 1 0 TB1RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run Function I2TB1: Timer on/off in IDLE mode TB1PRUN: Prescaler TB1RUN: TMBR1 Note: Bits 1, 4 and 5 are read as undefined. Figure 12.5 Timer Run Registers TMP1941AF-139 2003-03-27 TMP1941AF TMRB2 Run register 7 TB2RUN (0xFFFF_F1A0) Name Read/Write Reset Value TB2RDE R/W 0 Double Buffering 0: Disable 1: Enable 6 R/W 0 Must be written as 0. 5 4 3 I2TB2 R/W 0 IDLE 0: Off 1: On 2 TB2PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run 1 0 TB2RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run Function I2TB2: Timer on/off in IDLE mode TB2PRUN: Prescaler TB2RUN: TMRB2 Note: Bits 1, 4 and 5 are read as undefined. TMRB3 Run register 7 TB3RUN (0xFFFF_F1B0) Name Read/Write Reset Value TB3RDE R/W 0 Double Buffering 0: Disable 1: Enable 6 R/W 0 Must be written as 0. 5 4 3 I2TB3 R/W 0 IDLE 0: Off 1: On 2 TB3PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run 1 0 TB3RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run Function I2TB3: Timer on/off in IDLE mode TB3PRUN: Prescaler TB3RUN: TMRB3 Note: Bits 1, 4 and 5 are read as undefined. Figure 12.6 Timer Run Registers TMP1941AF-140 2003-03-27 TMP1941AF TMRB0 Mode Register 7 TB0MOD (0xFFFF_F182) Name Read/Write Reset Value 0 R/W 0 Must be written as 00. Function 6 5 TB0CP0 W* 1 Software capture 0: Capture 1: Don't care 4 3 2 TB0CLE R/W 0 UC0 clear control 0: Disable 1: Enable 1 TB0CLK1 0 0 TB0CLK0 0 TB0CPM1 TB0CPM0 0 0 Capture triggers 00: Disabled 01: TB0IN0TB0IN1 10: TB0IN0TB0IN0 11: TA1OUTTA1OUT TMRB0 clock source 00: TB0IN0 input 01: T1 10: T4 11: T16 Up-counter (UC0) clear control 0 Disabled 1 UC0 is reset upon a match with TB0RG1. Capture triggers 00 Capture disabled 01 10 11 Latches UC0 value into TB0CP0 at rising edges of TB0IN0 Latches UC0 value into TB0CP1 at rising edges of TB0IN1. Latches UC0 value into TB0CP0 at rising edges of TB0IN0. Latches UC0 value into TB0CP1 at falling edges of TB0IN0. Latches UC0 value into TB0CP0 at rising edges of TA1OUT. Latches UC0 value into TB0CP1 at falling edges of TA1OUT. Software capture 0 Latches UC0 value into TB0CP0. 1 Don't care Figure 12.7 TMRB0 Mode Register TMP1941AF-141 2003-03-27 TMP1941AF TMRB1 Mode Register 7 TB1MOD (0xFFFF_F192) Name Read/Write Reset Value 0 R/W 0 Must be written as 00. Function 6 5 TB1CP0 W* 1 Software capture 0: Capture 1: Don't care 4 3 2 TB1CLE R/W 0 UC1 clear control 0: Disable 1: Enable 1 TB1CLK1 0 0 TB1CLK0 0 TB1CPM1 TB1CPM0 0 0 Capture triggers 00: Disabled 01: TB1IN0TB1IN1 10: TB1IN0TB1IN0 11: TA1OUTTA1OUT TMRB1 clock source 00: TB1IN0 input 01: T1 10: T4 11: T16 Up-counter (UC1) clear control 0 Disabled 1 UC1 is reset upon a match with TB1RG1. Capture triggers 00 Capture disabled 01 10 11 Latches UC1 value into TB1CP0 at rising edges of TB1IN0 Latches UC1 value into TB1CP1 at rising edges of TB1IN1. Latches UC1 value into TB1CP0 at rising edges of TB1IN0. Latches UC1 value into TB1CP1 at falling edges of TB1IN0. Latches UC1 value into TB1CP0 at rising edges of TA1OUT. Latches UC1 value into TB1CP1 at falling edges of TA1OUT. Software capture 0 Latches UC1 value into TB1CP0. 1 Don't care Figure 12.8 TMRB1 Mode Register TMP1941AF-142 2003-03-27 TMP1941AF TMRB2 Mode Register 7 Name TB2MOD (0xFFFF_F1A2) Read/Write Reset Value R/W 0 0 Must be written as 00. Function 6 5 TB2CP0 W* 1 Software capture 0: Capture 1: Don't care 4 3 2 TB2CLE R/W 0 UC2 clear control 0: Disable 1: Enable 1 TB2CLK1 0 0 TB2CLK0 0 TB2CPM1 TB2CPM0 0 0 Capture triggers 00: Disabled 01: TB2IN0TB2IN1 10: TB2IN0TB2IN0 11: TA1OUTTA1OUT TMRB2 clock source 00: TB2IN0 input 01: T1 10: T4 11: T16 Up-counter (UC2) clear control 0 Disabled 1 UC2is reset upon a match with TB2RG1. Capture Triggers 00 01 10 11 Capture disabled Latches UC2 value into TB2CP0 at rising edges of TB2IN0. Latches UC2 value into TB2CP1 at rising edges of TB2IN1. Latches UC2 value into TB2CP0 at rising edges of TB2IN0. Latches UC2 value into TB2CP1 at falling edges of TB2IN0. Latches UC2 value into TB2CP0 at rising edges of TA1OUT. Latches UC2 value into TB2CP1 at falling edges of TA1OUT. Capture triggers Software capture 0 Latches UC2 value into TB2CP0. 1 Don't care Figure 12.9 TMRB2 Mode Register TMP1941AF-143 2003-03-27 TMP1941AF TMRB3 Mode Register 7 Name TB3MOD (0xFFFF_F1B2) Read/Write Reset Value R/W 0 0 Must be written as 00. Function 6 5 TB3CP0 W* 1 Software capture 0: Capture 1: Don't care 4 3 2 TB3CLE R/W 0 UC3 clear control 0: Disable 1: Enable 1 TB3CLK1 0 0 TB3CLK0 0 TB3CPM1 TB3CPM0 0 0 Capture triggers 00: Disabled 01: Disabled 10: Disabled 11: TA1OUTTA1OUT TMRB3 clock source 00: TB3IN0 input 01: T1 10: T4 11: T16 Up-counter (UC3) clear control 0 Disabled 1 UC3 is reset upon a match with TB3RG1. Capture triggers 00 Capture disabled 01 10 11 Capture disabled Capture disabled Latches UC3 value into TB3CP0 at rising edges of TA1OUT. Latches UC3 value into TB3CP1 at falling edges of TA1OUT. Software capture 0 Latches UC3 value into TB3CP0. 1 Don't care Figure 12.10 TMRB3 Mode Register TMP1941AF-144 2003-03-27 TMP1941AF TMRB0 Timer Flip-Flop Control Register 7 Name TB0FFCR (0xFFFF_F183) Read/Write Reset Value Function W* 1 1 0 0 Must be written as 11. 6 5 TB0C1T1 4 TB0C0T1 R/W 3 TB0E1T1 0 2 1 W* 0 TB0E0T1 TB0FF0C1 TB0FF0C0 0 1 1 TB0FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC0 UC0 TB0CP1 TB0CP0 UC0 = TB0RG1 UC0 = TB0RG0 * This field is always read as 11. TB0FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. Timer flip-flop (TB0FF0) control 00 Toggles TB0FF0. (software toggle) 01 10 11 Sets TB0FF0 to 1. Clears TB0FF0 to 0. Don't care (read as 11) When UC0 reaches TB0RG0 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC0 reaches TB0RG1 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC0 value is latched into TB0CP0 (see Note). 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC0 value is latched into TB0CP1. 0 Toggle-trigger disabled 1 Toggle-trigger enabled Note: Capturing the counter value into TB0CP0 via a software capture also generates a toggle-trigger to TB0FF0. Figure 12.11 TMRB0 Timer Flip-Flop Control Register TMP1941AF-145 2003-03-27 TMP1941AF TMRB1 Timer Flip-Flop Control Register 7 Name TB1FFCR (0xFFFF_F193) Read/Write Reset Value Function W* 1 1 0 0 Must be written as 11. 6 5 TB1C1T1 4 TB1C0T1 R/W 3 TB1E1T1 0 2 1 W* 0 TB1E0T1 TB1FF0C1 TB1FF0C0 0 1 1 TB1FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC1 TB1CP1 UC1 TB1CP0 UC1 = TB1RG1 UC1 = TB1RG0 * This field is always read as 11. TB1FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. Timer flip-flop (TB1FF0) control 00 Toggles TB1FF0. (software toggle) 01 10 11 Set TB1FF0 to 1. Clears TB1FF0 to 0. Don't care (read as 11) When UC1 reaches TB1RG0 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC1 reaches TB1RG1 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC1 value is latched into TB1CP0 (see Note). 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC1 value is latched into TB1CP1. 0 Toggle-trigger disabled 1 Toggle-trigger enabled Note: Capturing the counter value into TB1CP0 via a software capture also generates a toggle-trigger to TB1FF0. Figure 12.12 TMRB1 Timer Flip-Flop Control Register TMP1941AF-146 2003-03-27 TMP1941AF TMRB2 Timer Flip-Flop Control Register 7 Name TB2FFCR (0xFFFF_F193) Read/Write Reset Value Function W* 1 1 0 0 Must be written as 11. 6 5 TB2C1T1 4 TB2C0T1 R/W 3 TB2E1T1 0 2 1 W* 0 TB2E0T1 TB2FF0C1 TB2FF0C0 0 1 1 TB2FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC2 TB2CP1 UC2 TB2CP0 UC2 = TB2RG1 UC2 = TB2RG0 * This field is always read as 11. TB2FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. Timer flip-flop (TB2FF0) control 00 Toggles TB2FF0. (software toggle) 01 10 11 Set TB2FF0 to 1. Clears TB2FF0 to 0. Don't care (read as 11) When UC2 reaches TB2RG0 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC2 reaches TB2RG1 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC2 value is latched into TB2CP0 (see Note). 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC2 value is latched into TB2CP1. 0 Toggle-trigger disabled 1 Toggle-trigger enabled Note: Capturing the counter value into TB2CP0 via a software capture also generates a toggle-trigger to TB2FF0. Figure 12.13 TMRB2 Timer Flip-Flop Control Register TMP1941AF-147 2003-03-27 TMP1941AF TMRB3 Timer Flip-Flop Control Register 7 Name TB3FFCR (0xFFFF_F1B3) Read/Write Reset Value Function W* 1 1 0 0 Must be written as 11. 6 5 TB3C1T1 4 TB3C0T1 R/W 3 TB3E1T1 0 2 1 W* 0 TB3E0T1 TB3FF0C1 TB3FF0C0 0 1 1 TB3FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC3 TB3CP1 UC3 TB3CP0 UC3 = TB3RG1 UC3 = TB3RG0 * This field is always read as 11. TB3FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. Timer flip-flop (TB3FF0) control 00 Toggles TB3FF0. (software toggle) 01 10 11 Set TB3FF0 to 1. Clears TB3FF0 to 0. Don't care (read as 11) When UC3 reaches TB3RG0 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC3 reaches TB3RG1 value. 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC3 value is latched into TB3CP0 (see Note). 0 Toggle-trigger disabled 1 Toggle-trigger enabled When UC3 value is latched into TB3CP1. 0 Toggle-trigger disabled 1 Toggle-trigger enabled Note: Capturing the counter value into TB3CP0 via a software capture also generates a toggle-trigger to TB3FF0. Figure 12.14 TMRB3 Timer Flip-Flop Control Register TMP1941AF-148 2003-03-27 TMP1941AF 12.4 Operating Modes 12.4.1 16-Bit Interval Timer Mode In the following example, the TMRB0 is used to accomplish periodic interrupt generation. The interval time is set in Timer Register 1 (TB0RG1), and the INTTB01 interrupt is enabled. TB0RUN IMC7LL IMC7LH TB0FFCR TB0MOD TB0RG1 TB0RUN X = Don't care, 7 0 X X 1 0 * * 0 5 X 1 1 0 1 (** ** ** 0X 6 0 X X 1 0 43 X- 10 10 00 00 = 01, ** ** X- 210 0X0 000 100 011 1** 10, 11) *** *** 1X1 Stops the TMRB0. Enables INTTB01, sets its priority level to 4 and disables INTTB00. Disables the timer flip-flop toggle-trigger. Selects a prescalar output clock as the timer clock source and disables the capture function. Sets the interval time. (16 bits) Starts the TMRB0. - = No change 12.4.2 16-Bit Event Counter Mode This mode is used to count events by interpreting the rising edges of the external counter clock (TB0IN0) as events. The up-counter (UC0) counts up on each rising clock edge. The counter value is be latched into a capture register under software control. To determine the number of events (i.e., cycles) counted, the value in the capture register must be read. TB0RUN P7CR P7FC IMC7LL IMC7LH TB0FFCR TB0MOD TB0RG1 TB0RUN X = Don't care, Note: 7 0 - - X X 1 0 * 0 6 0 - - X X 1 0 * 0 5 X - - 1 1 0 1 * X 4 X 0 1 1 1 0 0 * X 3 - - - 0 0 0 0 * - 2 0 - - 0 1 0 1 * 1 1 X - - 0 0 1 0 * X 0 0 - - 0 0 1 0 * 1 Stops the TMRB0. Configures the P74 pin for input mode. Enables INTTB01 (interrupt level = 4) and disables INTTB00. Disables the timer flip-flop toggle-trigger. Selects the TB0IN0 input as the timer clock source. Sets a count value (16 bits). Starts the TMRB0. - = No change Even when the timer is used for event counting, the prescaler must be programmed to run (i.e., the TB0RUN.TB0PRUN bit must be set to 1). TMP1941AF-149 2003-03-27 TMP1941AF 12.4.3 16-Bit Programmable Pulse Generation (PPG) Mode The 16-bit PPG mode can be used to generate a square wave with any frequency and duty cycle. The pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (TB0FF0). A square wave is generated by toggling the timer flip-flop every time the up-counter UC0 reaches the values in each timer register (TB0RG0 and TB0RG1). The square-wave output is driven to the TB0OUT pin. In this mode, the following relationship must be satisfied: (TB0RG0 value) < (TB0RG1 value) TB0RG0 Match (INTTB00 Interrupt) TB0RG1 Match (INTTB01 Interrupt) TB0OUT Pin Figure 12.15 PPG Output Waveform Note: Stop the timer when changing the duty cycle in PPG mode. (Don't use the double-buffering function for this purpose.) TMP1941AF-150 2003-03-27 TMP1941AF Figure 12.16 shows a functional diagram of 16-bit PPG mode. TB0RUN.TB0RUN TB0OUT (PPG output) 16-Bit Up-Counter UC0 Clear F/F (TB0FF0) Selector TB0IN0 T1 T4 T16 Match 16-Bit Comparator 16-Bit Comparator Register Buffer 0 TB0RG1 Internal Data Bus Figure 12.16 Functional Diagram of 16-Bit PPG Mode The following is an example of running the timer in 16-bit PPG mode. 7 0 * * X 6 0 * * X 5 X * * 0 4 X * * 0 3 - * * 1 2 0 * * 1 1 X * * 1 0 0 * * 0 TB0RUN TB0RG0 TB0RG1 TB0FFCR Disables the TB0RG0 double-buffering and stops the TMRB0. Defines the duty cycle (16 bits). Defines the cycle period (16 bits). Toggles the TB0FF0 when a match is detected between UC0 and TB0RG0 and between UC0 and TB0RG1. Initially clears the TB0FF0 to 0. Selects a prescaler output clock as the timer clock source and disables the capture function. Configures the P76 pin as TB1OUT. Starts the TMRB0. TB0MOD P7CR P7FC TB0RUN X = Don't care, 0 - - 1 1 (** 1- 1- 0X 0 00 = 01, -- -- X- 1** 10, 11) --- --- 1X1 - = No change TMP1941AF-151 2003-03-27 TMP1941AF 12.4.4 Timing and Measurement Functions Using the Capture Capability The capture capability of the TMRBn provides versatile timing and measurement functions, including the following: * * * * One-shot pulse generation using an external trigger pulse Frequency measurement Pulse width measurement Time difference measurement (1) One-Shot Pulse Generation Using an External Trigger Pulse The TMRBn can be used to produce a one-time pulse as follows. The 16-bit up-counter (UC0) is programmed to function as a free-running counter, clocked by one of the prescalar outputs. The TB0IN0 pin is used as an active-high external trigger pulse input for latching the counter value into Capture Register 0 (TB0CP0). The TB0IN0 pin is shared with P74 and INT5. The Interrupt Controller (INTC) must be programmed to generate an INT5 interrupt upon detection of a rising edge on the TB0IN0/INT5 pin. A one-shot pulse has a delay and width controlled by the values stored in the timer registers (TB0RG0 and TB0RG1). Programming the TB0RG0 and TB0RG1 is the responsibility of the INT5 interrupt handler. The TB0RG0 is loaded with the sum of the TB0CP0 value (c) plus the pulse delay (d) - i.e., (c) + (d). The TB0RG1 is loaded with the sum of the TB0RG0 value plus the pulse width (p) - i.e., (c) + (d) + (p). Next, the TB0E1T1 and TB0E0T1 bits in the Timer Flip-Flop Control register (TB0FFCR) are set to 11, so that the timer flip-flop (TB0FF0) will toggle when a match is detected between the UC0 and the TB0RG0 and between the UC0 and the TB0RG1. With the TB0FF0 toggled twice, a one-shot pulse is produced. Upon a match between the UC0 and the TB0RG1, the TMRB0 generates the INTTB01 interrupt, which must disable the toggle-trigger for the TB0FF0. Figure 12.17 depicts one-shot pulse generation, with annotations showing (c), (d) and (p). The counter is free-running. Counter Clock (Internal Clock) c TB0IN0 Input Pin (External Trigger Pulse) The UC0 value is latched into TB0CP1. INT5 is generated. TB0RG0 Match Toggle is enabled. Toggle is disabled for a capture into TB0CP1. TB0OUT (Timer Output) Pin Delay (d) Pulse Width (p) Toggle is enabled. INTTB01 is generated. c+d c+d+p TB0RG1 Match Figure 12.17 One-Shot Pulse Generation (with a Delay) TMP1941AF-152 2003-03-27 TMP1941AF Example: Generating a one-shot pulse with a width of 2 ms and a delay of 3 ms on assertion of an external trigger pulse on the TB0IN0 pin Clocking conditions: System clock: High-speed (fc) High-speed clock gear: x1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) Settings in the main routine 7 TB0MOD TB0FFCR X X 6 X X 5 1 0 4 0 0 3 1 0 2 0 0 1 0 1 0 1 0 Places the counter in free-running mode. Selects T1 as the counter clock source. Latches UC0 value into TB0CP0 at rising edges of the TB0IN0 input. Clears TB0FF0 to 0. Disables the toggle-trigger for TB0FF0. P7CR P7FC IMC2HL IMC7LL IMC7LH TB0RUN - - X X X - 1 1 X X X 0 - - 1 1 1 X - - 1 1 1 X - - 0 0 0 - - - 1 0 0 1 - - 0 0 0 X - - 0 0 0 1 Configures the P76 pin as TB1OUT. Enables INT5 and disables INTTB00 and INTTB01. Starts the TMRB0. Settings in INT5 TB0RG0 TB0RG1 TB0FFCR TB0CP0 + 3ms/T1 TB0RG0 + 2ms/T1 X X - - 1 1 - - Enables the TB0FF0 toggle-trigger for TB0RG0 and TB0RG1 matches. IMC7LH X X 1 1 0 1 0 0 Enables INTTB01. Settings in INTTB01 TB0FFCR X X - - 0 0 - - Disables the TB0FF0 toggle-trigger for TB0RG0 and TB0RG1 matches. IMC7LH X = Don't care, X X 1 1 0 0 0 0 Disables INTTB01. - = No change TMP1941AF-153 2003-03-27 TMP1941AF If no delay is necessary, enable the TB0FF0 toggle-trigger for a capture of the UC0 value into the TB0CP0. Use the INT5 interrupt to load the TB0RG1 with a sum of the TB0CP0 value (c) plus the pulse width (p) and to enable the TB0FF0 toggle-trigger for a match between the UC0 and TB0RG1 values. A match generates the INTTB01 interrupt, which then is to disable the TB0FF0 toggle-trigger. Counter Clock (Prescaler Output Clock) c TB0IN0 Input (External Trigger Pulse) c+p The UC0 value is latched into TB0CP0. INT5 is generated. INTTB01 is generated. Toggle is enabled. TB0OUT (Timer Output) Pin Toggle is enabled for a capture into TB0CP0. Pulse Width (p) The UC0 value is latched into TB0CP1. TB0RG1 Match Toggle is left disabled for a capture into TB0CP1 so that it will not be toggled. Figure 12.18 One-Shot Pulse Generation (without a Delay) (2) Frequency Measurement The capture function can be used to measure the frequency of an external clock. Frequency measurement requires a 16-bit TMRBn channel running in event counter mode and the 8-bit TMRA01. The timer flip-flop (TA1FF) in the TMRA01 is used to define the duration during which a measurement is taken. Select the TB0IN0 pin as the clock source for the TMRB0. Set the TB0CPM[1:0] field in the TB0MOD to 11 to select the TA1FF output signal from the TMRA01 as a capture trigger input. This causes the TMRB0 to latch the 16-bit up-counter (UC0) value into Capture Register 0 (TB0CP0) on the low-to-high transition of the TA1FF and into Capture Register 1 (TB0CP1) on the next high-to-low transition of the TA1FF. Either the INTTA0 or INTTA1 interrupt generated by the 8-bit timer can be used to make a frequency calculation. Counter Clock (TB0IN0 Input) TA1OUT Capture into TB0CP0 Capture into TB0CP1 INTTA0/INTTA1 C1 C2 C1 C2 C1 C2 Figure 12.19 Frequency Measurement For example, if the TA1FF of the 8-bit timer is programmed to be at logic 1 for a period of 0.5 seconds and the difference between the values captured into the TB0CP0 and TB0CP1 is 100, then the TB0IN0 frequency is calculated as 100 / 0.5 s = 200 Hz. TMP1941AF-154 2003-03-27 TMP1941AF (3) Pulse Width Measurement The capture function can be used to measure the pulse width of an external clock. The external clock is applied to the TB0IN0 pin. The up-counter (UC0) is programmed to operate as a freerunning counter, clocked by one of the prescalar outputs. The capture function is used to latch the UC0 value into Capture Register 0 (TB0CP0) at the clock rising edge and into Capture Register 1 (TB0CP1) at the next clock falling edge. The TB0IN0 input is shared with the INT5 input; the Interrupt Controller (INTC) is to be programmed to generate the INT5 interrupt at the falling edge of the TB0IN0 input. Multplying the counter clock period by the difference between the values captured into the TB0CP0 and TB0CP1 gives the high pulse width of the TB0IN0 clock. For example, if the prescalar output clock has a period of 0.5 s and the difference between the TB0CP0 and TB0CP1 is 100, the high pulse width is calculated as 0.5 s x 100 = 50 s. Prescaler Output Clock C1 TB0IN0 Input (External Clock) Capture into TB0CP0 Capture into TB0CP1 C1 C2 C1 C2 C2 INT5 Figure 12.20 Pulse Width Measurement The low pulse width can be measured by the second INT5 interrupt. This is accomplished by multiplying the counter clock period by the difference between the TB0CP0 value at the first C2 and the TB0CP1 value at the second C1. TMP1941AF-155 2003-03-27 TMP1941AF (4) Time Difference Measurement The capture function can be used to measure the time difference between two event occurrences. The 16-bit up-counter (UC0) is programmed to operate as a free-running counter. The UC0 value is latched into Capture Register 0 (TB0CP0) on the rising edge of TB0IN0. The TB0IN0 pin is shared with INT5; the Interrupt Controller (INTC) is to be programmed to generate the INT5 interrupt at this time. Then, the UC0 value is latched into Capture Register 1 (TB0CP1) on the rising edge of TB0IN1. The TB0IN1 pin is shared with INT6; the INTC is to be programmed to generate the INT6 interrupt at this time. The time difference between the two events that occurred on the TB0IN0 and TB0IN1 pins is calculated by multiplying the counter clock period by the difference between the TB0CP1 and TB0CP0 values. Prescaler Output Clock C1 TB0IN0 Input TB0IN1 Input Capture into TB0CP0 C2 Capture into TB0CP1 INT5 INT6 Time Difference Figure 12.21 Time Difference Measurement TMP1941AF-156 2003-03-27 TMP1941AF 13. Serial I/O (SIO) The TMP1941AF serial I/O contains four channels named SIO0, SIO1, SIO3 and SIO4 (there is not SIO2). The SIO0 and SIO1 provide Universal Asynchronous Receiver/Transmitter (UART) mode and synchronous I/O Interface mode. The SIO2 and SIO3 provide only UART mode. * I/O Interface Mode Mode 0: Transmits/receives a serial clock (SCLK) as well as data streams for a synchronous clock mode of operation. * UART mode Mode 1: 7 data bits Mode 2: 8 data bits Mode 3: 9 data bits In Mode 1 and Mode 2, each character can include a parity bit. In Mode 3, an SIO channel operates in a wakeup mode for multidrop applications in which a master station is connected to several slave stations through a serial link. Figure 13.2 to Figure 13.5 are block diagrams of each SIO channel. The main components of an SIO channel are a clock prescalar, a serial clock generator, a receive buffer, a receive controller, a transimit buffer and a transmit controller. Each SIO channel is independently programmable, and functionally equivalent with a few exceptions listed below. In the following sections, any references to the SIO0 also apply to the other channels. Table 13.1 Differences Between the SIO Channels SIO0 Pins Used TXD0 (P90) RXD0 (P91) CTS0 /SCLK0 (P92) Available SIO1 TXD1 (P93) RXD1 (P94) CTS 1 /SCLK1 (P95) Available SIO3 TXD3 (P70) RXD3 (P71) Not available SIO4 TXD4 (P72) RXD4 (P73) Not available I/O Interface Mode TMP1941AF-157 2003-03-27 TMP1941AF * Mode 0 (I/O Interface Mode) bit 0 1 2 3 4 5 6 7 Goes out first * Mode 1 (7-Bit UART Mode) Without parity start bit 0 1 2 3 4 5 6 stop With parity start bit 0 1 2 3 4 5 6 parity stop (1 bit) * Mode 2 (8-Bit UART Mode) Without parity start bit 0 1 2 3 4 5 6 7 stop (1 bit) With parity start bit 0 1 2 3 4 5 6 7 parity stop (1 bit) * Mode 3 (9-Bit UART Mode) start bit 0 1 2 3 4 5 6 7 8 stop (1 bit) start bit 0 1 2 3 4 5 6 7 8 stop (wake-up, 1 bit) Bit 8: Address/data bit flag 1: Address character (select code) 0: Data character Figure 13.1 Data Formats TMP1941AF-158 2003-03-27 TMP1941AF 13.1 Block Diagrams Prescaler 4 8 16 32 64 T0 2 T2 T8 T32 Serial Clock Generator BR0CR. BR0CK[1:0] BR0CR. BR0S[3:0] T0 T2 T8 T32 Selector Divider BR0ADD. BR0K[3:0] Selector Selector UART Mode TA0TRG (from TMRA0) SIOCLK /2 SCLK0 Input (Shared with P92) Selector fsys/2 BR0CR. BR0ADDE Baud Rate Generator SC0MOD0. SC0MOD0. SC[1:0] SM[1:0] I/O Interface Mode I/O Interface Mode SCLK0 Output (Shared with P92) Receive Counter (/16 for UART) SC0CR. IOC INTRX0 Interrupt Request INTTX0 Interrupt Request Transmit Counter (/16 for UART) SC0MOD0. Serial Channel WU Interrupt Control RXDCLK SC0MOD0. Receive RXE Control SC0CR PE EVEN Parity Control RXD0 (Shared with P91) Receive Buffer 1 (Shift Register) TXDCLK Transmit Control SC0MOD0. CTSE CTS0 (Shared with P92) RB8 Receive Buffer 2 (SC0BUF) Error Flag TB8 Transmit Buffer (SC0BUF) SC0CR OERR PERR FERR Internal Data Bus Internal Data Bus Internal Data Bus TXD0 (Shared with P90) Figure 13.2 SIO0 Block Diagram TMP1941AF-159 2003-03-27 TMP1941AF T0 2 Prescaler 4 8 16 32 64 T2 T8 T32 Serial Clock Generator BR1CR. BR1CK[1:0] BR1CR. BR1S[3:0] T0 T2 T8 T32 Selector Divider BR1ADD. BR1K[3:0] Selector Selector UART Mode TA0TRG (from TMRA0) SIOCLK /2 SCLK1 Input (Shared with P95) Selector fsys/2 BR1CR. BR1ADDE Baud Rate Generator SC1MOD0. SC1MOD0. SC[1:0] SM[1:0] I/O Interface Mode I/O Interface Mode SCLK1 Output (Shared with P95) Receive Counter (/16 for UART) SC1CR. IOC INTRX1 Interrupt Request INTTX1 Interrupt Request Transmit Counter (/16 for UART) SC1MOD0. Serial Channel WU Interrupt Control RXDCLK SC1MOD0. Receive RXE Control SC1CR PE EVEN Parity Control RXD1 (Shared with P94) Receive Buffer 1 (Shift Register) TXDCLK Transmit Control SC1MOD0. CTSE CTS 1 (Shared with P95) RB8 Receive Buffer 2 (SC1BUF) Error Flag TB8 Transmit Buffer (SC1BUF) SC1CR OERR PERR FERR Internal Data Bus Internal Data Bus Internal Data Bus TXD1 (Shared with P93) Figure 13.3 SIO1 Block Diagram TMP1941AF-160 2003-03-27 TMP1941AF T0 2 Prescaler 4 8 16 32 64 T2 T8 T32 Serial Clock Generator BR3CR. BR3CK[1:0] BR3CR. BR3S[3:0] T0 T2 T8 T32 Selector Divider BR3ADD. BR3K[3:0] Selector Selector UART Mode TA0TRG (from TMRA0) SIOCLK fsys/2 BR3CR. BR3ADDE Baud Rate Generator SC3MOD0. SC3MOD0. SC[1:0] SM[1:0] INTRX3 Interrupt Request INTTX3 Interrupt Request Transmit Counter (/16 for UART) Receive Counter (/16 for UART) SC3MOD0. Serial Channel WU Interrupt Control RXDCLK SC3MOD0. Receive RXE Control SC3CR PE EVEN Parity Control RXD3 (Shared with P71) Receive Buffer 1 (Shift Register) TXDCLK Transmit Control RB8 Receive Buffer 2 (SC3BUF) Error Flag TB8 Transmit Buffer (SC3BUF) SC3CR OERR PERR FERR Internal Data Bus Internal Data Bus Internal Data Bus TXD3 (Shared with P70) Figure 13.4 SIO3 Block Diagram TMP1941AF-161 2003-03-27 TMP1941AF T0 2 Prescaler 4 8 16 32 64 T2 T8 T32 Serial Clock Generator BR4CR. BR4CK[1:0] BR4CR. BR4S[3:0] T0 T2 T8 T32 Selector Divider BR4ADD. BR4K[3:0] Selector Selector UART Mode TA0TRG (from TMRA0) SIOCLK fsys/2 BR4CR. BR4ADDE Baud Rate Generator SC4MOD0. SC4MOD0. SC[1:0] SM[1:0] INTRX4 Interrupt Request INTTX4 Interrupt Request Transmit Counter (/16 for UART) Receive Counter (/16 for UART) SC4MOD0. Serial Channel WU Interrupt Control RXDCLK SC4MOD0. Receive RXE Control SC4CR PE EVEN Parity Control RXD4 (Shared with P71) Receive Buffer 1 (Shift Register) TXDCLK Transmit Control RB8 Receive Buffer 2 (SC4BUF) Error Flag TB8 Transmit Buffer (SC4BUF) SC4CR OERR PERR FERR Internal Data Bus Internal Data Bus Internal Data Bus TXD4 (Shared with P70) Figure 13.5 SIO4 Block Diagram TMP1941AF-162 2003-03-27 TMP1941AF 13.2 SIO Components 13.2.1 Prescaler The SIO0 has a 6-bit prescalar that slows the rate of a clocking source to the serial clock generator. The prescalar clock source (T0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG. The serial clock is selectable from several clocks; the prescalar is only enabled when the baud rate generator output clock is selected as a serial clock. Table 13.2 shows prescalar output clock resolutions (@fc = 32 MHz). Table 13.2 Prescaler Output Clock Resolutions @ fc = 40 MHz Peripheral Clock Select SYSCR1. FPSEL Clock Gear Value SYSCR1. GEAR[1:0] 00 (fc) Prescaler Clock Source SYSCR0.PRCK[1:0] 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 3 Prescaler Output Clock Resolution T0 fc/22 (0.1 s) fc/2 (0.2 s) fc/24 (0.4 s) fc/25 (0.8 s) fc/2 (0.1 s) 2 T2 fc/24 (0.4 s) fc/23 (0.2 s) fc/2 (0.1 s) 2 5 4 3 T8 fc/26 (1.6 s) fc/25 (0.8 s) fc/2 (0.4 s) 4 7 6 5 T32 fc/28 (6.4 s) fc/27 (3.2 s) fc/26 (1.6 s) fc/29 (12.8 s) fc/28 (6.4 s) fc/27 (3.2 s) fc/210 (25.6s) fc/29 (12.8 s) fc/28 (6.4 s) fc/211 (51.2s) fc/210 (25.6s) fc/29 (12.8s) fc/28 (6.4 s) fc/27 (3.2 s) fc/26 (1.6 s) fc/28 (6.4 s) fc/27 (3.2 s) fc/26 (1.6 s) fc/28 (6.4 s) fc/27 (3.2 s) fc/26 (1.6 s) fc/28 (6.4 s) fc/27 (3.2 s) fc/26 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/2 (0.2 s) fc/26 (1.6 s) fc/2 (0.8 s) 5 4 fc/2 (3.2 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/28 (6.4 s) fc/2 (3.2 s) 7 6 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (0.4 s) fc/27 (3.2 s) fc/2 (1.6 s) 6 5 4 fc/2 (1.6 s) fc/29 (12.8s) fc/2 (6.4 s) 8 7 6 11 (fc/8) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (0.8 s) fc/2 (0.4 s) fc/23 (0.2 s) fc/2 (0.1 s) 2 4 3 fc/2 (3.2 s) fc/2 (1.6 s) fc/25 (0.8 s) fc/2 (0.4 s) 4 6 5 4 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (0.4 s) fc/2 (0.2 s) fc/24 (0.4 s) fc/2 (1.6 s) fc/2 (0.8 s) fc/2 (0.4 s) fc/26 (1.6 s) fc/2 (0.8 s) 5 4 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (0.4 s) fc/26 (1.6 s) fc/2 (0.8 s) 5 11 (fc/8) 01 (fperiph/2) 10 (fperiph) Note 1: The prescaler's output clock Tn must be selected so that the relationship Tn < fsys/2 is satisfied. Note 2: Do not change the clock gear value while the timer is running. Note 3: The -- character means "Don't use." Prescalar output taps can be divide-by-1 (T0), divide-by-4 (T2), divide-by-16 (T8) and divide-by64 (T32). TMP1941AF-163 2003-03-27 TMP1941AF 13.2.2 Baud Rate Generator (1) Baud Rate Generator Configuration The frequency used to transimit and receive data through the SIO0 is derived from the baud rate generator. The clock source for the baud rate generator can be selected from the 6-bit prescalar outputs (T0, T2, T8, T32) through the programming of the BR0CK[1:0] field in the BR0CR. The baud rate generator contains a clock divider that can divide the selected clock by 1, n + (m / 16), or 16 (where n is an integer between 2 and 15, and m is an integer between 0 and 15). The clock divisor is programmed into the BR0ADDE and BR0S[3:0] bits in the BR0CR and the BR0K[3:0] bits in the BR0ADD. * UART Mode a. When BR0CR.BR0ADDE = 0 When the BR0CR.BR0ADDE bit is cleared, the BR0ADD.BR0K[3:0] field has no meaning or effect. In this case, the baud rate generator input clock is divided down by a value of N (1 to 16) programmed in the BR0CR.BR0S[3:0] field. b. When BR0CR.BR0ADDE = 1 Setting the BR0CR.BR0ADDE bit enables the N + (16 - K) / 16 clock division function. The baud rate generator input clock is divided down according to the value of N (2 to 15) programmed in the BR0CR.BR0S[3:0] field and the value of K (1 to 15) programmed in the BR0ADD.BR0K[3:0] field. Note: Setting N to 0 or 16 disables the N + (16 - K) / 16 clock division function. When N = 0 or 16, the BR0CR.BR0ADDE bit must be cleared. * I/O Interface Mode I/O Interface mode can not utilize the N + (16 - K) / 16 clock division function. The BR0CR.BR0ADDE must be cleared, so the baud rate generator input clock is divided down by a value of N (1 to 16) programmed in the BR0CR.BR0S[3:0] field. (2) Baud Rate Calculations * UART Mode Baud Rate = baud rate generator input clock / 16 baud rate generator divisor When the clock input to the baud rate generator is 8-MHz T0, the maximum baud rate is 500 kbps (with no clock division by the baud rate generator). The baud rate generator can by bypassed if the user wants to use the fsys/2 clock as a serial clock. In this case, the maximum baud rate is 1 Mbps @fsys = 32 MHz. * I/O Interface Mode Baud Rate = baud rate generator input clock /2 baud rate generator divisor When the clock input to the baud rate generator is 8-MHz T0, the maximum baud rate is 2 Mbps (with the clock divided by 2 by the baud rate generator). TMP1941AF-164 2003-03-27 TMP1941AF (3) Calculation Examples * Integral Clock Division (Divide-by-N) fperiph = 24.576-MHz fc T0 = fperiph/4 Baud rate generator input clock: T2 Clock divisor N (BR0CR.BR0S[3:0]) = 10 BR0CR.BR0ADDE = 0 Clocking conditions System clock: High-speed (fc) High-speed clock gear:1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) The baud rate is determined as follows: fc/16 / 16 10 = 24.576 x 106 / 16 / 10 / 16 = 9600 (bps) Baud Rate = Note: Clearing the BR0CR.BR0ADDE bit to 0 disables the N + (16 - K) / 16 clock division function. At this time, the BR0ADD.BR0K[3:0] field is ignored. * N + (16 - K) / 16 Clock Division (UART mode only) fperiph = 19.2-MHz fc T0 = fperiph/4 Baud rate generator input clock: T2 N (BR0CR.BR0S[3:0]) = 7 K (BR0ADD.BR0K[3:0]) = 3 BR0CR.BR0ADDE = 1 Clocking conditions System clock: High-speed (fc) High-speed clock gear:1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) The baud rate is determined as follows: fc /16 / 16 (16 - 3) 7+ 16 13 6 = 19.2 x 10 / 16 / (7 + ) / 16 = 9600 (bps) 16 Table 13.3 and Table 13.4 show the UART baud rates obtained with various combinations of clock inputs and clock divisor values. Baud Rate = (4) Using an External Clock as a Serial Clock The SIO0 and SIO1 can use an external clock as a serial clock, bypassing the baud rate generator. When an external clock is used, the baud rate is determined as shown below. * UART Mode Baud Rate = external clock input / 16 The external clock period must be greater than or equal to 4/fsys. Therefore, when fsys = 40 MHz, the maximum baud rate is 625 kbps (40 / 4 / 16). TMP1941AF-165 2003-03-27 TMP1941AF * I/O Interface Mode Baud Rate = external clock input clock The external clock period must be greater than 16/fsys. Therefore, when fsys = 40 MHz, the maximum baud rate is 2.5 Mbps (40 /16). For the timing parameters, refer to Section 18.6, Serial Channel Timing. Table 13.3 UART Baud Rate Selection When the baud rate generator is used and BR0CR.BR0ADDE = 0 Unit: kbps fc (MHz) 19.6608 Divisor N (Programmed in BR0CR.BR0S[3:0]) 1 2 4 8 0 Baud Rate Generator Input Clock T0 (fc/4) 307.200 153.600 76.800 38.400 19.200 76.800 38.400 460.800 230.400 153.600 115.200 76.800 38.400 T2 (fc/16) 76.800 38.400 19.200 9.600 4.800 19.200 9.600 115.200 57.600 38.400 28.800 19.200 9.600 T8 (fc/64) 19.200 9.600 4.800 2.400 1.200 4.800 2.400 28.800 14.400 9.600 7.200 4.800 2.400 T32 (fc/256) 4.800 2.400 1.200 0.600 0.300 1.200 0.600 7.200 3.600 2.400 1.800 1.200 0.600 24.576 29.4912 5 A 1 2 3 4 6 C Note: This table assumes: fsys = fc, clock gear = fc/1, prescaler clock source = fperiph/4 Table 13.4 UART Baud Rate Selection When the TMRA0 timer trigger output is used and the TMRA0 input clock is T1 Unit: kbps TA0REG0 1H 2H 3H 4H 5H 6H 8H AH 10H 14H fc (MHz) 29.4912 230.4 115.2 76.8 57.6 46.08 38.4 28.8 23.04 14.4 11.52 24.576 192 96 64 48 38.4 32 24 19.2 12 9.6 24 187.5 93.75 62.5 46.88 37.5 31.25 23.44 18.75 11.72 9.38 19.6608 153.6 76.8 51.2 38.4 30.72 25.6 19.2 15.36 9.6 7.68 16 125 62.5 41.67 31.25 25 20.83 15.63 12.5 7.81 6.25 12.288 96 48 32 24 19.2 16 12 9.6 6 4.8 Note 1: I/O Interface mode can not utilize the trigger output signal from the 8-bit timer TMRA0 as a serial clock. Note 2: This table assumes: fsys = fc, clock gear = fc/1, and prescaler clock source = fperiph/4 When the 8-bit timer TMRA0 is used to generate a serial clock, the baud rate is determined by the following equation: Baud Rate = clock frequency selected by SYSCR0.PRCK[1: 0] TA0REG x 2 x 16 When theTMRA0 clock source is T1. TMP1941AF-166 2003-03-27 TMP1941AF 13.2.3 Serial Clock Generator This block generates a basic clock (SIOCLK) that controls the transimit and receive circuit. * I/O Interface Mode When the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the output clock from the baud rate generator is divided by two to generate the SIOCLK clock. When the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the external SCLK0 clock is used as the SIOCLK clock; the SC0CR.SCLKS bit determines the active clock edge. * UART Mode The SIOCLK clock is selected from a clock produced by the baud rate generator, the system clock (fsys/2), the trigger output signal from the 8-bit timer TMRA0, and the external SCLK0 clock, according to the setting of the SC0MOD0.SC[1:0] field. 13.2.4 Receive Counter The receive counter is a 4-bit binary up-counter used in UART mode. This counter is clocked by SIOCLK. The receiver utilizes 16 clocks for each received bit, and oversamples each bit three times around their center (with 7th to 9th clocks). The value of a bit is determined by voting logic which takes the value of the majority of three samples. For example, if the three samples of a bit are 1, 0 and 1, then that bit is interpreted as a 1; if the three samples of a bit are 0, 0 and 1, then that bit is interpreted as a 0. 13.2.5 Receive Controller * I/O Interface Mode If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the receive controller samples the RXD0 input at the rising edge of the shift clock driven out from the SCLK0 pin. If the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the receive controller samples the RXD0 input at either the rising or falling edge of the SCLK0 clock, as programmed in the SC0CR.SCLKS bit. * UART Mode The receive controller contains the start bit detection logic. Once a valid start bit is detected, the receive controller begins sampling the incoming data streams. The start bit, each data bit and the stop bit are sampled three times for 2-of-3 majority voting. 13.2.6 Receive Buffer The receive buffer is double-buffered to prevent overrun errors. Received data is serially shifted bit by bit into Receive Buffer 1. When a whole character (i.e., 7 or 8 bits, as programmed) is loaded into Receive Buffer 1, it is transferred to Receive Buffer 2 (SC0BUF), and a receive-done interrupt (INTRX0) is generated. * I/O Interface Mode The double-buffer structure can be used in full-duplex mode, but not in half-duplex mode. For details, refer to Section 13.4. * UART Mode The CPU reads a character from Receive Buffer 2 (SC0BUF). Receive Buffer 1 can accept a new character through the RXD0 pin before the CPU picks up the previous character in Receive Buffer 2. However, the CPU must read Receive Buffer 2 before Receive Buffer 1 is filled with a new character. Otherwise, an overrun error occurs, causing the character previouly in Receive Buffer 1 to be lost. Even in that case, the contents of Receive Buffer 2 and the SC0CR.RB8 bit are preserved. TMP1941AF-167 2003-03-27 TMP1941AF The SC0CR.RB8 bit holds the parity bit for an 8-bit UART character and the most-significant bit (i.e., address/data flag) bit for a 9-bit UART character. In 9-bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address character is received. Setting the SC0MOD0.WU bit enables the wake-up feature. When the SC0CR.RB8 bit has received an address/data flag bit set to 1, the receiver generates the INTRX0 interrupt. 13.2.7 Transmit Counter The transmit counter is a 4-bit binary up-counter used in UART mode. Like the receive counter, the transmit counter is also clocked by SIOCLK. The transmitter generates a transimit clock (TXDCLK) pulse every 16 SIOCLK pulses. SIOCLK 15 TXDCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 Figure 13.6 Transimit Clock Generation 13.2.8 Transmit Controller * I/O Interface Mode If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the transimit controller shifts out each bit in the transmit buffer to the TXD0 pin at the rising edge of the shift clock driven out on the SCLK0 pin. If the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the transimit controller shifts out each bit in the transmit buffer to the TXD0 pin at either the rising or falling edge of the SCLK0 input, as programmed in the SC0CR.SCLKS bit. * UART Mode Once the CPU loads a character into the transimit buffer, the transmit controller begins transmission at the next rising edge of TXDCLK, producing a transmit shift clock (TXDSFT). TMP1941AF-168 2003-03-27 TMP1941AF Handshaking The SIO0 and SIO1 have the clear-to-send ( CTS ) pin. If the CTS operation is enabled, the CTS input must be low in order for the character to be transmitted. This feature can be used for flow control to prevent overrun in the receiver. The SC0MOD.CTSE bit enables and disables the CTS operation. If the CTS pin goes high in the middle of a transmission, the transimit controller stops transmission upon completion of the current character until CTS again goes low. If so enabled, the transmit controller generates the INTTX0 interrupt to notify the CPU that the transmit buffer is empty. After the CPU loads the next character into the transmit buffer, the transmit controller remains in idle state until it detects CTS going low. Although the SIO0 and SIO1 do not have the RTS pin, any general-purpose port pins can serve as the RTS pin. The receiving device uses the RTS output to control the CTS input of the transmitting device. Once the receiving device has received a character, RTS should be set to high in the receivedone interrupt handler to temporarily stop the transmitting device from sending the next character. This way, the user can easily implement a two-way handshake protocol. TMP1941AF TMP1941AF TXD CTS RXD RTS (Any port) Transmitting Device Receiving Device Figure 13.7 Handshaking Signals Write to the Transmit Buffer (Note 2) CTS No transmission takes place during this period. 13 14 15 16 1 2 3 14 15 16 1 2 3 (Note 1) SIOCLK TXDCLK TXD start bit bit 0 Note 1: Note 2: When CTS goes high in the middle of transmission, the transmitter stops transmission after the current character has been sent. The transmitter starts tansmission at the first falling edge of the TXDCLK clock after the CTS signal goes low. Figure 13.8 Clear-To-Send ( CTS ) Signal Timing TMP1941AF-169 2003-03-27 TMP1941AF 13.2.9 Transmit Buffer Once the CPU loads a character into the transmit buffer (SC0BUF), it is shifted out on the TXD0 output, with the least-significant bit first, clocked by the transmit shift clock from the transmit controller. When the transmit buffer is empty and ready to be loaded with the next character, the INTTX0 interrupt is generated to the CPU. A character can not be written to the transmit buffer in the middle of a transmission. 13.2.10 Parity Controller For transmit operations, setting the SC0CR.PE enables parity generation in 7- and 8-bit UART modes. The SC0CR.EVEN bit selects either even or odd parity. If enabled, the parity controller automatically generates parity for the character in the transmit buffer (SC0BUF). In 7-bit UART mode, the TB7 bit in the SC0BUF holds the parity bit. In 8-bit UART mode, the TB8 bit in the SC0MOD holds the parity bit. The parity bit is set after the character has been transmitted. The SC0CR.PE and SC0CR.EVEN bits must be programmed prior to a write to the transmit buffer. For receive operations, the parity controller automatically computes the expected parity when a character in Receive Buffer 1 is transferred to Receive Buffer 2 (SC0BUF). The received parity bit is compared to the SC0BUF.RB7 bit in 7-bit UART mode and to the SC0CR.RB8 bit in 8-bit UART mode. If a character is received with incorrect parity, the SC0CR.PERR bit is set. 13.2.11 Error Flags (UART mode only) The SC0CR has the following error flag bits that indicate the status of the received character for improved data reception reliability. * Overrun error (OERR) An overrun error is reported if all bits of a new character are received into Receive Buffer 1 when Receive Buffer 2 (SC0BUF) still contains a valid character. * Parity error (PERR) A parity error is reported when the parity bit attached to a character received on the RXD pin does not match the expected parity computed from the character transferred to Receive Buffer 2 (SC0BUF). * Framing error (FERR) A framing error is reported when a 0 is detected where a stop bit was expected. (The middle three of the 16 samples are used to determine the bit value.) Note 1: Note 2: Even if an error is present in a received character, the receive operation for the next character continues normally. Error flags are kept until read. TMP1941AF-170 2003-03-27 TMP1941AF 13.2.12 Signal Generation Timing (1) UART Mode Receive Operation 9 Data Bits Interrupt Framing Error Parity Error Overrun Error Middle of the stop bit Middle of the stop bit Middle of the last bit (i.e., bit 8) 8 Data Bits with Parity Middle of the stop bit Middle of the stop bit Middle of the last bit (i.e., parity bit) Middle of the last bit (i.e., parity bit) 8 Data Bits with No Parity 7 Data Bits with Parity 7 Data Bits with No Parity Middle of the stop bit Middle of the stop bit Middle of the last bit (i.e., parity bit) Middle of the stop bit Transmit Operation 9 Data Bits Interrupt Immediately before the stop bit is shifted out 8 Data Bits with Parity Immediately before the stop bit is shifted out 8 Data Bits with No Parity 7 Data Bits with Parity 7 Data Bits with No Parity Immediately before the stop bit is shifted out (2) I/O Interface Mode SCLK Output Mode Transmit Interrupt SCLK Input Mode Immediately after the rising edge of the last SCLK pulse (See Figure 13.29) Immediately after the rising or falling edge of the last SCLK pulse, as programmed (See Figure 13.30) When a received character has been transferred to Receive Buffer 2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See Figure 13.31) When a received character has been transferred to Receive Buffer 2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See Figure 13.32) SCLK Output Mode Receive Interrupt SCLK Input Mode Note 1: Note 2: Don't modify any control register during transmit or receive operations. Don't disable receive operations by clearing the SC0MOD0.RXE bit while any character is being received. TMP1941AF-171 2003-03-27 TMP1941AF 13.3 Register Description 7 SC0MOD0 (0xFFFF_F202) Name Read/Write Reset Value Function 0 0 0 0 Wake-up function 0: Disabled 1: Enabled Bit 8 of a Handshake Receive control transmitted control character 0: Disables 0: Disables receiver CTS operation 1: Enables 1: Enables receiver CTS operation TB8 6 CTSE 5 RXE 4 WU R/W 3 SM1 0 2 SM0 0 1 SC1 0 0 SC0 0 Serial transfer mode 00: I/O Interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: External clock (SCLK0 input) Wake-up function 9-Bit UART Mode 0 1 Interrupt on every received character Interrupt only when RB8 = 1 Other Modes Don't care Handshake ( CTS ) control 0 1 Disable (Accepts data streams at all times) Enable Note: In I/O Interface mode, a serial clock is selected by the SIO0 Control Register (SC0CR). Figure 13.9 SIO0 Mode Register 0 (SC0MOD0) TMP1941AF-172 2003-03-27 TMP1941AF 7 SC1MOD0 (0xFFFF_F20A) Read/Write Reset Value Function Name TB8 0 6 CTSE 0 5 RXE 0 4 WU R/W 0 Wake-up function 0: Disabled 1: Enabled 3 SM1 0 2 SM0 0 1 SC1 0 0 SC0 0 Bit 8 of a Handshake Receive transmitted control control character 0: Disables 0: Disables receiver CTS operation 1: Enables receiver 1: Enables CTS operation Serial transfer mode 00: I/O Interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: External clock (SCLK1 input) Wake-up function 9-Bit UART Mode 0 1 Interrupt on every received character Interrupt only when RB8 = 1 Other Modes Don't care Handshake ( CTS ) control 0 1 Disable (Accepts data streams at all times) Enable Note: In I/O Interface mode, a serial clock is selected by the SIO1 Control Register (SC1CR). Figure 13.10 SIO1 Mode Register 0 (SC1MOD0) TMP1941AF-173 2003-03-27 TMP1941AF 7 SC3MOD0 (0xFFFF_F282) Name Read/Write Reset Value Function 0 TB8 6 0 5 RXE 0 Receive control 0: Disables receiver 1: Enables receiver 4 WU R/W 0 Wake-up function 0: Disabled 1: Enabled 3 SM1 0 2 SM0 0 1 SC1 0 0 SC0 0 Bit 8 of a Must be transmitted written as character 0. Serial transfer mode 00: Reserved 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: Don't care Wake-up function 9-Bit UART Mode 0 1 Interrupt on every received character Interrupt only when RB8 = 1 Other Modes Don't care Figure 13.11 SIO3 Mode Register 0 (SC3MOD0) TMP1941AF-174 2003-03-27 TMP1941AF 7 SC4MOD0 Name (0xFFFF_F28A) Read/Write Reset Value Function TB8 0 6 0 5 RXE 0 Receive control 0: Disables receiver 1: Enables receiver 4 WU R/W 0 Wake-up function 0: Disabled 1: Enabled 3 SM1 0 2 SM0 0 1 SC1 0 0 SC0 0 Bit 8 of a Must be transmitted written as character 0. Serial transfer mode 00: Reserved 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: Don't care Wake-up function 9-Bit UART Mode 0 1 Interrupt on every received character Interrupt only when RB8 = 1 Other Modes Don't care Figure 13.12 SIO4 Mode Register 0 (SC4MOD0) TMP1941AF-175 2003-03-27 TMP1941AF 7 SC0CR (0xFFFF_F201) Read/Write Reset Value Function Bit 8 of a received character Name RB8 R 6 EVEN R/W 0 5 PE 0 4 OERR 0 3 PERR 0 1: Error has occurred. R (Cleared when read) 2 FERR 0 1 SCLKS R/W 0 0: SCLK0 0 IOC 0 0: Baud rate generator 1: SCLK0 input Parity type Parity 0: Disabled 0: Odd 1: Enabled 1: Even Overrun Parity Framing 1: SCLK0 Input clock in I/O Interface mode 0 1 Baud rate generator SCLK0 input Active edge for the SCLK0 input 0 1 Data is transmitted/received on the SCLK0 rising edge. Data is transmitted/received on the SCLK0 falling edge. Framing error flag Parity error flag Overrun error flag These bits are cleared to 0 when read. Input clock in I/O Interface mode 0 1 Odd parity Even parity Note 1: All error flags are cleared to 0 when read. Note 2: When SCLK0 is configured as an output, the SCLKS bit must be cleared (rising-edge triggered). Figure 13.13 SIO0 Control Register (SC0CR) TMP1941AF-176 2003-03-27 TMP1941AF 7 SC1CR (0xFFFF_F209) Read/Write Reset Value Function Bit 8 of a received character Name RB8 R 6 EVEN R/W 0 5 PE 0 4 OERR 0 3 PERR 0 1: Error has occurred. R (Cleared when read) 2 FERR 0 1 SCLKS R/W 0 0: SCLK1 0 IOC 0 0: Baud rate generator 1: SCLK1 input Parity type Parity 0: Disabled 0: Odd 1: Enabled 1: Even Overrun Parity Framing 1: SCLK1 Input clock in I/O Interface mode 0 1 Baud rate generator SCLK1 input Active edge for the SCLK1 input 0 1 Data is transmitted/received on the SCLK1 rising edge. Data is transmitted/received on the SCLK1 falling edge. Framing error flag Parity error flag Overrun error flag These bits are cleared to 0 when read. Input clock in I/O Interface mode 0 1 Odd parity Even parity Note 1: All error flags are cleared to 0 when read. Note 2: When SCLK1 is configured as an output, the SCLKS bit must be cleared (rising-edge triggered). Figure 13.14 SIO1 Control Register (SC1CR) TMP1941AF-177 2003-03-27 TMP1941AF 7 SC3CR (0xFFFF_F281) Read/Write Reset Value Function Bit 8 of a received character Name RB8 R 6 EVEN R/W 0 5 PE 0 4 OERR 0 3 PERR 0 R (Cleared when read) 2 FERR 0 1 R/W 0 0 0 Parity type Parity 1: Error has occurred. 0: Disabled 0: Odd Overrun Parity Framing 1: Enabled 1: Even Must be written as 00. Framing error flag Parity error flag Overrun error flag These bits are cleared to 0 when read. Parity type 0 1 Odd parity Even parity Note: All error flags are cleared to 0 when read. Figure 13.15 SIO3 Control Register (SC3CR) TMP1941AF-178 2003-03-27 TMP1941AF 7 SC4CR (0xFFFF_F289) Read/Write Reset Value Function Bit 8 of a received character Name RB8 R 6 EVEN R/W 0 5 PE 0 4 OERR 0 3 PERR 0 R (Cleared when read) 2 FERR 0 1 R/W 0 0 0 Parity type Parity 1: Error has occurred. 0: Disabled 0: Odd Overrun Parity Framing 1: Enabled 1: Even Must be written as 00. Framing error flag Parity error flag Overrun error flag These bits are cleared to 0 when read. Parity type 0 1 Odd parity Even parity Note: All error flags are cleared to 0 when read. Figure 13.16 SIO4 Control Register (SC4CR) TMP1941AF-179 2003-03-27 TMP1941AF 7 BR0CR (0xFFFF_F203) Name Read/Write Reset Value Function 0 Must be written as 0. 6 BR0ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled 5 BR0CK1 0 00: T0 01: T2 10: T8 11: T32 4 BR0CK0 R/W 0 3 BR0S3 0 2 BR0S2 0 1 BR0S1 0 0 BR0S0 0 Clock divisor value N Clock source for baud rate generator 00 01 10 11 Internal clock T0 Internal clock T2 Internal clock T8 Internal clock T32 7 BR0ADD (0xFFFF_F204) Name Read/Write Reset Value Function 6 5 4 3 BR0K3 0 2 BR0K2 R/W 0 1 BR0K1 0 0 BR0K0 0 Value of K in N+(16-K)/16 Clock divisor value for baud rate generator BR0CR.BR0ADDE = 1 BR0CR.BR0ADDE = 0 BR0CR. BR0S[3:0] BR0ADD. BR0K[3:0] 0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART) or thru thru 0001 (N = 1) 1111 (N = 15) 1111 (N = 15) 0000 (N = 16) Don't use. Don't use. Don't use. Divided by N + (16 - K) / 16 Divided by N 0000 0001(K = 1) thru 1111(K = 15) Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 - K) / 16 clock division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode. Note 2: To use the N + (16 - K) / 16 clock division function, the value of K must be programmed in the BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 - K) / 16 clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1). Note 3: The N + (16 - K) / 16 clock division function can only be used in UART mode. In I/O Interface mode, this must be disabled by clearing BR0CR.BR0ADDE to 0. Figure 13.17 SIO0 Baud Rate Generator Control Registers (BR0CR and BR0ADD) TMP1941AF-180 2003-03-27 TMP1941AF 7 BR1CR (0xFFFF_F20B) Read/Write Reset Value Function Name 0 Must be written as 0. 6 BR1ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled 5 BR1CK1 0 00: T0 01: T2 10: T8 11: T32 4 BR1CK0 R/W 0 3 BR1S3 0 2 BR1S2 0 1 BR1S1 0 0 BR1S0 0 Clock divisor value N Clock source for baud rate generator 00 01 10 11 Internal clock T0 Internal clock T2 Internal clock T8 Internal clock T32 7 Name BR1ADD (0xFFFF_F20C) Read/Write Reset Value Function 6 5 4 3 BR1K3 0 2 BR1K2 R/W 0 1 BR1K1 0 0 BR1K0 0 Value of K in N+(16-K)/16 Clock divisor value for baud rate generator BR1CR.BR1ADDE = 1 BR1CR.BR1ADDE = 0 BR1CR. BR1S[3:0] BR1ADD. BR1K[3:0] 0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART) or thru thru 0001 (N = 1) 1111 (N = 15) 1111 (N = 15) 0000 (N = 16) Invalid Invalid Invalid Divided by N + (16 - K) / 16 Divided by N 0000 0001(K = 1) thru 1111(K = 15) Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 - K) / 16 clock division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode. Note 2: To use the N + (16 - K) / 16 clock division function, the value of K must be programmed in the BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 - K) / 16 clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1). Note 3: The N + (16 - K) / 16 clock division function can only be used in UART mode. In I/O Interface mode, this must be disabled by clearing BR0CR.BR0ADDE to 0. Figure 13.18 SIO1 Baud Rate Generator Control Registers (BR1CR and BR1ADD) TMP1941AF-181 2003-03-27 TMP1941AF 7 BR3CR (0xFFFF_F283) Name Read/Write Reset Value Function 0 Must be written as 0. 6 BR3ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled 5 BR3CK1 0 00: T0 01: T2 10: T8 11: T32 4 BR3CK0 R/W 0 3 BR3S3 0 2 BR3S2 0 1 BR3S1 0 0 BR3S0 0 Clock divisor value N Clock source for baud rate generator 00 01 10 11 Internal clock T0 Internal clock T2 Internal clock T8 Internal clock T32 7 BR3ADD (0xFFFF_F284) Name Read/Write Reset Value Function 6 5 4 3 BR3K3 0 2 BR3K2 R/W 0 1 BR3K1 0 0 BR3K0 0 Value of K in N+(16-K)/16 Clock divisor value for baud rate generator BR3CR.BR3ADDE = 1 BR3CR.BR3ADDE = 0 BR3CR. BR3S[3:0] BR3ADD. BR3K[3:0] 0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART) or thru thru 0001 (N = 1) 1111 (N = 15) 1111 (N = 15) 0000 (N = 16) Invalid Invalid Invalid Divided by N + (16 - K) / 16 Divided by N 0000 0001(K = 1) thru 1111(K = 15) Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 - K) / 16 clock division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode. Note 2: To use the N + (16 - K) / 16 clock division function, the value of K must be programmed in the BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 - K) / 16 clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1). Note 3: The N + (16 - K) / 16 clock division function can only be used in UART mode. In I/O Interface mode, this must be disabled by clearing BR0CR.BR0ADDE to 0. Figure 13.19 SIO3 Baud Rate Generator Control Registers (BR3CR and BR3ADD) TMP1941AF-182 2003-03-27 TMP1941AF 7 BR4CR (0xFFFF_F28B) Read/Write Reset Value Function Name 0 Must be written as 0. 6 BR4ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled 5 BR4CK1 0 00: T0 01: T2 10: T8 11: T32 4 BR4CK0 R/W 0 3 BR4S3 0 2 BR4S2 0 1 BR4S1 0 0 BR4S0 0 Clock divisor value N Clock source for baud rate generator 00 01 10 11 Internal clock T0 Internal clock T2 Internal clock T8 Internal clock T32 7 Name BR4ADD (0xFFFF_F28C) Read/Write Reset Value Function 6 5 4 3 BR4K3 0 2 BR4K2 R/W 0 1 BR4K1 0 0 BR4K0 0 Value of K in N+(16-K)/16 Clock divisor value for baud rate generator BR4CR.BR4ADDE = 1 BR4CR.BR4ADDE = 0 BR4CR. BR4S[3:0] BR4ADD. BR4K[3:0] 0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART) or thru thru 0001 (N = 1) 1111 (N = 15) 1111 (N = 15) 0000 (N = 16) Invalid Invalid Invalid Divided by N + (16 - K) / 16 Divided by N 0000 0001(K = 1) thru 1111(K = 15) Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 - K) / 16 clock division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode. Note 2: To use the N + (16 - K) / 16 clock division function, the value of K must be programmed in the BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 - K) / 16 clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1). Note 3: The N + (16 - K) / 16 clock division function can only be used in UART mode. In I/O Interface mode, this must be disabled by clearing BR0CR.BR0ADDE to 0. Figure 13.20 SIO4 Baud Rate Generator Control Registers (BR4CR and BR4ADD) TMP1941AF-183 2003-03-27 TMP1941AF 7 TB7 SC0BUF (0xFFFF_F200) 7 RB7 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2 1 RB1 0 RB0 (For receive) 6 TB6 5 TB5 4 TB4 3 TB3 2 TB2 1 TB1 0 TB0 (For tranmit) Figure 13.21 SIO0 Transmit/Receive Buffer Register (SC0BUF) 7 SC0MOD1 (0xFFFF_F205) Name Read/Write Reset Value Function I2S0 R/W 0 SIO operation in IDLE mode 0: Off 1: On 6 FDPX0 R/W 0 Synchronous 0: Halfduplex 1: Fullduplex 5 4 3 2 1 0 Figure 13.22 SIO0 Mode Register 1 (SC0MOD1) 7 TB7 SC1BUF (0xFFFF_F208) 7 RB7 6 TB6 5 TB5 4 TB4 3 TB3 2 TB2 1 TB1 0 TB0 (For tranmit) 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2 1 RB1 0 RB0 (For receive) Figure 13.23 SIO1 Transmit/Receive Buffer Register (SC1BUF) 7 Name SC1MOD1 (0xFFFF_F20D) Read/Write Reset Value I2S0 R/W 0 SIO operation in IDLE mode 0: Off 1: On 6 FDPX0 R/W 0 Synchronous 0: Halfduplex 1: Fullduplex 5 4 3 2 1 0 Function Figure 13.24 SIO1 Mode Register 1 (SC1MOD1) TMP1941AF-184 2003-03-27 TMP1941AF 7 TB7 SC3BUF (0xFFFF_F280) 7 RB7 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2 1 RB1 0 RB0 (For receive) 6 TB6 5 TB5 4 TB4 3 TB3 2 TB2 1 TB1 0 TB0 (For tranmit) Figure 13.25 SIO3 Transmit/Receive Buffer Register (SC3BUF) 7 Name SC3MOD1 (0xFFFF_F285) Read/Write Reset Value Function I2S0 R/W 0 SIO operation in IDLE mode 0: Off 1: On 6 5 4 3 2 1 0 Figure 13.26 SIO3 Mode Register 1 (SC3MOD1) 7 TB7 SC4BUF (0xFFFF_F288) 7 RB7 6 TB6 5 TB5 4 TB4 3 TB3 2 TB2 1 TB1 0 TB0 (For tranmit) 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2 1 RB1 0 RB0 (For receive) Figure 13.27 SIO4 Transmit/Receive Buffer Register (SC4BUF) 7 Name SC4MOD1 (0xFFFF_F28D) Read/Write Reset Value Function I2S0 R/W 0 SIO operation in IDLE mode 0: Off 1: On 6 5 4 3 2 1 0 Figure 13.28 SIO4 Mode Register 1 (SC4MOD1) TMP1941AF-185 2003-03-27 TMP1941AF 13.4 Operating Modes 13.4.1 Mode 0 (I/O Interface Mode) Mode 0 utilizes a synchronization clock (SCLK), which can be configured for either output mode in which the SCLK clock is driven out from the TMP1941AF or input mode in which the SCLK clock is supplied externally. (1) Transmit Operations In SCLK Output mode, each time the CPU writes a character to the transmit buffer, the eight bits of the character is shifted out on the TXD0 pin, and the synchronization clock is driven out from the SCLK0 pin. When all the bits have been shifted out, the transmit-done interrupt (INTTX0) is generated. Transmit Data Write Timing SCLK0 Output TXD0 INTTX0 Interrupt bit 0 bit 1 bit 6 bit 7 bit 0 Figure 13.29 Transmit Operation in I/O Interface Mode (SCLK0 Output Mode) In SCLK0 Input mode, the CPU must write a character to the transmit buffer before the SCLK0 input is activated. The eight bits of a character in the transmit buffer are shifted out on the TXD0 pin, synchronous to the programmed edge of the SCLK0 input. When all the bits have been shifted out, the transmit-done interrupt (INTTX0) is generated. The CPU must load the next character into the transmit buffer by point A. Transmit Data Write Timing SCLK0 Input (SCLKS = 0: Rising Edge) SCLK0 Input (SCLKS = 1: Falling Edge) TXD0 INTTX0 Interrupt bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 A Figure 13.30 Transmit Operation in I/O Interface Mode (SCLK0 Input Mode) TMP1941AF-186 2003-03-27 TMP1941AF (2) Receive Operations In SCLK Output mode, each time the CPU picks up the character in Receive Buffer 2, the synchronization clock is driven out from the SCLK0 pin to shift the next character into Receive Buffer 1. When a whole 8-bit character has been loaded into Receive Buffer 1, it is transferred to Receive Buffer 2, and the receive-done interrupt (INTRX0) is generated. The SCLK output is initiated by setting the SC0MOD0.RXE bit to 1. Receive Data Read Timing SCLK0 Output RXD0 INTTX0 Interrupt bit 0 bit 1 bit 6 bit 7 bit 0 Figure 13.31 Receive Operation in I/O Interface Mode (SCLK0 Output Mode) In SCLK Input mode, the CPU must pick up the character in the Receive Buffer 2 before the SCLK0 input is activated to shift the next character into Receive Buffer 1. When a whole 8-bit character has been loaded into Receive Buffer 1, it is transferred to Receive Buffer 2, and the receive-done interrupt (INTRX0) is generated. The CPU must read the character in Receive Buffer 2 by point A. Until that is done, the receiver is not ready to accept the next character. In case the CPU reads the character in Receiver Buffer 2 after point A, reception of the next character begins at that point, causing the received data to be corrupted. For system applications in which the CPU might not be able to keep pace with incoming data streams, handshaking is required. Receive Data Read Timing SCLK0 Input (SCLKS = 0: Rising Edge) SCLK0 Input (SCLKS = 1: Falling Edge) RXD0 INTRX0 Interrupt bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 A Figure 13.32 Receive Operation in I/O Interface Mode (SCLK0 Input Mode) Note: Regardless of whether SCLK is in input mode or output mode, the receiver must be enabled by setting the SC0MOD.RXE bit to 1 in order to perform receive operations. TMP1941AF-187 2003-03-27 TMP1941AF (3) Full-Duplex Transmit/Receive Operations Setting the SC0MOD1.FDPX0 bit enables full-duplex communication. In this mode of operation, the double-buffering is enabled. When Receive Buffer 1 is filled with an 8-bit character, it is transferred to Receive Buffer 2 (SC0BUF), and the receive-done interrupt (INTRX0) is generated. While an 8-bit character is being received, an 8-bit character can be transmitted from the TXD0 pin simultaneously. When a whole 8-bit character has been shifted out, the transmitdone interrupt (INTTX0) is generated. In SCLK Output mode, loading the transimit buffer with a character restarts the transmit/receive operation. The CPU must pick up the received character before the next character fills Receive Buffer 1. Otherwise, the latter character is discarded. (The previous character is preserved. Transmission proceeds with no error.) Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1 Figure 13.33 Full-Duplex Transmit/Receive Operation in I/O Interface Mode (SCLK0 Output Mode) In SCLK Input Mode, the CPU must write a character to be transmitted into the transmit buffer by point A. No transimi/receive operation occurs until the transmit buffer is filled. In case the transmit buffer is loaded after point A, the transmit/receive operation begins at that point, causing the transimit/receive data to be corrupted. For system applications in which transmit underrun conditions could occur, handshaking is required. Receive Data Read Timing Transmit Data Write Timing SCLK0 Output TXD0 RXD0 INTTX0 Interrupt INTRX0 Interrupt bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1 A A Figure 13.34 Full-Duplex Transmit/Receive Operation in I/O Interface Mode (SCLK0 Input Mode) * Restrictions on SCLK Configured as an Input In I/O Interface mode, the CPU may be unable to access the receive or transmit buffer fast enough to support back-to-back transfers. When SCLK is configured as an output, one or more wait cycles are automatically inserted to prolong the SCLK intervals. However, when SCLK is TMP1941AF-188 2003-03-27 TMP1941AF configured as an input, the SCLK input must be delayed by external hardware so that the CPU can keep pace with the data rate. Generally, the wait period is a function of the fsys frequency and the data rate. The following figure gives some indication of the relationsip between SCLK and fsys frequencies for different wait periods. In reality, processing load during transfers also affect the maximum SCLK frequency. MHz 2.0 Sufficient wait period Wait period of one SCLK cycle Wait period of one-half SCLK cycle 1.5 SCLK Frequency 1.0 No wait (free-running SCLK) 0.5 0 0 10 fsys Note: The above figure assumes that the DMAC is utilized for reads of the receive buffer and writes of the transmit buffer. 20 30 40 MHz 13.4.2 Mode 1 (7-Bit UART Mode) Setting the SM[1:0] field in the SC0MOD0 to 01 puts the SIO0 in 7-bit UART mode. In this mode of operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity. Example: Transmitting 7-bit UART characters with an even-parity bit start bit 0 1 2 3 4 5 6 even parity stop Goes out first (transfer rate = 2400 bps @fc = 24.576 MHz) Clocking conditions: System clock: High-speed (fc) High-speed clock gear: 1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) Settings in the main routine P9CR P9FC SC0MOD SC0CR BR0CR IMCCLH SC0BUF 7 - - X X 0 - 6 - - 0 1 0 - * 5 - - - 1 1 1 * 4 - - X X 0 1 * 3 - - 0 X 1 0 * 2 - - 1 X 0 1 * 1 - - 0 0 1 0 * 0 1 1 1 0 0 0 * Configures the P90 pin as TXD0. Selects 7-bit UART mode. Selects even parity. Sets the transfer rate to 2400 bps. Enables the INTTX0 interrupt and sets its priority level to 4. Loads the transmit buffer with a character. * Transmit-done interrupt routine INTCLR X X 1 1 0 0 0 1 Clears the interrupt request. Interrupt processing End of interrupt processing X = Don't care, - = No change TMP1941AF-189 2003-03-27 TMP1941AF 13.4.3 Mode 2 (8-Bit UART Mode) Setting the SM[1:0] field in the SC0MOD0 to 10 puts the SIO0 in 8-bit UART mode. In this mode of operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity. Example: Transmitting 8-bit UART characters with an odd-parity bit start bit 0 1 2 3 4 5 6 odd parity stop Goes out first (transfer rate = 9600 bps @fc = 24.576 MHz) Clocking conditions: System clock: High-speed (fc) High-speed clock gear: 1 (fc) Prescaler clock: fperiph/4 (fperiph = fsys) Settings in the main routine P9CR SC0MOD SC0CR BR0CR IMCCLL 7 - - X 0 - 6 - 0 0 0 - 5 - 1 1 0 1 4 - X X 1 1 3 - 1 X 0 0 2 - 0 X 1 1 1 0 0 0 0 0 0 - 1 0 1 0 Configures P91 (RXD0) to be an input. Selects 8-bit UART mode and enables the receiver. Selects odd parity. Sets the transfer rate to 9600 bps. Enables the INTRX0 interrupt and sets its priority level to 4. Example of interrupt routine processing INTCLR 7 X 6 X 5 1 4 1 3 0 2 0 1 0 0 0 Clears the interrupt request. Checks for errors. Reg. SC0CR AND 0x1C if Reg. 0 then Error Reg. SC0BUF End of interrupt processing X = Don't care, - = No change 13.4.4 Mode 3 (9-Bit UART Mode) Setting the SM[1:0] field in the SC0MOD0 to 11 puts the SIO0 in 9-bit UART mode. In this mode, a parity bit cannot be used; thus, parity should be disabled by clearing the SC0CR.PE bit to 0. For transmit operations, the most-significant bit (9th bit) is stored in the TB8 bit in the SC0MOD0. For receive operations, the most-significant bit is stored in the RB8 bit in SC0CR. Reads and writes of the transmit/receive character must be done with the most-significant bit first, followed by the SC0BUF. Wake-up Feature In 9-bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address character is received. Setting the SC0MOD0.WU bit enables the wake-up feature. When the SC0CR.RB8 bit has received an address/data flag bit set to 1, the receiver generates the INTRX0 interrupt. TMP1941AF-190 2003-03-27 TMP1941AF TXD RXD TXD RXD TXD RXD TXD RXD Master Slave 1 Slave 2 Slave 3 Note: The slave controller's TXD pin must be configured as an open-drain output by programming the ODE register. Figure 13.35 Serial Link Using the Wake-Up Function Protocol (1) Put all the master and slave controllers in 9-bit UART mode. (2) Enables the receiver in each slave controller by setting the SC0MOD0.WU bit to 1. (3) The master controller transmits an address character (i.e, select code) that identifies a slave controller. The address character has the most-significant bit (bit 8) set to 1. start bit 0 1 2 3 4 5 6 7 8 "1" stop Slave controller select code (4) Each slave controller compares the received address to its station address and clears the WU bit if they match. (5) The master controller transmits data characters or block of data to the selected slave controller (with SC0MOD0.WU bit cleared). Data characters have the most-significant bit (bit 8) cleared to 0. start bit 0 1 2 3 Data 4 5 6 7 bit 8 "0" stop (6) Slave controllers not addressed continue to monitor the data stream, but discard any characters with the most-significant bit (RB8) cleared, and thus does not generate receive-done interrupts (INTRX0). The addressed slave controller with its WU bit cleared can transmit data to the master controller to notify that it has successfully received the message. TMP1941AF-191 2003-03-27 TMP1941AF Example: Connecting a master station with two slave stations through a serial link using the fsys/2 clock as a serial clock TXD RXD TXD RXD TXD RXD Master Slave 1 Select Code 0x0000_0001 Slave 2 Select Code 0x0000_1010 * Master controller settings Main routine 7 P9CR P9FC IMCCLL IMCCLH SC0MOD0 SC0BUF - - - - 1 6 - - - - 0 0 5 - - 1 1 1 0 4 - - 1 1 0 0 3 - - 0 0 1 0 2 - - 1 1 1 0 1 0 X 0 0 1 0 0 1 1 1 0 0 1 Configures the P90 pin as TXD0 and the P91 pin as RXD0 Enables INTRX0 and sets its interrupt level to 5. Enables INTTX0 and sets its interrupt level to 4. Selects 9-bit UART mode and selects fsys/2 as a serial clock. Loads the select code for slave 1. 0 Interrupt routine (INTTX0) INTCLR X SC0MOD0 0 SC0BUF * X - * 1 - * 1 - * 0 - * 0 - * 0 - * 1 - * Clears the interrupt request. Clears the TB0 bit to 0. Loads the transmit data. End of interrupt processing * Slave controller settings Main routine 7 P9CR P9FC ODE IMCCLL IMCCLH SC0MOD0 - - X - - 0 6 - - X - - 0 5 - - - 1 1 1 4 - - - 1 1 1 3 - - - 0 0 1 2 - - - 1 1 1 1 0 X - 1 0 1 0 1 1 1 0 1 0 Configures the P90 pin as TXD (open-drain output) and the P91 pin as RXD. Enables INTTX0 and INTRX0. Selects 9-bit UART mode, selects fsys/2 as the serial clock and and sets the WU bit to 1. Interrupt routine (INTRX0) X X 1 INTCLR SC0BUF Reg. if Reg. = Select code Then SC0MOD0 - - - 1 0 0 0 0 Clears the interrupt request. 0 - - - - Clears the WU bit to 0. TMP1941AF-192 2003-03-27 TMP1941AF 14. Serial Bus Interface (SBI) The TMP1941AF contains a Serial Bus Interface (SBI) channel, which has the following two operating modes: * * I2C Bus mode (with multi-master capability) Clock-Synchronous 8-Bit SIO mode In I2C Bus mode, the SBI is connected to external devices via two pins, PA6 (SDA) and PA7 (SCL). In Clock-Synchronous 8-Bit SIO mode, the SBI is connected to external devices via three pins, PA5 (SCK), PA6 (SO) and PA7 (SI). The following table shows the programming required to put the SBI in each operating mode. ODE.ODEA7 thru ODE.ODEA6 I2C Bus Mode Clock-Synchronous 8-Bit SIO Mode X = Don't care Note: With the TMP1940FDBF with flash memory, the SBI is unusable when the DSU feature is enabled. 11 XX PACR.PA7C thru PACR.PA5C 11X 011 010 PAFC.PA7F thru PAFC.PA5F 110 111 14.1 Block Diagram INTS2 Interrupt Request SCL SCK SIO Clock Control PA5 (SCK) Input/ Output Control SO SI PA6 (SO/SDA) T0 Divider SIO Data Control Noise Canceller I2C Bus Clock Synchronization / Control Transfer Control Logic Shift Register I C Bus Data Control 2 PA7 (SI/SCL) Noise Canceller SDA SBI0CR2/ SBI0SR I2C0AR SBI0DBR SBI Data Buffer Register SBI0CR1 SBI Control Register 1 SBI0BR0/1 SBI Baud Rate Registers 0 and 1 SBI Control Register 2 / I2C Bus SBI Status Register Address Register Figure 14.1 SBI Block Diagram TMP1941AF-193 2003-03-27 TMP1941AF 14.2 Registers A listing of the registers used to control the SBI follows: * * * * * * * Serial Bus Interface Control Register 1 (SBI0CR1) Serial Bus Interface Control Register 2 (SBI0CR2) Serial Bus Interface Data Buffer Register (SBI0DBR) I2C Bus Address Register (I2C0AR) Serial Bus Interface Status Register (SBI0SR) Serial Bus Interface Baud Rate Register 0 (SBI0BR0) Serial Bus Interface Baud Rate Register 1 (SBI0BR1) The functions of these registers vary, depending on the mode in which the SBI is operating. For a detailed description of the registers, refer to Section 14.5, I2C Bus Mode Configuration, and Section 14.8, Clock-Synchronous 8-Bit SIO Mode Operation. 14.3 I2C Bus Mode Data Formats Figure 14.2 shows the serial bus interface data formats used in I2C Bus mode. (a) Addressing format 8 bits S Slave address Once 1 RA /C WK 1 to 8 bits Data 1 A C K 1 to 8 bits Data 1 A CP K Repeated (b) Addressing format (with repeated START condition) 8 bits S Slave address Once 1 RA /C WK 1 to 8 bits Data Repeated 1 A CS K 8 bits Slave address Once 1 RA /C WK 1 to 8 bits Data Repeated 1 A CP K (c) Free data format (master-transmitter to slave-receiver) 8 bits S Data Once 1 A C K 1 to 8 bits Data 1 A C K Repeated 1 to 8 bits Data 1 A CP K S = START condition R/ W = Direction bit ACK = Acknowledge bit P = STOP condition 2 Figure 14.2 I C-Bus Mode Data Formats TMP1941AF-194 2003-03-27 TMP1941AF 14.4 Description of the Registers Used in I2C Bus Mode This section provides a summary of the registers which control I2C bus operation and provide I2C bus status information for bus access/monitoring. Serial Bus Interface Control Register 1 7 Name SBI0CR1 (0x FFFF_F240) Read/Write Reset Value BC2 6 BC1 W 5 BC0 4 ACK R/W 3 2 SCK2 W 0 1 SCK1 0 SCK0/ SWRMON R/W 1 0 0 0 0 0 Function Number of bits per transfer (Note 1) ACK clock pulse 0: No ACK 1: ACK Internal SCL output clock frequency (Note 2) / Software reset monitor On writes: SCK[2:0] = Internal SCL output clock frequency 000 001 010 011 100 101 110 111 0 1 n=4 n=5 n=6 n=7 n=8 n=9 n=10 500 kHz 278 kHz 147 kHz 75.8 kHz 38.5 kHz 19.4 kHz 9.73 kHz Reserved Assumptions: System clock: fc (= 40 MHz) Clock gear: fc/1 T0 = fperiph/4 (= 10 MHz) T0 Frequency = (Hz) 2n + 4 On reads: SWRMON = Software reset monitor Software reset operation is in progress. Software reset operation is not in progress. Number of bits per transfer BC [2:0] 000 001 010 011 100 101 110 111 ACK = 0 # of clock cycles 8 1 2 3 4 5 6 7 Data length 8 1 2 3 4 5 6 7 ACK = 1 # of clock cycles 9 2 3 4 5 6 7 8 Data length 8 1 2 3 4 5 6 7 Note 1: Clear the BC[2:0] field to 000 before switching the operating mode to Clock-Synchronous 8-Bit SIO mode. Note 2: For details on the SCL bus clock frequency, refer to Section 14.5.3, Serial Clock. Figure 14.3 I C Bus Mode Registers (1) 2 TMP1941AF-195 2003-03-27 TMP1941AF Serial Bus Interface Control Register 2 7 SBI0CR2 Name (0xFFFF_F243) Read/Write Reset Value MST 0 Master/ slave 0: Slave 1: Master 6 TRX W 0 Transmit/ receive 0: Receive 1: Transmit 5 BB 0 START / STOP generation 0: STOP condition 1: START condition 4 PIN 1 INTS2 interrupt clear 0: Don't care 1: Interrupt clear 3 SBIM1 0 2 SBIM0 0 W (Note 1) 1 SWRST1 0 W (Note 1) 0 SWRST0 0 Function Operating mode (Note 2) 00: Port mode 01: SIO mode 10: I2C Bus mode 11: Reserved Software reset A write of 10 followed by a write of 01 Operating mode (Note 2) 00 01 10 11 Port mode (serial bus interface output disabled) Clock-Synchronous 8-Bit SIO mode I2C Bus mode Reserved Note 1: Reading this register causes it to function as a status register (SBI0SR). See the next page. Note 2: Ensure that the bus is free before switching the operating mode to Port mode. Ensure that the port is at logic high before switching from Port mode to I2C Bus or SIO mode. 2 Figure 14.4 I C Bus Mode Registers (2) Table 14.1 Prescalar Output Clock (T0) Resolutions @fc = 40 MHz Peripheral Clock Prescalar Clock Prescalar Output Clock Resolution Clock Gear Value Select Select SYSCR1.GEAR[1:0] T0 SYSCR1.FPSEL SYSCR0.PRCK[1:0] 00 (fperiph/4) 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 11 (fc/8) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 11 (fc/8) 01 (fperiph/2) 10 (fperiph) Note: The -- character means "Don't use." fc/22 (0.1 s) fc/23 (0.2 s) fc/24 (0.4 s) fc/25 (0.8 s) fc/22 (0.2 s) TMP1941AF-196 2003-03-27 TMP1941AF Serial Bus Interface Status Register 7 SBI0SR Name (0xFFFF_F243) Read/Write Reset Value MST 0 Master/ slave 0: Slave 1: Master 6 TRX 0 Transmit/ receive 0: Receive 1: Transmit 5 BB 0 I2C Bus status 0: Free 1: Busy 4 PIN R 1 INTS2 interrupt status 0: Asserted 1: Not asserted 3 AL 0 Arbitration lost 0: 1: Detected 2 AAS 0 Addressed as slave 0: 1: Detected 1 AD0 0 Address 0 (general call) 0: 1: Detected 0 LRB 0 Last received bit 0: 0 1: 1 Function Last received bit 0 1 0 1 The last bit received was 0. The last bit received was 1. The address on the bus matches the I2COAR or general-call address (slave receiver mode only) Arbitration was lost to another master. Addressed as slave Arbitration lost 0 1 Note: Writing to this register causes it to function as a control register (SBI0CR2). See the previous page. Figure 14.5 I C Bus Mode Registers (3) 2 TMP1941AF-197 2003-03-27 TMP1941AF Serial Bus Interface Baud Rate Register 0 7 Name SBI0BR0 (0xFFFF_F244) Read/Write Reset Value Function 6 I2SBI0 R/W 0 IDLE 0: Off 1: On 5 4 3 2 1 0 W Must be written as 0. SBI on/off in IDLE mode 0 1 Off On Serial Bus Interface Baud Rate Register 1 7 Name SBI0BR1 (0xFFFF_F245) Read/Write Reset Value P4EN R/W 0 Internal clock 0: Off 1: On Controls the iternal baud rate generator 0 1 Off On 6 5 4 3 2 1 0 Function Serial Bus Interface Data Buffer Register 7 Name SBI0DBR (0xFFFF_F241) Read/Write Reset Value Note: DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (receive) / W (transmit) Undefined In transmitter mode, data must be written to this register, with bit 7 being the most-significant bit (MSB). I C Bus Address Register 7 I2C0AR (0xFFFF_F242) Read/Write Reset Value Function Name SA6 0 2 6 SA5 0 5 SA4 0 4 SA3 W 0 3 SA2 0 2 SA1 0 1 SA0 0 0 ALS 0 Address recognition mode When the SBI is addressed as a slave, this field specifies a 7-bit I2C-bus address to which the SBI responds. Address recognition mode 0 1 2 Recognizes the slave address. Does not recognize the slave address. Figure 14.6 I C Bus Mode Registers (4) TMP1941AF-198 2003-03-27 TMP1941AF 14.5 I2C Bus Mode Configuration 14.5.1 Acknowledgment Mode Setting the SBI0CR1.ACK bit selects Acknowledge mode. When operating as a master, the SBI generates a clock pulse for acknowledge automatically after each data. As a transmitter, the SBI releases the SDA line during this acknowledge cycle so that the receiver of the data transfer can drive the SDA line low to acknowledge receipt of the data. As a receiver, the SBI pulls the SDA line low during the acknowledge cycle after each data has been received. Clearing the SBI0CR1.ACK bit selects Non-Acknowledge mode. When operating as a master, the SBI does not generate acknowledge clock pulses. 14.5.2 Number of Bits Per Transfer The SBI0CR1.BC[2:0] field specifies the number of bits of the next data item to be transmitted or received. After a reset, this field is cleared to 000, causing a 7-bit slave address and the data direction ( R / W ) bit to be transferred in a packet of eight bits. At other times, the SBI0CR1.BC[2:0] field keeps a previously programmed value. 14.5.3 Serial Clock (1) I2C Bus Clock Source The SBI0CR1.SCK[2:0] field controls the maximum frequency of the SCL clock driven out on the SCL pin in master mode, as illustrated below. tHIGH tLOW 1/fscl tLOW = 2n - 1/T0 tHIGH = 2 n - 1/T0 + 4/T0 fscl = 1/(tLow + tHIGH) T0 = 2n+4 SBI0CR1.SCK[2:0] 000 001 010 011 100 101 110 n 4 5 6 7 8 9 10 Figure 14.7 I C Bus Clock Source 2 TMP1941AF-199 2003-03-27 TMP1941AF (2) Clock Synchronization Clock synchronization is performed using the wired-AND connection of all I2C-bus components to the bus. If two or more masters try to transfer messages on the I2C bus, the first to pull its clock line low wins the arbitration, overriding other masters producing a high on their clock lines. Clock signals of two or more devices on the I2C-bus are synchronized to ensure correct data transfers. Figure 14.8 shows a depiction of the clock synchronization mechanism for the I2C bus with two masters. Wait State Start counting HIGH period Internal SCL Level (Master A) Internal SCL Level (Master B) Counter reset SCL Bus Line a b c Figure 14.8 Clock Synchronization Example At point a, Master A pulls its internal SCL level low, bringing the SCL bus line low. The highto-low transition on the SCL bus line causes Master B to reset its high-level counter and pulls its internal SCL level low. Master A completes its low period at point b. However, the low-to-high transition on its internal SCL level does not change the state of the SCL bus line if Master B's internal SCL level is still within its low period. Therefore, Master A enters a high wait state, where it does not start counting off its high period. When Master B has counted off its low period at point c, its internal SCL level goes high, releasing the SCL bus line (high). There will then be no difference between the internal SCL levels and the state of the SCL bus line, and both Master A and Master B start counting off their high periods. This way, a synchronized SCL clock is generated with its high period determined by the master with the shortest clock high period and its low period determined by the one with the longest clock low period. 14.5.4 Slave Addressing and Address Recognition Mode When the SBI is configured to operate as a slave, the SA[6:0] field in the I2C0AR must be loaded with the 7-bit I2C-bus address to which the SBI is to respond. The ALS bit must be cleared for the SBI to recognize the incoming slave address. 14.5.5 Configuring the SBI as a Master or a Slave Setting the SBI0CR2.MST bit configures the SBI as a master, and clearing it configures the SBI as a slave. This bit is cleared by hardware when a STOP condition has been detected and when arbitration for the I2C bus has been lost. TMP1941AF-200 2003-03-27 TMP1941AF 14.5.6 Configuring the SBI as a Transmitter or a Receiver The SBI0CR2.TRX bit is set or cleared by hardware to configure the SBI as a transmitter or a receiver. As a slave, the SBI is put in either slave-receiver or slave-transmitter mode, depending on the value of the data direction ( R / W ) bit transmitted by the master. When the SBI is addressed as a slave, the TRX bit reflects the value of the R / W bit. The TRX bit is set or cleared on the following occasions: * * * when transferring data using addressing format when the received slave address matches the value in I2C0CR when a general-call address is received; i.e., the eight bits following the START condition are all zeros. As a master, the SBI is put in either master-transmitter or a master-receiver mode upon reception of an acknowledge from an addressed slave. The TRX bit changes to the opposite value of the R / W bit sent by the SBI. If the SBI does not receive an acknowledge from a slave, the TRX bit retains the previous value. The TRX bit is cleared by hardware when a STOP condition has been detected and when arbitration for the I2C bus has been lost. 14.5.7 Generating START and STOP Conditions When the SBI0SR.BB bit is cleared, the bus is free. At this time, writing 1s to the MST, TRX, BB and PIN bits in the SBI0CR2 causes the SBI to generate a START condition on the bus and shift out 8bit I2C-bus data. Before generating a START condition, the ACK bit must be set to 1. SCL Line 1 2 3 4 5 6 7 8 9 SDA Line START Condition A6 A5 A4 A3 A2 A1 A0 R/W Acknowledge Signal Slave Address and Direction bit Figure 14.9 Generating a START Condition and a Slave Address When the SBI0SR.BB bit is set, the bus is busy. When SBI0SR.BB=1, writing 1s to the MST, TRX and PIN bits and a 0 to the BB bit causes the SBI to start a sequence for generating a STOP condition on the bus to abort the transfer. The MST, TRX, BB and PIN bits should not be altered until a STOP condition appears on the bus. SCL Line SDA Line STOP Condition Figure 14.10 Generating a STOP Condition The BB bit can be read to determine if the I2C bus is in use. The BB bit is set when a START condition is detected and cleared when a STOP condition is detected. TMP1941AF-201 2003-03-27 TMP1941AF 14.5.8 Asserting and Deasserting Interrupt Requests When an SBI interrupt (INTS2) is generated, the Pending Interrupt Not (PIN) bit in the SBI0CR2 is cleared to 0. While the PIN bit is 0, the SBI pulls the SCL line low. After transmission or reception of one data word on the I2C bus, the PIN bit is automatically cleared. In transmitter mode, the PIN bit is subsequently set to 1 each time the SBI0DBR is written. In receiver mode, the PIN bit is set to 1 each time the SBI0DBR is read. It takes a period of tLOW for the SCL line to be released after the PIN bit is set. In Address Recognition mode (ALS=0), the PIN bit is cleared when the SBI is addressed as a slave and the received slave address matches the value in the I2C0CR or is all 0s (i.e., a general call). A write of 1 by software sets the PIN bit, but a write of 0 has no effect on this bit. 14.5.9 SBI Operating Modes The SBIM[1:0] field in the SBI0CR2 is used to select an operating mode of the SBI. To configure the SBI for I2C Bus mode, set the SBIM[1:0] field to 10. A switch to Port mode should only be attempted when the bus is free. 14.5.10 Lost-Arbitration Detection Monitor The I2C bus is a multi-master bus and has an arbitration procedure to ensure correct data transfers. A master may start a transfer only if the bus is free. A master that attempts to generate a START condition while the bus is busy loses bus arbitration, with no START condition occurring on the SDA and SCL lines. The I2C-bus arbitration takes place on the SDA line. Figure 14.11 shows the arbitration procedure for two masters. Up until point a, the internal data levels of Master A and Master B are the same. At point a Master B's internal data level makes a low-to-high transition while Master A's internal data level remains at logic low. However, the SDA bus line is held low because it is the wired-AND of the two data outputs. When the SCL bus clock goes high at point b, the addressed slave device reads the data transmitted by Master A (i.e., winning master). Master B loses arbitration and switches off its data output stage, releasing its SDA line (high), so that it does not affect the data transfer initiated by the winning master. In case two competing masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. SCL Bus Line Internal SDA Level (Master A) Internal SDA Level (Master B) SDA Bus Line a b Master B loses arbitration and connects a high output level to the bus. Figure 14.11 Arbitration Procedure of Two Masters TMP1941AF-202 2003-03-27 TMP1941AF A master compares its internal data level to the actual level on the SDA line at the rising edge of the SCL clock. The master loses arbitration if there is a difference between these two values. The losing master sets the AL bit in the SBI0SR to 1, which causes the MST and TRX bits in the same register to be cleared. That is, the losing master switches to slave-receiver mode. The AL bit is subsequently cleared when data is written to or read from the SBI0DBR and when the SBI0CR2 is programmed with new parameters. Master A Internal SCL Level Internal SDA Level 1 2 3 4 5 6 7 8 9 1 2 3 4 D7A D6A D5A D4A D3A D2A D1A D0A D7A' D6A' D5A' D4A' Clock output stops here Master B Internal SCL Level Internal SDA Level AL 1 2 3 4 D7B D6B Internal SDA level is held high because Master B has lost arbitration. MST TRX Access to the SBI0DBR or SBI0CR2 Figure 14.12 Master B Loses Arbitration (D7A - D7B, D6A - D6B) 14.5.11 Slave Address Match Monitor When acting as a slave-receiver, the ALS bit in the I2C0CR determines whether the SBI recognizes the incoming slave address or not. In Address Recognition mode (i.e., ALS=0), the Addressed-As-Slave (AAS) bit in the SBI0SR is set when an incoming address over the I2C bus matches the value in the I2C0CR or when the general-call address has been received. When ALS=1, the AAS bit is set when the first data word has been received. The AAS bit is cleared each time the SBI0DBR is read or written. 14.5.12 General-Call Detection Monitor When acting as a slave receiver, the AD0 bit in the SBI0SR is set when a general-call address has been received. The general-call address is detected when the eight bits following a START condition are all zeros. The AD0 bit is cleared when a START or STOP condition is detected on the bus. 14.5.13 Last Received Bit Monitor The LRB bit in the SBI0SR holds the value of the last bit received over the SDA line at the rising edge of the SCL clock. In Acknowledge mode, reading this bit immediately after generation of the INTS2 interrupt returns the value of the ACK signal. TMP1941AF-203 2003-03-27 TMP1941AF 14.5.14 Software Reset The SBI provides a software reset, which permits recovery from system lockups caused by external noise. A software reset is performed by a write of 10 followed by a write of 01 to the SWRST[1:0] field in the SBI0CR2. After a software reset, all control and status register bits are initialized to their reset values. Upon resetting the SBI, the SWRST[1:0] field is automatically cleared to 00. Note: A software reset causes the SBI operating mode to switch from I2C Bus mode to Port mode. This does not affect the Port A Function register, however. 14.5.15 Serial Bus Interface Data Buffer Register (SBI0DBR) The SBI0DBR is a data buffer interfacing to the I2C bus. All read and write operations to/from the I C bus are done via this register. 2 When the SBI is acting as a master, loading this register with a slave address and a data direction bit causes a START condition to be generated. 14.5.16 I2C Bus Address Register (I2C0AR) When the SBI is configured as a slave, the SA[6:0] field in the I2C0AR must be loaded with the 7-bit I2C-bus address to which the SBI is to respond. If the ALS bit in the I2C0AR is cleared, the SBI recognizes a slave address transmitted by the master device, interpreting incoming frame structures as per addressing format. If the ALS bit is set, the SBI does not recognize a slave address and interprets all frame structures as per free data format. 14.5.17 Baud Rate Register 1 (SBI0DBR1) Before the I2C bus can be used, the P4EN bit in the SBI0BR1 must be set to enable the SBI internal baud rate generation logic. 14.5.18 Baud Rate Register 0 (SBI0BR0) The I2SBI0 bit in the SBI0BR0 determines whether the SBI is shut down or not when the TMP1941AF is put in IDLE standby mode. This register must be programmed before executing an instruction for entering a standby mode. TMP1941AF-204 2003-03-27 TMP1941AF 14.6 Programming Sequences in I C Bus Mode 14.6.1 SBI Initialization First, program the P4EN bit in the SBI0BR1, and the ACK and SCK[2:0] bits in the SBI0CR1. Set the SBI0BR1.P4EN bit to 1 to enable the internal baud rate generation logic. Write 0s to bits 7-5 and bit 3 in the SBI0CR1. Next, program the I2C0AR. The SA[6:0] field in the I2C0AR defines the chip's slave address, and the ALS bit (bit 0) selects an address recognition mode. (The ALS bit must be cleared when using the addressing format.) Next, program the SBI0CR2 to initially configure the SBI in slave-receiver mode; i.e., clear the MST, TRX and BB bits to 0, set the PIN bit to 1 and set the SBIM[1:0] field to 10. Write 00 to the SWRST[1:0] field. SBI0BR1 SBI0CR1 I2C0AR SBI0CR2 7 1 0 X 0 6 0 0 X 0 5 0 0 X 0 4 0 X X 1 3 0 0 X 1 2 0 X X 0 1 0 X X 0 0 0 X X 0 Enable internal baud rate generator. Disable generation of ACK and select SCL clock frequency. Load a slave address and selects address recognition mode. Configure the SBI in slave-receiver mode. 2 Note: X = Don't care 14.6.2 Generating a START Condition and a Slave Address (1) Master Mode In master mode, the following steps are required to generate a START condition and a slave address on the I2C-bus. First, ensure that the bus is free (i.e., SBI0CR2.BB = 0). Next, set the ACK bit in the SBI0CR1 to enable generation of acknowledge clock pulses. Then, loads the SBI0DBR with a slave address and a data direction bit to be transmitted via the I2C bus. When BB=0, writing 1s to the MST, TRX, BB and PIN bits in the SBI0CR2 causes a START condition to be generated on the bus. Following a START condition, the SBI generates SCL clock pulses nine times: the SBI shifts out the contents of the SBI0DBR with the first eight SCL clocks, and releases the SDA line during the last (i.e., ninth) SCL clock to receive an acknowledgement signal from the addressed slave. The INTS2 interrupt request is generated on the falling edge of the ninth SCL clock pulse, and the PIN bit in the SBI0CR2 is cleared to 0. In master mode, the SBI holds the SCL line low while the PIN bit is 0. Upon interrupt, the TRX bit either remains set or is cleared according to the value of the transmitted direction bit, provided an acknowledgement signal has been returned from the slave. Settings in main routine Reg. Reg. if Reg. 76543210 SBI0SR Reg. & 0x20 0x00 Ensure that the bus is free. Select Acknowledgement mode. Load the slave address and a data direction bit. Generate a START condition. Then SBI0CR1 X X X 1 0 X X X SBI0DBR X X X X X X X X SBI0CR2 1 1 1 1 1 0 0 0 INTS2 interrupt routine INTCLR 0x34 Clear the interrupt request. Interrupt processing End of interrupt TMP1941AF-205 2003-03-27 TMP1941AF (2) Slave Mode In slave mode, the following steps are required to receive a START condition and a slave address via the I2C bus. Upon detection of a START condition, the SBI clocks in a 7-bit slave address and a data direction bit transmitted by the master during the first eight SCL clock pulses. If the received slave address matches its own address in the I2C0AR or is equal to the general-call address (00H), the SBI pulls the SDA line low during the last (i.e., ninth) SCL clock for acknowledgement. The INTS2 interrupt request is generated on the falling edge of the ninth SCL clock pulse, and the PIN bit in the SBI0CR2 is cleared to 0. In slave mode, the SBI holds the SCL line low while the PIN bit is 0. Note: The user can only use a DMA transfer: - when there is only one master and only one slave on the I2C bus; and - continuous transmission or reception is possible. SCL 1 2 3 4 5 6 7 8 9 SDA A6 A5 A4 A3 A2 A1 A0 R/ W ACK Acknowledgment from slave START Condition PIN Bit INTS2 Interrupt Request Slave Address + Direction Bit Master to Slave Slave to Master Figure 14.13 Generation of a START Condition and a Slave Address 14.6.3 Transferring a Data Word Each time a data word has been transmitted or received, the INTS2 interrupt is generated. It is the responsibility of the INTS2 interrupt service routine to test the MST bit in the SBI0CR to determine whether the SBI is in master or slave mode. (1) Master Mode (SBI0CR2.MST = 1) If the MST bit in the SBI0CR2 is set, then test the TRX bit in the same register to determine whether the SBI is in master-transmitter or master-receiver mode. Master-Transmitter Mode (SBI0CR2.TRX = 1) Test the LRB bit in the SBI0SR. If the LRB bit is set, that means the slave-receiver requires no further data to be sent from the master-transmitter. The master-transmitter must then generate a STOP condition as described later to stop transmission. If the LRB bit is cleared, that means the slave-receiver requires further data. If the number of bits per transfer is 8, then write the transmit data into the SBI0DBR. When using other data length, program the BC[2:0] and ACK bits in the SBI0CR1, and then write the transmit data into the SBI0DBR. When the SBI0DBR is loaded, the PIN bit in the SBI0SR is set to 1, and the transmit data is shifted out from the SDA pin, clocked by the SCL clock. Once the transfer is complete, the INTS2 interrupt is generated, the PIN bit is cleared, and the SCL line is pulled low. To transmit further data, test the LRB bit again and repeat the above procedure. TMP1941AF-206 2003-03-27 TMP1941AF INTS2 interrupt if MST = 0 Then go to slave-mode processing if TRX = 0 Then go to receiver-mode processing if LRB = 0 Then go to processing for generating a STOP condition Set number of bits to be transmitted and specify whether SBI0DBR X X X X X X X X ACK is required. Load the transmit data. SBI0DBR End of interrupt processing X = Don't care SCL Pin Write to SBI0DBR SDA Pin 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Acknowledgement signal from receiver PIN Bit INTS2 Interrupt Request Master to Slave Slave to Master Figure 14.14 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-Transmitter Mode) Master-Receiver Mode (SBI0CR2.TRX = 0) If the number of bits per transfer is 8, read the SBI0DBR. When using other data length, program the BC[2:0] and ACK bits in the SBI0CR1, and then read the SBI0DBR. The first read of the SBI0DBR is a dummy read because data has not yet been received. A dummy read returns an undefined value. Upon this read, the SCL line is released, the PIN bit in the SBI0SR is set, and the SCL clock is driven out to receive a data word into the SBI0DBR. The master-transmitter generates an acknowledgement signal (i.e., a low level) on the SDA line following the last received bit. Read of the received data. SCL 1 2 3 4 5 6 7 8 9 SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK Next D7 Acknowledgement signal to transmitter PIN Bit INTS2 Interrupt Request Master to Slave Slave to Master Figure 14.15 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-Receiver Mode) To prepare to terminate the data transfer, the master-receiver must clear the ACK bit in the SBI0CR1 immediately before the read of the second to last data word. This causes an acknowledge clock pulse not to be generated on the last data word. When the transfer is complete, the INTS2 interrupt is generated. After interrupt processing, the INTS2 interrupt handler must set the BC[2:0] field in the SBI0CR1 to 001 and read the SBI0DBR, TMP1941AF-207 2003-03-27 TMP1941AF so that a clock is generated on the SCL line once. With the ACK bit cleared, the master-receiver holds the SDA line high, which signals the end of transfer to the slave-transmitter. Then, the SBI generates the INTS2 interrupt again, whereupon the INTS2 interrupt service routine must generate a STOP condition to stop communication via the I2C bus. SCL 9 1 2 3 4 5 6 7 8 1 SDA D7 D6 D5 D4 D3 D2 D1 D0 Negative acknowledge (high) to transmitter PIN Bit INTS2 Interrupt Request Read out the received data after clearing the SBI0CR1.ACK bit. Read out the received data after setting the SBI0CR1.BC[2:0] field to 001. Master to Slave Slave to Master Figure 14.16 Terminating Data Transmission in Master-Receiver Mode Example: When receiving N data words INTS2 interrupt (after data transmission) 76543210 SBI0CR1 X X X X 0 X X X Reg. SBI0DBR End of interrupt INTS2 interrupt (first to (N-2)th data reception) Set the number of bits to be received and specify whether ACK is required. Dummy read 76543210 Reg. SBI0DBR End of interrupt INTS2 interrupt ((N-1)th data reception) Read the first to (N-2)th data words. 76543210 SBI0CR1 X X X 0 0 X X X Reg. SBI0DBR End of interrupt INTS2 interrupt (Nth data reception) Disable generation of acknowledgement clock. Read the (N-1)th data word. 76543210 SBI0CR1 0 0 1 0 0 X X X Reg. SBI0DBR End of interrupt Generate a clock once. Read the Nth data word. INTS2 interrupt (after completing data reception) 76543210 SBI0CR1 0 0 1 0 0 X X X Reg. SBI0DBR End of interrupt X = Don't care Generate a clock once. Read the Nth data word. TMP1941AF-208 2003-03-27 TMP1941AF (2) Slave Mode (SBI0CR2.MST = 0) If the MST bit in the SBI0CR2 is cleared, the SBI is in slave mode. In slave mode, the SBI generates the INTS2 interrupt on four occasions: 1) when the SBI has received any slave address; 2) when the SBI has received a general-call address; 3) when the received slave address matches its own address in the I2C0AR; and 4) when a data transfer has been completed in response to a general-call. Also, if the SBI, as a master, loses arbitration for the I2C bus, it switches to slave mode. If arbitration is lost during a data transfer, SCL continues to be generated until the data word is complete; then the INTS2 interrupt is generated. When the INTS2 interrupt occurs, the PIN bit in the SBI0SR is cleared, and the SCL line is pulled low. When the SBI0DBR is read or written or when the PIN bit is set back to 1, the SCL line is released after a period of tLOW. Processing to be done in slave mode varies, depending on whether or not the SBI has switched over to slave mode as a result of lost arbitration. Test the AL, TRX, AAS and AD0 bits in the SBI0SR to determine the processing required, as summarized in Table 14.2. Example: When the received slave address matches the SBI's own address and the data direction ( R / W ) bit is 1 INTS2 interrupt if TRX = 0 Then go to other processing if AL = 1 Then go to other processing if AAS = 0 Then go to other processing SBI0CR1 X X X 1 0 X X X SBI0DBR X X X X 0 X X X X = Don't care Set the number of bits to be transmitted. Load the transmit data. TMP1941AF-209 2003-03-27 TMP1941AF Table 14.2 Processing in Slave Mode TRX 1 AL 1 AAS AD0 1 0 State Arbitration was lost while the slave address was being transmitted, and the SBI received a slave address with the direction bit set transmitted by another master. In slave-receiver mode, the SBI received a slave address with the direction bit set transmitted by the master. Processing Set the SBI0CR1.BC[2:0] field to the number of bits in a data word and write the transmit data into the SBI0DBR. 0 1 0 0 0 In slave-transmitter mode, the SBI has Test the SBI0SR.LRB bit. If the LRB bit is completed a transmission of one data word. set, that means the master-receiver does not require further data. Set the SBI0CR2.PIN bit to 1 and clear the TRX bit to 0 to release the bus. If the LRB bit is cleared, that means the master-receiver requires further data. Set the SBI0CR1.BC[2:0] field to the number of bits in the data word and write the transmit data to the SBI0DBR. Read the SBI0DBR (a dummy read) to set Arbitration was lost while a slave address was being transmitted, and received either a the SBI0CR2.PIN bit to 1, or write a 1 to slave address with the direction bit cleared this bit. or a general-call address transmitted by another master. Arbitration was lost while a slave address or a data word was being transmitted, and the transfer terminated. In slave-receiver mode, the SBI received either a slave address with the direction bit cleared or a general-call address transmitted by the master. In slave-receiver mode, the SBI has completed a reception of a data word. Set the SBI0CR1.BC[2:0] field to the number of bits in the data word and read the received data from the SBI0DBR. 0 1 1 1/0 0 0 0 1 1/0 0 1/0 14.6.4 Generating a STOP Condition When the SBI0SR.BB bit is set, setting the MST, TRX and PIN bits in the SBI0CR2 to 1 and clearing the BB bit in the same register causes the SBI to start a sequence for generating a STOP condition on the I2C bus. Do not alter the contents of these bits until the STOP condition is present on the bus. If another device is holding down the SCL bus line, the SBI waits until the SCL line is released (high) again; when SCL is high, the SBI drives the SDA pin high to generate a STOP condition. 76543210 SBI0CR2 1 1 0 1 1 0 0 0 1 MST 1 TRX 0 BB 1 PIN SCL Pin SDA Pin Generate a STOP condition. STOP Condition PIN Bit BB Bit (read) Figure 14.17 Generating a STOP Condition TMP1941AF-210 2003-03-27 TMP1941AF 14.6.5 Repeated START Condition A data transfer is always terminated by a STOP condition. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave or change the data direction without first generating a STOP condition. The following describes the steps required to generate a repeated START condition. First, clear the MST, TRX and BB bits in the SBI0CR2 and set the PIN bit in the same register to release the bus. This causes the SDA pin to be held high and the SCL pin to be released. Because no STOP condition is generated on the bus, other devices think that the bus is busy. Then, poll the SBI0SR.BB bit until it is cleared to ensure that the SCL pin is released. Next, poll the LRB bit until it is set to ensure that no other device is pulling the SCL bus line low. Once the bus is determined to be free this way, use the steps described in Section 14.6.2 to generate a START condition. To satisfy the minimum setup time of the START condition, in Standard-mode, at least 4.7-s wait period must be created by software after the bus becomes free. 76543210 SBI0CR2 0 0 0 1 1 0 0 0 if SBI0SR Release the bus. Check that the SCL pin is released. Check that no other device is pulling the SCL line low. 4.7-s Wait SBI0CR1 X X X 1 0 X X X SBI0DBR X X X X X X X X SBI0CR2 1 1 1 1 1 0 0 0 X = Don't care Select Acknowledge mode. Load a slave address and the direction bit. Generate a START condition. 0 MST 0 TRX 0 BB 1 PIN 1 MST 1 TRX 1 BB 1 PIN 4.7 s (min) START Condition SCL Bus Line SCL Pin SDA Pin LRB Bit BB Bit PIN Bit 9 Figure 14.18 Repeated START Condition TMP1941AF-211 2003-03-27 TMP1941AF 14.7 Description of Registers Used in Clock-Synchronous 8-Bit SIO Mode This section provides a summary of the registers which control clock-synchronous 8-bit SIO operation and provides its status information for monitoring. Serial Bus Interface Control Register 1 7 SBI0CR1 (0xFFFF_F240) Name Read/Write Reset Value 0 Start transfer 0: Stop 1: Start 0 Abort transfer 0: Continue 1: Abort SIOS 6 SIOINH W 5 SIOM1 0 4 SIOM0 0 3 2 SCK2 W 0 1 SCK1 0 0 SCK0 R/W 1 Function Transfer mode 00: Transmit mode 01: Reserved 10: Transmit/Receive mode 11: Receive mode Serial clock frequency / Software reset monitor On writes: SCK[2:0] = Serial clock frequency 000 001 010 011 100 101 110 111 n=3 1.25 MHz n=4 625 kHz n = 5 312.5 kHz n = 6 156.3 kHz n = 7 78.13 kHz n = 8 39.06 kHz n = 9 19.53 kHz External clock Assumptions: System clock: fc (= 40 MHz) Clock gear: fc/1 T0 = fperiph/4 (= 10 MHz) T0 Frequency = n (Hz) 2 Note: Clear the SIOS bit and set the SIOINH bit before programming the transfer mode and serial clock frequency bits. Serial Bus Interface Data Buffer Register 7 SBI0DBR (0xFFFF_F241) Name Read/Write Reset Value DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (receive)/ W (transmit) Undefined Figure 14.19 SIO Mode Registers (1) TMP1941AF-212 2003-03-27 TMP1941AF Serial Bus Interface Control Register 2 7 SBI0CR2 (0xFFFF_F243) Name Read/Write Reset Value 6 5 4 3 SBIM1 W 0 2 SBIM0 0 1 0 Function SBI operating mode 00: Port mode 01: Clock-Synchronous 8-Bit SIO mode 10: I2C Bus mode 11: Reserved Serial Bus Interface Register 7 SBI0SR (0xFFFF_F243) Name Read/Write Reset Value 6 5 4 3 SIOF R 0 Serial transfer status 2 SEF 0 Shift operation status 1 0 Function 0: Terminated 1: In progress Serial Bus Interface Baud Rate Register 0 7 SBI0BR0 (0xFFFF_F244) Name Read/Write Reset Value Function 6 I2SBI0 R/W 0 IDLE 0: Off 1: On 5 4 3 2 1 0 W Must be written as 0. Serial Bus Interface Baud Rate Register 1 7 SBI0BR1 (0xFFFF_F245) Name Read/Write Reset Value P4EN R/W 0 Internal clock 0: Off 1: On 6 5 4 3 2 1 0 Must be written as 0. Function Figure 14.20 SIO Mode Registers (2) TMP1941AF-213 2003-03-27 TMP1941AF 14.8 Clock-Synchronous 8-Bit SIO Mode Operation 14.8.1 Serial Clock (1) Clock Source The clock source for the SIO mode can be selected from internal and external clocks through the programming of the SCK[2:0] field in the SBI0CR1. * Internal clocks One of the seven internal clocks can be used as a serial clock, which is driven onto the SCK pin. At the beginning of a transfer, the SCK clock will start out at logic high. If software is slow and the reading of the received data or the writing of the transmit data can not keep up with the serial clock rate, the SBI automatically inserts a wait period, as shown below. During this period, the serial clock is temporarily stopped to suspend a shift operation. Automatically inserted wait period SCK Output 1 2 3 7 8 1 2 6 7 8 1 2 3 SO Output Writes of the transmit data a0 a a1 a2 a5 a6 a7 b0 b b1 b4 c b5 b6 b7 c0 c1 c2 Figure 14.21 Automatic Wait Insertion * External clock (SBI0CR1.SCK[2:0] = 111) If the SCK[2:0] field in the SBI0CR1 contains 111, the SBI uses an external clock supplied from the SCK pin as a serial clock. For proper shift operations, the clock high width and the clock low width must satisfy the following relationship. SCK Pin tSCKL tSCKH tSCKL, tSCKH > 8/fsys Figure 14.22 Maximum External Clock Frequency TMP1941AF-214 2003-03-27 TMP1941AF (2) Shift Edge Types In transmit mode, leading-edge shift is used. In receive mode, trailing-edge shift is used. * Leading-edge shift Every bit of SIO data is shifted by the leading edge of the serial clock (falling edge of SCK). * Trailing-edge shift Every bit of SIO data is shifted by the trailing edge of the serial clock (rising edge of SCK). SCK Pin SO Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Shift Register 76543210 *7654321 **765432 ***76543 ****7654 *****765 ******76 ******7 (a) Leading-Edge Shift SCK Pin SI Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Shift Register ******** 0******* 10****** 210***** 3210**** 43210*** 543210** 6543210* 76543210 (b) Trailing-Edge Shift Figure 14.23 Shift Edge Types TMP1941AF-215 2003-03-27 TMP1941AF 14.8.2 SIO Transfer Modes The SBI supports three SIO transfer modes: receive mode, transmit mode and transmit/receive mode. The SIOM[1:0] field in the SBI0CR1 is used to select a transfer mode. (1) 8-Bit Transmit Mode Configure the SIO interface in transmit mode and write the transmit data into the SBI0DBR. Then setting the SIOS bit in the SBI0CR1 initiates a transmission. The contents of the SBI0DBR is moved to an internal shift register and then shifted out on the SO pin, with the least-significant bit (LSB) first, synchronous to the serial clock. Once the transmit data is transferred to the shift register, the SBI0DBR becomes empty, and the buffer-empty interrupt (INTS2) is generated. In internal clock mode, the SIO interface will be in wait state (SCK will stop) until the INTS2 interrupt service routine provides the next transmit data to the SBI0DBR. Once the SBI0DBR is loaded, the SIO interface will automatically get out of the wait state. In external clock mode, the INTS2 interrupt service routine must provide the next transmit data to the SBI0DBR before the previous transmit data has been shifted out. Therefore, the data rate is a function of the maximum latency between when the INTS2 interrupt is generated and when the SBI0DBR is loaded by the interrupt service routine. At the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the SO pin between when the SBI0SR.SIOF bit is set and when SCK subsequently goes low. Transmission can be terminated by the INTS2 interrupt service routine clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, the remaining bits in the SBI0DBR continue to be shifted out before transmission ends. In this case, software can check the SBI0SR.SIOF bit to determine whether transmission has come to an end (0 = end-of-transmission). If the SIOINH bit is set, the ongoing transmission is aborted immediately, and the SIOF bit is cleared at that point. In external clock mode, the SIOS bit must be cleared before the SIO interface begins shifting out the next transmit data. Otherwise, the SIO will stop after sending out dummy data. 76543210 SBI0CR1 0 1 0 0 0 X X X SBI0DBR X X X X X X X X SBI0CR1 1 0 0 0 0 X X X Select transmit mode. Write the transmit data. Start transmission. INTS2 interrupt SBI0DBR X X X X X X X X Write the next transmit data. TMP1941AF-216 2003-03-27 TMP1941AF The SIOS bit is cleared. SIOS Bit SIOF Bit SEF Bit SCK Output SO Pin INTS2 Interrupt Request SBI0DBR a b * a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Writes of the transmit data (a) Internal Clock Mode The SIOS bit is cleared. SIOS Bit SIOF Bit SEF Bit SCK Input SO Pin INTS2 Interrupt Request SBI0DBR a b * a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Writes of the transmit data (b) External Clock Mode Figure 14.24 Transmit Mode Example: MIP16 code to terminate transmission by SIOS (external clock mode) ADDIU : LB AND BNEZ ADDIU : LB AND BEQZ ADDIU STB r3, r0, 0x04 r2,(SBI0SR) r2, r3 r2, STEST1 r3, r0, 0x20 r2, (PA) r2, r3 r2, STEST2 r3, r0, 0x00000111 r3, (SBI0CR1) STEST1 ; If SBI0SR.SEF = 1 then loop STEST2 ; If SCK = 0 then loop ; SIOS 0 TMP1941AF-217 2003-03-27 TMP1941AF SCK Pin SIOF Bit SO Pin bit 6 bit 7 tSODH = 3.5 / fsys /2 seconds (min.) Figure 14.25 Retention Time of the Last Transmitted Bit (2) 8-Bit Receive Mode Configure the SIO interface in receive mode. Then setting the SIOS bit in the SBI0CR1 enables reception. The receive data is clocked into the internal shift register via the SI pin, synchronous to the serial clock. Once the shift register is fully loaded, the received byte is transferred to the SBI0DBR, and the buffer-full interrupt (INTS2) is generated. The INTS2 interrupt service routine must then pick up the received data from the SBI0DBR. In internal clock mode, the SIO interface will be in wait state (SCK will stop) until the INTS2 interrupt service routine reads the data from the SBI0DBR. In external clock mode, shift operations continue, synchronous to the external clock. In this mode, the maximum data rate is a function of the maximum latency between when the INTS2 interrupt is generated and when the SBI0DBR is read by the interrupt service routine. Reception can be terminated by the INTS2 interrupt service routine clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, reception continues until the shift register is fully loaded and transferred to the SBI0DBR. In this case, software can check the SBI0SR.SIOF bit to determine whether reception has come to an end (0 = end-of-reception). If the SIOINH bit is set, the ongoing reception is aborted immediately, and the SIOF bit is cleared at that point. (The received data becomes invalid; there is no need to read it out.) Note: The contents of the SBI0DBR is not preserved after changing the transfer mode. Before changing the transfer mode, clear the SIOS bit to complete the ongoing reception and have the INTS2 interrupt service routine pick up the last received data. 76543210 SBI0CR1 0 1 1 1 0 X X X SBI0CR1 1 0 1 1 0 0 0 0 INTS2 interrupt Reg. Select receive mode. Start reception. SBI0DBR Read the received data. TMP1941AF-218 2003-03-27 TMP1941AF The SIOS bit is cleared. SIOS Bit SIOF Bit SEF Bit SCK Output SI Pin IINTS2 Interrupt Request SBI0DBR a Read of the received data b Read of the received data a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Figure 14.26 Receive Mode (Internal Clock Mode) (3) 8-Bit Transmit/Receive Mode Configure the SIO interface in transmit/receive mode and write the transmit data into the SBI0DBR. Then setting the SIOS bit in the SBI0CR1 initiates transmission and reception. The transmit data is shifted out through the SO pin, with the least-significant bit (LSB) first, with the falling edge of the serial clock, while at the same time the receive data is shifted in through the SI pin with the rising edge of the serial clock. Once the shift register is fully loaded with eight bits of the received data, it is transferred to the SBI0DBR, and the INTS2 interrupt is generated. The INTS2 interrupt service routine must then pick up the received data from the SBI0DBR and writes the next transmit data into the SBI0DBR. Because the SBI0DBR is shared between transmit and receive operations, the received data must be read before the next transmit data is written. In internal clock mode, the SIO interface will be in wait state (SCK will stop) after a read of the received data until a write of the transmit data. In external clock mode, shift operations continue, synchronous to the external clock. Therefore, software must read the received data and write the transmit data before the next shift operation begins. In this mode, the maximum data rate is a function of the maximum latency between when the INTS2 interrupt is generated and when the interrupt service routine reads the received data and writes the transmit data. At the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the SO pin between when the SBI0SR.SIOF bit is set and when SCK subsequently goes low. Transmission/reception can be terminated by the INTS2 interrupt service routine clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, reception continues until the shift register is fully loaded and transferred to the SBI0DBR. In this case, software can check the SBI0SR.SIOF bit to determine whether transmission/reception has come to an end (0 = end-ofreception/transmission). If the SIOINH bit is set, the ongoing transmission/reception is aborted immediately, and the SIOF bit is cleared at that point. Note: The contents of the SBI0DBR is not preserved after changing the transfer mode. Before changing the transfer mode, clear the SIOS bit to complete the ongoing transmission/reception and have the INTS2 interrupt service routine pick up the last received data. TMP1941AF-219 2003-03-27 TMP1941AF The SIOS bit is cleared. SIOS Bit SIOF Bit SEF Bit SCK Output SO Pin SI Pin IINTS2 Interrupt Request SBI0DBR a c b d (d) Read of the received data * a0 c0 a1 c1 a2 c2 a3 c3 a4 c4 a5 c5 a6 c6 a7 c7 b0 d0 b1 d1 b2 d2 b3 d3 b4 d4 b5 d5 b6 d6 b7 d7 (a) Write of the transmit data (c) Read of the (b) Write of the received data transmit data Figure 14.27 Receive/Transmit Mode (Internal Clock Mode) SCK Pin SIOF Bit SO Pin bit 6 Bit 7 of the last byte transmitted tSODH = 4/fsys/2 seconds (min.) Figure 14.28 Retention Time of the Transmit Data in Receive/Transmit Mode 76543210 SBI0CR1 0 1 1 0 0 X X X SBI0DBR X X X X X X X X SBI0CR1 1 0 1 0 0 X X X INTS2 interrupt Select receive/transmit mode. Write the transmit data. Start reception/transmission. SBI0DBR SBI0DBR X X X X X X X X Reg. Read the received data. Write the transmit data. TMP1941AF-220 2003-03-27 TMP1941AF 15. Analog-to-Digital Converter (ADC) The TMP1941AF has a 8-channel, multiplexed-input, 10-bit successive-approximation ananlog-to-digital converter (ADC). Figure 15.1 shows a block diagram of the ADC. The eight analog input channels (AN0-AN7) can be used as general-purpose digital inputs (Port 5) if not needed as analog channels. Note: Ensure that the ADC has halted before executing an insturction to place the TMP1941AF in IDLE, SLEEP or STOP mode to reduce power supply current. Otherwise, the TMP1941AF might go into a standby mode while the internal analog comparator is still active. In SLOW mode, the ADC must be disabled. Internal Data Bus Internal Data Bus Internal Data Bus A/D Mode Control Register 1 (ADMOD1) ADTRGE ADCH[2:0] VREFON A/D Mode Control Register 0 (ADMOD0) EOCF ADBF ITM0 REPEAT SCAN ADS scan Channel Selection Control Circuit busy end start Interrupt Request (INTAD) repeat interrupt ADTRG A/D Converter Control Circuit AN7 (P57) AN6 (P56) AN5 (P55) AN4 (P54) AN3/ ADTRG (P53) AN2 (P52) AN1 (P51) AN0 (P50) Multiplexer Sample-andHold + - Comparator A/D Conversion Result Registers (ADREG04L-37L) (ADREG04H-37H) VREFH VREFL D/A Converter Figure 15.1 ADC Block Diagram TMP1941AF-221 2003-03-27 TMP1941AF 15.1 Register Description The ADC has two mode control registers (ADMOD0 and ADMOD1), four conversion result high/low register pairs (ADREG04H/L, ADREG15H/L, ADREG26H/L, ADREG37H/L) and a clock select register (ADCCLK). The conversion result registers contain the digital values of completed conversions. The clock select register selects an A/D conversion clock. Figure 15.2 to Figure 15.6 show the registers available in the ADC. A/D Mode Control Register 0 7 Name ADMOD0 (0xFFFF_F310) Read/Write Reset Value EOCF R 0 End-ofconversion flag Function 0 A/D conversion busy flag 0 0 0 6 ADBF 5 4 3 ITM0 R/W 2 REPEAT 0 1 SCAN 0 Channel scan mode 0: Fixedchannel 1: Channel scan 0 ADS 0 A/D conversion start 0: Don't care 1: Start This bit is always read as 0. 0: Before or 0: Idle during 1: During conversion conversion 1: Completed Must be Must be Interrupt Continuous written as 0. written as 0. See below. conversion mode 0: Single 1: Continuous Interrupt in fixed-channel continuous conversion mode Fixed-Channel Continuous Conversion Mode SCAN = 0, REPEAT = 1 0 1 Generates INTAD interrupt when a single conversion has been completed. Generates INTAD interrupt when a sequence of four conversions has been completed. Note: The EOCF bit is cleared when read. Figure 15.2 A/D Mode Control Register 0 (ADMOD0) TMP1941AF-222 2003-03-27 TMP1941AF A/D Mode Control Register 1 7 ADMOD1 (0xFFFF_F311) Read/Write Reset Value Function Name VREFON R/W 0 VREF control 0: Off 1: On 6 I2AD R/W 0 ADC operation in IDLE mode 0: Off 1: On 5 4 3 ADTRGE 0 2 ADCH2 R/W 0 1 ADCH1 0 0 ADCH0 0 Analog input channel select External conversion trigger 0: Disable 1: Enable Analog Input Channel Select SCAN ADCH[2:0] 000 001 010 011 (Note) 100 101 110 111 0 Fixed-Channel Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 1 Channel Scan Mode AN0 AN0AN1 AN0AN1AN2 AN0AN1AN2AN3 AN4 AN4AN5 AN4AN5AN6 AN4AN5AN6AN7 A/D external conversion trigger ( ADTRG input) 0 1 Disable Enable Note 1: Set the VREFON bit to 1 before setting the ADS bit in the ADMOD0 to start a conversion. Note 2: The AN3 pin is shared with the ADTRG pin. Therefore, when the external conversion trigger input ( ADTRG ) is enabled (i.e., when ADMOD1.ADTRGE = 1), the ADCH[2:0] field must not be programmed to 011. Figure 15.3 A/D Mode Control Register (ADMOD1) TMP1941AF-223 2003-03-27 TMP1941AF A/D Conversion Result Low Register 0/4 7 Name ADREG04L (0xFFFF_F300) Read/Write Reset Value Function ADR01 R Undefined Lower 2 bits of an A/D conversion result 6 ADR00 5 4 3 2 1 0 ADR0RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 0/4 7 Name ADREG04H (0xFFFF_F301) Read/Write Reset Value Function ADR09 6 ADR08 5 ADR07 4 ADR06 R Undefined 3 ADR05 2 ADR04 1 ADR03 0 ADR02 Upper 8 bits of an A/D conversion result A/D Conversion Result Low Register 1/5 7 Name ADREG15L (0xFFFF_F302) Read/Write Reset Value Function ADR11 R Undefined Lower 2 bits of an A/D conversion result 6 ADR10 5 4 3 2 1 0 ADR1RF R 0 Conversion result store flag 1: Stored A/D Conversion Result High Register 1/5 7 Name ADREG15H (0xFFFF_F303) Read/Write Reset Value Function 9 Channel x conversion result bits ADREGxH 765 ADREGxL 210 8 ADR19 6 ADR18 5 ADR17 4 ADR16 R Undefined 3 ADR15 2 ADR14 1 ADR13 0 ADR12 Upper 8 bits of an A/D conversion result 7 6 5 4 3 2 1 0 4 3 2 1 0 7 6 5 4 3 Note 1: Bits 5-1 are always read as 1s. Note 2: Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the ADREGxH/L register pair. This bit is cleared when either the ADREGxH or the ADREGxL is read. Figure 15.4 A/D Convesion Result High/Low Registers (1) TMP1941AF-224 2003-03-27 TMP1941AF A/D Conversion Result Low Register 2/6 7 Name ADREG26L (0xFFFF_F304) Read/Write Reset Value ADR21 R Undefined Lower 2 bits of an A/D conversion result 6 ADR20 5 4 3 2 1 0 ADR2RF R 0 Conversion result store flag 1: Stored Function A/D Conversion Result High Register 2/6 7 ADREG26H (0xFFFF_F305) Read/Write Reset Value Function Name ADR29 6 ADR28 5 ADR27 4 ADR26 R Undefined 3 ADR25 2 ADR24 1 ADR23 0 ADR22 Upper 8 bits of an A/D conversion result A/D Conversion Result Low Register 3/7 7 Name ADREG37L (0xFFFF_F306) Read/Write Reset Value ADR31 R Undefined Lower 2 bits of an AD conversion result 6 ADR30 5 4 3 2 1 0 ADR3RF R 0 Conversion result store flag 1: Stored Function A/D Conversion Result High Register 3/7 7 Name ADREG37H (0xFFFF_F307) Read/Write Reset Value Function 9 Channel x conversion result bits ADREGxH 765 ADREGxL 210 8 ADR39 6 ADR38 5 ADR37 4 ADR36 R Undefined 3 ADR35 2 ADR34 1 ADR33 0 ADR32 Upper 8 bits of A/D conversion result 7 6 5 4 3 2 1 0 4 3 2 1 0 7 6 5 4 3 Note 1 Note 2 Bits 5-1 are always read as 1s. Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the ADREGxH/L register pair. This bit is cleared when either the ADREGxH or the ADREGxL is read. Figure 15.5 A/D Conversion Result High/Low Registers (2) TMP1941AF-225 2003-03-27 TMP1941AF A/D Conversion Clock Select Register 7 ADCCLK (0xFFFF_EE04) Read/Write Reset Value Function Name 6 5 4 3 2 1 ADCCK1 R/W 0 0 ADCCK0 R/W 0 A/D conversion clock (fadc) select 00: fsys/2 01: fsys/4 10: fsys/8 11: Reserved Note 1: The ADC operates off the selected A/D conversion clock, which must be selected from Table 15.3, Conversion Time, to assure conversion accuracy. Note 2: Programming the ADCCLK register should only be attempted when an A/D conversion is not in progress. Figure 15.6 A/D Conversion Clock Select Register (ADCCLK) TMP1941AF-226 2003-03-27 TMP1941AF 15.2 Operation 15.2.1 Analog Reference Voltages The VREFH and VREFL pins provide the reference voltages for the ADC. These pins estabilish the full-scale range for the internal resistor string, which divides the range into 1024 steps. The digital result of the conversion is derived by comparing the sampled analog input voltage to the resistor string voltages. Clearing the VREFON bit in the ADMOD1 turns off the switch between VREFH and VREFL. Once the VREFON bit is cleared, the internal reference voltage requires a recovery time of 3 s to stabilize after the VREFON bit is again set to 1. This recovery time is independent of the system clock frequency. The ADS bit in the ADMOD0 must then be set to initiate an conversion. 15.2.2 Selecting an Analog Input Channel (s) There are two basic conversion modes: fixed-channel mode and channel scan mode. The SCAN bit in the ADMOD0 affects the conversion channel(s) that will be selected as follows. * Fixed-channel mode (ADMOD0.SCAN = 0) When the SCAN bit in the ADMOD0 is cleared, the ADC runs conversions on a single input channel selected from AN0-AN7 via the ADCH[2:0] field in the ADMOD1. * Channel scan mode (ADMOD0.SCAN = 1) When the SCAN bit in the ADMOD0 is set, the ADC runs conversions on sequential channels in a specific group selected via the ADCH[2:0] field in the ADMOD1. Refer to Table 15.1. After a reset, the ADMOD0.SCAN bit defaults to 0, and the ADMOD1.ADCH[2:0] field defaults to 000. Thus, the AN0 pin is selected as the conversion channel. The AN0-AN7 pins can be used as general-purpose input ports if not used as analog input channels. Table 15.1 Analog Input Channel Selection ADMOD1.ADCH[2:0] 000 001 010 011 100 101 110 111 Fixed-Channel Mode ADMOD1.SCAN = 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Channel Scan Mode ADMOD0.SCAN = 1 AN0 AN0AN1 AN0AN1AN2 AN0AN1AN2AN3 AN4 AN4AN5 AN4AN5AN6 AN4AN5AN6AN7 15.2.3 Starting an A/D Conversion The ADC initiates a conversion or a sequence of conversions when the ADS bit in the ADMOD0 is set, or when a falling edge is applied to the ADTRG pin if the ADTRGE bit in the ADMOD1 is set. When a conversion starts, the Busy flag (ADMOD0.ADBF) is set. Writing a 1 to the ADS bit causes the ADC to abort any ongoing conversion and start sampling the selected channel to begin a new conversion. The Conversion Result Store flag (ADREGxL.ADRxRF) indicates whether the result register contains a valid digital result at that point. In external conversion trigger mode, a falling edge on the ADTRG pin is ignored while a conversion is in progress. TMP1941AF-227 2003-03-27 TMP1941AF 15.2.4 Conversion Modes and Conversion-Done Interrupts The ADC supports the following four conversion modes: * * * * Fixed-channel single conversion mode Channel scan single conversion mode Fixed-channel continuous conversion mode Channel scan continuous conversion mode The REPEAT and SCAN bits in the ADMOD1 select the conversion mode. The ADC generates the INTAD interrupt and sets the EOCF bit in the ADMOD0 at the end of the conversion process. * Fixed-Channel Single Conversion Mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 00. In this mode, the ADC performs a single conversion on a single selected channel. When a conversion is completed, the ADC sets the ADMOD0.EOCF bit, clears the ADMOD0.ADBF bit and generates the INTAD interrupt. * Channel Scan Single Conversion Mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 01. In this mode, the ADC performs a single conversion on each of a selected group of channels. When a single conversion sequence is completed, the ADC sets the ADMOD0.EOCF bit, clears the ADMOD0.ADBF bit and generates the INTAD interrupt. * Fixed-Channel Continuous Conversion Mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 10. In this mode, the ADC repeatedly converts a single selected channel. When a conversion process is completed, the ADC sets the ADMOD.EOCF bit. The ADMOD0.ADBF bit remains set. The ITM0 bit in the ADMOD0 controls interrupt generation in this mode. If the ITM0 bit is cleared, the ADC generates an interrupt after each conversion. If the ITM0 bit is set, the ADC generates an interrupt after every four conversions. * Channel Scan Continuous Conversion Mode This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 11. In this mode, the ADC repeatedly converts the selected group of channels. When a single conversion sequence is completed, the ADC sets the ADMOD0.EOCF bit and generates the INTAD interrupt. The ADMOD0.ADBF bit remains set. In continuous conversion modes, clearing the ADMOD0.REPEAT bit stops the conversion sequence after the ongoing conversion process is completed. If the I2AD bit in the ADMOD1 is cleared, putting the TMP1941AF in any standby mode (IDLE, SLEEP or STOP) causes the ADC to be immediately disabled, even if a conversion is in progress. Once the TMP1941AF exits the standby mode, the ADC restarts a conversion sequence when in a continuous conversion mode, but remains inactive when in a single conversion mode. Table 15.2 summarizes interrupt request generation in each of the conversion modes. TMP1941AF-228 2003-03-27 TMP1941AF Table 15.2 Interrupt Request Generation in Each AD Conversion Mode Mode Fixed-Channel Single Conversion Mode Channel Scan Single Conversion Mode Fixed-Channel Continuous Conversion Mode Channel Scan Continuous Conversion Mode X = Don't care Interrupt Request Generation After a conversion After a scan conversion sequence After each conversion After every four conversions After each scan conversion sequence ADMOD0 ITM0 X X 0 1 X REPEAT 0 0 1 1 SCAN 0 1 0 1 15.2.5 Conversion Time The conversion process requires 86 conversion clocks per channel. For example, this results in a conversion time of 8.6 s with 10-MHz fadc. The A/D conversion clock can be selected from fsys/2, fsys/4 and fsys/8 through the programming of the ADCCK[1:0] field in the ADCCLK register. To assure conversion accuracy, conversion time must be no shorter than 8.6 s. Table 15.3 Conversion Time Conversion Clock fsys 40 MHz 32 MHz 20 MHz 16 MHz 10 MHz 8 MHz fsys/2 Don't use. Don't use. 8.6 s 10.75 s 17.2 s 21.5 s fsys/4 8.6 s 10.75 s 17.2 s 21.5 s 34.4 s 43.0 s fsys/8 17.2 s 21.5 s 34.4 s 43.0 s 68.8 s 86.0 s 15.2.6 Storing and Reading the A/D Conversion Result Conversion results are loaded into conversion result high/low register pairs (ADREG04H/L to ADREG37H/L). These registers are read-only. In fixed-channel continuous conversion mode, conversion data goes into the ADREG04H/L to the ADREG37H/L sequentially. In other modes, channels AN0 and AN4 share the ADREG04H/L; channels AN1 and AN5 share the ADREG15H/L; channels AN2 and AN6 share the ADREG26H/L; and channels AN3 and AN7 share the ADREG37H/L. Table 15.4 shows the relationships between the analog input channels and the A/D conversion result registers. TMP1941AF-229 2003-03-27 TMP1941AF Table 15.4 Relationships Between Analog Input Channels and A/D Conversion Result Registers A/D Conversion Result Register Analog Input Channel (Port 5) Fixed-Channel Continuous Conversion Mode (for each sequence of four conversions) ADREG04H/L ADREG15H/L ADREG26H/L ADREG37H/L Other Modes AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADREG04H/L ADREG15H/L ADREG26H/L ADREG37H/L ADREG04H/L ADREG15H/L ADREG26H/L ADREG37H/L Bit 0 (ADRxRF) in each ADREGxL register indicates whether the conversion result has been read. This bit is set when the conversion result is loaded into the ADREGxH/L pair, and cleared when either the ADREGxH or ADREGxL is read. Reading the conversion result clears the End-of-Conversion flag (ADMOD0.EOCF). TMP1941AF-230 2003-03-27 TMP1941AF 15.3 Programming Examples * Converting the analog input voltage on the AN3 pin to a digital value and storing the converted value in a memory location (0xFFFF_B800) using an A/D interrupt (INTAD) handler routine Settings in the main routine IMCEHH ADMOD1 ADMOD0 765 XX0 1XX XX0 4 1 X 0 3 0 0 0 2 1 0 0 1 0 1 0 0 0 1 1 Enables INTAD and sets its priority level to 4. Selects AN3 as the analog input channel. Starts conversion in fixed-channel single conversion mode. Interrupt routine processing example r4 r4 ADREG37 >>6 r4 (FFFFB800H) Loads the conversion result into general-purpose register r4 from ADREG37L and ADREG37H. Shifts the contents of r4 six bits to the right, padding 0s to the vacated MSB bits. Stores the contents of r4 to address 0xFFFF_B800. * Converting the analog input voltages on AN0-AN2 sequentially in channel scan continuous conversion mode IMCEHH ADMOD1 ADMOD0 X = Don't care Notes: The ADC supports both polled and interrupt-driven operation. The CPU can perform polling operation to detect completion of a conversion. * * * Don't poll the ADRxRF bit in the ADREGxxL register. In single conversion modes, poll the ADBF bit in the ADMOD0. In any conversion modes, the EOCF bit in the ADMOD0 can be polled. After the EOCF bit is set, one or two fadc clocks are required as shown below before the ADREGxH/L can be read. Conversion Mode Time Required Before Reading the ADREGxx Fixed-channel single conversion mode Fixed-channel continuous conversion mode Channel scan single scan conversion mode Channel scan continuous conversion mode fadc: A/D conversion clock selected by the ADCCLK register 1 fadc clock 1 fadc clock 2 fadc clocks 2 fadc clocks XX010000 1XXX0011 XX000001 Disables INTAD. Selects AN0-AN2 as analog input channels. Starts conversion in channel scan continuous conversion mode. TMP1941AF-231 2003-03-27 TMP1941AF 16. Watchdog Timer (WDT) The TMP1941AF contains a watchdog timer (WDT). The WDT is used to regain control of the system in the event of software or system lockups due to spurious noises, etc. When a watchdog timer time-out occurs, the WDT generates a nonmaskable interrupt to the CPU. Also, the time-out event can be programmed for system reset generation, which is accomplished by routing the time-out signal to the internal reset pin. 16.1 Implementation Figure 16.1 shows a block diagram of the WDT. WDMOD.RESCR RESET Pin Reset Control Internal Reset Interrupt Request (INTWDT) WDMOD. WDTP[1:0] Selector 21 215 217 219 2 Q fsys/2 22-Stage Binary Counter Reset R S Internal Reset WDMOD.WDTE Write of 4EH Write of B1H Watchdog Timer Control Register (WDCR) Internal Data Bus Figure 16.1 WDT Block Diagram TMP1941AF-232 2003-03-27 TMP1941AF The WDT contains a 22-stage binary counter clocked by the fsys/2 clock. This binary counter provides 215, 217, 219 or 221 as a counter overflow signal, as programmed into the WDTP[1:0] field in the WDMOD. When a counter overflow occurs, the WDT generates a WDT interrupt, as shown below. WDT Counter Overflow 0 n WDT Interrupt A write of a special clear-count code WDT Clear (via software) Figure 16.2 Default Operation Also, the counter overflow can be programmed to cause a system reset as the time-out action. If so programmed, a counter overflow causes the WDT to assert the internal reset signal for a 22- to 29-state time. After a reset, the fsys clock is, by default, generated by dividing the high-speed oscillator clock (fc) by eight through the clock gear function; the WDT clock source (fsys/2) is derived from this fsys clock. Overflow WDT Counter n WDT Interrupt Internal Reset 22-29 States (8.8-11.6 s @ fc = 40 MHz, fsys = 5 MHz, fsys/2 = 2.5 MHz) Note: The TMP1941AF continues sampling the PLLOFF pin during a reset operation caused by the WDT. Therefore, the PLLOFF pin must be tied to either logic high or logic low. Figure 16.3 Reset Operation TMP1941AF-233 2003-03-27 TMP1941AF 16.2 Register Description The WDT is controlled by two registers called WDMOD and WDCR. 16.2.1 Watchdog Timer Mode Register (WDMOD) * Time-out Period (WDMOD.WDTP[1:0]) This 2-bit field determines the duration of the WDT time-out interval. Upon reset, the WDTP[1:0] field defaults to 00. Figure 16.5 shows possible time-out periods. * WDT Enable (WDMOD.WDTE) Upon reset, the WDTE bit is set to 1, enabling the WDT. To disable the WDT, the clearing of the WDTE bit must be followed by a write of a special key code (B1H) to the WDCR register. This prevents a "lost" program from disabling the WDT operation. The WDT can be re-enabled only by setting the WDTE bit. * System Reset (WDMOD.RESCR) This bit is used to program the WDT to generate a system reset on a time-out. Upon reset, this bit is cleared; thus the time-out does not cause a system reset. 16.2.2 Watchdog Timer Control Register (WDCR) This register is used to disable the WDT and to clear the WDT binary counter. * Disabling the WDT The WDT can be disabled by clearing the WDMOD.WDTE to 0 and then writing the special disable code (B1H) to the WDCR register. WDMOD WDCR 0- - - - - - - 10110001 Clears the WDTE bit to 0. Writes the disable code (B1H) to the WDCR. * Enabling the WDT The WDT can be enabled only by setting the WDTE bit in the WDMOD to 1. * Clearing the WDT counter Writing the special clear-count code (4EH) to the WDCR resets the binary counter to zero. The counting process begins again. WDCR Note: 01001110 Writes the clear-count code (4EH) to the WDCR. Writing the disable code (B1H) to the WDCR causes the binary counter to be reset to zero. TMP1941AF-234 2003-03-27 TMP1941AF 7 WDMOD (0xFFFF_F090) Name Read/Write Reset Value WDTE R/W 1 WDT enable Function 1: Enable 0 Time-out period 00: 216/fsys 01: 218/ fsys 10: 220/ fsys 11: 222/ fsys 6 WDTP1 R/W 5 WDTP0 0 4 3 2 I2WDT R/W 0 IDLE 0: Off 1: On 1 RESCR 0 1: System reset 0 R/W 0 Must be written as 0. System reset 0 1 Internally routes the WDT time-out signal to the system reset Time-out peiord (@ fc = 40 MHz, fs = 32.768 kHz) System Clock Select SYSCR1.SYSCK 1 (fs) Watchdog Timer Time-out Period Clock Gear Value SYSCR1.GEAR[1:0] 00 xxx 00 (fc) 0 (fgear) 01 (fc/2) 10 (fc/4) 11 (fc/8) 2.0 s 1.638 ms 3.277 ms 6.554 ms 13.107 ms WDMOD.WDTP[1:0] 01 8.0 s 6.554 ms 13.107 ms 26.214 ms 52.429 ms WDT enable 0 1 Disable Enable 10 32.0 s 26.214 ms 52.429 ms 104.858 ms 209.715 ms 11 128.0 s 104.858 ms 209.715 ms 419.430 ms 838.861 ms Figure 16.4 Watchdog Timer Mode Register (WDMOD) 7 WDCR Name Reset Value Function (0xFFFF_F091) Read/Write 6 5 4 W 3 2 1 0 B1H: WDT disable code 4EH : WDT clear-count code Special code B1H 4EH Other values WDT disable code WDT clear-count code Don't care Figure 16.5 Watchdog Timer Control Register (WDCR) TMP1941AF-235 2003-03-27 TMP1941AF 16.3 Operation The watchdog timer is a kind of timer that generates an interrupt request if it times out. The WDT of the TMP1941AF allows the user to program the time-out period in the WDTP[1:0] field in the WDMOD. While enabled, the software can reset the counter to zero at any time by writing a special clear-count code. If the software is unable to reset the counter before it reaches the time-out count, the WDT generates the INTWDT interrupt. In response to the interrupt, the CPU jumps to a system recovery routine to regain control of the system. The WDT begins counting immediately after reset. When the TMP1941AF goes into SLEEP or STOP mode, the WDT counter is reset to zero automatically and stops counting. The WDT continues counting while an off-chip peripheral has mastership of the bus (i.e., BUSAK = 0). In IDLE mode, the I2WDT bit in the WDMOD determines whether or not to disable the WDT. The I2WDT bit can be programmed before putting the TMP1941AF in IDLE mode. Examples: * Clearing the WDT binary counter WDCR 76543210 01001110 Writes the clear-count code (4EH) to the WDCR. * Programming the time-out interval to 218/fsys WDMOD 76543210 1 0 1 - - - - - * Disabling the watchdog timer WDMOD WDCR 76543210 0- - - - - - - 10110001 Clears the WDTE bit to 0. Writes the disable code (B1H) to the WDCR. TMP1941AF-236 2003-03-27 TMP1941AF 17. Real-Time Clock (RTC) The TMP1941AF contains a real-time clock (RTC). Clocked by a 32.768-kHz clock, the RTC provides a periodic interrupt at a programmed interval: 0.0625 seconds, 0.125 seconds, 0.25 seconds or 0.50 seconds. The RTC can continue operating in any standby modes in which the low-speed oscillator is active. The RTC interrupt (INTRTC) can be used as a wake-up signal to exit a standby mode (except STOP mode). The IMCGB3 register located within the CG must be programmed to use the INTRTC interrupt. 17.1 Implemention Figure 17.1 shows a block diagram of the RTC. Interrupt Request (INTRTC) 8-Bit Accumulator 211 212 213 214 14-Stage Binary Counter RTCREG RTCCR.RTCSEL RTCCR.RTCRUN Selector Run/Clear fs (32.768 kHz) Figure 17.1 RTC Block Diagram The RTC Control Register (RTCCR) provides control over the RTC. The organization of the RTCCR is shown below. 7 RTCCR (0xFFFF_F0A0) Read/Write Reset Value Function Name R/W 0 Must be written as 0. 6 5 4 3 RTCRCLR R/W 0 Accumulator clear 0: Clear RTCREG 1: Don't care 2 RTCSEL1 0 00: 214/fs 01: 213/fs 10: 212/fs 11: 211/fs R/W 1 RTCSEL0 0 0 RTCRUN R/W 0 0: Stop and clear the counter. 1: Begin counting. Interrupt interval (fs = 32.768 kHz) 00 01 10 11 0.50 seconds 0.25 seconds 0.125 seconds 0.0625 seconds Figure 17.2 RTC Control Register (RTCCR) TMP1941AF-237 2003-03-27 TMP1941AF The RTC provides an 8-bit read-only accumulator (RTCREG) that counts the number of INTRTC interrupts that have occurred. The accumulator allows the user to keep track of time up to 127.5 seconds if the interrupt interval is programmed to 0.5 seconds. Accumulator 7 RTCREG Name (0xFFFF_F0A4) Read/Write Reset Value Function RUI7 0 6 RUI6 0 5 RUI5 0 4 RUI4 R 0 3 RUI3 0 2 RUI2 0 1 RUI1 0 0 RUI0 0 Accumulate count value Figure 17.3 RTC Accumulator Register (RTCREG) The RTCREG is incremented with a delay of one fs clock after the INTRTC interrupt is generated. Reads of the RTCREG must be performed in SLOW mode. The resetting of the RTCREG is inhibited for one fs clock cycle after the INTRTC interrupt is generated. The RTCREG can be reset to zero by executing the accumulator-clear command twice in SLOW mode. fs Clock INTRTC Interrupt Accumulate Count Value n n+1 Don't execute an instruction to reset the accumulator during this period. Example 1: Clearing the accumulator SYSCR1 RTCCR RTCCR SYSCR1 7 X 0 0 X 6 X X X X 5 1 X X 0 4 - X X - 3 - 0 0 - 2 X - - X 1 - - - - 0 - 1 1 - Puts the TMP1941AF in SLOW mode. Executes accumulator-clear command twice. Puts the TMP1941AF back in NORMAL Mode. Example 2: Programming the RTC interrupt interval Initialization IMCGB3 IMCEHL EICRCG INTCLR RTCCR 7 0 0 0 0 0 6 0 0 0 0 0 5 1 0 0 1 0 4 1 1 0 1 0 3 0 0 0 1 1 2 0 X 1 0 X 1 0 X 1 1 X 0 1 X 1 0 1 Sets the interrupt level. Clears the interrupt request via the CG block. Clears the interrupt request via the INTC block. Starts counting. INTRTC interrupt EICRCG INTCLR 76543210 00000111 00111010 Clears the interrupt request via the CG block. Clears interrupt request via the INTC block. Interrupt processing End of interrupt X = Don't care Note: To disable interrupts, program the IMCEHL and then the IMCGB3 in this order. TMP1941AF-238 2003-03-27 TMP1941AF 18. Electrical Characteristics The letter x in equations presented in this chapter represents the cycle period of the fsys clock selected through the programming of the SYSCR1.SYSCK bit. The fsys clock may be derived from either the highspeed or low-speed crystal oscillator. The programming of the clock gear function also affects the fsys frequency. All relevant values in this chapter are calculated with the high-speed (fc) system clock (SYSCR1.SYSCK=0) and a clock gear factor of 1/fc (SYSCR1.GEAR[1:0]=00). 18.1 Maximum Ratings Parameter Supply voltage Input voltage Low-level output current High-level output current Per pin Total Per pin Total Symbol VCC VIN IOL IOL IOH IOH PD TSOLDER TSTG TOPR Rating -0.5 to 4.0 -0.5 to VCC + 0.5 5 80 -5 -80 600 260 -65 to 150 -40 to 85 Unit V V mA Power dissipation (Ta = 85C) Soldering temperature (10 s) Storage temperature Operating temperature mW C C C VCC = DVCC = AVCC; VSS = DVSS= AVSS Note: Maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no maximum rating value is exceeded with respect to current, voltage, power dissipation, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning. TMP1941AF-239 2003-03-27 TMP1941AF 18.2 DC Electrical Characteristics (1/2) Ta = -40 to 85C Parameter Symbol Condition fosc = 4 to 10 MHz fsys = 2 to 40 MHz fs = 30 to 34 kHz fosc = 4 to 7 MHz fsys = 2 to 28 MHz fs = 30 to 34 kHz fosc = 16 to 20 MHz fsys = 1 to 20 MHz fs = 30 to34 kHz fosc = 16 to 20 MHz fsys = 1 to 20 MHz fs = 30 to 34 kHz fosc = 20 to 40 MHz fsys = 1.25 to 20 MHz fs = 30 to 34 kHz (SYSCR1.DFOSC = 0) (Note 2) Min 3.0 Typ (Note 1) Max Unit PLLON 2.7 Supply voltage AVCC = VCC AVSS = VSS = 0 V VCC PLLOFF (Crystal) 2.7 3.6 V PLLOFF (External clock) 2.7 AD0-15 A16-23, A0-7, RD , WR , HWR , WAIT , BUSRQ , BUSAK , R / W , P37-PA7 (except P77) PLLOFF , BW0, VIL 0.6 VIL1 -0.3 0.3VCC Low-level input voltage BW1, RESET , NMI , P77 (INT0) X1 AD0-15 A16-23, A0-7, RD , WR , HWR , WAIT , BUSRQ , BUSAK , R / W , P37-PA7 (except P77) PLLOFF , BW0, VIL2 VIL4 VIH 0.25VCC 0.2VCC 2.0 V VCC 2.7 V VIH1 0.7VCC VCC + 0.3 High-level input voltage BW1, RESET , NMI , P77 (INT0) X1 VIH2 0.80VCC VIH4 VOL VOH IOL = 1.6 mA IOH = -400 A VCC 2.7 V 0.8VCC 0.45 2.4 V Low-level output voltage High-level output voltage Note 1: VCC = 3.3 V, Ta = 25C, unless otherwise noted. Note 2: The DFOSC bit in the SYSCR1 register must be cleared to 0. TMP1941AF-240 2003-03-27 TMP1941AF 18.3 DC Electrical Characteristics (2/2) Ta = -40 to 85C Parameter Input leakage current Output leakage current Power-down voltage (STOP mode, RAM backup) Pull-up resistor at Reset Pin capacitance (except power/ground pins) Schmitt hysteresis Symbol ILI ILO VSTOP RRST CIO Condition 0.0 VIN VCC 0.2 VIN VCC - 0.2 VIL2 = 0.2VCC, VIH2 = 0.8VCC VCC = 3.3 V 0.3 V fc = 1 MHz Min Typ (Note 1) Max 0.02 0.05 5 10 3.6 450 10 Unit A V k pF 2.2 100 PLLOFF, BW0, BW1, RESET , NMI , INT0 Programmable pull-up resistor NORMAL (Note 2); Gear = 1/1 IDLE (Doze) IDLE (Halt) NORMAL (Note 2); Gear = 1/1 IDLE (Doze) IDLE (Halt) SLOW SLLEP STOP VTH PKH VCC 2.7 V VCC = 3.3 V 0.3 V VCC = 3.3 V 0.3 V fsys = 40 MHz (fOSC = 10 MHz, PLLON) VCC = 3.3 V 0.3 V fsys = 20 MHz (fOSC = 20 MHz, PLLOFF) VCC = 3.3 V 0.3 V fs = 32.768 kHz VCC = 3.3 V 0.3 V fs = 32.768 kHz VCC = 2.7 to 3.6 V 0.4 100 75 27 22 25 13 11 70 20 5 450 85 40 36 40 20 18 220 180 150 V k mA mA ICC A A A Note 1: VCC = 3.3 V, Ta = 25C, unless otherwise noted. Note 2: Measured with the operating CPU (scanning ports), 16-bit bus (ALE = 1.5 cycles, 1 wait state), open output pins and input pins levels held at fixed logic values. IREF excluded. TMP1941AF-241 2003-03-27 TMP1941AF 18.4 AC Electrical Characteristics (1) VCC = 3.0 to 3.6 V, Ta = 0 to 70C, ALE width = 0.5 clock cycle (recommended when tSYS is 50 ns or longer) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Parameter System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD or WR asserted RD or WR negated to ALE high A0-A15 valid to RD or WR asserted A0-A23 valid to RD or WR asserted A0-A23 hold after RD or WR negated A0-A15 valid to D0-D15 data in A0-A23 valid to D0-D15 data in Symbol tSYS tAL tLA tLL tLC tCL tACL tACH tCAR tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW Equation Min 31.25 0.4x - 12 0.4x - 8 0.4x - 6 0.4x - 8 x - 15 x - 20 x - 20 x - 15 x (2 + W) - 37 x (2 + W) - 37 x (1 + W) - 22 x (1 + W) - 10 0 x - 15 x (1 + W) - 10 x (1 + W) - 18 x - 15 1.5x - 30 1.5x - 30 (0.5 + N - 1) x + 2 (0.5 + N) x - 17 fsys = 20 MHz * Max 33333 Min 50 8 12 14 12 35 30 30 35 Max Unit ns ns ns ns ns ns ns ns ns 63 63 28 40 0 35 40 32 35 45 45 27 58 ns ns ns ns ns ns ns ns ns ns ns ns RD asserted to D0-D15 data in RD width low D0-D15 hold after RD negated RD negated to next A0-A15 output WR width low D0-D15 valid to WR negated D0-D15 hold after WR negated A0-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD or WR asserted *W=0 W: Number of wait-state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (1 + N) wait insertion AC measurement conditions: * Output levels: High = 2.4 V, Low = 0.45 V, CL = 30 pF * Input levels: High = 2 V, Low = 0.6 V TMP1941AF-242 2003-03-27 TMP1941AF (2) VCC = 3.0 to 3.6 V, Ta = 0 to 70C, ALE width = 1.5 clock cycles No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Parameter System clock period (x) A0-A15 valid to ALE low A0-A15 hold after ALE low ALE pulse width high ALE low to RD or WR asserted Symbol tSYS tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW Equation Min 31.25 1.4x - 12 0.4x - 8 1.4x - 6 0.4x - 8 x - 15 2x - 20 2x - 20 x - 15 x (3 + W) - 37 x (3 + W) - 37 x (1 + W) - 22 x (1 + W) - 10 0 x - 15 x (1 + W) - 10 x (1 + W) - 18 x - 15 2.5x - 30 2.5x - 30 (0.5 + N - 1) x + 2 (0.5 + N) x - 17 fsys = 40 MHz* Max 33333 23 2 29 2 10 30 30 10 38 38 3 15 0 10 15 7 10 32 32 15 20 Min Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns RD or WR negated to ALE high A0-A15 valid to RD or WR asserted A0-A23 valid to RD or WR asserted A0-A23 hold after RD or WR negated A0-A15 valid to D0-D15 data in A0-A23 valid to D0-D15 data in RD asserted to D0-D15 data in RD width low D0-D15 hold after RD negated RD negated to next A0-A15 output WR width low D0-D15 valid to WR negated D0-D15 hold after WR negated A0-A23 valid to WAIT input A0-A15 valid to WAIT input WAIT hold after RD or WR asserted *W=0 W: Number of wait-state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (1 + N) wait insertion AC measurement conditions: * Output levels: High = 2.4 V, Low = 0.45 V, CL = 30 pF * Input levels: High = 2 V, Low = 0.6 V TMP1941AF-243 2003-03-27 TMP1941AF Bus Cycle = 4 CLK Cycles Internal CLK S0 tLL S1 S2 S3 S0 ALE tAL tCL tLA AD0-AD15 A0-A15 tADL tADH AD16-AD23 tACH tACL tLC tRR tRD tCAR tRAE tHR D0-D15 RD CS0 - CS3 R/W Note: The internal CLK is not the system clock driven out from the SCOUT pin. Figure 18.1 Read Cycle Timing (ALE = 1.5, Zero Wait State) TMP1941AF-244 2003-03-27 TMP1941AF Bus Cycle = 5 CLK Cycles Internal CLK S0 tLL S1 W1 S2 S3 S0 ALE tAL tCL tLA AD0-AD15 A0-A15 tADL tADH A16-A23 tACH tACL tLC tRR tRD tCAR tRAE tHR D0-D15 RD CS0 - CS3 R/ W Note: The internal CLK is not the system clock driven out from the SCOUT pin. Figure 18.2 Read Cycle Timing (ALE = 1.5, 1 Programmed Wait State) TMP1941AF-245 2003-03-27 TMP1941AF Bus Cycle = 6 CLK Cycles Internal CLK S1 W W S2 S3 S0 ALE AD0-AD15 A0-A15 D0-D15 AD16-AD23 RD tCW CS0 - CS3 R/ W tAWL/H WAIT Note1: Note2: If tAWH and/or tAWL cannot be satisified, a bus cycle must be initiated with the WAIT pin asserted. The internal CLK is not the system clock driven out from the SCOUT pin. Figure 18.3 Read Cycle Timing (ALE = 1.5, 2 Externally Generated Wait States with N=1) TMP1941AF-246 2003-03-27 TMP1941AF Bus Cycle = 4 CLK Cycles Internal CLK tLL ALE tAL tCL tLA AD0-AD15 A0-A15 D0-D15 tDW tACH tACL tLC tWW tCAR tWD AD16-AD23 WR , HWR CS0 - CS3 R/ W Note: The internal CLK is not the system clock driven out from the SCOUT pin. Figure 18.4 Write Cycle Timing (ALE = 1, Zero Wait State) TMP1941AF-247 2003-03-27 TMP1941AF 18.5 ADC Electrical Characteristics AVCC = VCC, AVSS = VSS Parameter Analog reference voltage (+) Analog reference voltage (-) Analog input voltage Analog supply current ADMOD1.VREFON = 1 Symbol VREFH VREFL VAIN Condition VCC = 3.3 0.3 V VCC = 3.3 0.3 V VCC = 3.3V 0.3 V VCC = 2.7 to 3.6 V VCC = 3.3 V 0.3 V Min VCC - 0.2 V VSS VREFL Typ VCC VSS 1.05 0.02 1 Max VCC VSS + 0.2 V VREFH 1.5 5.0 3 Unit V mA A LSB IREF (VREFL = VSS) ADMOD1.VREFON = 0 (VREFH = VCC) Total error (not including quantization error) Note 1: 1 LSB = (VREFH - VREFL) / 1024 (V) Note 2: The A/D converter must be stopped when operating the TMP1941AF with the low-speed clock (fs). Note 3: The supply current flowing through the AVCC pin is included in the digital supply current parameter (ICC). TMP1941AF-248 2003-03-27 TMP1941AF 18.6 SIO Timing 18.6.1 I/O Interface Mode In the tables below, the letter x represents the fsys cycle period, which varies, depending on the programming of the clock gear function. (1) SCLK Input Mode Parameter SCLK period TxD data to SCLK rise or fall* RxD data valid to SCLK rise or fall* Symbol tSCY tOSS tSRD Equation Min 16x (tSCY/2) - 5x - 23 (tSCY/2) + 3x 2x + 8 20 MHz Max Min Max 800 127 550 108 0 40 MHz Min Max 400 52 275 58 0 Unit ns ns ns ns ns TxD data hold after SCLK rise or fall* tOHS RxD data hold after SCLK rise or fall* tHSR 0 * SCLK rise or fall: Measured relative to the programmed active edge of SCLK. (2) SCLK Output Mode Parameter SCLK period (programmable) TxD data to SCLK rise TxD data hold after SCLK rise RxD data valid to SCK rise RxD data hold after SCK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x (tSCY/2) - 15 (tSCY/2) - 15 x + 23 0 20 MHz Max Min Max 800 385 385 73 0 40 MHz Min Max 400 185 185 48 0 Unit ns ns ns ns ns SCLK SCK Output Mode / Active-High SCL Input Mode SCLK Active-Low SCK Input Mode Transmit Data (TxD) tSCY tOSS 0 tSRD 1 tOHS 2 tHSR 1 VALID 2 VALID 3 VALID 3 Receive Data (RxD) 0 VALID TMP1941AF-249 2003-03-27 TMP1941AF 18.7 SBI Timing 18.7.1 I2C Mode In the table below, the letters x and T represent the fsys and T0 cycle periods, respectively. The letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the SBI0CR1. Parameter SCL clock frequency Hold time for START condition Low period of the SCL clock SCL clock high width Input Output Input Output tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Softwaredependent tHIGH (2(n-1) + 4) T Softwaredependent Symbol tSC tHD:STA tLOW Equation Min 0 Standard Mode Fast Mode fsys = 8 MHz, n = 4 fsys = 32 MHz, n = 4 Unit Max Min Max Min Max 0 4.0 4.7 100 0 0.6 1.3 1 (Note 1) 0.6 1.5 0.6 0 100 0.6 1.3 400 kHz s s s s s s s ns s s 2(n-1) T 4 (Note 1) 4.0 6 4.7 0 250 4.0 4.7 Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between STOP and START conditions Note 1: Different from the Philips I2C-bus specification. Note 2: The ouptut data hold time is equal to 12x. Note 3: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the fall edge of SCL. However, the TMP1941AF SBI does not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the SCL and SDA lines. tSCL tf SCL tHD;STA SDA S Sr P tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF tLOW tr tHIGH S: START condition, Sr: Repeated START condition, P: STOP condition Note 4: To operate the SBI in I2C Fast mode, the fsys frequency must be no less than 20 MHz. To operate the SBI in I2C Standard mode, the fsys frequency must be no less than 4 MHz. Note 5: Although THE I2C BUS SPECIFICATION from Philips states that I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off, the TMP1941AF does not comply with this requirement. Note 6: The SDA hold time from the falling edge of SCL varies with the fsys frequency, as shown at left. The fsys frequency must be determined, considering the devices connected on the I2C bus. If the devices on the I2C bus drive the SDA line within a minimum delay of 100 ns from the falling edge of SCL, the required hold time must be less than 100 ns; thus the fsys frequency must be 20 MHz or larger. ns 400 Required Hold Time 300 200 100 0 10 20 fsys 30 40 MHz TMP1941AF-250 2003-03-27 TMP1941AF 18.7.2 Clock-Synchronous 8-Bit SIO Mode In the tables below, the letters x and T represent the fsys and T0 cycle periods, respectively. The letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the SBI0CR1. The electrical specifications below are for an SCK signal with a 50% duty cycle. (1) SCK Input Mode Parameter SCK period SO data to SCK rise SO data hold after SCK rise SI data valid to SCK rise SI data hold after SCK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x (tSCY/2) - (6x + 30) (tSCY/2) + 4x 0 4x + 10 40 MHz Max Min 400 20 300 0 110 Max Unit ns ns ns ns ns (2) SCK Output Mode Parameter SCK period (programmable) SO data to SCK rise SO data hold after SCK rise SI data valid to SCK rise SI data hold after SCK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 2n x T (tSCY/2) - 20 (tSCY/2) - 20 2x + 30 0 40 MHz Max Min 800 380 380 80 0 Max Unit ns ns ns ns ns tSCY SCK tOSS Transmit Data (SO) 0 tSRD Receive Data (SI) 0 VALID 1 VALID 1 tHSR 2 VALID 3 VALID tOHS 2 3 TMP1941AF-251 2003-03-27 TMP1941AF 18.8 Event Counters (TA0IN, TA2IN, TB0IN0, TB0IN1, TB2IN0) In the table below, the letter x represents the fsys cycle period. Parameter Clock low pulse width Clock high pulse width Symbol tVCKL tVCKH Equation Min 2x + 100 2x + 100 40 MHz Min 150 150 Max Max Unit ns ns 18.9 Timer Capture (TB0IN0, TB0IN1, TB1IN0, TB1IN1, TB2IN0, TB2IN1) In the table below, the letter x represents the fsys cycle period. Parameter Low pulse width High pulse width Symbol tCPL tCPH Equation Min 2x + 100 2x + 100 40 MHz Min 150 150 Max Max Unit ns ns 18.10 General Interrupts In the table below, the letter x represents the fsys cycle period. Parameter Low pulse width for INT0-INTA High pulse width for INT0-INTA Symbol tINTAL tINTAH Equation Min x + 100 x + 100 40 MHz Min 125 125 Max Max Unit ns ns 18.11 NMI and STOP/SLEEP Wake-up Interrupts Parameter Low pulse width for NMI and INT0-INT4 High pulse width for INT0-INT4 Symbol tINTBL tINTBH Equation Min 100 100 40 MHz Min 100 100 Max Max Unit ns ns 18.12 SCOUT Pin In the table below, the letter T represents the cycle period of the SCOUT output clock. Parameter Clock low pulse width Clock high pulse width Symbol tSCH tSCL Equation Min 0.5T - 5 0.5T - 5 40 MHz Min 7.5 7.5 Max Max Unit ns ns tSCH SCOUT tSCL TMP1941AF-252 2003-03-27 TMP1941AF 18.13 Bus Request and Bus Acknowledge Signals BUSRQ (Note 1) BUSAK tBAA tABA AD0-AD15 (Note 2) A0-A23, RD , WR (Note 2) CS0 - CS3 , R / W , HWR ALE Parameter Bus float to BUSAK asserted Bus float after BUSAK negated Symbol tABA tBAA Equation Min 0 0 40 MHz Min 0 0 Max 80 80 Max 80 80 Unit ns ns Note 1: If the current bus cycle has not terminated due to wait-state insertion, the TMP1941AF does not respond to BUSRQ until the wait state ends. This broken lines indicate that output buffers are disabled, not that the signals are at indeterminate states. The pin holds the last logic value present at that pin before the bus is relinquished. This is dynamically accomplished through external load capacitances. The equipment manufacturer may maintain the bus at a predefined state by means of off-chip resistors, but he or she should design, considering the time (determined by the CR constant) it takes for a signal to reach a desired state. The on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states. Note 2: TMP1941AF-253 2003-03-27 TMP1941AF 19. I/O Register Summary The internal I/O registers configure and access the I/O ports, and control on-chip functions. These registers occupy 8-kbyte addresses from 0xFFFF_E000 through 0xFFFF_FFFF. 1. 2. 3. 4. 5. 6. 7. 8. 9. I/O ports Watchdog Timer (WDT) Real-Time Clock (RTC) 8-Bit Timers (TMRAs) 16-Bit Timer/Event Counters (TMRBs) Serial I/O (SIO0 and SIO1) Serial Bus Interface (SBI) Serial I/O (SIO3 and SIO4) A/D Converter (ADC) 10. Interrupt Controller (INTC) 11. DMA Controller (DMAC) 12. Chip Select/Wait Controller 13. Clock Generator (CG) Table Organization Mnemonic Register Name Address 7 6 1 0 Bit Name Read/Write Reset Value Function Access R/W: Read/write. The user can read and write the register bit. R: W: Read only. Write only. W*: The user can read and write the register bit, but a read always returns a value of 1. TMP1941AF-254 2003-03-27 TMP1941AF 1. I/O Ports Address 0xFFFF_F010 1 2 3 4 5 6 7 8 P3 9 A P3CR B P3FC C D E P4 F Mnemonic Address Mnemonic Address 0xFFFF_F030 1 2 3 Mnemonic P8 P9 P8CR P8FC Address Mnemonic 0xFFFF_F020 P4CR 1 P4FC 2 3 4 5 P5 6 7 8 9 A B P7 C D E P7CR F P7FC 0xFFFF_F050 ODE 1 2 3 4 5 6 7 8 9 A B C D E F 4 P9CR 5 P9FC 6 PA 7 8 PACR 9 PAFC A B C D E F 2. WDT Address Mnemonic 0xFFFF_F090 WDMOD 1 WDCR 2 3 4 5 6 7 8 9 A B C D E F 3. RTC Address Mnemonic 0xFFFF_F0A0 RTCCR 1 2 3 4 RTCREG 5 6 7 8 9 A B C D E F 4. 8-Bit Timers Address Mnemonic 0xFFFF_F100 TA01RUN 1 2 TA0REG 3 TA1REG 4 TA01MOD 5 TA1FFCR 6 7 8 TA23RUN 9 A TA2REG B TA3REG C TA23MOD D TA3FFCR E F 5. 16-Bit Timer/Event Counters Address Mnemonic Address Mnemonic Address Mnemonic Address Mnemonic 0xFFFF_F180 TB0RUN 1 2 TB0MOD 3 TB0FFCR 4 5 6 7 8 9 A B TB0RG0L TB0RG0H TB0RG1L TB0RG1H 0xFFFF_F190 TB1RUN 1 2 TB1MOD 3 TB1FFCR 4 5 6 7 8 9 A B TB1RG0L TB1RG0H TB1RG1L TB1RG1H 0xFFFF_F1A0 TB2RUN 1 2 TB2MOD 3 TB2FFCR 4 5 6 7 8 9 A B TB2RG0L TB2RG0H TB2RG1L TB2RG1H 0xFFFF_F1B0 TB3RUN 1 2 TB3MOD 3 TB3FFCR 4 5 6 7 8 9 A B TB3RG0L TB3RG0H TB3RG1L TB3RG1H C TB0CP0L D TB0CP0H E TB0CP1L F TB0CP1H C TB1CP0L D TB1CP0H E TB1CP1L F TB1CP1H C TB2CP0L D TB2CP0H E TB2CP1L F TB2CP1H C TB3CP0L D TB3CP0H E TB3CP1L F TB3CP1H Figure 19.1 I/O Register Address Map (1/5) TMP1941AF-255 2003-03-27 TMP1941AF 6. SIO0 and SIO1 Address 0xFFFF_F200 1 2 3 Mnemonic SC0BUF SC0CR SC0MOD0 BR0CR 7. SBI Address 0xFFFF_F240 1 2 3 Mnemonic SBI0CR1 SBI0DBR I2C0AR SBI0CR2/SR 8. SIO3 and SIO4 Address 0xFFFF_F280 1 2 3 Mnemonic SC3BUF SC3CR SC3MOD0 BR3CR 9. ADC Address 0xFFFF_F300 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic ADREG04L ADREG04H ADREG15L ADREG15H ADREG26L ADREG26H ADREG37L ADREG37H 4 BR0ADD 5 SC0MOD1 6 7 8 9 A B SC1BUF SC1CR SC1MOD0 BR1CR 4 SBI0BR0 5 SBI0BR1 6 7 4 BR3ADD 5 SC3MOD1 6 7 8 9 A B SC4BUF SC4CR SC4MOD0 BR4CR C BR1ADD D SC1MOD1 E F Address Mnemonic C BR4ADD D SC4MOD1 E F 0xFFFF_F310 ADMOD0 1 ADMOD1 2 3 4 5 6 7 8 9 A B C D E F Figure 19.1 I/O Register Address Map (2/5) TMP1941AF-256 2003-03-27 TMP1941AF 10. INTC Address Mnemonic Address 0xFFFF_E010 1 2 3 4 IMC5L 5 6 IMC5H 7 8 9 A B C IMC7L D E IMC7H F Mnemonic Address Mnemonic Address Mnemonic 0xFFFF_E000 IMC0L 1 2 IMC0H 3 4 IMC1L 5 6 7 8 9 A IMC2H B C IMC3L D E IMC3H F 0xFFFF_E020 IMC8L 1 2 IMC8H 3 4 5 6 7 8 IMCAL 9 A IMCAH B C D E F 0xFFFF_E030 IMCCL 1 2 IMCCH 3 4 IMCDL 5 6 IMCDH 7 8 IMCEL 9 A IMCEH B C IMCFL D E IMCFH Address Mnemonic Address 0xFFFF_E050 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic Address Mnemonic Address 0xFFFF_E070 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic 0xFFFF_E040 IVR 1 2 3 4 5 6 7 8 9 A B C D E F Note: 0xFFFF_E060 INTCLR 1 2 3 4 5 6 7 8 9 A B C D E F Any attempt to access an address in the shaded areas causes a bus error to be signaled to the TX19 core processor. Any attempt to access an address in the ranges 0xFFFF_E080 through 0xFFFF_E0FF and 0xFFFF_E10C through 0xFFFF_E1FF also causes a bus error. Figure 19.1 I/O Register Address Map (3/5) TMP1941AF-257 2003-03-27 TMP1941AF 11. DMAC Address Mnemonic Address Mnemonic Address Mnemonic Address Mnemonic 0xFFFF_E200 CCR0 1 2 3 4 CSR0 5 6 7 8 SAR0 9 A B C DAR0 D E F Address Mnemonic Address 0xFFFF_E210 BCR0 1 2 3 4 5 6 7 8 DTCR0 9 A B C D E F Mnemonic Address 0xFFFF_E220 CCR1 1 2 3 4 CSR1 5 6 7 8 SAR1 9 A B C DAR1 D E F Mnemonic Address 0xFFFF_E230 BCR1 1 2 3 4 5 6 7 8 DTCR1 9 A B C D E F Mnemonic 0xFFFF_E240 CCR2 1 2 3 4 CSR2 5 6 7 8 SAR2 9 A B C DAR2 D E F Address Mnemonic 0xFFFF_E250 BCR2 1 2 3 4 5 6 7 8 DTCR2 9 A B C D E F Address 0xFFFF_E290 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic 0xFFFF_E260 CCR3 1 2 3 4 CSR3 5 6 7 8 SAR3 9 A B C DAR3 D E F Address 0xFFFF_E2A0 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic 0xFFFF_E270 BCR3 1 2 3 4 5 6 7 8 DTCR3 9 A B C D E F Address 0xFFFF_E2B0 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic 0xFFFF_E280 DCR 1 2 3 4 5 6 7 8 9 A B C DHR D E F Note: Any attempt to access an address in the shaded areas causes a bus error to be signaled to the TX19 core processor. Any attempt to access an address in the range 0xFFFF_E2C0 through 0xFFFF_E2FF also causes a bus error. Any attempt to access an address in the range 0xFFFF_E300 through 0xFFFF_E3FF is disallowed. Figure 19.1 I/O Register Address Map (4/5) TMP1941AF-258 2003-03-27 TMP1941AF 12. CS/Wait Controller Address Mnemonic Address 0xFFFF_E410 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic Address Mnemonic Address 0xFFFF_E490 1 2 3 4 5 6 7 8 9 A B C D E F Mnemonic 0xFFFF_E400 BMA0 1 2 3 4 BMA1 5 6 7 8 BMA2 9 A B C BMA3 D E F 0xFFFF_E480 B01CS 1 2 3 4 B23CS 5 6 7 8 BEXCS 9 A B C D E F 13. CG Address 0xFFFF_EE00 1 2 3 5 6 7 8 9 A B C D E F Mnemonic SYSCR0 SYSCR1 SYSCR2 SYSCR3 Address 0xFFFF_EE10 1 2 3 Mnemonic IMCGA0 IMCGA1 IMCGA2 IMCGA3 Address Mnemonic 0xFFFF_EE20 EICRCG 1 2 3 4 5 6 7 8 9 A B C D E F 4 ADCCLK 4 IMCGB0 5 6 7 IMCGB3 8 9 A B C D E F Note: Any attempt to access an address in the shaded areas causes a bus error to be signaled to the TX19 core processor. Any attempt to access an address in the following ranges also cause a bus error. 0xFFFF_E420 thru 0xFFFF_E47F 0xFFFF_E450 thru 0xFFFF_E4FF 0xFFFF_E700 thru 0xFFFF_EDFF 0xFFFF_EE30 thru 0xFFFF_EEFF An attempt to access an address in the following ranges also cause a bus error. 0xFFFF_F040 thru 0xFFFF_F04F 0xFFFF_F060 thru 0xFFFF_F08F 0xFFFF_F0B0 thru 0xFFFF_F0FF 0xFFFF_F110 thru 0xFFFF_F17F 0xFFFF_F1C0 thru 0xFFFF_F1FF 0xFFFF_F210 thru 0xFFFF_F23F 0xFFFF_F248 thru 0xFFFF_F27F 0xFFFF_F290 thru 0xFFFF_F2FF 0xFFFF_F320 thru 0xFFFF_FFFF Figure 19.1 I/O Register Address Map (5/5) TMP1941AF-259 2003-03-27 TMP1941AF 19.1 I/O Ports I/O Port Data Registers Mnemonic Name Address P3 Port 3 Register FFFF F018H 7 P37 R/W 1 Input mode P57 6 5 4 R/W 1 3 1 P43 1 2 1 0 P4 Port 4 Register FFFF F01EH P56 P55 P44 1 P54 P42 R/W 1 Input mode P52 P41 1 P51 P40 1 P50 P5 Port 5 Register FFFF F025H P53 R Input mode P73 R/W 1 Input mode P83 R/W 1 Input mode P93 R/W 1 P77 P7 Port 7 Register FFFF F02BH 1 P87 P8 Port 8 Register FFFF F030H 1 P97 P9 Port 9 Register FFFF F031H P76 1 P86 1 P96 P75 1 P85 1 P95 1 PA5 1 P74 1 P84 1 P94 1 PA4 R/W 1 P72 1 P82 1 P92 1 P71 1 P81 1 P91 1 PA1 1 P70 1 P80 1 P90 1 PA0 1 1 1 Output mode PA7 PA6 1 Input mode PA3 1 Input mode PA2 1 PA Port A Register FFFF F036H 1 I/O Port Control and Function Registers (1 of 2) Mnemonic Name Address P3CR Port 3 Control Register FFFF F01AH 7 P37C 0 0: IN, 1: OUT 6 P36C 0 5 P35C W 0 4 P34C 0 3 P33C 0 2 P32C 0 1 0 P4CR Port 4 Control Register P44C FFFF F020H 0 P44F P43C 0 P43F 0 0: Port 1: CS3 output P73C W P42C W 1 0: IN, 1: OUT P42F W 1 0: Port 1: CS2 output P72C 0 P72F 0 0: Port 1: TA2IN input / TXD4 output P41C 0 P41F 0 0: Port 1: CS1 output P71C 0 P71F 0 0: Port 1: TA1OUT output / RXD3 input P40C 0 P40F 0 0: Port 1: CS0 output P70C 0 P70F 0 0: Port 1: TA0IN input / TXD3 output P4FC Port 4 Function Register FFFF F021H 0 0: Port 1: SCOUT output P7CR Port 7 Control Register P77C FFFF F02EH 0 P77F 0 0: Port 1: Wake-up INT0 input P76C 0 P76F 0 0: Port 1: TB0OUT output P75C 0 P75F 0 0: Port 1: TB0IN1 input P74C 0 0 0: IN 1: OUT P74F 0 0: Port 1: TB0IN0 input P73F 0 0: Port 1: TA3OUT output / RXD4 input P7FC Port 7 Function Register FFFF F02FH Note: P77F must be set to 1 when INT0 is used to exit STOP mode with SYSCR2.DRVE cleared. TMP1941AF-260 2003-03-27 TMP1941AF I/O Port Control and Function Registers (2 of 2) Mnemonic Name Address P8CR Port 8 Port 8 Control Register FFFF F032H 7 P87C 0 6 P86C 0 P86F 5 P85C 0 P85F 0 0: Port 1: TB2OUT output P95C 0 P95F W 0 0: Port 1: SCLK1 output or CTS1 / SCLK1 input 4 P84C 3 P83C 2 P82C 0 P82F 0 0: Port 1: TB1OUT output P92C 0 P92F W 0 0: Port 1: SCLK0 output or CTS0 / SCLK0 input 1 P81C 0 P81F 0 0: Port 1: TB1IN1 input P91C 0 0 P80C 0 P80F 0 0: Port 1: TB1IN0 input P90C 0 P90F W 0 0: Port 1: TXD0 output W 0 0 0: IN, 1: OUT P84F W 0 0: Port 1: TB2IN1 input P94C W P83F 0 0: Port 1: TB2IN0 input P93C P8FC Port 8 Port 8 Function Register FFFF F033H 0 0 Must be 0: Port written as 0. 1: TB3OUT output P97C P96C 0 P9CR Port 9 Port 9 Control Register FFFF F034H 0 0 0 0: IN, 1: OUT P93F 0 0: Port 1: TXD1 output P9FC Port 9 Port 9 Function Register FFFF F035H PACR Port A Port A Control Register PA7C FFFF F038H 0 PA7F PA6C 0 PA6F 0 0: Port 1: SDA/SO output PA5C 0 PA5F 0 0: Port 1: SCK output PA4C W PA3C PA2C 0 PA2F PA1C 0 PA1F PA0C 0 PA0F 0 0 0: IN, 1: OUT W PA3F PAFC Port A Port A Function Register FFFF F039H 0 0: Port 1: SCL output 0 0 0 0 0 Must be 0: Port 0: Port 0: Port 0: Port written as 0. 1: Wake-up 1: Wake-up 1: Wake-up 1: Wake-up INT4 input INT3 input INT2 input INT1 input Note: PA0F-PA3F must be set to 1 when INT1-INT4 are used to exit STOP mode with SYSCR2.DRVE cleared. Open-Drain Enable Register Mnemonic Name Address OpenDrain Enable Register 7 6 5 ODE72 0 4 ODE70 0 3 ODEA7 R/W 0 2 ODEA6 1 ODE93 0 ODE90 ODE FFFF F050H 0 0 0 P72 P70 PA7 PA6 P93 P90 0: Push-pull 0: Push-pull 0: Push-pull 0: Push-pull 0: Push-pull 0: Push-pull 1: Open1: Open1: Open1: Open1: Open1: Opendrain drain drain drain drain drain TMP1941AF-261 2003-03-27 TMP1941AF 19.2 Interrupt Controller Interrupt Controller (1 of 12) Mnemonic Name Address 7 6 5 EIM01 4 EIM00 3 DM0 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL02 1 IL01 0 IL00 0 0 Interrupt sensitivity 00: Low level Must be written as 00. IMC0L Interrupt Mode Control Register 0L 0 0 0 When DM0 = 0 Interrupt Number 0 (Software Set) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM0 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E000H 15 14 13 EIM11 12 EIM10 11 DM1 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL12 9 IL11 8 IL10 0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 When DM1 = 0 Interrupt Number 1 (INT0 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM1 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM21 20 EIM20 19 DM2 R/W 0 DMA trigger 0: Disable 1: Enable 18 IL22 17 IL21 16 IL20 0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge IMC0H Interrupt Mode Control Register 0H FFFF E002H 0 0 When DM2 = 0 Interrupt Number 2 (INT1 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM2 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM31 28 EIM30 27 DM3 R/W 0 DMA trigger 0: Disable 1: Enable 26 IL32 25 IL31 24 IL30 0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 When DM3 = 0 Interrupt Number 3 (INT2 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM3 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. Note1: When using INT0-INT4 to exit STOP and SLEEP modes, program their sensitivity in the IMCGA0 to IMCGA3 and IMCGB0 located within the CG. In this case, the EIMx[1:0] fields in the IMC0L, IMC0H and IMC1L have no effect, but must always be set to "high-level" (i.e., 01). Note 2: Interrupt sensitivity must be programmed before interrupt priority levels are programmed into the ILx[2:0] field. TMP1941AF-262 2003-03-27 TMP1941AF Interrupt Controller (2 of 12) Mnemonic Name Address 7 6 5 EIM41 4 EIM40 3 DM4 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL42 1 IL41 0 IL40 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge IMC1L Interrupt Mode Control Register 1L 0 0 0 When DM4 = 0 Interrupt Number 4 (INT3 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM4 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E004H 15 14 13 EIM51 12 EIM50 11 DM5 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL52 9 IL51 8 IL50 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 When DM5 = 0 Interrupt Number 5 (INT4 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM5 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIMA1 20 EIMA0 19 DMA R/W 0 DMA trigger 0: Disable 1: Enable 18 ILA2 17 ILA1 16 ILA0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge IMC2H Interrupt Mode Control Register 2H FFFF E00AH 0 0 0 When DMA = 0 Interrupt Number 10 (INT5 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DMA = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIMB1 28 EIMB0 27 DMB R/W 0 DMA trigger 0: Disable 1: Enable 26 ILB2 25 ILB1 24 ILB0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 When DMB = 0 Interrupt Number 11 (INT6 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DMB = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-263 2003-03-27 TMP1941AF Interrupt Controller (3 of 12) Mnemonic Name Address 7 6 5 EIMC1 4 EIMC0 3 DMC R/W 0 DMA trigger 0: Disable 1: Enable 2 ILC2 1 ILC1 0 ILC0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge IMC3L Interrupt Mode Control Register 3L 0 0 0 When DMC = 0 Interrupt Number 12 (INT7 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DMC = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E00CH 15 14 13 EIMD1 12 EIMD0 11 DMD R/W 0 DMA trigger 0: Disable 1: Enable 10 ILD2 9 ILD1 8 ILD0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 When DMD = 0 Interrupt Number 13 (INT8 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DMD = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIME1 20 EIME0 19 DME R/W 0 DMA trigger 0: Disable 1: Enable 18 ILE2 17 ILE1 16 ILE0 1 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge IMC3H Interrupt Mode Control Register 3H FFFF E00EH 0 0 0 When DME = 0 Interrupt Number 14 (INT9 pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DME = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIMF1 28 EIMF0 27 DMF R/W 0 DMA trigger 0: Disable 1: Enable 26 ILF2 25 ILF1 24 ILF0 0 0 Interrupt sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 When DMF = 0 Interrupt Number 15 (INTA pin) 000: Interrupt disabled. 001-111: Priority level (1-7) When DMF = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-264 2003-03-27 TMP1941AF Interrupt Controller (4 of 12) Mnemonic Name Address 7 6 5 EIM141 4 EIM140 3 DM14 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL142 1 IL141 0 IL140 0 0 Must be written as 11. IMC5L Interrupt Mode Control Register 5L 0 0 0 When DM14 = 0 Interrupt Number 20 (INTTA0) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM14 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E014H 15 14 13 EIM151 12 EIM150 11 DM15 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL152 9 IL151 8 IL150 0 0 Must be written as 11. 0 0 0 When DM15 = 0 Interrupt Number 21 (INTTA1) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM15 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM161 20 EIM160 19 DM16 R/W 0 DMA trigger 0: Disable 1: Enable 18 IL162 17 IL161 16 IL160 0 0 Must be written as 11. IMC5H Interrupt Mode Control Register 5H FFFF E016H 0 0 0 When DM16 = 0 Interrupt Number 22 (INTTA2) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM16 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM171 28 EIM170 27 DM17 R/W 0 DMA trigger 0: Disable 1: Enable 26 IL172 25 IL171 24 IL170 0 0 Must be written as 11. 0 0 0 When DM17 = 0 Interrupt Number 23 (INTTA3) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM17 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-265 2003-03-27 TMP1941AF Interrupt Controller (5 of 12) Mnemonic Name Address 7 6 5 EIM1C1 4 EIM1C0 3 DM1C R/W 0 DMA trigger 0: Disable 1: Enable 2 IL1C2 1 IL1C1 0 IL1C0 0 0 Must be written as 11. IMC7L Interrupt Mode Control Register 7L 0 0 0 When DM1C = 0 Interrupt Number 28 (INTTB00) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM1C = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E01CH 15 14 13 EIM1D1 12 EIM1D0 11 DM1D R/W 0 DMA trigger 0: Disable 1: Enable 10 IL1D2 9 IL1D1 8 IL1D0 0 0 Must be written as 11. 0 0 0 When DM1D = 0 Interrupt Number 29 (INTTB01) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM1D = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM1E1 20 EIM1E0 19 DM1E R/W 0 DMA trigger 0: Disable 1: Enable 18 IL1E2 17 IL1E1 16 IL1E0 0 0 Must be written as 11. IMC7H Interrupt Mode Control Register 7H FFFF E01EH 0 0 0 When DM1E = 0 Interrupt Number 30 (INTTB10) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM1E = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM1F1 28 EIM1F0 27 DM1F R/W 0 DMA trigger 0: Disable 1: Enable 26 IL1F2 25 IL1F1 24 IL1F0 0 0 Must be written as 11. 0 0 0 When DM1F = 0 Interrupt Number 31 (INTTB11) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM1F = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-266 2003-03-27 TMP1941AF Interrupt Controller (6 of 12) Mnemonic Name Address 7 6 5 EIM201 4 EIM200 3 DM20 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL202 1 IL201 0 IL200 0 0 Must be written as 11. IMC8L Interrupt Mode Control Register 8L 0 0 0 When DM20 = 0 Interrupt Number 32 (INTTB20) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM20 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E020H 15 14 13 EIM211 12 EIM210 11 DM21 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL212 9 IL211 8 IL210 0 0 Must be written as 11. 0 0 0 When DM21 = 0 Interrupt Number 33 (INTTB21) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM21 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM221 20 EIM220 19 DM22 R/W 0 DMA trigger 0: Disable 1: Enable 18 IL222 17 IL221 16 IL220 0 0 Must be written as 11. IMC8H Interrupt Mode Control Register 8H FFFF E022H 0 0 0 When DM22 = 0 Interrupt Number 34 (INTTB30) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM22 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM231 28 EIM230 27 DM23 R/W 0 DMA trigger 0: Disable 1: Enable 26 IL232 25 IL231 24 IL230 0 0 Must be written as 11. 0 0 0 When DM23 = 0 Interrupt Number 35 (INTTB31) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM23 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-267 2003-03-27 TMP1941AF Interrupt Controller (7 of 12) Mnemonic Name Address 7 6 5 EIM281 4 EIM280 3 DM28 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL282 1 IL281 0 IL280 0 0 Must be written as 11. IMCAL Interrupt Mode Control Register AL 0 0 0 When DM28 = 0 Interrupt Number 40 (INTTBOF0) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM28 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E028H 15 14 13 EIM291 12 EIM290 11 DM29 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL292 9 IL291 8 IL290 0 0 Must be written as 11. 0 0 0 When DM29 = 0 Interrupt Number 41 (INTTBOF1) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM29 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM2A1 20 EIM2A0 19 DM2A R/W 0 DMA trigger 0: Disable 1: Enable 18 IL2A2 17 IL2A1 16 IL2A0 0 0 Must be written as 11. IMCAH Interrupt Mode Control Register AH FFFF E02AH 0 0 0 When DM2A = 0 Interrupt Number 42 (INTTBOF2) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM2A = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM2B1 28 EIM2B0 27 DM2B R/W 0 DMA trigger 0: Disable 1: Enable 26 IL2B2 25 IL2B1 24 IL2B0 0 0 Must be written as 11. 0 0 0 When DM2B = 0 Interrupt Number 43 (INTTBOF3) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM2B = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-268 2003-03-27 TMP1941AF Interrupt Controller (8 of 12) Mnemonic Name Address 7 6 5 EIM301 4 EIM300 3 DM30 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL302 1 IL301 0 IL300 0 0 Must be written as 11. IMCCL Interrupt Mode Control Register CL 0 0 0 When DM30 = 0 Interrupt Number 48 (INTRX0) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM30 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E030H 15 14 13 EIM311 12 EIM310 11 DM31 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL312 9 IL311 8 IL310 0 0 Must be written as 11. 0 0 0 When DM31= 0 Interrupt Number 49 (INTTX0) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM31= 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM321 20 EIM320 19 DM32 R/W 0 DMA trigger 0: Disable 1: Enable 18 IL322 17 IL321 16 IL320 0 0 Must be written as 11. IMCCH Interrupt Mode Control Register CH FFFF E032H 0 0 0 When DM32 = 0 Interrupt Number 50 (INTRX1) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM32 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM331 28 EIM330 27 DM33 R/W 0 DMA trigger 0: Disable 1: Enable 26 IL332 25 IL331 24 IL330 0 0 Must be written as 11. 0 0 0 When DM33 = 0 Interrupt Number 51 (INTTX1) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM33= 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-269 2003-03-27 TMP1941AF Interrupt Controller (9 of 12) Mnemonic Name Address 7 6 5 EIM341 4 EIM340 3 DM34 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL342 1 IL341 0 IL340 0 0 0 Must be written as 11. IMCDL Interrupt Mode Control Register DL FFFF E034H 0 0 When DM34 = 0 Interrupt Number 52 (INTS2) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM34 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 15 14 13 12 11 R/W 0 Must be written as 0. 10 9 8 0 0 0 Must be written as 00. 0 0 Must be written as 000. 23 22 21 EIM361 20 EIM360 19 DM36 R/W 0 DMA trigger 0: Disable 1: Enable 18 IL362 17 IL361 16 IL360 0 0 Must be written as 11. IMCDH Interrupt Mode Control Register DH FFFF E036H 0 0 0 When DM36 = 0 Interrupt Number 54 (INTRX3) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM36 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM371 28 EIM370 27 DM37 R/W 0 DMA trigger 0: Disable 1: Enable 26 IL372 25 IL371 24 IL370 0 0 Must be written as 11. 0 0 0 When DM37 = 0 Interrupt Number 55 (INTTX3) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM37 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-270 2003-03-27 TMP1941AF Interrupt Controller (10 of 12) Mnemonic Name Address 7 6 5 EIM381 4 EIM380 3 DM38 R/W 0 DMA trigger 0: Disable 1: Enable 2 IL382 1 IL381 0 IL380 0 0 Must be written as 11. IMCEL Interrupt Mode Control Register EL 0 0 0 When DM38 = 0 Interrupt Number 56 (INTRX4) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM38 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E038H 15 14 13 EIM391 12 EIM390 11 DM39 R/W 0 DMA trigger 0: Disable 1: Enable 10 IL392 9 IL391 8 IL390 0 0 Must be written as 11. 0 0 0 When DM39 = 0 Interrupt Number 57 (INTTX4) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM39 = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM3A1 20 EIM3A0 19 DM3A R/W 0 DMA trigger 0: Disable 1: Enable 18 IL3A2 17 IL3A1 16 IL3A0 0 0 Must be written as 01. IMCEH Interrupt Mode Control Register EH FFFF E03AH 0 0 0 When DM3A = 0 Interrupt Number 58 (INTRTC) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM3A = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM3B1 28 EIM3B0 27 DM3B R/W 0 DMA trigger 0: Disable 1: Enable 26 IL3B2 25 IL3B1 24 IL3B0 0 0 0 Must be written as 11. 0 0 When DM3B = 0 Interrupt Number 59 (INTAD) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM3B = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-271 2003-03-27 TMP1941AF Interrupt Controller (11 of 12) Mnemonic Name Address 7 6 5 EIM3C1 4 EIM3C0 3 DM3C R/W 0 DMA trigger 0: Disable 1: Enable 2 IL3C2 1 IL3C1 0 IL3C0 0 0 Must be written as 10. IMCFL Interrupt Mode Control Register FL 0 0 0 When DM3C = 0 Interrupt Number 60 (INTDMA0) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM3C = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. FFFF E03CH 15 14 13 EIM3D1 12 EIM3D0 11 DM3D R/W 0 DMA trigger 0: Disable 1: Enable 10 IL3D2 9 IL3D1 8 IL3D0 0 0 Must be written as 10. 0 0 0 When DM3D = 0 Interrupt Number 61 (INTDMA1) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM3D = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 23 22 21 EIM3E1 20 EIM3E0 19 DM3E R/W 0 DMA trigger 0: Disable 1: Enable 18 IL3E2 17 IL3E1 16 IL3E0 0 0 Must be written as 10. IMCFH Interrupt Mode Control Register FH FFFF E03EH 0 0 0 When DM3E = 0 Interrupt Number 62 (INTDMA2) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM3E = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. 31 30 29 EIM3F1 28 EIM3F0 27 DM3F R/W 0 DMA trigger 0: Disable 1: Enable 26 IL3F2 25 IL3F1 24 IL3F0 0 0 Must be written as 10. 0 0 0 When DM3F = 0 Interrupt Number 63 (INTDMA3) 000: Interrupt disabled. 001-111: Priority level (1-7) When DM3F = 1 DMAC channel select 000-011: Ch. number (0-3) 100-111: Don't use. TMP1941AF-272 2003-03-27 TMP1941AF Interrupt Controller (12 of 12) Mnemonic Name Address 7 6 IVRL R 0 0 0 0 Interrupt vector for the source of the current interrupt 0 0 0 0 5 4 3 2 1 0 15 0 IVR Interrupt Vector Register FFFF E040H 14 0 13 IVRH R/W 0 12 0 11 0 10 0 9 IVRL R 8 0 0 Interrupt vector for the source of the current interrupt 23 0 22 0 21 0 20 IVRH R/W 0 19 0 18 0 15 0 16 0 31 0 Interrupt Request Clear Register 30 0 29 0 28 IVRH R/W 0 27 0 26 0 25 0 24 0 7 FFFF E060H 6 5 EICLR5 4 EICLR4 3 EICLR3 2 EICLR2 1 EICLR1 0 EICLR0 INTCLR W IVRL[9:4] value for an interrupt to be cleared TMP1941AF-273 2003-03-27 TMP1941AF 19.3 Chip Select/Wait Controller Chip Select/Wait Controller (1 of 4) Mnemonic Name Address 7 6 5 4 MA0 R/W 1 1 1 1 Bits 9-0 specify the address bits (A23-A14) to be masked. 0: The corresponding address bit is not masked. 1: The corresponding address bit is masked. 1 1 1 1 3 2 1 0 15 0 Must be written as 0. 14 0 Must be written as 0. 13 0 Must be written as 0. 12 MA0 R/W 0 Must be written as 0. 11 0 Must be written as 0. 10 0 Must be written as 0. 9 0 Address mask 0: Not masked 1: Masked 8 0 BMA0 Base/ Mask Address Register FFFF E400H 23 22 21 20 BA0 R/W 19 18 17 16 0 0 0 0 0 0 A23-A16 of the starting address for CS0 0 0 31 30 29 28 BA0 R/W 27 26 25 24 0 0 0 0 0 0 A31-A24 of the starting address for CS0 0 0 7 6 5 4 MA1 R/W 3 2 1 0 1 1 1 1 Bits 9-0 specify the address bits (A23-A14) to be masked. 0: The corresponding address bit is not masked. 1: The corresponding address bit is masked. 1 1 1 1 15 Base/ Mask Address Register 0 Must be written as 0. 14 0 Must be written as 0. 13 0 Must be written as 0. 12 MA1 R/W 0 Must be written as 0. 11 0 Must be written as 0. 10 0 Must be written as 0. 9 0 Address mask 0: Not masked 1: Masked 8 0 BMA1 FFFF E404H 23 0 22 0 21 20 BA1 R/W 19 18 17 0 16 0 0 0 0 0 A23-A16 of the starting address for CS1 31 0 30 0 29 28 BA1 R/W 27 26 25 0 24 0 0 0 0 0 A31-A24 of the starting address for CS1 TMP1941AF-274 2003-03-27 TMP1941AF Chip Select/Wait Controller (2 of 4) Mnemonic Name Address 7 6 5 4 MA2 R/W 1 1 1 1 Bits 8-0 specify the address bits (A23-A15) to be masked 0: The corresponding address bit is not masked. 1: The corresponding address bit is masked. 1 1 1 1 3 2 1 0 15 0 Must be written as 0. 14 0 Must be written as 0. 13 0 Must be written as 0. 12 MA2 R/W 0 Must be written as 0. 11 0 Must be written as 0. 10 0 Must be written as 0. 9 0 Must be written as 0. 8 0 Address mask 0: Not masked 1: Masked BMA2 Base/ Mask Address Register FFFF E408H 23 0 22 0 21 20 BA2 R/W 19 18 17 0 16 0 0 0 0 0 A23-A16 of the starting address for CS2 31 0 30 0 29 28 BA2 R/W 27 26 25 0 24 0 0 0 0 0 A31-A24 of the starting address for CS2 7 6 5 4 MA3 R/W 3 1 2 1 1 1 0 1 1 1 1 1 Bits 8-0 specify the address bits (A23-A15) to be masked 0: The corresponding address bit is not masked. 1: The corresponding address bit is masked. 15 0 Must be written as 0. 14 0 Must be written as 0. 13 0 Must be written as 0. 12 MA3 R/W 0 Must be written as 0. 11 0 Must be written as 0. 10 0 Must be written as 0. 9 0 Must be written as 0. 8 0 Address mask 0: Not masked 1: Masked BMA3 Base/ Mask Address Register FFFF E40CH 23 0 22 0 21 20 BA3 R/W 19 18 17 0 16 0 0 0 0 0 A23-A16 of the starting address for CS3 31 0 30 0 29 28 BA3 R/W 27 26 25 0 24 0 0 0 0 0 A31-A24 of the starting address for CS3 TMP1941AF-275 2003-03-27 TMP1941AF Chip Select/Wait Controller (3 of 4) Mnemonic Name Address 7 B0OM W 0 0 Chip select output waveform 00: ROM/SRAM Don't use any other value. 6 5 4 B0BUS 0 Data bus width 0: 16-bit 1: 8-bit 3 2 B0W 1 0 W 0 1 0 1 Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 15 14 13 12 11 B0E W 0 CS0 enable 0: Disable 1: Enable 10 9 B0RCV W 8 B01CS Chip Select/ Wait Control Register FFFF E480H 0 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. 23 B1OM W 22 21 20 B1BUS 0 Data bus width 0: 16-bit 1: 8-bit 19 18 B1W 17 16 0 0 Chip select output waveform 00: ROM/SRAM Don't use any other value. W 0 1 0 1 Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0110: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 31 30 29 28 27 B1E W 0 CS1 enable 0: Disable 1: Enable 26 25 B1RCV W 24 0 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. TMP1941AF-276 2003-03-27 TMP1941AF Chip Select/Wait Controller (4 of 4) Mnemonic Name Address 7 B2OM W 0 0 Chip select output waveform 00: ROM/SRAM Don't use any other value. 6 5 4 B2BUS 0 Data bus width 0: 16-bit 1: 8-bit 3 2 B2W 1 0 1 W 0 1 0 Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 15 14 13 12 11 10 9 B2RCV W 8 B23CS Chip Select/ Wait Control Register FFFF E484H B2E B2M W W 1 0 CS2 enable CS2 space select 0: Disable 1: Enable 0: Whole 4-Gbyte space 1: CS space 0 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. 23 22 21 20 B3BUS 0 Data bus width 0: 16-bit 1: 8-bit 19 18 B3W 17 16 B3OM W 0 0 Chip select output waveform 00: ROM/SRAM Don't use any other value. W 0 1 0 1 Number of wait-state cycles 0000: No wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 31 30 29 28 27 B3E W 0 CS3 enable 0: Disable 1: Enable 26 25 B3RCV W 24 0 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. 7 BEXOM W 6 5 4 BEXBUS 0 Data bus width 0: 16-bit 1: 8-bit 3 2 BEXW 1 0 0 1 BEXCS Chip Select/ Wait Control Register FFFF E488H 0 0 Chip select output waveform 00: ROM/SRAM Don't use any other value. W 0 1 Sets the number of wait cycles 0000-0111: 0-7 wait states 1111: (1+N) wait states, as determined by the WAIT pin Don't use any other value. 15 14 13 12 11 10 9 BEXRCV W 8 0 0 Number of dummy cycles (Read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: No dummy cycle 11: Don't use. TMP1941AF-277 2003-03-27 TMP1941AF 19.4 Clock Generator (CG) Clock Generator (1 of 2) Mnemonic Name Address 7 XEN 1 High-speed oscillator 6 XTEN 0 Low-speed oscillator 5 RXEN 1 High-speed oscillator after exiting STOP mode 0: Disable 1: Enable 4 RXTEN 3 RSYSCK 2 WUEF 1 PRCK1 0 PRCK0 R/W 0 0 Low-speed Clock select oscillator after exiting after exiting STOP mode STOP mode 0: Disable 1: Enable 0: Highspeed 1: Lowspeed SYSCR0 System Clock Control Register 0 FFFF EE00H 0: Disable 1: Enable 0: Disable 1: Enable 0 0 0 Prescaler clock select Oscillator warm-up 00: fperiph/4 period (WUP) timer 01: fperiph/2 10: fperiph On writes: 11: Reserved 0: Don'tcare 1: Start WUP On reads: 0: Expired 1: Not expired System Clock Control Register 1 SYSCK 0 System clock (fsys) select FPSEL R/W 0 fperiph select DFOSC 0 High-speed oscillator frequency divide factor 0: Divide-by2 1: Divide-by1 GEAR1 R/W GEAR0 1 1 High-speed clock (fc) gear select 00: fc 01: fc/2 10: fc/4 11: fc/8 SYSCR1 FFFF EE01H 0: Highspeed 0: fgear (fgear) 1: fc 1: Lowspeed (fs) DRVOSCH R/W 0 High-speed oscillator drive capability 0: High 1: Low DRVOSCL R/W 0 Low-speed oscillator drive capability 0: High 1: Low WUPT1 WUPT0 R/W R/W 1 0 Oscillator warm-up time 00: Reserved 01: 28/input frequency 10: 214/input frequency 11: 216/input frequency SYSCR2 System Clock Control Register 2 STBY1 STBY0 R/W R/W 1 1 Standby mode select 00: Reserved 01: STOP mode 10: SLEEP mode 11: IDLE mode FFFF EE02H DRVE R/W 0 1: Pins are driven in STOP mode. 0: Pins are not driven in STOP mode. LUPTM R/W SYSCR3 System Clock Control Register 3 FFFF EE03H SCOSEL R/W 0 SCOUT output select 0: fs 1: fsys ALESEL R/W 1 ALE output width select 0: fsys x 0.5 1: fsys x 1.5 LUPFG 0 0 PLL lock PLL lock 0: Locked time select 1: Unlocked 0: 216/input frequency 1: 212/input frequency ADCCK1 ADCCK0 R/W R/W 0 0 ADC conversion clock (fadc) select 00: fsys/2 01: fsys/4 10: fsys/8 11: Don't use. ADCCLK ADC Conversion Clock Register FFFF EE04H TMP1941AF-278 2003-03-27 TMP1941AF Clock Generator (2 of 2) Mnemonic Name Address Interrupt CG Control Register A0 7 6 5 EMCG01 4 EMCG00 3 2 1 0 INT0EN R/W 0 INT0 enable 0: Disable 1: Enable IMCGA0 FFFF EE10H R/W 1 0 Wake-up INT0 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge EMCG11 R/W 1 0 Wake-up INT1 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge EMCG21 R/W 1 0 Wake-up INT2 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge EMCG31 EMCG30 1 0 Wake-up INT3 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge EMCG41 EMCG40 1 0 Wake-up INT4 sensitivity 00: Low level 01: High level 10: Falling edge 11: Rising edge 1 0 Must be written as 10. EMCG20 EMCG10 IMCGA1 Interrupt CG Control Register A1 FFFF EE11H INT1EN R/W 0 INT1 enable 0: Disable 1: Enable IMCGA2 Interrupt CG Control Register A2 FFFF EE12H INT2EN R/W 0 INT2 enable 0: Disable 1: Enable IMCGA3 Interrupt CG Control Register A3 FFFF EE13H 0 INT3 enable 0: Disable 1: Enable IMCGB0 Interrupt CG Control Register B0 FFFF EE14H 0 INT4 enable 0: Disable 1: Enable IMCGB1 Interrupt CG Control Register B1 FFFF EE15H 0 Must be written as 0. 0 Must be written as 0. INTRTCEN R/W 0 INTRTC enable 0:Disable 1: Enable IMCGB2 Interrupt CG Control Register B2 FFFF EE16H 1 0 Must be written as 10. IMCGB3 Interrupt CG Control Register B3 FFFF EE17H EMCG71 R/W EMCG72 1 0 Must be written as 11. Interrupt Request Clear Register FFFF EE20H EICRCG ICRCG2 ICRCG1 ICRCG0 W 0 0 0 Clear interrupt request (Only when relevant interrupts are programmed to be used to exit STOP/SLEEP mode.) 000: INT0 100: INT4 001: INT1 101: Reserved 010: INT2 110: Reserved 011: INT3 111: INTRTC TMP1941AF-279 2003-03-27 TMP1941AF 19.5 DMA Controller (DMAC) DMA Controller (1 of 16) Mnemonic Name Address 7 SAC0 0 Source address count (bits 8 & 7) 00: Incremented 01: Decremented 1x: Fixed 6 DIO 0 Destination (I/O) 0: Memory 1: I/O 5 DAC1 4 DAC0 R/W 3 TrSiz1 0 Transfer size 0x: 32 bits 10: 16 bits 11: 8 bits 2 TrSiz0 0 1 DPS1 0 Device port size 0x: 32 bits 10: 16 bits 11: 8 bits 0 DPS0 0 0 0 Destination address count 00: Incremented 01: Decremented 1x: Fixed 15 0 Must be written as 0. DMA Channel Control Register 0 FFFF E200H 14 ExR 0 External request mode 1: External transfer request 0: Internal transfer request 13 PosE 0 Must be written as 0. 12 Lev R/W 0 Must be written as 1. 11 SReq 0 Snoop request 0: Disabled 1: Enabled 10 RelEn 9 SIO 8 SAC1 0 Source address count (bits 8 & 7) 00: Incremented 01: Decremented 1x: Fixed 0 0 Bus release Source (I/O) request 0: Memory enable 1: I/O 0: Disabled 1: Enabled CCR0 23 NIEn 1 Normal completion interrupt enable 0: Disabled 1: Enabled 22 AbIEn 1 Abnormal termination interrupt enable 0: Disabled 1: Enabled 21 1 Must be written as 0. 20 R/W 0 Must be written as 0. 19 0 Must be written as 0. 18 0 Must be written as 0. 17 Big 1 Must be written as 0. 16 0 Must be written as 0. 31 Str W 0 1: Channel 0 start 30 0 29 0 28 0 27 0 26 0 25 0 24 W 0 Must be written as 0. TMP1941AF-280 2003-03-27 TMP1941AF DMA Controller (2 of 16) Mnemonic Name Address 7 0 6 0 5 0 4 0 3 0 2 0 Must be written as 0. 1 R/W 0 Must be written as 0. 0 0 Must be written as 0. 15 0 DMA Channel Status Register 0 FFFF E204H 14 0 13 0 12 0 11 0 10 0 9 0 8 0 CSR0 23 NC 0 22 AbC R/W 0 21 0 20 BES 0 19 BED R 0 18 Conf 0 17 0 16 0 1: Normal 1: Abnormal Must be 1: Bus error 1: Bus error 1: Configuration completion termination written as 0. (source) (destination) error status flag status flag 31 Act R 0 1: Channel 0 active 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-281 2003-03-27 TMP1941AF DMA Controller (3 of 16) Mnemonic Name Address 7 SAddr7 6 SAddr6 5 SAddr5 4 SAddr4 R/W Undefined 3 SAddr3 2 SAddr2 1 SAddr1 0 SAddr0 15 SAddr15 DMA Source Address Register 0 14 SAddr14 13 SAddr13 12 SAddr12 R/W Undefined 11 SAddr11 10 SAddr10 9 SAddr9 8 SAddr8 SAR0 FFFF E208H 23 SAddr23 22 SAddr22 21 SAddr21 20 SAddr20 R/W Undefined 19 SAddr19 18 SAddr18 17 SAddr17 16 SAddr16 31 SAddr31 30 SAddr30 29 SAddr29 28 SAddr28 R/W Undefined 27 SAddr27 26 SAddr26 25 SAddr25 24 SAddr24 7 DAddr7 6 DAddr6 5 DAddr5 4 DAddr4 R/W Undefined 3 DAddr3 2 DAddr2 1 DAddr1 0 DAddr0 15 DAddr15 DMA Destination Address Register 0 FFFF E20CH 14 DAddr14 13 DAddr13 12 DAddr12 R/W Undefined 11 DAddr11 10 DAddr10 9 DAddr9 8 DAddr8 DAR0 23 DAddr23 22 DAddr22 21 DAddr21 20 DAddr20 R/W Undefined 19 DAddr19 18 DAddr18 17 DAddr17 16 DAddr16 31 DAddr31 30 DAddr30 29 DAddr29 28 DAddr28 R/W Undefined 27 DAddr27 26 DAddr26 25 DAddr25 24 DAddr24 7 BC7 6 BC6 5 BC5 4 BC4 R/W Undefined 3 BC3 2 BC2 1 BC1 0 BC0 15 BC15 DMA Byte Count Register 0 FFFF E210H 14 BC14 13 BC13 12 BC12 R/W Undefined 11 BC11 10 BC10 9 BC9 8 BC8 BCR0 23 BC23 22 BC22 21 BC21 20 BC20 R/W Undefined 19 BC19 18 BC18 17 BC17 16 BC16 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-282 2003-03-27 TMP1941AF DMA Controller (4 of 16) Mnemonic Name Address 7 0 6 0 5 DACM2 4 DACM1 3 DACM0 R/W 2 SACM2 1 SACM1 0 SACM0 DTCR0 DMA Transfer Control Register 0 0 0 0 Bit position at which destination addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved 0 0 0 Bit position at which source addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved FFFF E218H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-283 2003-03-27 TMP1941AF DMA Controller (5 of 16) Mnemonic Name Address 7 SAC0 0 Source address count (bits 8 & 7) 00: Incremented 01: Decremented 1x: Fixed 6 DIO 0 Destination (I/O) 0: Memory 1: I/O 5 DAC1 0 4 DAC0 R/W 0 3 TrSiz1 0 2 TrSiz0 0 1 DPS1 0 Device port size 0x: 32 bits 10: 16 bits 11: 8 bits 0 DPS0 0 Destination address count Transfer size 00: Incremented 0x: 32 bits 01: Decremented 10: 16 bits 1x: Fixed 11: 8 bits 15 0 14 ExR 0 13 PosE 0 12 Lev R/W 0 11 SReq 0 10 RelEn 0 9 SIO 0 8 SAC1 0 Source address count (bits 8 & 7) 00: Inc 01: Dec 1x: Fixed CCR1 DMA Channel Control Register 1 FFFF E220H Must be External written as 0. request mode 1: External 0: Internal Must be Must be Snoop written as 0. written as 1. request 0: Disabled 1: Enabled Bus release Source (I/O) request 0: Memory enable 1: I/O 0: Disabled 1: Enabled 23 NIEn 1 Normal completion interrupt enable 0: Disabled 1: Enabled 22 AbIEn 1 Abnormal termination interrupt enable 0: Disabled 1: Enabled 21 1 20 19 18 0 17 Big 1 16 0 R/W 0 0 Must be Must be Must be Must be Must be Must be written as 0. written as 0. written as 0. written as 0. written as 0. written as 0. 31 Str W 0 1: Channel 1 start 30 0 29 0 28 0 27 0 26 0 25 0 24 W 0 Must be written as 0. TMP1941AF-284 2003-03-27 TMP1941AF DMA Controller (6 of 16) Mnemonic Name Address 7 0 6 0 5 0 4 0 3 0 2 0 1 R/W 0 0 0 Must be written Must be Must be as 0. written as written as 0. 0. 15 0 DMA Channel Status Register 1 14 0 13 0 12 0 11 0 10 0 9 0 8 0 CSR1 FFFF E224H 23 NC 0 22 AbC R/W 0 21 0 20 BES 0 19 BED R 0 18 Conf 0 17 0 16 0 1: Normal 1: Abnormal Must be 1: Bus error 1: Bus error 1: Configuration termination termination written as 0. (source) (destination) error status status flag flag 31 Act R 0 1: Channel 1 active 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-285 2003-03-27 TMP1941AF DMA Controller (7 of 16) Mnemonic Name Address 7 SAddr7 6 SAddr6 5 SAddr5 4 SAddr4 R/W Undefined 3 SAddr3 2 SAddr2 1 SAddr1 0 SAddr0 15 SAddr15 DMA Source Address Register 1 14 SAddr14 13 SAddr13 12 SAddr12 R/W 11 SAddr11 10 SAddr10 9 SAddr9 8 SAddr8 SAR1 FFFF E228H Undefined 23 SAddr23 22 SAddr22 21 SAddr21 20 SAddr20 R/W Undefined 19 SAddr19 18 SAddr18 17 SAddr17 16 SAddr16 31 SAddr31 30 SAddr30 29 SAddr29 28 SAddr28 R/W Undefined 27 SAddr27 26 SAddr26 25 SAddr25 24 SAddr24 7 DAddr7 6 DAddr6 5 DAddr5 4 DAddr4 R/W Undefined 3 DAddr3 2 DAddr2 1 DAddr1 0 DAddr0 15 DAddr15 DMA Destination Address Register 1 FFFF E22CH 14 DAddr14 13 DAddr13 12 DAddr12 R/W Undefined 11 DAddr11 10 DAddr10 9 DAddr9 8 DAddr8 DAR1 23 DAddr23 22 DAddr22 21 DAddr21 20 DAddr20 R/W Undefined 19 DAddr19 18 DAddr18 17 DAddr17 16 DAddr16 31 DAddr31 30 DAddr30 29 DAddr29 28 DAddr28 R/W Undefined 27 DAddr27 26 DAddr26 25 DAddr25 24 DAddr24 7 BC7 6 BC6 5 BC5 4 BC4 R/W Undefined 3 BC3 2 BC2 1 BC1 0 BC0 15 BC15 DMA Byte Count Register 1 FFFF E230H 14 BC14 13 BC13 12 BC12 R/W Undefined 11 BC11 10 BC10 9 BC9 8 BC8 BCR1 23 BC23 22 BC22 21 BC21 20 BC20 R/W Undefined 19 BC19 18 BC18 17 BC17 16 BC16 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-286 2003-03-27 TMP1941AF DMA Controller (8 of 16) Mnemonic Name Address 7 0 6 0 5 DACM2 4 DACM1 3 DACM0 R/W 2 SACM2 1 SACM1 0 SACM0 DTCR1 DMA Transfer Control Register 1 FFFF E238H 0 0 0 Bit position at which destination addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved 0 0 0 Bit position at which source addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-287 2003-03-27 TMP1941AF DMA Controller (9 of 16) Mnemonic Name Address 7 SAC0 0 Source address count (bits 8 & 7) 00: Incremented 01: Decremented 1x: Fixed 6 DIO 0 Destination (I/O) 0: Memory 1: I/O 5 DAC1 0 4 DAC0 R/W 0 3 TrSiz1 0 Transfer size 0x: 32 bits 10: 16 bits 11: 8 bits 2 TrSiz0 0 1 DPS1 0 Device port size 0x: 32 bits 10: 16 bits 11: 8 bits 0 DPS0 0 Destination address count 00: Incremented 01: Decremented 1x: Fixed 15 0 Must be written as 0. DMA Channel Control Register 2 FFFF E240H 14 ExR 0 External request mode 1: External transfer request 0: Internal transfer request 13 PosE 0 Must be written as 0. 12 Lev R/W 0 Must be written as 1. 11 SReq 0 Snoop request 0: Disabled 1: Enabled 10 RelEn 0 Bus release request enable 0: Disabled 1: Enabled 9 SIO 0 Source (I/O) 0: Memory 1: I/O 8 SAC1 0 Source address count (bits 8 & 7) 00: Incremented 01: Decremented 1x: Fixed CCR2 23 NIEn 1 Normal completion interrupt enable 0: Disabled 1: Enabled 22 AbIEn 1 Abnormal termination interrupt enable 0: Disabled 1: Enabled 21 1 Must be written as 0. 20 R/W 0 Must be written as 0. 19 0 Must be written as 0. 18 0 Must be written as 0. 17 Big 1 Must be written as 0. 16 0 Must be written as 0. 31 Str W 0 1: Channel 2 start 30 0 29 0 28 0 27 0 26 0 25 0 24 W 0 Must be written as 0. TMP1941AF-288 2003-03-27 TMP1941AF DMA Controller (10 of 16) Mnemonic Name Address 7 0 6 0 5 0 4 0 3 0 2 0 Must be written as 0. 1 R/W 0 Must be written as 0. 0 0 Must be written as 0. 15 0 DMA Channel Status Register 2 FFFF E244H 14 0 13 0 12 0 11 0 10 0 9 0 8 0 CSR2 23 NC 22 21 20 19 18 17 0 16 0 AbC BES R/W 0 0 0 0 1: Normal 1: Abnormal Must be 1: Bus completion termination written as 0. error status flag status flag (source) BED Conf R 0 0 1: Bus error 1: Configuration (destination) error 31 Act R 0 1: Channel 2 active 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-289 2003-03-27 TMP1941AF DMA Controller (11 of 16) Mnemonic Name Address 7 SAddr7 6 SAddr6 5 SAddr5 4 SAddr4 R/W Undefined 3 SAddr3 2 SAddr2 1 SAddr1 0 SAddr0 15 SAddr15 DMA Source Address Register 2 14 SAddr14 13 SAddr13 12 SAddr12 R/W Undefined 11 SAddr11 10 SAddr10 9 SAddr9 8 SAddr8 SAR2 FFFF E248H 23 SAddr23 22 SAddr22 21 SAddr21 20 SAddr20 R/W Undefined 19 SAddr19 18 SAddr18 17 SAddr17 16 SAddr16 31 SAddr31 30 SAddr30 29 SAddr29 28 SAddr28 R/W Undefined 27 SAddr27 26 SAddr26 25 SAddr25 24 SAddr24 7 DAddr7 6 DAddr6 5 DAddr5 4 DAddr4 R/W Undefined 3 DAddr3 2 DAddr2 1 DAddr1 0 DAddr0 15 DAddr15 DMA Destination Address Register 2 FFFF E24CH 14 DAddr14 13 DAddr13 12 DAddr12 R/W Undefined 11 DAddr11 10 DAddr10 9 DAddr9 8 DAddr8 DAR2 23 DAddr23 22 DAddr22 21 DAddr21 20 DAddr20 R/W Undefined 19 DAddr19 18 DAddr18 17 DAddr17 16 DAddr16 31 DAddr31 30 DAddr30 29 DAddr29 28 DAddr28 R/W Undefined 27 DAddr27 26 DAddr26 25 DAddr25 24 DAddr24 7 BC7 6 BC6 5 BC5 4 BC4 R/W Undefined 3 BC3 2 BC2 1 BC1 0 BC0 15 BC15 DMA Byte Count Register 2 FFFF E250H 14 BC14 13 BC13 12 BC12 R/W Undefined 11 BC11 10 BC10 9 BC9 8 BC8 BCR2 23 BC23 22 BC22 21 BC21 20 BC20 R/W Undefined 19 BC19 18 BC18 17 BC17 16 BC16 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-290 2003-03-27 TMP1941AF DMA Controller (12 of 16) Mnemonic Name Address 7 0 6 0 5 DACM2 4 DACM1 3 DACM0 R/W 2 SACM2 1 SACM1 0 SACM0 DTCR2 DMA Transfer Control Register 2 0 0 0 Bit position at which destination addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved 0 0 0 Bit position at which source addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved FFFF E258H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-291 2003-03-27 TMP1941AF DMA Controller (13 of 16) Mnemonic Name Address FFFF E260H 7 SAC0 0 Source address count (bits 8 & 7) 00: Incremented 01: Decremented 1x: Fixed 6 DIO 0 Destination (I/O) 0: Memory 1: I/O 5 DAC1 0 4 DAC0 R/W 0 3 TrSiz1 0 Transfer size 0x: 32 bits 10: 16 bits 11: 8 bits 2 TrSiz0 0 1 DPS1 0 Device port size 0x: 32 bits 10: 16 bits 11: 8 bits 0 DPS0 0 Destination address count 00: Incremented 01: Decremented 1x: Fixed 15 0 Must be written as 0. DMA Channel Control Register 3 14 ExR 0 External request mode 1: External transfer request 0: Internal transfer request 13 PosE 0 Must be written as 0. 12 Lev R/W 0 Must be written as 1. 11 SReq 0 Snoop request 0: Disabled 1: Enabled 10 RelEn 0 Bus release request enable 0: Disabled 1: Enabled 9 SIO 0 Source (I/O) 0: Memory 1: I/O 8 SAC1 0 Source address count (bits 8 & 7) 00: Incremented 01: Decremented 1x: Fixed CCR3 23 NIEn 1 Normal completion interrupt enable 0: Disabled 1: Enabled 22 AbIEn 1 Abnormal termination interrupt enable 0: Disabled 1: Enabled 21 1 Must be written as 0. 20 R/W 0 Must be written as 0. 19 0 Must be written as 0. 18 0 Must be written as 0. 17 Big 1 Must be written as 0. 16 0 Must be written as 0. 31 Str W 0 1: Channel 3 start 30 0 29 0 28 0 27 0 26 0 25 0 24 W 0 Must be written as 0. TMP1941AF-292 2003-03-27 TMP1941AF DMA Controller (14 of 16) Mnemonic Name Address 7 0 6 0 5 0 4 0 3 0 2 0 Must be written as 0. 1 0 R/W 0 0 Must be Must be written as written 0. as 0. 15 0 DMA Channel Status Register 3 FFFF E264H 14 0 13 0 12 0 11 0 10 0 9 0 8 0 CSR3 23 NC 22 21 20 19 18 17 0 16 0 AbC BES BED Conf R/W R 0 0 0 0 0 0 1: Normal 1: Abnormal Must be 1: Bus error 1: Bus error 1: Configuration termination termination written as 0. (source) (destination) error status flag status flag 31 Act R 0 1: Channel 3 active 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-293 2003-03-27 TMP1941AF DMA Controller (15 of 16) Mnemonic Name Address 7 SAddr7 6 SAddr6 5 SAddr5 4 SAddr4 R/W Undefined 3 SAddr3 2 SAddr2 1 SAddr1 0 SAddr0 15 SAddr15 DMA Source Address Register 3 14 SAddr14 13 SAddr13 12 SAddr12 R/W Undefined 11 SAddr11 10 SAddr10 9 SAddr9 8 SAddr8 SAR3 FFFF E268H 23 SAddr23 22 SAddr22 21 SAddr21 20 SAddr20 R/W Undefined 19 SAddr19 18 SAddr18 17 SAddr17 16 SAddr16 31 SAddr31 30 SAddr30 29 SAddr29 28 SAddr28 R/W Undefined 27 SAddr27 26 SAddr26 25 SAddr25 24 SAddr24 7 DAddr7 6 DAddr6 5 DAddr5 4 DAddr4 R/W Undefined 3 DAddr3 2 DAddr2 1 DAddr1 0 DAddr0 15 DAddr15 DMA Destination Address Register 3 FFFF E26CH 14 DAddr14 13 DAddr13 12 DAddr12 R/W Undefined 11 DAddr11 10 DAddr10 9 DAddr9 8 DAddr8 DAR3 23 DAddr23 22 DAddr22 21 DAddr21 20 DAddr20 R/W Undefined 19 DAddr19 18 DAddr18 17 DAddr17 16 DAddr16 31 DAddr31 30 DAddr30 29 DAddr29 28 DAddr28 R/W Undefined 27 DAddr27 26 DAddr26 25 DAddr25 24 DAddr24 7 BC7 6 BC6 5 BC5 4 BC4 R/W Undefined 3 BC3 2 BC2 1 BC1 0 BC0 15 BC15 DMA Byte Count Register 3 FFFF E270H 14 BC14 13 BC13 12 BC12 R/W Undefined 11 BC11 10 BC10 9 BC9 8 BC8 BCR3 23 BC23 22 BC22 21 BC21 20 BC20 R/W Undefined 19 BC19 18 BC18 17 BC17 16 BC16 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 TMP1941AF-294 2003-03-27 TMP1941AF DMA Controller (16 of 16) Mnemonic Name Address 7 0 6 0 5 DACM2 4 DACM1 3 DACM0 R/W 2 SACM2 1 SACM1 0 SACM0 DTCR3 DMA Transfer Control Register 3 0 0 0 Bit position at which destination addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved 0 0 0 Bit position at which source addresses are counted 000: Bit 0 001: Bit 4 010: Bit 8 011: Bit 12 100: Bit 16 101: Reserved 110: Reserved 111: Reserved FFFF E278H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 15 0 DCR DMA Control Register FFFF E280H 14 0 13 0 12 0 11 0 10 0 9 0 8 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 31 Rst W 0 1: DMAC software reset 30 0 29 0 28 0 27 0 26 0 25 0 24 0 7 DOT7 6 DOT6 5 DOT5 4 DOT4 R/W Undefined 3 DOT3 2 DOT2 1 DOT1 0 DOT0 15 DOT15 DMA Data Holding Register FFFF E28CH 14 DOT14 13 DOT13 12 DOT12 R/W Undefined 11 DOT11 10 DOT10 9 DOT9 8 DOT8 DHR 23 DOT23 22 DOT22 21 DOT21 20 DOT20 R/W Undefined 19 DOT19 18 DOT18 17 DOT17 16 DOT16 31 DOT31 30 DOT30 29 DOT29 28 DOT28 R/W Undefined 27 DOT27 26 DOT26 25 DOT25 24 DOT24 TMP1941AF-295 2003-03-27 TMP1941AF 19.6 8-Bit Timers (TMRAs) Mnemonic Name Address 7 TA0RDE R/W TA01RUN TMRA01 Run Register FFFF F100H 0 Double Buffering 0: Disable 1: Enable TA2RDE R/W TA23RUN TMRA23 Run Register FFFF F108H 0 Double Buffering 0: Disable 1: Enable TA01M1 TMRA01 Mode Register 6 5 4 3 I2TA01 0 IDLE 0: Off 1: On 2 1 0 TA0RUN TA01PRUN TA1RUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run 0 0 Run/Stop Control 0: Stop & clear 1: Run I2TA23 0 IDLE 0: Off 1: On TA23PRUN TA3RUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run TA1CLK0 TA2RUN 0 0 Run/Stop Control 0: Stop & clear 1: Run TA01M0 PWM01 0 PWM period 00: Reserved 6 01: 2 -1 10: 27-1 11: 28-1 PWM21 0 PWM period 00: Reserved 6 01: 2 -1 10: 27-1 11: 28-1 PWM00 R/W 0 TA1CLK1 TA0CLK1 TA0CLK0 TA01MOD FFFF F104H 0 0 Operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit PPG 11: 8-bit PWM TA23M1 TA23M0 0 0 TMRA1 clock source 00: TA0TRG 01: T1 10: T16 11: T256 TA3CLK1 R/W TA3CLK0 0 0 TMRA0 clock source 00: TA0IN input 01: T1 10: T4 11: T16 TA2CLK1 TA2CLK0 PWM20 0 TA23MOD TMRA23 Mode Register FFFF F10CH 0 0 Operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit PPG 11: 8-bit PWM 0 0 TMRA3 clock source 00: TA2TRG 01: T1 10: T16 11: T256 TAFF1C1 0 0 TMRA2 clock source 00: TA2IN input pin 01: T1 10: T4 11: T16 TAFF1IS 0 TA1FF toggle trigger 0: TMRA0 1: TMRA1 TA1FFCR TMRA01 Timer FlipFlop Control Register FFFF F105H TAFF1C0 TAFF1IE R/W 1 1 0 00: Toggles TA1FF. TA1FF (software toggle) toggle 01: Sets TA1FF to 1. enable 10: Clears TA1FF to 0. 0: Disable 11: Don't-care 1: Enable This field is always read as 11. TAFF3C0 TAFF3IE R/W 1 1 0 00: Toggles TA3FF TA3FF (software toggle). toggle 01: Sets TA3FF to 1 enable 10: Clears TA3FF to 0 0: Disable 11: Don't care 1: Enable This field is always read as 11. TAFF3C1 TA3FFCR TMRA23 Timer FlipFlop Control Register FFFF F10DH TAFF3IS 0 TA3FF trigger 0: TMRA2 1: TMRA3 TMP1941AF-296 2003-03-27 TMP1941AF 19.7 16-Bit Timer/Event Counters (TMRBs) 16-Bit Timer Control (1 of 2) Mnemonic Name Address 7 TB0RDE R/W TB0RUN TMRB0 Run Register FFFF F180H 0 Double Buffering 0: Disable 1: Enable TB1RDE R/W TB1RUN TMRB1 Run Register FFFF F190H 0 Double Buffering 0: Disable 1: Enable TB2RDE R/W TB2RUN TMRB2 Run Register FFFF F1A0H 0 Double Buffering 0: Disable 1: Enable TB3RDE R/W TB3RUN TMRB3 Run Register FFFF F1B0H 0 Double Buffering 0: Disable 1: Enable R/W TB0MOD TMRB0 Mode Register FFFF F182H 0 0 Must be written as 00. 0 Must be written as 0. 0 Must be written as 0. 0 Must be written as 0. 0 Must be written as 0. 6 5 4 3 I2TB0 0 IDLE 0: Off 1: On 2 TB0PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run TB1PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run TB2PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run TB3PRUN R/W 0 Prescalar Run/Stop Control 0: Stop 1: Run TB0CLE R/W 0 UC0 clear control 0: Disable 1: Enable TB1CLE R/W 0 UC1 clear control 0: Disable 1: Enable TB2CLE R/W 0 UC2 clear control 0: Disable 1: Enable TB3CLE R/W 0 UC3 clear control 0: Disable 1: Enable 1 0 TB0RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run TB1RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run TB2RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run TB3RUN R/W 0 Run/Stop Control 0: Stop & clear 1: Run TB0CLK0 I2TB1 0 IDLE 0: Off 1: On I2TB2 0 IDLE 0: Off 1: On I2TB3 0 IDLE 0: Off 1: On TB0CP0 W* 1 Software capture 0: Capture 1: Don't care TB1CP0 W* 1 Software capture 0: Capture 1: Don't care TB2CP0 W* 1 Software capture 0: Capture 1: Don't care TB3CP0 W* 1 Software capture 0: Capture 1: Don't care TB0CPM1 TB0CPM0 TB0CLK1 0 0 Capture triggers 00: Disabled 01: TB0IN0TB0IN1 10: TB0IN0TB0IN0 11: TA1OUTTA1OUT TB1CPM1 TB1CPM0 0 0 TMRB0 clock source 00: TB0IN0 input 01: T1 10: T4 11: T16 TB1CLK1 TB1CLK0 R/W TB1MOD TMRB1 Mode Register FFFF F192H 0 0 Must be written as 00. 0 0 Capture triggers 00: Disabled 01: TB1IN0TB1IN1 10: TB1IN0TB1IN0 11: TA1OUTTA1OUT TB2CPM1 TB2CPM0 0 0 TMRB1 clock source 00: TB1IN0 input 01: T1 10: T4 11: T16 TB2CLK1 TB2CLK0 R/W TB2MOD TMRB2 Mode Register FFFF F1A2H 0 0 Must be written as 00. 0 0 Capture triggers 00: Disabled 01: TB2IN0TB2IN1 10: TB2IN0TB2IN0 11: TA1OUTTA1OUT TB3CPM1 TB3CPM0 0 0 TMRB2 clock source 00: TB2IN0 input 01: T1 10: T4 11: T16 TB3CLK1 TB3CLK0 R/W TB3MOD TMRB3 Mode Register FFFF F1B2H 0 0 Must be written as 00. 0 0 Capture triggers 00: Disabled 01: Disabled 10: Disabled 11: TA1OUTTA1OUT 0 0 TMRB3 clock source 00: TB3IN0 input 01: T1 10: T4 11: T16 TMP1941AF-297 2003-03-27 TMP1941AF 16-Bit Timer Control (2 of 2) Mnemonic Name Address 7 TMRB0 Timer FlipFlop Control Register 6 5 TB0C1T1 4 3 2 TB0E0T1 0 1 0 W* 1 1 Must be written as 11. FFFF F183H TB0FFCR TB0C0T1 TB0E1T1 R/W 0 0 0 TB0FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC0 TB0CP1 TB1C1T1 UC0 TB0CP0 UC0 = TB0RG1 * This field is always read as 11. W* TMRB1 Timer FlipFlop Control Register 1 1 Must be written as 11. FFFF F193H UC0 = TB0RG0 TB1E0T1 0 TB0FF0C1 TB0FF0C0 W* 1 1 TB0FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. TB1FF0C1 TB1FF0C0 W* 1 1 TB1FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. TB2FF0C1 TB2FF0C0 W* 1 1 TB2FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. TB3FF0C1 TB3FF0C0 W* 1 1 TB3FF0 control 00: Toggle 01: Set 10: Clear 11: Don't care * This field is always read as 11. TB1FFCR TB1C0T1 TB1E1T1 R/W 0 0 0 TB1FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC1 TB1CP1 TB2C1T1 UC1 TB1CP0 UC1 = TB1RG1 * This field is always read as 11. W* TMRB2 Timer FlipFlop Control Register 1 1 Must be written as 11. FFFF F1A3H UC1 = TB1RG0 TB2E0T1 0 TB2FFCR TB2C0T1 TB2E1T1 R/W 0 0 0 TB2FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC2 TB2CP1 TB3C1T1 UC2 TB2CP0 UC2 = TB2RG1 * This field is always read as 11. W* TMRB3 Timer FlipFlop Control Register 1 1 Must be written as 11. FFFF F1B3H UC2 = TB2RG0 TB3E0T1 0 TB3FFCR TB3C0T1 TB3E1T1 R/W 0 0 0 TB3FF0 toggle-trigger 0: Trigger disabled 1: Trigger enabled UC3 TB3CP1 UC3 TB3CP0 UC3 = TB3RG1 * This field is always read as 11. UC3 = TB3RG0 TMP1941AF-298 2003-03-27 TMP1941AF 19.8 Serial I/O (SIO) SIO0 Mnemonic Name Address SC0CR Serial Channel 0 Control Register FFFF F201H 7 RB8 R 0 Bit 8 of a received character TB8 0 Bit 8 of a transmitted character 6 EVEN 5 PE 4 3 2 1 SCLKS R/W 0 0:SCLK0 1:SCLK0 0 IOC 0 0: Baud rate generator 1: SCLK0 input SC0 R/W 0 0 Parity type Parity 0: Odd 0: Disabled 1: Even 1: Enabled CTSE 0 Handshake control 0: Disables CTS operation 1: Enables CTS operation BR0ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled FDPX0 R/W 0 Synchronous 0: Halfduplex 1: Fullduplex RXE 0 Receive control 0: Disables receiver 1: Enables receiver OERR PERR FERR R (Cleared when read) 0 0 0 1: Error has occurred. Overrun Parity Framing SC0MOD0 Serial Channel 0 Mode Register 0 FFFF F202H WU R/W 0 Wake-up function 0: Disabled 1: Enabled SM1 SM0 SC1 0 0 Serial transfer mode 00: I/O Interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode 0 0 Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: External clock (SCLK0 input) BR0CR Baud Rate Generator 0 Control Register FFFF F203H 0 Must be written as 0. BR0CK1 0 00: T0 01: T2 10: T8 11: T32 BR0CK0 R/W 0 BR0S3 0 BR0S2 0 BR0S1 0 BR0S0 0 Clock divisor value N BR0ADD Baud Rate Generator 0 Control Register Serial Channel 0 Mode Register 1 FFFF F204H I2S0 R/W 0 IDLE 0: Off 1: On BR0K3 0 BR0K2 R/W BR0K1 BR0K0 0 0 0 Value of K in N+(16-K)/16 SC0MOD1 FFFF F205H TMP1941AF-299 2003-03-27 TMP1941AF SIO1 Mnemonic Name Address Serial Channel 1 Control Register 7 RB8 R 0 Bit 8 of a received character TB8 0 Bit 8 of a transmitted character 6 EVEN 5 PE 4 3 2 1 SCLKS 0 IOC SC1CR FFFF F209H R/W 0 0 Parity type Parity 0: Odd 0: Disabled 1: Even 1: Enabled CTSE 0 Handshake control 0: Disables CTS operation 1: Enables CTS operation BR1ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled FDPX0 R/W 0 Synchronous 0: Halfduplex 1: Fullduplex RXE 0 Receive control 0: Disables receiver 1: Enables receiver OERR PERR FERR R (Cleared when read) 0 0 0 1: Error has occurred. Overrun WU R/W 0 Wake-up function 0: Disabled 1: Enabled Parity SM1 Framing SM0 R/W 0 0 0: SCLK1 0: Baud rate 1: SCLK1 generator 1: SCLK1 input SC1 SC0 SC1MOD0 Serial Channel 1 Mode Register 0 FFFF F20AH 0 0 Serial transfer mode 00: I/O Interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode 0 0 Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: External clock (SCLK1 input) Baud Rate Generator 1 Control Register 0 Must be written as 0. BR1CK1 0 00: T0 01: T2 10: T8 11: T32 BR1CK0 R/W 0 BR1S3 0 BR1S2 0 BR1S1 0 BR1S0 0 BR1CR FFFF F20BH Clock divisor value N BR1ADD Baud Rate Generator 1 Control Register FFFF F20CH I2S0 BRK1K3 0 BRK1K2 R/W BRK1K1 BRK1K0 0 0 0 Value of K in N+(16-K)/16 SC1MOD1 Serial Channel 1 Mode Register 1 FFFF F20DH 0 IDLE 0: Off 1: On TMP1941AF-300 2003-03-27 TMP1941AF SIO3 Mnemonic Name Address Serial Channel 3 Control Register 7 RB8 R 6 EVEN R/W 0 Parity type 0: Odd 1: Even CTSE 0 Must be written as 0. 5 PE 0 Parity 0: Disabled 1: Enabled RXE 0 Receive control 0: Disables receiver 1: Enables receiver BR3CK1 0 00: T0 01: T2 10: T8 11: T32 4 OERR 0 3 PERR 0 1: Error has occurred. R (Cleared when read) 2 FERR 0 1 R/W 0 0 0 SC3CR FFFF F281H 0 Bit 8 of a received character TB8 0 Must be written as 00. Overrun WU R/W 0 Wake-up function 0: Disabled 1: Enabled Parity SM1 0 Framing SM0 0 SC1 0 SC0 0 SC3MOD0 Serial Channel 3 Mode Register 0 FFFF F282H Bit 8 of a transmitted character Serial transfer mode 00: Reserved 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode BR3S3 BR3S2 0 Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: Don't care BR3S1 0 BR3S0 0 Baud Rate Generator 3 Control Register 0 FFFF F283H Must be written as 0. BR3ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled BR3CK0 R/W 0 0 BR3CR Clock divisor value N BR3ADD Baud Rate Generator 3 Control Register FFFF F284H I2S0 R/W FFFF F285H 0 IDLE 0: Off 1: On BR3K3 0 BR3K2 R/W 0 BR3K1 0 BR3K0 0 Value of K in N+(16-K)/16 SC3MOD1 Serial Channel 3 Mode Register 1 SIO4 Mnemonic Name Address Serial Channel 4 Control Register FFFF F289H 7 RB8 R 0 Bit 8 of a received character TB8 6 EVEN 5 PE 4 3 2 1 0 SC4CR R/W 0 0 Parity type Parity 0: Odd 0: Disabled 1: Even 1: Enabled CTSE 0 Must be written as 0. RXE 0 Receive control 0: Disables receiver 1: Enables receiver BR4CK1 0 00: T0 01: T2 10: T8 11: T32 OERR PERR FERR R (Cleared when read) 0 0 0 1: Error has occurred. Overrun WU R/W 0 Wake-up function 0: Disabled 1: Enabled Parity SM1 Framing SM0 R/W 0 0 Must be written as 00. SC1 SC0 SC4MOD0 Serial Channel 4 Mode Register 0 FFFF F28AH 0 Bit 8 of a transmitted character 0 0 Serial transfer mode 00: Reserved 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode BR4S3 BR4S2 0 0 0 Serial clock (for UART) 00: TA0TRG (timer) 01: Baud rate generator 10: Internal fsys/2 clock 11: Don't care BR4S1 0 BR4S0 0 Baud Rate Generator 4 Control Register 0 Must be written as 0. BR4ADDE 0 N+ (16-K)/16 function 0: Disabled 1: Enabled BR4CK0 R/W 0 0 BR4CR FFFF F28BH Clock divisor value N BR4ADD Baud Rate Generator 4 Control Register Serial Channel 4 Mode Register 1 FFFF F28CH I2S0 R/W 0 IDLE 0: Off 1: On BR4K3 0 BR4K2 R/W BR4K1 BR4K0 0 0 0 Value of K in N+(16-K)/16 SC4MOD1 FFFF F28DH TMP1941AF-301 2003-03-27 TMP1941AF 19.9 Serial Bus Interface (SBI) Mnemonic Name Address 7 BC2 FFFF F240H (I2C Bus Mode) 6 BC1 5 BC0 4 ACK 3 2 1 0/ SBI0CR1 Serial Bus Interface Control Register 1 W R/W 0 0 0 0 Number of bits per transfer ACK clock (when ACK = 0) pulse 000: 8, 001: 1, 010: 2 0: No ACK 011: 3, 100: 4, 101: 5 1: ACK 110: 6, 111: 7 SIOS SIOINH SIOM1 SIOM0 W 0 0 0 0 FFFF Start Abort Transfer mode F240H transfer transfer 00: Transmit mode (SIO Mode) 0: Stop 0: Continue 01: Reserved 1: Start 1: Abort 10: Transmit/Receive mode 11: Receive mode FFFF F241H DB7 DB6 DB5 SCK0 SCK2 SCK1 SWRMON W W R/W 0 0 1 Internal SCL output clock frequency (on writes) / Software reset monitor 000: 4, 001: 5, 010: 6 011: 7, 100: 8, 101: 9 110: 10, 111: Reserved SCK2 SCK1 SCK0 W R/W 0 0 1 Serial clock frequency (on writes) / Software reset monitor 000: 3, 001: 4, 010: 5 011: 6, 100: 7, 101: 8 110: 9, 111: External clock DB2 DB1 DB0 SBI0DBR SBI Data Buffer Register DB4 DB3 R (receive) / W (transmit) Undefined SA3 W 0 SA2 0 SA6 0 I2C0AR I2C bus Address Register FFFF F242H SA5 0 SA4 0 SA1 0 SA0 0 ALS 0 Address recognition 0: Recognize 1: Does not recognize SWRST0 0 When the SBI is addressed as a slave, this field specifies a 7-bit I2C-bus address to which the SBI responds. MST 0 Master/ slave FFFF F243H (I2C Bus Mode) SBI0CR2 on writes SBI0SR on reads Serial Bus Interface Control 2 /Status Register TRX 0 Transmit/ receive BB 0 START/ STOP generation PIN W 1 INTSBI interrupt clear SBIM1 0 SBIM0 0 SWRST1 0 Operating mode 00: Port mode 01: SIO mode 10: I2C Bus mode 11: Reserved AL R 0 Arbitration lost 0: 1: Detected SIOF R 0 Serial transfer status 0: Terminated 1: In progress 0 Shift operation status 0: Terminated 1: In progress AAS 0 Addressed as slave 0: 1: Detected SEF Software reset A write of 10 followed by a write of 01 MST 0 Master/ slave TRX 0 Transmit/ receive BB 0 I2C Bus status PIN 1 INTS2 interrupt status AD0 0 Address 0 (general call) 0: 1: Detected LRB 0 Last received bit 0: 0 1: 1 FFFF F243H (SIO Mode) SBI0BR0 Serial Bus Interface Control Register 0 FFFF F244H I2SBI0 R/W 0 IDLE 0: Off 1: On W 0 Must be written as 0. SBI0BR1 Serial Bus Interface Control Register 1 FFFF F245H P4EN R/W 0 Internal clock 0: Off 1: On TMP1941AF-302 2003-03-27 TMP1941AF 19.10 A/D Converter (ADC) Mnemonic Name Address 7 EOCF R 0 End-ofconversion flag 0: Before conversion or conversion in progress 1: Conversion completed VREFON R/W 0 VREF control 0: Off 1: On FFFF F311H 0 IDLE 0: Off 1: On 0 A/D conversion busy flag 0: Idle 1: Conversion in progress 0 Must be written as 0. 0 Must be written as 0. 6 ADBF 5 4 3 ITM0 2 REPEAT 1 SCAN 0 ADS 0 1: A/D conversion start ADMOD0 A/D Mode Control Register 0 FFFF F310H R/W 0 0 0 Interrupt 1: 1: Channel timing in Continuous scan fixedconversion conversion channel continuous conversion mode I2AD ADTRGE 0 External conversion trigger 0: Disable 1: Enable ADCH2 R/W ADCH1 ADCH0 0 0 0 Analog input channel select 000 001 010 011 100 101 110 111 SCAN=0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADR04 ADMOD1 A/D Mode Control Register 1 SCAN=1 AN0 AN0 AN1 AN0 AN1 AN2 AN0 AN1 AN2 AN3 AN4 AN4 AN5 AN4 AN5 AN6 AN6 AN7 ADR03 ADR0RF R 0 ADR02 ADREG04L A/D Conversion Result Reg 0/4 Low A/D Conversion Result Reg 0/4 High A/D Conversion Result Reg 1/5 Low ADR01 FFFF F300H R ADR00 ADR07 ADR06 R Undefined ADR05 Undefined ADR09 ADR08 ADREG04H FFFF F301H ADR11 FFFF F302H R Undefined ADR19 FFFF F303H ADR21 FFFF F304H R Undefined ADR29 FFFF F305H ADR31 ADR30 R Undefined ADR38 ADR37 ADR28 ADR20 ADR27 ADR18 ADR10 ADR17 ADREG15L ADR15 R Undefined ADR25 R Undefined ADR35 R Undefined ADR14 ADR13 ADR1RF R 0 ADR12 A/D Conversion ADREG15H Result Reg 1/5 High A/D Conversion Result Reg 2/6 Low ADR16 ADREG26L ADR24 ADR23 ADR2RF R 0 ADR22 A/D Conversion ADREG26H Result Reg 2/6 High ADREG37L AD Result Reg 3/7 low A/D Conversion Result Reg 3/7 High ADR26 FFFF F306H ADR34 ADR33 ADR3RF R 0 ADR32 ADR39 FFFF F307H ADR36 ADREG37H ADCCK1 R/W 0 ADCCK0 0 ADCCLK A/D Conversion Clock Select Register FFFF EE04H A/D conversion clock 00: fsys/2 01: fsys/4 10: fsys/8 11: Reserved TMP1941AF-303 2003-03-27 TMP1941AF 19.11 Watchdog Timer (WDT) Mnemonic Name Address WDT Mode Register 7 WDTE R/W 1 1: WDT enable 6 WDTP1 R/W 0 00: 216/fsys 01: 218/ fsys 10: 220/ fsys 11: 222/ fsys 5 WDTP0 0 4 3 2 I2WDT 0 IDLE 0: Off 1: On 1 RESCR R/W 0 1: System reset 0 0 Must be written as 0. WDMOD FFFF F090H WDCR WDT Control Register FFFF F091H W B1H: WDT disable code; 4EH: WDT clear-count code 19.12 Real-Time Clock (RTC) Mnemonic Name Address 7 R/W 0 Must be written as 0. 6 5 4 3 2 1 0 RTCRUN R/W 0 0: Stop and clear the counter. 1: Begin counting. RUI0 0 RTCCR RTC Control Register FFFF F0A0H RTCRCLR RTCSEL1 RTCSEL0 R/W R/W 0 0 0 14 0: Clears 00: 2 /fs 13 Accumulator. 01: 2 /fs 10: 212/fs 11: 211/fs RUI3 R 0 RUI2 0 RUI1 0 RTCREG RTC Accumulator Register RUI7 FFFF F0A4H 0 RUI6 0 RUI5 0 RUI4 0 TMP1941AF-304 2003-03-27 TMP1941AF 20. I/O Port Equivalent-Circuit Diagrams * How to read circuit diagrams The circuit diagrams in this chapter are drawn using the same gate symbols as for the 74HCxx Series standard CMOS logic ICs. The signal named STOP has a unique function. This signal goes active-high if the CPU sets the HALT bit when the STBY[1:0] field in the SYSCR2 register is programmed to 01 (i.e., STOP mode) and the Drive Enable (DRVE) bit in the same register is cleared. If the DRVE bit is set, the STOP signal remains inactive (at logic 0). * The input protection circuit has a resistor in the range of several tens to several hundreds of ohms. s AD0-AD7, AD8-AD15, A8-A15, P44, P71, P73-P76, P80-P87, P91-P92, P94-P95, PA0-PA5 Vcc Output Data Output Enable STOP Input Data P-ch N-ch Input/Output Input Enable s A16-A23, A0-A7, RD , WR Vcc Output Data Output STOP s HWR , WAIT , BUSRQ , BUSAK , R / W , P37, P40-43 Vcc Output Data Output Enable STOP Input Data P-ch Vcc Programmable Pullup Resistor Input/Output N-ch Input Enable TMP1941AF-305 2003-03-27 TMP1941AF s Port 5 (AN0-AN7) Analog Input Channel Select Analog Input Input Input Data Input Enable s P77 (INT0) Vcc Output Data Output Enable STOP Input Data Schmitt-Trigger Input/Output s P70, P72, P90, P93, PA6-PA7 Vcc Output Data Open-Drain Output Enable Output Enable STOP Input Data P-ch N-ch Input/Output Input Enable s P96 (XT1), P97 (XT2) Clock Input Enable Oscillator Circuit Input Data Output Data Output Enable Input Enable Input Data Output Data Output Enable STOP Low-Frequency Oscillator Enable P96(XT1) P97(XT2) TMP1941AF-306 2003-03-27 TMP1941AF s NMI, AM0-AM1, PLLOFF NMI PLLOFF Schmitt-Trigger Input s ALE Vcc Internal ALE P-ch Output Output Enable N-ch s RESET Vcc Reset Schmitt-Trigger WDTOUT Reset Enable Input s X1, X2 Oscillator Circuit X2 High-Frequency Oscillator Enable X1 Clock s VREFH, VREFL VREFON P-ch VREFH Ladder Resistors VREFL TMP1941AF-307 2003-03-27 TMP1941AF 21. Notations, Precautions and Restrictions 21.1 Notations and Terms (1) I/O register fields are often referred to as fgear: Clock selected by the SYSCR1.GEAR[1:0] bits The fsys cycle is referred to as a state. In addition, the clock selected by the SYSCR1.FPSEL bit and the prescalar clock source selected by the SYSCR0.PRCK[1:0] bits are referred to as fperiph and T0 respectively. 21.2 Precautions and Restrictions (1) Processor Revision Identifier The Process Revision Identifier (PRId) register in the TX19 core of the TMP1941AF contains 0x0000_2C90. (2) AM0- AM1 Pins The BW0 and BW1 pins must be connected to the DVcc pin to ensure that their signal levels do not fluctuate during chip operation. (3) Oscillator Warm-Up Counter If an external crystal is utilized, an interrupt signal programmed to bring the TMP1941AF out of STOP mode triggers the on-chip warm-up counter. The system clock is not supplied to the on-chip logic until the warm-up counter expires. (4) Programmable Pullup Resistors When port pins are configured as input ports, the integrated pullup resistors can be enabled and disabled under software control. The pullup resistors are not programmable when port pins are configured as output ports. The relevant port registers must be programmed by using store instructions. (5) External Bus Mastership The pin states while the bus is granted to an external device are described in Chapter 7, I/O Ports. (6) Watchdog Timer (WDT) Upon reset, the WDT is enabled. If the watchdog timer function is not required, it must be disabled after reset. When relevant pins are configured as bus arbitration signals, the I/O peripherals including the WDT can operate during external bus mastership. (7) A/D Converter (ADC) The ladder resistor network between the VREFH and VREFL pins can be disconnected under software control. This helps to reduce power dissipation, for example, in STOP mode. (8) Undefined Bits in I/O Registers Undefined I/O register bits are read as undefined states. Therefore, software must be coded without relying on the states of any undefined bits. TMP1941AF-308 2003-03-27 TMP1941AF (9) Usage Restrictions Overflow Exception #1 Problem: When an overflow exception is taken, the EPC register might contain an incorrect return address, pointing to the instruction immediately following the one that caused an overflow. The restart location in the EPC register should be the address of the arithmetic instruction that caused the exception, rather than the following instruction. Detects an overflow and writes to EPC. n Arithmetic Instruction (e.g., ADD) F D E M W n+4 Next Instruction F D E M W Instruction Pipeline Detects an interrupt. Writes to EPC. EPC Register n n+4 In the above example, the processor writes address n to the EPC register upon detection of an overflow. However, executing the next instruction generates an interrupt at the same time, causing the processor to rewrite the EPC register with address n+4 in the next cycle. * Problem-Causing Situation: A) Software uses the ADD, ADDI or SUB instruction in the 32-bit ISA. B) The ADD, ADDI or SUB instruction causes an overflow. C) Another exception is requested simultaneously with the overflow. This problem occurs when all of these conditions are true. Workarounds: * * * Before returning from the overflow exception handler, determine whether the instruction pointed to by the EPC register caused an overflow. Make sure that two arithmetic instructions will not appear consecutively. Disable interrupts prior to arithmetic instructions. You should always use one of these workarounds to avoid this problem. Toshiba's compiler uses no instructions that could cause an overflow. Therefore, since condition c) above never becomes true, this problem does not occur. Note: TMP1941AF-309 2003-03-27 TMP1941AF Overflow Exception #2 Problem: If an overflow exception caused a jump to the exception handler and the first instruction in that exception handler caused another exception, the EPC register should point to the address of the first instruction in the exception handler. However, the EPC register might contain the address that caused the overflow exception. * Problem-Causing Situation: When, with the instruction pipeline full, an overflow exception was taken at the following sequence of instructions and then the first instruction in the overflow exception handler causes another exception ADD, ADDI or SUB <= # Instruction that causes an overflow Jump or branch instruction <= # Instruction with a delay slot Delay slot Note: Toshiba's compiler uses no instructions that could cause an overflow. Therefore, this problem does not occur. Workaround: Don't place a jump or branch instruction immediately following an instruction that could cause an overflow (ADD, ADDI or SUB). TMP1941AF-310 2003-03-27 TMP1941AF When Using Multiple DMAC Channels (External Bus Interface Unit) Problem: Switching between DMA channels might cause an external chip select (CS) signal to be incorrectly driven active for one cycle. RD, WR, ALE and other external bus control signals are not driven active. DMAC Bus Mastership e.g., DMAC Ch. 1 Internal Select Signal e.g., DMAC Ch. 2 Internal Select Signal DMAC Ch. 3 Internal Select Signal CS from External Bus I/F Unit In cases where the DMAC continually assumes bus mastership, switching from one channel to another causes channel 3 to be selected for one cycle as shown above. If the destination address for channel 3 references an external address space and a chip select is programmed for that address space, the external bus interface unit drives the chip select signal off chip even though no bus cycle has been started. * Problem-Causing Situation: A) The system hardware uses two or more DMAC channels. B) The system hardware uses one or more external CS channels. C) While a DMA request for one channel is being serviced, a next DMA request has been received on another channel and left pending. Or, two or more channels have received DMA requests simultaneously. D) The destination address for channel 3 points to an external address space. (Upon reset, the content of the destination address register is undefined. Therefore, even when channel 3 is not used, its destination address register might be pointing to an external address space.) This problem occurs when all of these conditions are true. Workaround: The system hardware must be designed not to operate with CS alone. TMP1941AF-311 2003-03-27 TMP1941AF LWL and LWR Instructions Problem: The LWL or LWR instruction might provide incorrect results. * Problem-Causing Situation #1: a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to that of the LWL or LWR instruction. b. The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will be executed consecutively.) c. The DMAC is programmed for data cache snooping. Once the load instruction is executed, the DMAC initiates a DMA transaction. After it has been serviced, the LWLor LWR instruction is executed. This problem occurs when all of these conditions are true. * Problem-Causing Situation #2: a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to that of the LWL or LWR instruction. b. The Doze or Halt bit in the Config register is set to 1 immediately before the load instruction. c. The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will be executed consecutively.) d. After the load instruction is executed, the processor is put in the STOP, SLEEP or IDLE mode. e. After an interrupt signaling brings the processor out of the STOP, SLEEP or IDLE mode, the LWL or LWR instruction is executed. Note: This applies to the case in which an interrupt signaling does not generate an interrupt upon exit from STOP, SLEEP or IDLE mode. In other words, either the IEc bit in the Status register is cleared (interrupts disabled), or if the IEc bit is set, the priority level of the incoming interrupt signaling is lower than the mask level programmed in the CMask field in the Status register. (Exit from STOP, SLEEP or IDLE mode can be accomplished even with such settings.) This problem occurs when all of these conditions are true. Workarounds: To use the LWL or LWR instruction, 1) Place a NOP between a load instruction and the LWL or LWR instruction, or 2) Disable the data cache snooping of the DMAC before the LWL or LWR instruction is executed. Also, don't put the processor in STOP, SLEEP or IDLE mode before the LWL or LWR instruction is executed. TMP1941AF-312 2003-03-27 TMP1941AF Overflow Exception When a DSU Probe Is Used Problem: It looks as if an overflow exception caused a jump to the reset and nonmaskable exception vector address (0xBFC0_0000). * Problem-Causing Situation: When an overflow exception occurs, with the processor connected to a DSU probe Toshiba's compiler uses no instructions that could cause an overflow. Therefore, this problem does not occur. Note: Workaround: Don't place a jump or branch instruction immediately following an instruction that could cause an overflow (ADD, ADDI or SUB). IDLE (Doze) Mode Problem: A deadlock might occur when returning to normal operating mode from IDLE (Doze) mode. * Problem-Causing Situation: When the DMAC initiates a DMA transaction with snooping enabled after the Doze bit in the Config register is set and before the CPU clock stops. Workaround: If snooping is enabled, stop the DMAC before putting the processor in IDLE (Doze) mode. TMP1941AF-313 2003-03-27 TMP1941AF TMP1941AF-314 2003-03-27 |
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