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256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM
HYB 514256B/BJ-50/-60/-70 HYB 514256BL/BJL-50/-60/-70
Advanced Information 262 144 words by 4-bit organization * Fast access and cycle time 50 ns access time 95 ns cycle time (-50 version) 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) * Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) * Low power dissipation max. 495 mW active (-50 version) max. 440 mW active (-60 version) max. 385 mW active (-70 version) max. 5.5 mW standby max. 1.1 mW standby for L-version
* * * *
* *
*
Single + 5 V ( 10 %) supply with a built-in VBB generator Output unlatched at cycle end allows twodimensional chip selection Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability All inputs, outputs and clocks TTL-compatible 512 refresh cycles/8 ms 512 refresh cycles/64 ms for L-version only Plastic Packages: P-DIP-20-2, P-SOJ-26/20-1
Ordering Information Type HYB 514256B-50 HYB 514256B-60 HYB 514256B-70 HYB 514256BJ-50 HYB 514256BJ-60 HYB 514256BJ-70 HYB 514256BL-50 HYB 514256BL-60 HYB 514256BL-70 HYB 514256BJL-50 HYB 514256BJL-60 HYB 514256BJL-70 Ordering Code Q67100-Q1044 Q67100-Q530 Q67100-Q433 Q67100-Q1054 Q67100-Q536 Q67100-Q537 on request Q67100-Q542 Q67100-Q543 on request Q67100-Q608 Q67100-Q607 Package P-DIP-20-2 P-DIP-20-2 P-DIP-20-2 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 P-DIP-20-2 P-DIP-20-2 P-DIP-20-2 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 Description DRAM (access time 50ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)
Semiconductor Group
55
01.95
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
The HYB 514256B/BJ/BL/BJL is the new generation dynamic RAM organized as 262 144 words by 4-bit. The HYB 514256B/BJ/BL/BJL utilizes CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514256B/BJ/BL/BJL to be packaged in a standard plastic P-DIP-20-2,or plastic P-SOJ-26/20-1. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. These HYB 514256BL/BJL are specially selected for battery backup applications. Pin Definitions and Functions Pin No. A0-A8 RAS OE I/O1-I/O4 CAS WE Function Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) No Connection
VCC VSS
N.C.
Semiconductor Group
56
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
Pin Configuration (top view)
P-SOJ-26/20-1
P-DIP-20-2
Semiconductor Group
57
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
Block Diagram Semiconductor Group 58
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 C Storage temperature range......................................................................................- 55 to + 150 C Soldering temperature ............................................................................................................260 C Soldering time .............................................................................................................................10 s Input/output voltage ........................................................................................................ - 1 to + 7 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation..................................................................................................................... 0.6 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current, any input (0 V VIN 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT VCC) Average VCC supply current: -50 version -60 version -70 version (RAS, CAS, address cycling: tRC = tRC min.) Average VCC supply current, RAS only mode: -50 version -60 version -70 version (RAS cycling: CAS = VIH : tRC = tRC min.) Symbol Limit Values min. max. 6.5 0.8 - 0.4 10 10 2.4 - 1.0 2.4 - - 10 - 10 Unit Test Condition V V V V A A
1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
1)
- - - - - - -
90 80 70 2 90 80 70
mA mA mA mA mA mA mA
2) 3) 2) 3) 2) 3)
Standby VCC supply current (RAS = CAS = VIH) ICC2
-
2) 2) 2)
ICC3
Semiconductor Group
59
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
DC Characteristics (cont'd) TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 % Parameter Average VCC supply current, fast page mode: -60 version -70 version -50 version (RAS = VIL , CAS, address cycling: tPC = tPC min.) Standby VCC supply current L-Version (RAS = CAS = VCC - 0.2 V) Average VCC supply current, CAS-before-RAS refresh mode: -50 version -60 version -70 version (RAS, CAS cycling: tRC = tRC min.) For L-version only: Battery backup current: average power supply current, battery backup mode: (CAS = CAS before RAS cycling or 0.2 V, OE = VCC - 0.2 V WE = VCC - 0.2 V or 0.2 V, A0 to A8 = VCC - 0.2 V or 0.2 V, I/O1 to I/O4 = VCC - 0.2 V or 0.2 V or open, tRC = 125 s, tRAS = tRAS min. ~ 1 s) Symbol Limit Values min. max. 70 60 50 Unit Test Condition mA mA mA
2) 3 2) 3) 2) 3)
ICC4
- - -
ICC5
- -
1 200
mA A
1) 1)
ICC6
- - - 90 80 70 mA mA mA
2) 2) 2)
ICC7
-
300
A
2)
Semiconductor Group
60
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
AC Characteristics 4) 13) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -50 min. Random read or write cycle time Read-modify-write cycle time Fast page mode cycle time max. - - - - 50 15 25 30 - 15 50 - 10.000 min. 110 160 40 90 - - - - 0 0 3 40 60 Limit Values -60 max. - - - - 60 15 30 35 - 20 50 - 10.000 min. 130 185 45 100 - - - - 0 0 3 50 70 -70 max. - - - - 70 20 35 40 - 20 50 - 10.000 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRC tRWC tPC
95 140 35 80 - - - - 0 0 3 35 50 50 15 50 15 30 55 20 15 5 10
Fast page mode read-modify- tPRWC write cycle time Access time from RAS Access time from CAS Access time from column address Access time from CAS precharge CAS to output in low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS pulse width (fast page mode) RAS hold time CAS hold time CAS pulse width RAS hold time from CAS precharge (Fast Page Mode) CAS precharge to WE delay time (FPM RMW) RAS to CAS delay time
11) 6) 11) 6) 11)
tRAC tCAC tAA
6) 12)
tCPA
6) 12) 4)
tCLZ tOFF
7)
tT
5)
tRP tRAS tRASP tRSH tCSH tCAS tRHCP tCPWD tRCD
100.000 60 - - 10.000 - - 35 25 - - 15 60 15 35 60 20 15 5 10
100.000 70 - - 10.000 - - 45 30 - - 20 70 20 45 65 20 15 5 10
100.000 ns - - 10.000 - - 50 35 - - ns ns ns ns ns ns ns ns
RAS to column address delay tRAD 12) time CAS to RAS precharge time CAS precharge time
tCRP tCP
Semiconductor Group
61
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
AC Characteristics (cont'd) 4) 13) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -50 min. Row address setup time Row address hold time Column address setup time Column address hold time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Refresh period Refresh period L-version Write command setup time CAS to WE delay time RAS to WE delay time
10) 10) 10) 9) 9) 8)
Limit Values -60 min. 0 10 0 15 30 0 0 0 10 10 15 15 0 15 - - 0 45 90 60 5 15 0 max. - - - - - - - - - - - - - - 8 64 - - - - - - - min. 0 10 0 15 35 0 0 0 15 15 20 20 0 15 - - 0 50 100 65 5 15 0 -70 max. - - - - - - - - - - - - - - 8 - - - - - - - - max. - - - - - - - - - - - - - - 8 64 - - - - - - -
Unit
tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH
8)
0 10 0 10 25 0 0 0 10 10 15 15 0 10 - - 0 40 75 50 5 10 0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns
tWCH tWP tRWL tCWL tDS tDH tREF tREF tWCS tCWD tRWD
Column address to WE delay tAWD 10) time CAS setup time (CAS-before- tCSR RAS cycle) CAS hold time (CAS-beforeRAS cycle) RAS to CAS precharge time
tCHR tRPC
Semiconductor Group
62
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
AC Characteristics (cont'd) 4) 13) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -50 min. CAS precharge time (CASbefore-RAS counter test cycle) OE access time RAS hold time referenced to OE Output buffer turn-off delay time from OE Data to CAS low delay 14) CAS high to data delay OE to data delay
15) 15)
Limit Values -60 min. 30 max. - min. 40 -70 max. - max. -
Unit
tCPT
25
ns
tOEA tROH tOEZ tDZC tDZO tCDD tODD
- 10 0 0 0 15 15
15 - 15 - - - -
- 10 0 0 0 20 20
15 - 20 - - - -
- 10 0 0 0 20 20
20 - 20 - - - -
ns ns ns ns ns ns
OE high to data delay 15)
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A8) Input capacitance (RAS, CAS, WE, OE) Output capacitance (I/O1 ... I/O4) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 C5O
Semiconductor Group
63
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
Notes :
1) All voltages are referenced to VSS . 2) ICC1 , ICC3 , ICC4 , ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 6) Measured with a load equivalent to 2 TTL loads and 100 pF. 7) tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open-circuit conditions and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-modify-write cycles. 10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle; if tRWD tRWD (min.), tCWD tCWD (min.) and tAWD tAWD (min.), the cycle is a read-modify-write cycle and I/O will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met, tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13) AC measurements assume tT = 5ns. 14) Either tDZC or tDZO must be satisfied. 15) Either tCDD or tODD must be satisfied.
Semiconductor Group
64
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
Waveforms
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A8
V IH VIL
Row Address
tRCH tRAH tRCS tRRH tAA tOEA
WE
V IH VIL
OE
V IH VIL
tDZC tDZO tCAC tCLZ
Hi Z
tCDD tODD
V I/O1-I/O4 IH (Inputs) V IL
tOFF tOEZ
Valid Data Out Hi Z
V I/O1-I/O4 OH (Outputs) V OL
tRAC
"H" or "L"
Read Cycle
Semiconductor Group
65
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A8
V IH VIL
.
Row Address
tRAH
WE
V IH VIL
tWCS
tCWL t WP tWCH tRWL
OE
V IH VIL
tDS
V I/O1-I/O4 IH (Inputs) V IL
tDH
Valid Data In
I/O1-I/O4 OH (Outputs) V
OL
V
Hi Z
"H" or "L"
Write Cycle (Early Write)
Semiconductor Group
66
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A8
V IH VIL
.
Row Address
tRAH
WE
V IH VIL
tCWL tRWL tWP
tOEH
OE
V IH VIL
tODD tDZO tDZC tDS tOEZ
tDH
V I/O1-I/O4 IH (Inputs) V IL
Valid Data
tCLZ tOEA
Hi-Z
V I/O1-I/O4 OH (Outputs) V OL
Hi-Z
"H" or "L"
Write Cycle (OE Controlled Write)
Semiconductor Group
67
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRWC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tCRP
CAS
V IH VIL
tRAH
A0 - A8
V IH VIL
tCAH tASC
Column Address
tASR
Row Address
tASR
Row Address
tRAD
V IH
tAWD tCWD tRWD
tCWL tRWL tWP
WE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
tDS tDH
Valid Data in
I/O1-I/O4 (Inputs) VIL
V IH
tCLZ tCAC
Data Out
tODD tOEZ
V I/O1-I/O4 OH (Outputs) V OL
tRAC
"H" or "L"
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
68
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Address Column Address
V
RAS
IH
V IL
tCSH tRCD tCAS tRAL tASR
Row Address
tRSH tCRP
Semiconductor Group
V
CAS
IH
V IL
tRAD tCAH tASC
Column Address
tASR
tRAH
tCAH
V
A0-A8
IH
V IL
Row Address
Fast Page Mode Read-Modify-Write Cycle
V
tRCS tAA tOEA tOEA tWP tWP tOEA tAWD tAWD tAWD
tRWD tCWD tCWL tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WE
IH
V IL
69
tWP
V
IH
OE
V IL
tCPA tDZC
Data In
tCPA tODD
Data In
V
IH
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tDS
Data Out Data Out
tDZC tCLZ tOEH
tODD
Data In
I/O1-I/O4 (Inputs) V IL
tODD tCAC tAA
tOEH tOEZ tDS tDH
tOEH tAA tOEZ tDS
Data Out
tDH
I/O1-I/O4 OH (Outputs) V
V
OL
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
"H" or "L"
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRASP
V IH
tRP
RAS
VIL
tRCD
V IH
tPC tCP tCAS tCSH tCAS
tRHCP tRSH tCAS tCRP
CAS
VIL
tRAH tASR
A0-A8
V IH VIL
Row Addr
tASC
tCAH
Column Address
tASC
tCAH tASC
tCAH tASR
Row Address Column Address
Column Address
tRAD tRCH tRCS tRCS tRCS
tRCH
V IH
WE
VIL
V IH
tAA tOEA
tCPA tAA tOEA
tCPA tAA tOEA tDZC tDZO tODD
tRRH
OE
VIL
tDZC tDZO tODD tCAC tRAC tCLZ tOFF tOEZ
Valid Data Out
tDZC tDZO
tCDD tODD
I/O1-I/O4 IH (Inputs) V IL
V
tCAC tOFF tCLZ tOEZ
Valid Data Out
tCAC tCLZ
tOFF tOEZ
Valid Data Out
I/O1-I/O4 OH (Outputs) V
OL
V
"H" or "L"
Fast Page Mode Read Cycle
Semiconductor Group
70
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tCAS tRCD tCP
tCAS
tRSH tCAS tCRP
V IH
CAS
VIL
tRAL tRAH tASR tCAH tASC
Column Address
tASC tCAH
Column Address
A0-A8
V IH VIL
tASC
tCAH
tASR
Row Address
Row Addr
Column Address
tRAD
V IH VIL
tCWL tWCS tWCH tWP
tCWL tWCS tWCH tWP
tCWL tRWL tWCS tWCH tWP
WE
OE
V IH VIL
tDH tDS
V I/O1-I/O4 IH (Inputs) V IL Valid Data In
tDH tDS
Valid Data In
tDH tDS
Valid Data In
I/O1-I/O4 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Fast Page Mode Early Write Cycle
Semiconductor Group
71
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
V IH
CAS
VIL
tRAH tASR
tASR
Row Address
A0-A8
V IH VIL
Row Address
I/O1-I/O4 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
RAS-Only Refresh Cycle
Semiconductor Group
72
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRC tRP
RAS
V IH VIL
tRAS
tRP
tRPC tCSR
CAS
V IH VIL
tCRP tCHR tRPC
tCP tWRP tWRH
WE
V IH VIL
tOEZ
OE
V IH VIL
tCDD
I/O1-I/O4 IH (Inputs) V IL
V
tODD
I/O1-I/O4 OH (Outputs)VOL
V HI-Z
tOFF
"H" or "L"
CAS-Before-RAS Refresh Cycle
Semiconductor Group
73
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRC
V IH VIL
tRC tRP tRAS tRP
tRAS
RAS
tRCD
V IH VIL
tRSH tCHR tCRP
CAS
tRAD tRAH tASR tASC tWRP tCAH tWRH tASR
Row Address
A0-A8
V IH VIL
Row Addr
Column Address
tRCS
WE
V IH VIL
tRRH
tAA tOEA
OE
V IH VIL
tDZC tDZO
tCDD tODD
V I/O1-I/O4 IH (Inputs) V IL
tCAC tCLZ tRAC tOEZ
Valid Data Out
tOFF
I/O1-I/O4 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Read)
Semiconductor Group
74
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
tRC tRP
RAS
V IH VIL
tRC tRAS tRP
tRAS
tRCD
V IH VIL
tRSH
tCHR
tCRP
CAS
tRAD tRAH tASR tASC tCAH
Column Address
tASR
Row Address
A0-A8
V IH VIL
Row Addr
tWCS
tWCH tWP
WE
V IH VIL
OE
V IH VIL
tDS
IH I/O1-I/O4 (Inputs) V IL V
tDH
Valid Data
I/O1-I/O4 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Early Write)
Semiconductor Group
75
HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K x 4-DRAM
V
tRAS
IH
tRP tRSH tCAS
RAS
V
IL
tCSR
V
tCHR
tCPT
CAS
IH
V
IL
V
tASC
IH
tCAH tAA tCAC
tRAL tASR
Row Address
A0-A8
V
IL
Column Address
Read Cycle
WE
V V IH
tWRP tWRH
IL
tRCS
tRRH tRCH
tOEA
OE
V V IH IL
I/O1-I/O4 (Inputs)
V V
tDZC tDZO
tODD tCLZ tOEZ
Valid Data Out
tCDD tOFF
IH
IL
I/O1-I/O4 (Outputs)
V OH V OL
Write Cycle
V IH
tWRP tWRH
tWCS
tRWL tCWL tWCH
WE
V V
IL IH
OE
V
IL
tDS
I/O1-I/O4 (Inputs) I/O1-I/O4 (Outputs)
V V IH IL HI-Z
tDH tCWL tRWL tWP tOEH tDS tDH
Data In
Valid Data In
V IH V IL V IH
Read-Modify-Write Cycle
WE
V IL
tWRP
tWRH
tRCS tAA
tAWD tCWD tCAC tOEA
V
OE
IH
V
IL
I/O1-I/O4 (Inputs)
V V
tDZC tDZO
IH
IL
I/O1-I/O4 (Outputs)
V OH V OL
tCLZ
HI-Z
tCAC
D.Out
tODD tOEZ
HI-Z
"H" or "L"
Semiconductor Group
76

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