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QFN-10
CSP-8
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
500-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING
FEATURES
* * * * * * * * * * * * * * Up to 93% Efficiency at 3-MHz Operation Up to 500-mA Output Current at VI = 2.7 V 3-MHz Fixed Frequency Operation Best in Class Load and Line Transient Complete 1-mm Component Profile Solution -0.5% / +1.3% PWM DC Voltage Accuracy Over Temperature 35-ns Minimum On-Time Power-Save Mode Operation at Light Load Currents Fixed and Adjustable Output Voltage Only 86-A Quiescent Current 100% Duty Cycle for Lowest Dropout Synchronizable On the Fly to External Clock Signal Integrated Active Power-Down Sequencing (TPS6232x only) Available in a 10-Pin QFN (3 x 3 mm) and 8-Pin NanoFreeTM and NanoStarTM (CSP) Packaging
DESCRIPTION
The TPS623xx device is a high-frequency synchronous step-down dc-dc converter optimized for battery-powered portable applications. Intended for low-power applications, the TPS623xx supports up to 500-mA load current and allows the use of tiny, low cost chip inductor and capacitors. The device is ideal for mobile phones and similar portable applications powered by a single-cell Li-Ion battery or by 3-cell NiMH/NiCd batteries. With an output voltage range from 5.4 V down to 0.6 V, the device supports low-voltage DSPs and processors in smart-phones, PDAs as well as notebooks, and handheld computers. The TPS62300 operates at 3-MHz fixed switching frequency and enters the power-save mode operation at light load currents to maintain high efficiency over the entire load current range. For low noise applications, the device can be forced into fixed frequency PWM mode by pulling the MODE/SYNC pin high. The device can also be synchronized to an external clock signal in the range of 3 MHz. In the shutdown mode, the current consumption is reduced to less than 1 A. The TPS623xx is available in a 10-pin leadless package (3 x 3 mm QFN) and an 8-pin chip-scale package (CSP).
100 90 80 Efficiency - % 70 60 50 40 30 20 10 0 0.1 1 10 100 1k IO - Load Current - mA L = 2.2 H, CO = 4.7 F VI = 3.6 V, VO = 1.8 V
APPLICATIONS
* * * * * * Cell Phones, Smart-Phones WLAN and BluetoothTM Applications Micro DC-DC Converter Modules PDAs, Pocket PCs USB-Based DSL Modems Digital Cameras
TPS62303YZD 2.7 V . . 6 V VI C1 4.7 F A2 VIN B2 EN SW B1 D1 1 H VOUT C2 C1 MODE/SYNC ADJ D2 A1 GND FB L1 C2 VO 1.8 V/500 mA
4.7 F
Figure 1. Smallest Solution Size Application (Fixed Output Voltage)
Figure 2. Efficiency vs Load Current
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a trademark of Bluetooth SIG, Inc. NanoFree, NanoStar are trademarks of Texas Instruments. PowerPAD is a trademark of Texas Instsruments.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2004, Texas Instruments Incorporated
PRODUCT PREVIEW
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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ORDERING INFORMATION
TA PART NUMBER (1) TPS62300 TPS62301 TPS62302 TPS62303 -40C to 85C TPS62304 TPS62305 TPS62306 TPS62320 OUTPUT VOLTAGE Adjustable 1.5 V 1.6 V 1.8 V 1.2 V 1.875 V 1.9 V Adjustable PACKAGE QFN-10 CSP-8 (lead-free) QFN-10 CSP-8 (lead-free) QFN-10 CSP-8 (lead-free) QFN-10 CSP-8 (lead-free) QFN-10 CSP-8 (lead-free) QFN-10 QFN-10 QFN-10 CSP-8 (lead-free) CSP-8 QFN-10 TPS62321 1.5 V CSP-8 (lead-free) CSP-8 (1) ORDERING TPS62300DRC TPS62300YZD TPS62301DRC TPS62301YZD TPS62302DRC TPS62302YZD TPS62303DRC TPS62303YZD TPS62304DRC TPS62304YZD TPS62305DRC TPS62306DRC TPS62320DRC TPS62320YZD TPS62320YED TPS62321DRC TPS62321YZD TPS62321YED PACKAGE MARKING AMN N/A AMO N/A AMQ N/A AMR N/A AMS N/A ANU ANV AMX N/A N/A AMY N/A N/A
PRODUCT PREVIEW
The YZ package is available in tape and reel. Add R suffix (TPS62300YZR) to order quantities of 3000 parts. Add T suffix (TPS62300YxDT) to order quantities of 250 parts
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT Voltage at VIN, AVIN (2) Voltage at SW VI
(2)
-0.3 V to 7.0 V -0.3 V to 7.0 V -0.3V to 3.6 V
(2)
Voltage at FB, ADJ Voltage at EN, MODE/SYNC Voltage at VOUT (2) Power dissipation
-0.3 V to VIN + 0.3 V 0.3 V to 5.4 V Internally limited -40C to 85C 150C -65C to 150C
TA Tstg (1) (2)
Operating temperature range Storage temperature range
TJ (max) Maximum operating junction temperature
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS (1)
PACKAGE DRC YZD YED (1) RJA 49C/W 250C/W 250C/W POWER RATING FOR TA 25C 2050 mW 400 mW 400 mW DERATING FACTOR ABOVE TA = 25C 21 mW/C 4 mW/C 4 mW/C
Maximum power dissipation is a function of TJ(max), JA and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max)-TA] / JA
2
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
ELECTRICAL CHARACTERISTICS
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 H, CO = 10 F, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER SUPPLY CURRENT VI IQ I(SD) V(UVLO) V(EN) V(MODE/SYNC) V(EN), V(MODE/SYNC) I(EN), I(MODE/SYNC) Input voltage range IO = 0 mA. PFM mode enabled, device not switching Operating quiescent current Shutdown current Undervoltage lockout threshold IO = 0 mA. Switching with no load (MODE/SYNC = VIN) EN = GND 2.7 86 3.6 0.1 2.40 1.0 2.55 6.0 105 V A mA A V TEST CONDITIONS MIN TYP MAX UNIT
ENABLE, MODE/SYNC EN high-level input voltage MODE/SYNC high-level input voltage EN, MODE/SYNC low-level input voltage EN, MODE/SYNC input leakage current EN, MODE/SYNC = GND or VIN 0.01 1.2 1.3 0.4 1.0 V V V A
POWER SWITCH rDS(on) I(LK_PMOS) rDS(on) R(DIS) I(LK_NMOS) P-channel MOSFET on resistance P-channel leakage current N-channel MOSFET on resistance Discharge resistor for power-down sequence (TPS6232x only) N-channel leakage current P-MOS current limit N-MOS current limit - sourcing N-MOS current limit - sinking Input current limit under short-circuit conditions Thermal shutdown Thermal shutdown hysteresis OSCILLATOR fSW f(SYNC) Oscillator frequency Synchronization range Duty cycle of external clock signal 2.65 2.65 20% 3.0 3.35 3.35 80% MHz MHz V(DS) = 6.0 V 2.7 V VI 6.0 V 2.7 V VI 6.0 V 2.7 V VI 6.0 V VO = 0 V 670 550 -460 780 720 -600 390 150 20 VI = V(GS) = 3.6 V VI = V(GS) = 2.8 V V(DS) = 6.0 V VI = V(GS) = 3.6 V VI = V(GS) = 2.8 V 330 400 30 420 520 750 1000 1 750 1000 50 1 890 890 -740 m
A m m A mA mA mA mA C C
3
PRODUCT PREVIEW
m
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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ELECTRICAL CHARACTERISTICS (continued)
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 H, CO = 10 F, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER OUTPUT VO V(FB) A(PT) ton(MIN) Adjustable output voltage range Regulated feedback voltage TPS62300 TPS62320 TPS62300 TPS62320 1.496 0.6 0.4 1.5 35 700 V(FB) > 0.4 V TPS62300 TPS62320 TPS62300 TPS62320 TPS6230x TPS6232x TPS62305 VO Adjustable output voltage DC accuracy (1) TPS62300 TPS62320 TPS6230x TPS6232x TPS62305 DC output voltage load regulation DC output voltage load regulation (power train in direct drive mode) DC output voltage line regulation DC output voltage line regulation (power train in direct drive mode) Integrator slew rate VO Power-save mode ripple voltage Start-up time I(LK_SW) Leakage current into SW pin Reverse leakage current into SW pin IO = 1 mA, MODE/SYNC = GND IO = 200 mA, Time from active EN to VO VI > VO, 0 V V(SW) VIN, EN = GND VI = open, V(SW) = 6.0 V, EN = GND PWM mode operation, VI = 3.6 V, No Load TA = 25C -40C TA 85C TA = 25C -40C TA 85C TA = 25C -40C TA 85C IO = 0 mA to 500 mA, MODE/SYNC = VI V(ADJ) externally forced to 1.067 V, IO = 0 mA to 500 mA, MODE/SYNC = VI VI = VO + 0.5 V (min 2.7 V) to 6.0 V, IO = 100 mA, MODE/SYNC = VI V(ADJ) externally forced to 1.067 V, VI = VO + 0.5 V (min 2.7 V) to 6.0 V, IO = 100 mA, MODE/SYNC = VI 100 V(FB) = 0.4 V -2.0% 2.7 V VI 6.0 V, 0 mA IO(DC) 500 mA PFM/PWM mode operation -2.0% -2.0% -0.5% -0.5% -0.5% -0.5% -0.3% -0.5% -0.001 -0.0003 0.11 700 1000 1000 1 +2.0% +2.0% +2.7% +1.3% +1.3% +1.3% +1.3% +1.7% +2.0% -0.002 -0.0006 0.2 %/mA %/mA %/V 1300 1.504 ns k k nA 5.4 V V TEST CONDITIONS MIN TYP MAX UNIT
DC power train amplification (VO/V(ADJ)) Minimum on-time (P-channel MOSFET) Resistance into VOUT sense pin Resistance into ADJ pin
I(FB)
Feedback input bias current Adjustable output voltage (1) Fixed output voltage
PRODUCT PREVIEW
Fixed output voltage DC accuracy
0.035 150 0.025 VO 250 0.1 0.1
0.1 200
%/V V/s VP-P s
1 1
A
(1)
Output voltage specification for the adjustable version does not include tolerance of external voltage programming resistors.
4
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
PIN ASSIGNMENTS
TPS62300, TPS62320 QFN-10 (TOP VIEW) TPS6230x, TPS6232x Fixed Output Voltage (QFN-10) (TOP VIEW)
VIN AVIN EN ADJ FB
SW PGND MODE/SYNC AGND VOUT
VIN AVIN EN NC NC
SW PGND MODE/SYNC AGND VOUT
TPS6230x, TPS6232x CSP-8 (TOP VIEW)
TPS6230x, TPS6232x CSP-8 (BOTTOM VIEW)
GND SW MODE/SYNC VOUT
A1 B1 C1 D1
A2 B2 C2 D2
VIN EN ADJ FB
VIN EN ADJ FB
A2 B2 C2 D2
A1 B1 C1 D1
GND SW MODE/SYNC VOUT
TERMINAL FUNCTIONS
TERMINAL NAME VIN AVIN EN NO. QFN 1 2 3 B2 NO. CSP A2 I/O I I I Supply voltage for output power stage. This is the input voltage pin of the device. Connect directly to the input bypass capacitor. This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be terminated. This is the internal reference voltage used to regulate VO. This pin is not connected on fixed output voltage version of TPS6230xDRC and TPS6232xDRC. Do not connect ADJ pin on fixed output voltage version of TPS6230xYZD and TPS6232xYED. On TPS62300 and TPS62320, this pin can also be used as an external control input. The output voltage is 1.5x the applied voltage at ADJ. FB VOUT AGND 5 6 7 D2 D1 I I This is the feedback pin of the device. For the adjustable version, an external resistor divider is connected to this pin. The internal voltage divider is disabled for the adjustable version. This pin is not connected on fixed output voltage version of TPS6230xDRC and TPS6232xDRC. Do not connect the FB pin on the fixed output voltage version of TPS6230xYZD and TPS6232xYED. Output feedback sense input. Connect VOUT to the converter's output. Analog ground. Connect to PGND via the PowerPADTM underneath IC. Input for synchronization to external clock signal. This pin must not be left floating and must be terminated. Synchronizes the converter switching frequency to an external clock signal MODE/SYNC 8 C1 I MODE/SYNC = LOW (GND): The device is operating in fixed frequency pulse width modulation mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents. MODE/SYNC = HIGH (VIN): Low-noise mode enabled, fixed frequency PWM operation forced. PGND SW PowerPADTM 9 10 A1 B1 I/O N/A Power ground. This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs. Internally connected to PGND. DESCRIPTION
ADJ
4
C2
I/O
5
PRODUCT PREVIEW
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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FUNCTIONAL BLOCK DIAGRAM
MODE/SYNC EN VIN
AVIN
Undervoltage Lockout Bias Supply VREF = 0.4 V Band Gap 3-MHz Oscillator + PLL Sawtooth Generator Soft-Start Power-Save Mode Comp Low
N-MOS Current Limit Compator
_ + + _
REF REF
Thermal Shutdown
Switching Logic
2R R VOUT 2C VREF FB C
RAMP HEIGHT 0.1 VIN
P-MOS Current Limit Compator
-
-
+
+
- -
Gate Driver R(DIS) Anti Shoot-Through SW
+ _
+
+
A(DC) = 3
+
-
+ +
Summing Comparator
EN
TPS6232x Only
Mid-, High-Frequency Zero-Pole Pair A R2 R1
P
PRODUCT PREVIEW
P
VOUT
See note A ADJ A Comparator Low -1.5% VOUT(NOMINAL)
+ _
PGND
AGND
NOTE A:
For the adjustable versions (TPS62300 and TPS62320) the internal feedback divider is disabled.
PARAMETER MEASUREMENT INFORMATION
U1 1 2.7 V . . 6 V VI C1 2 3 8 AVIN VIN EN SW VOUT ADJ 10 6 4 R1 L1 C2 VO 1.6 V/500 mA
10 mF
5 MODE/SYNC FB 7 AGND PGND 9 A A
R2 A
List of Components: U1 = TPS6230x L1 = FDK MIPW3226 Series C1, C2 = X5R/X7R
6
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE Efficiency Line transient response Load transient response VO VFB IQ fs DC output voltage Regulated feedback voltage No load quiescent current Switching frequency Duty cycle jitter rDS(on) P-channel MOSFET rDS(on) N-channel MOSFET rDS(on) PWM operation Power-save mode operation Dynamic voltage management Start-up Power down (TPS6232x) vs Input voltage vs Input voltage vs Load current vs Temperature vs Input voltage vs Temperature vs Load current vs Input voltage 3, 4, 5, 6 7 8 9, 10, 11, 12, 13, 14, 15, 16 17 18 19 20 21 22 23 24 25 28, 29 30 26, 27
EFFICIENCY vs LOAD CURRENT
100 90 80 70 Efficiency - % 60 50 40 30 20 10 0 0.1 1 10 100 IO - Load Current - mA 1000 PWM Operation L = 2.2 mH PFM/PWM Operation L = 0.9 mH VI = 3.6 V, VO = 1.8 V PFM/PWM Operation L = 2.2 mH 100 90 80 70 Efficiency - % 60 50 40 30 20 10 0 0.1 VI = 3.6 V, VO = 1.6 V
EFFICIENCY vs LOAD CURRENT
PFM/PWM Operation L = 2.2 mH
PWM Operation L = 0.9 mH
1 10 100 IO - Load Current - mA
1000
Figure 3.
Figure 4.
7
PRODUCT PREVIEW
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY vs LOAD CURRENT
90 80 70 Efficiency - % Efficiency - % 60 50 40 30 20 10 VI = 3.6 V, VO = 1.2 V 0.1 1 10 100 IO - Load Current - mA 1000 PWM Operation L = 2.2 mH PFM/PWM Operation L = 2.2 mH 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 IO - Load Current - mA 1000 VI = 5 V, VO = 3.3 V PWM Operation L = 0.9 mH
EFFICIENCY vs LOAD CURRENT
PFM/PWM Operation L = 2.2 mH
IO = 100 mA 90 80 70 Efficiency - % IO = 1 mA 60 50 40 30 20 10 0 2.7 3
VI = 1 V/div - 3.6 V Offset
IO = 10 mA
PFM/PWM Operation VO = 1.8 V
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6 VI - Input Voltage - V t - Time - 100 ms/div
Figure 7.
Figure 8.
8
V O = 10 mV/div - 1.6 V Offset
PRODUCT PREVIEW
0
Figure 5. EFFICIENCY vs INPUT VOLTAGE
100 IO = 400 mA VO = 1.6 V
Figure 6.
LINE TRANSIENT RESPONSE
L = 0.9 mH, CO = 10 mF
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN PWM OPERATION
I O = 50 mA or 200 mA/div I O = 50 mA or 200 mA/div VI = 3.6 V, VO = 1.6 V MODE/SYNC = HIGH L = 0.9 mH, CO = 10 mF
LOAD TRANSIENT RESPONSE IN PWM OPERATION
VI = 3.6 V, VO = 1.6 V MODE/SYNC = HIGH L = 0.9 mH, CO = 10 mF
V O = 10 mV/div - 1.6 V Offset
IO = 10 to 100 mA Load Step
IO = 10 to 400 mA Load Step
IO = 10 to 400 mA Load Step t - Time - 2 ms/div
V O = 10 mV/div - 1.6 V Offset
IO = 10 to 100 mA Load Step
t - Time - 50 ms/div
Figure 9. LOAD TRANSIENT RESPONSE IN PWM OPERATION
I O = 50 mA or 200 mA/div I O = 100 mA/div VI = 3.6 V, VO = 1.6 V MODE/SYNC = HIGH L = 0.9 mH, CO = 10 mF
Figure 10. LOAD TRANSIENT RESPONSE IN PFM MODE
VI = 3.6 V, VO = 1.6 V L = 0.9 mH, CO = 10 mF
IO = 100 to 10 mA Load Step
V O = 10 mV/div - 1.6 V Offset
IO = 400 to 10 mA Load Step
PFM Operation t - Time - 50 ms/div
t - Time - 2 ms/div
Figure 11.
Figure 12.
V O = 20 mV/div - 1.6 V Offset
9
PRODUCT PREVIEW
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN PWM OPERATION
IO = 50 mA or 200 mA/div VI = 3.6 V, VO = 1.6 V IO = 50 mA or 200 mA/div MODE/SYNC = HIGH L = 0.9 mH, CO = 4.7 mF
LOAD TRANSIENT RESPONSE IN PWM OPERATION
VI = 3.6 V, VO = 1.6 V MODE/SYNC = HIGH L = 0.9 mH, CO = 4.7 mF
VO = 10 mV/div - 1.6 V Offset
IO = 10 to 100 mA Load Step
IO = 10 to 100 mA Load Step
IO = 10 to 400 mA Load Step
IO = 10 to 400 mA Load Step t - Time - 2 ms/div
t - Time - 50 ms/div
Figure 13. LOAD TRANSIENT RESPONSE IN PFM OPERATION
IO = 50 mA or 200 mA/div IO = 100 mA/div VI = 3.6 V, VO = 1.6 V MODE/SYNC = HIGH L = 0.9 mH, CO = 4.7 mF
Figure 14. LOAD TRANSIENT RESPONSE IN PFM OPERATION
VI = 3.6 V, VO = 1.6 V L = 0.9 mH, CO = 4.7 mF
VO = 20 mV/div - 1.6 V Offset
IO = 400 to 10 mA Load Step
IO = 100 to 10 mA Load Step
PFM Operation t - Time - 50 ms/div
t - Time - 2 ms/div
Figure 15.
Figure 16.
10
VO = 20 mV/div - 1.6 V Offset
VO = 20 mV/div - 1.6 V Offset
PRODUCT PREVIEW
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE vs LOAD CURRENT
1.628 VI = 3.6 V, VO = 1.6 V, L = 2.2 mH 406 TPS62300 V(FB) - Regulated Feedback Voltage - mV 405.5 405 404.5 VI = 4.2 V 404 403.5 403 VI = 2.7 V 402.5 402 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85 TA - Ambient Temperature - 5C VI = 3.6 V
REGULATED FEEDBACK VOLTAGE vs TEMPERATURE
1.618 VO - Output Voltage - V
1.608
PWM Operation
1.598
1.588
PFM/PWM Operation
1.578 1.568 0.1
1
10 100 IO - Load Current - mA
1000
Figure 17. QUIESCENT CURRENT vs INPUT VOLTAGE
96 94 I Q- Quiescent Current - A 92 90 88 86 84 82 80 2.7 TA = -405C TA = 855C TA = 255C 3.3 3.25 3.2 3.15
Figure 18. OSCILLATOR FREQUENCY vs INPUT VOLTAGE
f s - Oscillator Frequency - MHz
TA = -405C
TA = 255C 3.1 TA = 855C 3.05 3 2.95 2.9 2.7 MODE/SYNC = HIGH
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 VI - Input Voltage - V
6
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 VI - Input Voltage - V
6
Figure 19.
Figure 20.
11
PRODUCT PREVIEW
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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TYPICAL CHARACTERISTICS (continued)
P-CHANNEL rDS(ON) vs INPUT VOLTAGE
700 rDS(on) - Static Drain-Source On-Resistance - m 650 600 550 500 450 400 350 300 250 200 150 2.5 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 TA = -405C TA = 855C TA = 255C
DUTY CYCLE JITTER
VI = 3.6 V, VO = 1.6 V, L = 0.9 mH, CO = 10 mF TRIGGER ON RISING EDGE IO = 320 mA
SW - 1 V/div
MODE/SYNC = HIGH
rDS(on) - Static Drain-Source On-Resistance - m
SW - 2 V/div
350 TA = 255C 300 250 200 150 2.5 TA = -405C
VI = 3.6 V, VO = 1.6 V 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 t - Time - 200 ns/div
Figure 23.
Figure 24.
12
VO - 10 mV/div - 1.6 V Offset
PRODUCT PREVIEW
t - Time - 25 ns/div
Figure 21. N-CHANNEL rDS(ON) vs INPUT VOLTAGE
550 500 450 400 TA = 855C I L - 200 mA/div IO = 200 mA
Figure 22.
PWM OPERATION
L = 0.9 mH, CO = 10 mF
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
TYPICAL CHARACTERISTICS (continued)
POWER-SAVE MODE OPERATION
I L - 200 mA/div VO - 200 mV/div
DYNAMIC VOLTAGE MANAGEMENT
VI = 3.6 V, VO = 1 V / 1.5 V
VO = 1.5 V
VO = 1 V V(ADJ) = 0.67 V V(ADJ) = 1 V ADJ - 500 mA/div RL = 270 W t - Time - 20 ms/div
VO - 20 mV/div - 1.6 V Offset
I L - 500 mA/div
VI = 3.6 V, VO = 1.6 V IO = 40 mA L = 0.9 mH, CO = 10 mF t - Time - 2 ms/div
L = 0.9 mH, CO = 10 mF, MODE/SYNC = LOW
Figure 25. DYNAMIC VOLTAGE MANAGEMENT
VO - 200 mV/div VI = 3.6 V, VO = 1 V / 1.5 V EN - 2 V/div VI = 3.6 V, VO = 1.6 V, IO = 0 mA
Figure 26. START-UP
VO - 1 V/div
VO = 1.5 V
VO = 1 V
V(ADJ) = 1 V
I L - 500 mA/div
RL = 5 W L = 0.9 mH, CO = 10 mF, MODE/SYNC = HIGH
I L - 200 mA/div
L = 2.2 mH, CO = 4.7 mF, t - Time - 50 ms/div
t - Time - 20 ms/div
Figure 27.
Figure 28.
VADJ - 2 V/div
V(ADJ) = 0.67 V
ADJ - 500 mA/div
13
PRODUCT PREVIEW
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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TYPICAL CHARACTERISTICS (continued)
START-UP
EN - 2 V/div EN - 2 V/div VI = 3.6 V, VO = 1.6 V, IO = 320 mA
POWER DOWN (TPS62321)
VI = 3.6 V, VO = 1.5 V, IO = 0 mA
V(ADJ) - 2 V/div
VO - 1 V/div
I L - 200 mA/div
VO - 500 mV/div
L = 2.2 mH, CO = 4.7 mF,
L = 0.9 mH, CO = 10 mF
PRODUCT PREVIEW
t - Time - 50 ms/div
t - Time - 400 ms/div
Figure 29.
Figure 30.
DETAILED DESCRIPTION OPERATION
The TPS6230x and TPS6232x are synchronous step-down converters typically operating with a 3-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter operates in power-save mode with pulse frequency modulation (PFM). The operating frequency is set to 3 MHz and can be synchronized on-the-fly to an external oscillator. During PWM operation, the converter uses a unique fast response, voltage mode, controller scheme with input voltage feed-forward. This achieves best-in-class load and line response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The device integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. When the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit. The current limit in the N-channel MOSFET is important for small duty-cycle operation when the current in the inductor does not decrease because of the P-channel MOSFET current limit delay, or because of start-up conditions where the output voltage is low.
POWER-SAVE MODE
With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically, the switching losses are minimized, and the device runs with a minimum quiescent current and maintaining high efficiency. In power-save mode, the converter only operates when the output voltage trips below a set threshold voltage (-1.5% VO(NOMINAL)). It ramps up the output voltage with several pulses and goes into power-save mode once the output voltage exceeds the nominal output voltage. As a consequence, the average output voltage is slightly lower than its nominal value in the power-save mode operation.
14
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
DETAILED DESCRIPTION (continued)
VO(NOMINAL)
3-MHz Operation
Comp Low Thershold -1.5% VO(NOMIAL)
Figure 31. Power-Save Mode Threshold
MODE SELECTION AND FREQUENCY SYNCHRONIZATION
The MODE/SYNC pin is a multipurpose pin which allows mode selection and frequency synchronization. Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converter operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide load current range.
The TPS6230x and TPS6232x can also be synchronized to an external 3-MHz clock signal by the MODE/SYNC pin. During synchronization, the mode is set to fixed-frequency operation and the P-channel MOSFET turnon is synchronized to the falling edge of the external clock. This creates the ability for multiple converters to be connected together in a master-slave configuration for frequency matching of the converters (see the application section for more details, Figure 37).
SOFT START
The TPS6230x and TPS6232x have an internal soft-start circuit that limits the inrush current during start-up. This prevents possible input voltage drops when a battery or a high-impedance power source is connected to the input of the converter. The soft start is implemented as a digital circuit increasing the switch current in steps of typically 195 mA, 390 mA, 585 mA, and the typical switch current limit of 780 mA. Therefore, the start-up time mainly depends on the output capacitor and load current.
LOW-DROPOUT OPERATION 100% DUTY CYCLE
In 100% duty cycle mode, the TPS6230x and TPS6232x offer a low input-to-output voltage difference. In this mode, the P-channel MOSFET is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation, depending on the load current and output voltage, can be calculated as: * VI(MIN) = VO(MAX) + IO(MAX)x (rDS(on) MAX + RL) * IO(MAX) : Maximum output current * rDS(on) MAX : Maximum P-channel switch rDS(on) * RL : DC resistance of the inductor * VO(MAX) : nominal output voltage plus maximum output voltage tolerance
15
PRODUCT PREVIEW
Pulling the MODE/SYNC pin high forces the converter to operate in the PWM mode even at light load currents. The advantage is that the converter operates with a fixed frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements.
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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DETAILED DESCRIPTION (continued) ENABLE
The device starts operation when EN is set high and starts up with the soft start as previously described. Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.1 A. In this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off. When an output voltage is present during shutdown mode, which can be caused by an external voltage source or super capacitor, the reverse leakage is specified under electrical characteristics. For proper operation, the EN pin must be terminated and must not be left floating. In addition, the TPS6232x devices integrate a resistor, typically 35 , to actively discharge the output capacitor when the device turns off. The required time to discharge the output capacitor at VO depends on load current.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions.
SHORT-CIRCUIT PROTECTION
As soon as the output voltage falls below 50% of the nominal output voltage, the converter current limit is reduced by 50% of the nominal value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half of its nominal current limit until the output voltage exceeds 50% of the nominal output voltage. This needs to be considered when a load acting as a current sink is connected to the output of the converter.
PRODUCT PREVIEW
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 150C, the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction temperature falls below typically 130C again.
APPLICATION INFORMATION ADJUSTABLE OUTPUT VOLTAGE
When the adjustable output voltage versions, TPS62300 or TPS62320, are used, the output voltage is set by the external resistor divider (see Figure 32). The output voltage is calculated as:
V O + 1.5 V ref 1 ) R1 with an internal reference voltage V typical + 0.4 V ref R2
(1)
To keep the operating quiescent current to a minimum, it is recommended that R2 be set in the range of 300 k to 500 k. Route the FB line away from noise sources, such as the inductor or the SW line.
TPS62300 2.7 V . . 6 V VI C1 4.7 mF L1 SW 10 VOUT 6 3 EN 4 R1 ADJ 8 MODE/SYNC 5 FB 7 AGND PGND 9 1 AVIN 2 VIN A A C2 VO 1.6 V/500 mA
4.7 mF
R2 A
Figure 32. Adjustable Output Voltage Version
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
APPLICATION INFORMATION (continued) OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The TPS6230x and TPS6232x series of step-down converters have internal loop compensation. Therefore, the external L-C filter must be selected to work with the internal compensation. The device has been designed to operate with inductance values between a minimum of 0.7 H and maximum of 6.2 H. The internal compensation is optimized to operate with an output filter of L = 1 H and CO = 10 F. Such an output filter has its corner frequency at: 1 1 c + + + 50.3 kHz 2p L C 2p 1 mH 10 mF O (2) Operation with a higher corner frequency (e.g., L = 1 H, CO = 4.7 F) is possible. However, it is recommended the loop stability be checked in detail. Selecting a larger output capacitor value (e.g., 22 F) is less critical because the corner frequency moves to lower frequencies with fewer stability problems. The possible output filter combinations are listed in Table 1. Regardless of the inductance value, operation is recommended with 10-F output capacitor in applications with di dt (e.g., 1600 mA/s). high-load transients Table 1. Output Filter Combinations
INDUCTANCE (L) 1.0 H 2.2 H OUTPUT CAPACITANCE (CO) 4.7 F (ceramic capacitor) 2.2 F (ceramic capacitor)
The inductor value also has an impact on the pulse skipping operation. The transition into power-save mode begins when the valley inductor current goes below a level set internally. Lower inductor values result in higher ripple current which occurs at lower load currents. This results in a dip in efficiency at light load operations.
17
PRODUCT PREVIEW
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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INDUCTOR SELECTION
Even though the inductor does not influence the operating frequency, the inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its dc resistance and saturation current. The inductor ripple current (IL) decreases with higher inductance and increases with higher VI or VO. V V *V DI I O DI + O DI +I )L L L(MAX) O(MAX) 2 V L sw I (3) with: fSW = switching frequency (3 MHz typical) L = inductor value IL = peak-to-peak inductor ripple current IL(MAX) = maximum inductor current Normally, it is advisable to operate with a ripple of less than 30% of the average output current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following frequency-dependent components: * The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) * Additional losses in the conductor from the skin effect (current displacement at high frequencies) * Magnetic field losses of the neighboring windings (proximity effect) * Radiation losses The following inductor series from different suppliers have been used with the TPS6230x and TPS6232x converters. Table 2. List of Inductors
MANUFACTURER FDK Taiyo Yuden TDK Wuerth Elektronik SERIES MIPW3226 LQ CB2016 LQ CB2012 LQ CBL2012 VLF3010AT WE-TPC XS DIMENSIONS 3.2 x 2.6 x 1.0 = 8.32 mm3 2.0 x 1.6 x 1.6 = 5.12 mm3 2.0 x 1.2 x 1.2 = 2.88 mm3 2.0 x 1.2 x 1.0 = 2.40 mm3 2.8 x 2.6 x 1.0 = 7.28 mm3 3.3 x 3.5 x 0.95 = 10.97 mm3
PRODUCT PREVIEW
OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS6230x and TPS6232x allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:
DV V +O O V I V *V I O L sw 1 8 C O sw ) ESR , maximum for high V I
(4)
At light loads, the device operates in power-save mode and the output voltage ripple is independent of the output capacitor value. The output voltage ripple is set by the internal comparator thresholds and propagation delays. The typical output voltage ripple is 1.5% of the nominal output voltage VO.
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interferences with other circuits in the system. For most applications, a 2.2-F or 4.7-F capacitor is sufficient. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: * Switching node, SW * Inductor current, IL * Output ripple voltage, VO(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the converter's stability. Without any ringing, the loop has usually more than 45 of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range.
PROGRAMMING THE OUTPUT VOLTAGE WITH A DAC
On TPS62300 and TPS62320 devices, the output voltage can be dynamically programmed to any voltage between 0.6 V and VI (or 5.4 V whichever is lower) with an external DAC driving the ADJ and FB pins (see Figure 33). The output voltage is then equal to A(PT)x V(DAC) with a Power Train amplification A(PT) typical = 1.5. When the output voltage is driven low, the converter reduces its output quickly in forced PWM mode, boosting the output energy back to the input. If the input is not connected to a low-impedance source capable of absorbing the energy, the input voltage can rise above the absolute maximum voltage of the part and get damaged. The faster VO is commanded low, the higher is the voltage spike at the input. For best results, ramp the ADJ/FB signal as slow as the application allows. To avoid over-slew of the regulation loop of the converter, avoid abrupt changes in output voltage of > 300 mV/s (depending on VI , output voltage step size and L/C combination). If ramp control is unavailable, an RC filter can be inserted between the DAC output and ADJ/FB pins to slow down the control signal.
TPS62300 1 AVIN 2 VIN VI CI SW 10 VOUT 6 L VO = 1.5 x V(DAC) CO RF CF 10 kW A V(DAC)
3 EN ADJ 4 8 MODE/SYNC FB 5 7 AGND A PGND 9 A
Figure 33. Filtering the DAC Voltage
19
PRODUCT PREVIEW
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VO immediately shifts by an amount equal to I(LOAD) x ESR, where ESR is the effective series resistance of CO. I(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VO to its steady-state value.
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the TPS6230x and TPS6232x devices demand careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold on Figure 34. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to minimize the effects of ground noise. Connect these ground nodes together (star point) underneath the IC and make sure that small signal components returning to the AGND pin do not share the high current path of C1 and C2. The output voltage sense line (VOUT) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring connected to the reference ground. The voltage setting resistive divider should be placed as close as possible to the AGND pin of the IC.
TPS62300 1 AVIN SW 2 VIN VOUT 3 EN ADJ 8 MODE/SYNC FB 7 AGND 10 6 4 R1 5 R2 C2 L1 VO
VI C1
PRODUCT PREVIEW
20
PGND 9
Figure 34. Layout Diagram
GND VI
VO
VO sense signal
EN
Figure 35. Suggested QFN Layout (Top)
MODE / SYNC
GND
Figure 36. Suggested QFN Layout (Bottom)
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the power-dissipation limits of a given component Three basic approaches for enhancing thermal performance are listed below: * Improving the power dissipation capability of the PCB design * Improving the thermal coupling of the component to the PCB * Introducing airflow in the system The maximum recommended junction temperature (TJ) of the TPS6230x and TPS6232x devices is 125C. The thermal resistance of the 8-pin CSP package (YZD and YED) is RJA = 250C/W. Specified regulator operation is assured to a maximum ambient temperature TA of 85C. Therefore, the maximum power dissipation is about 160 mW. More power can be dissipated if the maximum ambient temperature of the application is lower or if the PowerPADTM package (DRC) is used. T *T J(MAX) A P + + 125C * 85C + 160 mW D(MAX) R 250C W qJA (5)
The TPS6230x and TPS6232x are also available in an 8-bump chip scale package (YZD, NanoFreeTM and YED, NanoStarTM). The package dimensions are given as: * D = 1.970 0.05 mm * E = 0.970 0.05 mm
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PRODUCT PREVIEW
CHIP SCALE PACKAGE DIMENSIONS
TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
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APPLICATION EXAMPLES
TPS62303YZD 2.7 V - 6 V V IN C IN A2 B2 C1 A1 VIN EN MODE/SYNC GND VOUT SW ADJ FB D1 B1 C2 D2 L1 C 1 V OUT 1.8 V / 500 mA
Ch1
Ch2
10 F
10 F
Ch4
TPS62304YZD A2 B2 C1 1G08 Low: None Synchronized Operation PFM/PWM Automatic Switch High: Synchronized Operation Forced 3 MHz Fixed Frequency Operation List of Components: L1, L2 = Taiyo Yuden LQ CB2016 CIN, C1, C2, = X5R/X7R Ceramic Capacitor A1 VIN EN MODE/SYNC GND SW VOUT ADJ FB B1 D1 C2 D2 L2 C2 10 F V OUT
1.2 V / 500 mA
Ch3
Ch1: SW (1.8-V Output), Ch2: IL1 Ch3: SW (1.2-V Output), Ch4: IL2
Figure 37. Dual, Out-of-Phase, 3-MHz, 500-mA Step-Down Regulator Features Less Than 50-mm2 Total Solution Size
EN
22 nF EN 2.2 M Fast Start-Up LDO 10 k EN VIN GND VOUT(LDO) = 0.98 x VOUT(NOM) VOUT
PRODUCT PREVIEW
22
2.7 V . . 6 V C V IN IN
TPS62300YZD A2 B2 VIN EN VOUT SW D1 B1 C2 D2 L1 1 H C1 VOUT 1.8 V / 500 mA
VO IL1
10 F
C1 MODE/SYNC ADJ A1 GND FB
10 F
VI = 2.8 V, RL = 10 W
List of Components: L1 = Taiyo Yuden LQ CB2016 CIN, C1 = X5R/X7R Ceramic Capacitor
Ch1: VO Ch3: Inductor Current: IL1 Ch3: EN - External Control Signal
Figure 38. Speed-Up Circuitry for Fast Turnon Time
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TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305 TPS62306, TPS62320, TPS62321
SLVS528 - JULY 2004
TPS62300 VIN VOUT L1 EN MODE/SYNC GND SW R1 ADJ 9.5 k FB R2 8.2 k V O- Output Voltage - V 2.2 H VOUT C1 4.7 F 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 DAC Control Range VO = 1.5 x 0.98 x V(DAC) 0.2 0.4 0.6 0.8 1 1.2 V(DAC) - Control Voltage - V 1.4 Default Voltage = R1 1.5 x Vref x 1+ R2
2.7 V - 6 V VIN
CI 10 F
()
2.85 V
DAC6571 VDD
I2C I/F
SDA SCL A0 GND VDAC
List of Components:
L1 = Wuerth Elektronik WE-TPC XS CI , C1, = X5R/X7R Ceramic Capacitor
Figure 39. Dynamic Voltage Management Using I2C I/F
23
PRODUCT PREVIEW
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