View TDA9965_293911.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
TDA9965 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
Product specification Supersedes data of 2003 Feb 11 2003 Nov 26
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
FEATURES * Clamp and Track/Hold (CTH) circuit with adjustable bandwidth, Programmable Gain Amplifier (PGA), 12-bit Analog-to-Digital Converter (ADC) and reference regulator * Fully programmable via a 3-wire serial interface * Sampling frequency up to 30 MHz * PGA gain from 0 to 36 dB (in 0.05 dB steps) * CTH programmable bandwidth from 35 to 284 MHz typical * Standby mode (20 mW typical) * Low power consumption of only 425 mW typical * 5 V operation and 2.5 to 5.25 V operation for the digital outputs ORDERING INFORMATION TYPE NUMBER TDA9965HL PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
TDA9965
* TTL compatible inputs; TTL and CMOS compatible outputs. APPLICATIONS * CCD camera systems. GENERAL DESCRIPTION The TDA9965 is a 12-bit analog-to-digital interface for a CCD camera. The device includes a CTH circuit, PGA and a low-power 12-bit ADC, together with its reference voltage regulator. The CTH has a bandwidth circuit controlled by on-chip DACs via a serial interface. A 10-bit digital clamp controls the ADC input clamp level.
VERSION SOT313-2
QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ADCres Vi(IN)(p-p) GCTH PGAdyn fpix(max) Ntot(rms) Vn(i)(eq)(rms) Ptot Note 1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB. 2003 Nov 26 2 PARAMETER analog supply voltage digital supply voltage digital output supply voltage analog supply current digital supply current digital output supply current ADC resolution CTH input voltage (peak-to-peak value) CTH output amplifier gain PGA dynamic range maximum pixel frequency code fco(CTH) = 0000 total noise from CTH input to ADC GPGA = 0 dB; output (RMS value) code fco(CTH) = 0000 equivalent input noise (RMS value) total power consumption GPGA = 30 dB; code fco(CTH) = 0000; note 1 with internal regulator with internal regulator fpix = 30 MHz; CL = 10 pF on all data outputs; ramp input CONDITIONS MIN. 4.75 4.75 2.5 - - - - - - - 30 - - - TYP. 5 5 3 65 19 1 12 2 0 36 - 0.75 45 425 MAX. 5.25 5.25 5.25 - - - - - - - - - - - UNIT V V V mA mA mA bits V dB dB MHz LSB V mW
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Nov 26
AGND4 IN AGND5 STGE AGND1 VCCA1 AGND2 VCCA2 Vref
BLOCK DIAGRAM
Philips Semiconductors
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
VCCD2 DGND2 48 1 47 SHD 46 SHP 45 CLAMP CLAMP TRACK AND HOLD CLPOB 44 CLPADC 43
VCCD1 CLKADC DGND1 STDBY D11 42 41 40 39 38
D10 37
2
CLOCK
36
D9
3 4 5 6 4-BIT DAC 10
35
D8 D7
34
33
D6
32 7 8 9
TDA9965
12-BIT ADC
12
VCCO2 OGND2
OUTPUT BUFFER
31
handbook, full pagewidth
3
30
VCCO1 OGND1
PGAOUT
10
PGA REF = 3.2 V
29
28 10-BIT DAC ADCIN 11 26
D5
27
D4
D3
n.c.
12
REGULATOR 16 DEC VRT REF32
INIT-ONPOWER 17 18 VCCA3 19
SERIAL INTERFACE 20 SEN SCLK 21 22 23 D0 24 D1
25
D2
Product specification
13
14 VRB
15
FCE424
TDA9965
SDATA
REGEN
AGND3
Fig.1 Block diagram.
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
PINNING SYMBOL AGND4 IN AGND5 STGE AGND1 VCCA1 AGND2 VCCA2 Vref PGAOUT ADCIN n.c. REGEN VRB VRT DEC REF32 VCCA3 AGND3 SEN SCLK SDATA D0 D1 D2 D3 D4 D5 OGND1 VCCO1 OGND2 VCCO2 D6 D7 D8 D9 D10 D11 STDBY 2003 Nov 26 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 analog ground 4 data input signal from CCD analog ground 5 clamp storage capacitor pin analog ground 1 analog supply voltage 1 analog ground 2 analog supply voltage 2 ADC clamp reference voltage input; short-circuited to ground via a capacitor PGA amplifier signal output ADC analog signal input; externally connected to pin PGAOUT not connected regulator enable input (active HIGH) regulator reference voltage bottom regulator reference voltage top regulator decoupling; decoupled to ground via a capacitor internal reference voltage; decoupled to ground via a capacitor analog supply voltage 3 analog ground 3 enable input for the serial interface shift register (active LOW) serial clock input for the serial interface DESCRIPTION
TDA9965
serial data input: 10-bit PGA gain, 4-bit DAC for the frequency cut-off, 10 low significant bits for the digital ADC clamp and edge pulse control ADC digital output 0 (LSB) ADC digital output 1 ADC digital output 2 ADC digital output 3 ADC digital output 4 ADC digital output 5 digital output ground 1 digital output supply voltage 1 digital output ground 2 digital output supply voltage 2 ADC digital output 6 ADC digital output 7 ADC digital output 8 ADC digital output 9 ADC digital output 10 ADC digital output 11 (MSB) standby control input (active HIGH); all output bits are logic 0 when standby is enabled 4
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
SYMBOL VCCD1 DGND1 CLKADC CLPADC CLPOB SHP SHD VCCD2 DGND2 PIN 40 41 42 43 44 45 46 47 48 digital supply voltage 1 digital ground 1 ADC clock input clamp control pulse input for ADC analog input signal clamp control pulse input at optical black preset sample and hold pulse input data sample and hold pulse input digital supply voltage 2 digital ground 2 DESCRIPTION
TDA9965
42 CLKADC
43 CLPADC
48 DGND2
41 DGND1
44 CLPOB
47 VCCD2
40 VCCD1
38 D11
AGND4 1 IN 2 AGND5 3
37 D10
handbook, full pagewidth
39 STDBY
46 SHD
45 SHP
36 D9 35 D8 34 D7 33 D6 32 VCCO2 31 OGND2
STGE 4 AGND1 5 VCCA1 6
TDA9965HL
AGND2 7 VCCA2 8 Vref 9 30 VCCO1 29 OGND1 28 D5 27 D4 26 D3 25 D2
PGAOUT 10 ADCIN 11 n.c. 12
REGEN 13
VRB 14
VRT 15
DEC 16
REF32 17
VCCA3 18
AGND3 19
SEN 20
SCLK 21
SDATA 22
D0 23
D1 24
FCE531
Fig.2 Pin configuration.
2003 Nov 26
5
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage digital output supply voltage supply voltage difference between VCCA and VCCD between VCCD and VCCO Vi Io Tstg Tamb Tj Note 1. All supplies are connected together. HANDLING input voltage output current storage temperature ambient temperature junction temperature referenced to AGND -1.0 -1.0 -0.3 -10 -55 -20 - CONDITIONS note 1 note 1 note 1 MIN. -0.3 -0.3 -0.3
TDA9965
MAX. +7.0 +7.0 +7.0 +1.0 +4.0 +7.0 +10 +150 +75 150 V V V V V V
UNIT
mA C C C
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 76 UNIT K/W
2003 Nov 26
6
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
CHARACTERISTICS VCCA = VCCD = 5 V; VCCO = 3 V; fpix = 30 MHz; Tamb = -20 to +75 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO Digital inputs CLOCK INPUT: PIN CLKADC (REFERENCED TO DGND) VIL VIH IIL IIH Zi Ci VIL VIH Ii VIL VIH Ii Vi(IN)(p-p) Ii(IN) tW(SHP) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance VCLKADC = 0.8 V VCLKADC = 2.0 V 0 2.0 -1 - - - 0 2.0 -2 0 2.0 -10 - -3 Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; see Fig.5 9 - - - - 63 1 - - - - - - 2 - - analog supply voltage digital supply voltage digital output supply voltage analog supply current digital supply current digital output supply current with internal regulator with internal regulator fpix = 30 MHz; CL = 10 pF on all data outputs; ramp input 4.75 4.75 2.5 - - - 5 5 3 65 19 1 PARAMETER CONDITIONS MIN. TYP.
TDA9965
MAX.
UNIT
5.25 5.25 5.25 - - -
V V V mA mA mA
0.8 VCCD +1 20 - - 0.8 VCCD +2
V V A A k pF
CONTROL INPUTS: PINS SEN, SCLK, SDATA, STDBY, CLPOB, CLPADC AND REGEN LOW-level input voltage HIGH-level input voltage input current V V A V V A V A ns
SAMPLE AND HOLD INPUTS: PINS SHP AND SHD LOW-level input voltage HIGH-level input voltage input current 0.8 VCCD +10 - +3 -
Clamp and Track/Hold (CTH) circuit: pins IN, SHD and SHP CTH input voltage (peak-to-peak value) input current SHP pulse width
2003 Nov 26
7
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
SYMBOL tW(SHD) PARAMETER SHD pulse width CONDITIONS Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; see Fig.5 code fco(CTH) 0000 0001 0010 0100 1000 1111 th(IN-SHP) th(IN-SHD) CTH input hold time compared see Fig.5 to control pulse SHP CTH input hold time compared see Fig.5 to control pulse SHD - - - - - - - - 8 13 17 23 33 51 3 3 9 MIN. - TYP.
TDA9965
MAX. -
UNIT ns
- - - - - - - -
ns ns ns ns ns ns ns ns
Programmable Gain Amplifier (PGA) output: pin PGAOUT VPGAOUT(p-p) PGA output amplifier dynamic voltage level (peak-to-peak value) PGA output amplifier black level voltage PGA output amplifier output impedance PGA output current drive minimum gain of PGA circuit maximum gain of PGA circuit code C(CLP) = 0 fpix at 10 kHz for minimum and maximum values static code GPGA = 0 code GPGA 767 - 2000 - mV
VPGAOUT(b) ZPGAOUT IPGAOUT GPGA(min) GPGA(max) fpix(max) tW(CLKADC)H
- - - - - 30
1.475 5 - 0 36 - -
- - 1 - - - -
V mA dB dB
Analog-to-Digital Converter (ADC) maximum pixel frequency CLKADC pulse width HIGH Vi(IN) = 1000 mV; transition (99.5%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128; see Fig.5 Vi(IN) = 1000 mV; transition (99.5%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128 rising and falling edges; 10% to 90% with internal regulator MHz ns 12
tW(CLKADC)L
CLKADC pulse width LOW
12
-
-
ns
SRCLKADC Vi(ADCIN)(p-p) Ii(ADCIN) VRB VRT
CLKADC input slew rate ADC input voltage (peak-to-peak value) ADC input current ADC reference voltage bottom ADC reference voltage top
0.5 - -2 - -
- 2 - 1.30 3.65
- - +120 - -
V/ns V A V V
2003 Nov 26
8
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
SYMBOL DNL td(s) PARAMETER differential non linearity sampling delay CONDITIONS ramp input see Fig.5 - - - MIN. - 13 TYP. 0.5
TDA9965
MAX. 0.9 5 -
UNIT LSB ns
Total chain characteristics (CTH + PGA + ADC) td(SHD-CLKADC) delay between SHD and CLKADC Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128; see Fig.5 Vi(IN) = 32 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 767; see Fig.5 GPGA = 0 dB; code fco(CTH) = 0000 GPGA = 30 dB; code fco(CTH) = 0000; note 1 OCCD(max) maximum offset voltage between CCD floating level and CCD dark pixel level equivalent input noise (RMS value) see Fig.11 ns
th(SHD-CLKADC) SHD hold time compared to CLKADC
-
0
-
ns
Ntot(rms)
total noise from CTH input to ADC output (RMS value)
- - -200
0.85 6 -
- - +200
LSB LSB mV
Vn(i)(eq)(rms)
GPGA = 30 dB; code fco(CTH) = 0000; note 1 IOH = -1 mA IOL = 1 mA see Fig.5 VCCO = 5.25 V VCCO = 3 V VCCO = 2.5 V
-
45
-
V
Digital outputs (fpix = 30 MHz; CL = 10 pF) VOH VOL th(o) td(o) HIGH-level output voltage LOW-level output voltage output hold time output delay VCCO - 0.5 - 0 10 - - - 5 - - 20 26 30 - VCCO 0.5 - 25 31 35 - V V ns ns ns ns
Serial interface fSCLK(max) Note 1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB. maximum clock frequency of serial interface MHz
2003 Nov 26
9
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
TDA9965
handbook, full pagewidth
SDATA
SHIFT REGISTER SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 A0 LSB 10 MSB LATCH SELECTION A1
SCLK
SEN
(SD0 to SD9) PGA GAIN LATCHES
(SD0 to SD3)
(SD0 to SD2) EDGE CONTROL LATCHES edge control clocks
(SD0 to SD9) CLAMP ADC LATCHES
FREQUENCY LATCHES
PGA control
frequency control CTH
10-bit LSB ADC clamp
FCE709
Fig.3 Serial interface block diagram.
handbook, full pagewidth
tsu2 MSB th1 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 LSB SD0
SDATA
A1
A0
SD9
SCLK
SEN tsu1 th2 tsu3
MGU158
tsu1 = tsu2 = tsu3 = 4 ns (minimum); th1 = th2 = 4 ns (minimum).
Fig.4 Loading sequence of control DACs input data via the serial interface.
2003 Nov 26
10
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
Table 1 Serial interface programming ADDRESS BITS SDATA BITS SD0 to SD9 A1 0 0 1 1 A0 0 1 0 1 clamp reference of ADC (SD0 to SD9), note 1 cut-off frequency of CTH (SD0 to SD3) PGA gain control (SD0 to SD9)
TDA9965
edge control for pulses SHP, SHD, CLPOB, CLPADC and CLKADC (note 2): SD0 = 1, SHP and SHD sample on LOW level SD1 = 1, CLPADC and CLPOB activated on HIGH level SD2 = 1, CLKADC activated with rising edge
Notes 1. PGA gain register must always be refreshed after clamp code register content has been changed. 2. When pin CLPADC = HIGH (SD1 = 1; serial interface), the ADC input is clamped to the voltage level of Vref. Pin Vref is connected to ground via a capacitor. When the power supplies increase from zero to VCC, the init-on-power block initializes the circuit as follows: * Cut-off frequency of the CTH circuit is set to: code fco(CTH) = 0 * PGA gain control is set to: code GPGA = 0 * Clamp code of the ADC is set to: code ADCCLP = 0 * SHP and SHD sample on HIGH level; CLKADC activated with rising edge * CLPOB and CLPADC activated on HIGH level. Table 2 Standby selection PIN STDBY HIGH LOW Note 1. In case an external regulator is used, it has to be switched off in standby mode in order to avoid an extra power consumption of the TDA9965. DATA BITS SD9 to SD0 logic 0 active ICCA + ICCD 4 mA (typical); note 1 84 mA (typical)
2003 Nov 26
11
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
TDA9965
handbook, full pagewidth
IN from CCD
N
N+1
N+2
N+3
th(IN-SHP) tW(SHP) SHP 0.8 V th(IN-SHD) tW(SHD) SHD 0.8 V 2.0 V 2.0 V
ADCIN
N-1
N
N+1
N+2
td(SHD-CLKADC) tW(CLKADC)H CLKADC 50% td(s) th(o)
th(SHD-CLKADC) 2.0 V 0.8 V td(o) 90%
DATA
N-3
N-2
N-1
N 10%
MGU389
The polarities used in this case are: - SHP and SHD sample on HIGH level - CLKADC activated with rising edge.
Fig.5 Pixel frequency timing diagram.
2003 Nov 26
12
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
TDA9965
handbook, full pagewidth
1 pixel
1 pixel
PGAOUT
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBLACK
DUMMY
VIDEO
CLPOB WINDOW CLPOB (active HIGH) CLPADC WINDOW CLPADC (active HIGH)
MGU861
CLPADC WINDOW
Fig.6 Line frequency timing diagram.
FCE775
handbook, halfpage
48
handbook, halfpage
300
FCE758
GPGA (dB) 36
BW (MHz)
200
24
100 12
0 0 256 512 768 1024 PGA control DAC input code
0 0000
0010
0100
1000 1111 CTH control code
Fig.7
PGA gain as a function of PGA control DAC input code.
Fig.8
CTH bandwidth as a function of CTH control code.
2003 Nov 26
13
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
TDA9965
handbook,I halfpage
FCE689
(A)
handbook,I halfpage
(A)
400
600
50
0 2.4 - 600 70 mV
MCE191
V (V)
0 -50
VO - 64 LSB
VO
VO + 64 LSB
(1)
V (V)
-400
(1) VO depends on the clamp code.
Fig.9
Typical clamp current as a function of voltage on pin STGE.
Fig.10 Typical clamp current as a function of voltage on pin Vref.
handbook, halfpage
+200 mV
-200 mV
FCE688
Fig.11 Maximum offset voltage between CCD floating and dark pixel level.
2003 Nov 26
14
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
APPLICATION DIAGRAM
TDA9965
handbook, full pagewidth
5.0 V
from timing generator
5.0 V
(2)
(2)
CLPADC
DGND2
CLKADC
DGND1
VCCD2
CLPOB
VCCD1
SHD
SHP
STDBY
D11 38
AGND4 CCD 33 pF 47 nF
(3)
48 1 2 3 4 5 6
47
46
45
44
43
42
41
40
39
IN AGND5 STGE AGND1
(2)
D10 37 D9 36 35 34 33 32 31 D8 D7 D6 VCCO2 OGND2 VCCO1 OGND1 D5 D4 D3 D2
(2) (2)
5.0 V
(2)
VCCA1 AGND2
TDA9965
7 8 9 10 11 12 13 REGEN 14 VRB 15 VRT 16 DEC 17 REF32 18 VCCA3 19 AGND3 20 SEN 21 SCLK 22 SDATA 23 D0 30 29 28 27 26 25 24 D1
5.0 V
(3)
VCCA2 Vref
100 nF PGAOUT
(1)
ADCIN n.c.
1 nF 1 nF 2.2 nF
1 F
(2)
5.0 V
serial interface
MGU195
(1) The clamp level of the signal input at pin ADCIN can be tuned from code 0 to code 1023 in one LSB step of the ADC via the serial interface (clamp ADC activated). (2) All supply pins must be decoupled with 100 nF capacitors as closely as possible to the device. (3) The capacitors on pins STGE and Vref have typical values, performing a typical device start-up time of 300 s from standby to active (supplies on).
Fig.12 Application diagram.
2003 Nov 26
15
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
TDA9965
handbook, full pagewidth
5.0 V
from timing generator
5.0 V
(2)
(2)
CLPADC
DGND2
CLKADC
DGND1
VCCD2
CLPOB
VCCD1
SHD
SHP
STDBY
D11
38
AGND4 CCD1 33 pF 47 nF
(3)
48 1 2 3 4 5 6
47
46
45
44
43
42
41
40
39
IN AGND5 STGE AGND1
(2)
D10
37 D9 36 35 34 33 32 31 D8 D7 D6 VCCO2 OGND2 VCCO1 OGND1 D5 D4 D3 D2
(2) (2)
5.0 V
(2)
VCCA1 AGND2
TDA9965
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 30 29 28 27 26 25 24
5.0 V
(3)
VCCA2 Vref
100 nF PGAOUT
(1)
ADCIN n.c.
REGEN
VRB
VRT
REF32
AGND3
SCLK
SEN
D0 D11
38
1 nF
1 nF 2.2 nF
1 F
VCCA3
(2)
5.0 V
serial interface
5.0 V
from timing generator
5.0 V
(2)
(2)
CLPADC
DGND2
CLKADC
DGND1
VCCD2
CLPOB
VCCD1
SHD
SHP
STDBY
SDATA
DEC
AGND4 CCD2 33 pF 47 nF
(3)
48 1 2 3 4 5 6
47
46
45
44
43
42
41
40
39
IN AGND5 STGE AGND1
(2)
D10
37 D9 36 35 34 33 32 31 D8 D7 D6 VCCO2 OGND2 VCCO1 OGND1 D5 D4 D3 D2
(2) (2)
5.0 V
(2)
VCCA1 AGND2
TDA9965
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 30 29 28 27 26 25 24
5.0 V
(3)
VCCA2 Vref
100 nF PGAOUT
(1)
ADCIN n.c.
VRB
VRT
REGEN
REF32
AGND3
SCLK
SEN
D0
2.2 nF
(2)
VCCA3
5.0 V 1 nF 1 nF 1 F
serial interface
SDATA
DEC
D1
D1
For notes (1), (2) and (3) see Fig.12
FCE825
Fig.13 Application diagram with 2 CCDs.
2003 Nov 26
16
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
Power and grounding recommendations Care must be taken to minimize noise when designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as classical operational amplifiers) must be taken into account, particularly with respect to power and ground connections. The connections between CCD interface and CTH input should be as short as possible and a ground ring protection around these connections can be beneficial. Separate analog and digital supplies provide the best performance. If it is not possible to do this on the board, then decouple the analog supply pins effectively from the
TDA9965
digital supply pins. The decoupling capacitors must be placed as close as possible to the IC package. In a two-ground system, in order to minimize the noise from package and die parasitics, the following recommendations must be implemented: * The ground pin associated with the digital outputs must be connected to the digital ground plane and special care should be taken to avoid feedthrough in the analog ground plane. The analog and digital ground planes must be connected with an inductor as close as possible to the IC package, in order to have the same DC voltage on the ground planes. * The digital output pins and their associated lines should be shielded by the digital ground plane, which can be used as return path for the digital signals.
2003 Nov 26
17
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
TDA9965
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
ISSUE DATE 00-01-19 03-02-25
2003 Nov 26
18
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2003 Nov 26 19
TDA9965
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP PMFP(8) Notes not suitable not suitable(4)
TDA9965
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable
suitable not not recommended(5)(6) recommended(7)
not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Hot bar or manual soldering is suitable for PMFP packages.
2003 Nov 26
20
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
TDA9965
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 Nov 26
21
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R78/06/pp22
Date of release: 2003
Nov 26
Document order number:
9397 750 12251

▲Up To Search▲

Price & Availability of TDA9965

	To Download TDA9965 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .