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IMPORTANT: See the document titled, PCI 9056 Blue Book Revision 0.91 Correction, before designing to this Blue Book. That correction document includes details on features omitted from this Blue Book and it corrects incorrect information in this Blue Book. Please download the correction document from http://www.plxtech.com/products/9056/ or contact your local PLX Sales Representative for a hard copy.
PLX Technology, Inc. 870 Maude Avenue, Sunnyvale, CA USA 94085
Tel: 408 774-9060 Fax: 408 774-2169
CONFIDENTIAL & PROPRIETARY PRELIMINARY INFORMATION PCI 9056 Data Book
The enclosed specification is the confidential, proprietary, and copyrighted intellectual property of PLX Technology, Inc. This item may not be transferred from the custody or control of PLX Technology, Inc. except as authorized by PLX Technology, Inc. and only then by way of loan for limited purposes. This document may not be reproduced in whole or part and must be returned to PLX Technology, Inc. upon request and in all events upon completion of the purpose of the loan. Neither this item nor the information it contains may be used by or disclosed to persons not having a need for such use or disclosure consistent with the purpose of the loan without prior written consent of PLX Technology, Inc.
Document #: Issued To: Name: Company: Date: Authorized: PCI 9056 -
x
PCI 9056 Data Book
Preliminary Information
PCI 9056 Data Book
Version 0.91b
February 2002
Website: Email: Phone: Fax:
http://www.plxtech.com 9056@plxtech.com 408 774-9060 800 759-3735 408 774-2169
Preliminary Information
(c) 2002 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology, the PLX logo, and Data Pipe Architecture are registered trademarks of PLX Technology, Inc. Other brands and names are the property of their respective owners. Order Number: 9056-SIL-DB-P1-0.91b Printed in the USA, February 2002
Preliminary Information
Contents
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv
Supplemental Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvi Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvi
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1. Company and Product Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2. Data Pipe Architecture Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2.1. High-Speed Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2.1.1. Direct Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2.1.1.1. Direct Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2.1.1.2. Direct Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1.2. DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1.2.1. Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1.2.2. Scatter/Gather Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1.2.3. Hardware DMA Controls--EOT and Demand Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.2. Intelligent Messaging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3. PCI 9056 I/O Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3.1. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3.1.1. High-Performance Motorola MPC850/MPC860 PowerQUICC Designs . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3.1.2. High-Performance CompactPCI Adapter Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3.1.3. High-Performance PC Adapter Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3.1.4. High-Performance Embedded Host Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4. PCI 9056 Major Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.1. Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.2. Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.3. Messaging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.4. Hosting Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.5. Electrical/Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.6. Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.5. Compatibility with Other PLX Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.5.1. Pin Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.5.2. Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.5.3. PCI 9056 Comparison with Other PLX Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
v
Contents
2. M Mode Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1. PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1. Direct Slave Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2. PCI Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2.1. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2.2. Direct Master Local-to-PCI Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.3. PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2. Local Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1. Local Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.2. Direct Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.3. Direct Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.4. Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.4.1. Wait States--Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.4.2. Wait States--PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5. Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5.1. Burst and Bterm Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5.2. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.5.2.1. Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.5.3. Partial Lword Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.6. Local Bus Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.7. Local Bus Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.8. Direct Slave Accesses to 8- or 16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.9. Local Bus Data Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3. Big Endian/Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.1. PCI Bus Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.2. Local Bus Big/Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.2.1. 32-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2.2. 16-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2.3. 8-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.2.4. Local Bus Big/Little Endian Mode Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.1. Vendor and Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.1.1. Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4.1.2. Local Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4.2. Serial EEPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4.2.1. Long Serial EEPROM Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.2.2. Extra Long Serial EEPROM Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4.2.3. New Capabilities Function Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4.2.4. Recommended Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4.3. Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4.3.1. PCI Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4.3.2. Local Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4.4. Serial EEPROM and Configuration Initialization Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
3. M Mode Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1. Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1. Adapter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1.1. PCI Bus Input RST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1.2. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1.3. Power Management Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2. Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.1. PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.2. Local LRESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.3. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.4. Power Management Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1
vi
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Contents
3.2. PCI 9056 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.4. Direct Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.4.1. Direct Master Operation (Local Master-to-Direct Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.4.1.1. Direct Master Memory and I/O Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4.1.2. Direct Master FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4.1.3. Direct Master Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.1.4. Direct Master I/O Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.1.5. Direct Master I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.1.6. Direct Master Delayed Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.1.7. Direct Master Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.1.8. RETRY# Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1.8.1. Direct Master Write FIFO Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1.8.2. Direct Master Delayed Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1.9. Direct Master Configuration (PCI Configuration Type 0 or Type 1 Cycles) . . . . . . . . . . . . . . . . . . . 3-6 3.4.1.9.1. Direct Master Configuration Cycle Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1.10. Direct Master PCI Dual Address Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1.11. PCI Master/Target Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.1.12. Direct Master Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.2. IDMA/SDMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.2.1. IDMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.2.2. SDMA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.3. Direct Slave Operation (PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.3.1. Direct Slave Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3.2. Direct Slave Delayed Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3.3. Direct Slave Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.3.4. Direct Slave Delayed Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.3.5. Direct Slave Local Bus TA# Timeout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.3.6. Direct Slave Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.3.7. Direct Slave PCI-to-Local Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4.3.7.1. Direct Slave Local Bus Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4.3.7.2. Direct Slave PCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.4.3.7.3. Direct Slave Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.3.7.3.1. Direct Slave Transfer Size Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.3.8. Direct Slave Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.4. Deadlock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.4.1. Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.4.4.1.1. Software/Hardware Solution for Systems without Backoff Capability . . . . . . . . . . . . . . . . . . . 3-17 3.4.4.1.2. Preempt Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.4.4.2. Software Solutions to Deadlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5. DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5.1. DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.5.2. Block DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.5.2.1. Block DMA PCI Dual Address Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.3. Scatter/Gather DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.3.1. Scatter/Gather DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.3.2. DMA Clear Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.3.3. DMA Descriptor Ring Management (Valid Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.4. DMA Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.4.1. DMA Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.5. DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.6. DMA Channel 0 and Channel 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.7. DMA Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.7.1. Local-to-PCI Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.5.7.2. PCI-to-Local Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.5.7.3. DMA Local Bus Error Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.5.7.4. DMA Unaligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.5.8. Demand Mode DMA, Channel 0 and Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.5.9. End of Transfer (EOT#) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
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3.5.10. DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.11. Local Bus Latency and Pause Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6. M Mode Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1. M Mode Direct Master Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2. M Mode Direct Slave Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3. M Mode DMA Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-29 3-29 3-30 3-30 3-38 3-52
4. C and J Modes Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1. PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1. Direct Slave Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2. PCI Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2.1. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2.2. Direct Master Local-to-PCI Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.3. PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2. Local Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1. Local Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2. Direct Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.3. Direct Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.4. Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.4.1. Wait States--Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.4.2. Wait States--PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.5. Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.5.1. Burst and Bterm Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.5.2. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.5.2.1. Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.5.3. Partial Lword Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.6. Recovery States (J Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.7. Local Bus Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.8. Local Bus Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.9. Direct Slave Accesses to 8- or 16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.10. Local Bus Data Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3. Big Endian/Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.1. PCI Bus Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2. Local Bus Big/Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2.1. 32-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2.2. 16-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.2.3. 8-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.2.4. Local Bus Big/Little Endian Mode Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4.1. Vendor and Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4.1.1. Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4.1.2. Local Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4.2. Serial EEPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4.2.1. Long Serial EEPROM Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.4.2.2. Extra Long Serial EEPROM Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.4.2.3. New Capabilities Function Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.2.4. Recommended Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.3. Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.4.3.1. PCI Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.4.3.2. Local Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.4.4. Serial EEPROM and Configuration Initialization Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
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PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
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5. C and J Modes Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1. Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1. Adapter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1.1. PCI Bus Input RST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1.2. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1.3. Power Management Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2. Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2.1. PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2.2. Local LRESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2.3. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2.4. Power Management Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2. PCI 9056 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4. Direct Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4.1. Direct Master Operation (Local Master-to-Direct Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4.1.1. Direct Master Memory and I/O Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4.1.2. Direct Master FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.1.3. Direct Master Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.1.4. Direct Master I/O Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.1.5. Direct Master I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.1.6. Direct Master Delayed Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.1.7. Direct Master Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.1.8. Direct Master Configuration (PCI Configuration Type 0 or Type 1 Cycles) . . . . . . . . . . . . . . . . . . . 5-6 5.4.1.8.1. Direct Master Configuration Cycle Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.4.1.9. Direct Master PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.4.1.10. PCI Master/Target Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.4.1.11. Direct Master Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4.2. Direct Slave Operation (PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4.2.1. Direct Slave Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.2.2. Direct Slave Delayed Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.2.3. Direct Slave Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.2.4. Direct Slave Delayed Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.2.5. Direct Slave Local Bus READY# Timeout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.2.6. Direct Slave Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.2.7. Direct Slave PCI-to-Local Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.2.7.1. Direct Slave Local Bus Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.2.7.2. Direct Slave PCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.2.7.3. Direct Slave Byte Enables (C Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.2.7.4. Direct Slave Byte Enables (J Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.2.7.4.1. Direct Slave Byte Enables Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.2.8. Direct Slave Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.4.3. Deadlock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.4.3.1. Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4.3.1.1. Software/Hardware Solution for Systems without Backoff Capability . . . . . . . . . . . . . . . . . . . 5-15 5.4.3.1.2. Preempt Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4.3.2. Software Solutions to Deadlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.5. DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.5.1. DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.2. Block DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.2.1. Block DMA PCI Dual Address Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.5.3. Scatter/Gather DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.5.3.1. Scatter/Gather DMA PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.5.3.2. DMA Clear Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.5.3.3. DMA Descriptor Ring Management (Valid Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.4. DMA Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5.4.1. DMA Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5.5. DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5.6. DMA Channel 0 and Channel 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
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5.5.7. DMA Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5.7.1. Local-to-PCI Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.5.7.2. PCI-to-Local Bus DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.5.7.3. DMA Unaligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.5.8. Demand Mode DMA, Channel 0 and Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.5.9. End of Transfer (EOT#) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.5.10. DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.5.11. Local Bus Latency and Pause Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.6. C and J Modes Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.6.1. C Mode Only Direct Master Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5.6.2. C Mode Only Direct Slave Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 5.6.3. C Mode Only DMA Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90 5.6.4. J Mode Only DMA Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
6. PCI/Local Interrupts and User I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1. Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1. PCI Interrupts (INTA#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2. Local Interrupt Input (LINTi#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3. Local Interrupt Output (LINTo#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4. Master/Target Abort Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5. Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6. Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.1. Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.1.1. M Mode Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.1.2. C and J Modes Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6.2. PCI-to-Local Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.7. Built-In Self Test Interrupt (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.8. DMA Channel 0 and Channel 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.9. All Modes PCI SERR# (PCI NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.10. M Mode PCI SERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.11. Local NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.12. M Mode Local TEA# (Local NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.13. C and J Modes Local LSERR# (Local NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2. User Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-1 6-1 6-2 6-2 6-2 6-2 6-3 6-3 6-3 6-3 6-3 6-3 6-4 6-4 6-4 6-4 6-4 6-5
7. Intelligent I/O (I2O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1. I2O-Compatible Message Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1. Inbound Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2. Outbound Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3. I2O Pointer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4. Inbound Free List FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5. Inbound Post Queue FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.6. Outbound Post Queue FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.7. Outbound Post Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.8. Inbound Free Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.9. Outbound Free List FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.10. I2O Enable Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-2 7-3 7-3 7-3 7-4 7-4 7-5 7-5
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Contents
8. PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1. PCI Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2. 66 MHz PCI Clock Power Management D2 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3. Power Management D3cold Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4. System Changes Power Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.5. Non-D3cold Wake-Up Request Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-2 8-2 8-3 8-3
9. CompactPCI Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1. Silicon Behavior during Initialization on PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2. Controlling Connection Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1. Connection Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1.1. Board Slot Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1.2. Board Healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1.3. Platform Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2. Software Connection Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.1. Ejector Switch and Blue LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.2. ENUM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.3. Hot Swap Control/Status Register (HS_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.4. Hot Swap Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9-1 9-2 9-2 9-2 9-2 9-2 9-3 9-3 9-3 9-4 9-4
10. PCI Vital Product Data (VPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1. VPD Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2. VPD Serial EEPROM Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3. Sequential Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4. Random Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-1 10-1 10-1 10-2
11. Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1. Summary of New Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2. Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.1. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.2. Local Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.3. Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.4. DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.2.5. Messaging Queue Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.3. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.4. Local Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11.5. Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.6. DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11.7. Messaging Queue Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44
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Preliminary Information
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Contents
12. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2. Pinout Common to All Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3. M Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12.4. C Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.5. J Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12.6. Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.6.1. IEEE 1149.1 Test Access Port (JTAG Debug Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.6.2. JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.6.3. JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
13. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1. General Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. Local Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3. Local Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
14. Physical Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1. Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2. Ball Grid Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
A. General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1. Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2. United States and International Representatives, and Distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.3. Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1
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Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
FIGURES
PCI 9056 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxviii 1-1. Direct Master Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2. Direct Slave Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-3. High-Performance MPC850 or MPC860 PowerQUICC Adapter Design . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-4. PCI 9056 CompactPCI Peripheral Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-5. PCI 9056 PC Adapter Card with C or J Mode Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-6. PCI 9056 PC Adapter Card with Local PCI I/O and PCI-to-PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1-7. PCI 9056 PC Adapter Card with Local PCI I/O and IOP 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1-8. PCI 9056 Embedded Host System with Generic Host CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1-9. PCI 9056 Embedded Host System with IOP 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 2-1. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2. Big/Little Endian--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-3. Big/Little Endian--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-4. Big/Little Endian--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-5. Serial EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-6. PCI 9056 Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-7. Address Decode Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 3-1. Direct Master Access to the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-2. Direct Master Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-3. Direct Master Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-4. Direct Master Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-5. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-6. Direct Slave Delayed Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-7. Direct Slave Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-8. Direct Slave Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-9. Direct Slave Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-10. Local Bus Direct Slave Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-11. Block DMA Mode Initialization (Single Address or Dual Address PCI) . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3-12. DMA, PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3-13. DMA, Local-to-PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3-14. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3-15. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus) . . . . . . . . . 3-21 3-16. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus) . . . . . . . . . . . 3-21 3-17. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0 and/or DMADAC1) Register Dependent] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3-18. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18] and/or DMAMODE1[18]) Descriptor Dependent (PCI Address High Added)] . . 3-24 3-19. Local-to-PCI Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3-20. PCI-to-Local Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 4-1. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-2. Big/Little Endian--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-3. Big/Little Endian--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-4. Big/Little Endian--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-5. Serial EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-6. PCI 9056 Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
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Preliminary Information
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Figures
4-7. Address Decode Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 5-1. Direct Master Access of the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-2. Direct Master Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-3. Direct Master Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-4. Direct Master Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-5. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5-6. Direct Slave Delayed Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-7. Direct Slave Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5-8. Direct Slave Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5-9. Direct Slave Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5-10. Local Bus Direct Slave Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5-11. Block DMA Mode Initialization (Single Address or Dual Address PCI) . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5-12. DMA, PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5-13. DMA, Local-to-PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5-14. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5-15. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus) . . . . . . . . . 5-19 5-16. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus) . . . . . . . . . . . 5-19 5-17. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0 and/or DMADAC1) Register Dependent] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5-18. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18] and/or DMAMODE1[18]) Descriptor Dependent] (PCI Address High Added) . . 5-21 5-19. Local-to-PCI Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5-20. PCI-to-Local Bus DMA Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 6-1. Interrupt and Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-2. Mailbox and Doorbell Message Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 7-1. Typical I2O Server/Adapter Card Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2. Driver Architecture Compared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-3. I2O Circular FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 9-1. Redirection of BD_SEL# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9-2. Board Healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9-3. PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 13-1. PCI 9056 Local Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13-2. PCI 9056 Local Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13-3. PCI 9056 ALE Output Delay to the Local Clock at 33 MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 14-1. Mechanical Dimensions--Top, Side, and Bottom Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14-2. Ball Grid Assignments (A1-A8 through T1-T8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14-3. Ball Grid Assignments (A9-A16 through T9-T16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
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Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
TABLES
Data Assignment Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi Supplemental Documentation Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi 1-1. Local Bus Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1-2. FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1-3. Bus Master I/O Accelerator PLX Product Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 2-1. Direct Slave Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-3. Local-to-PCI Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-4. Local-to-PCI I/O Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-5. Local-to-PCI Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-6. Local Bus Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-7. Burst and Bterm on the Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-8. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-9. PCI Bus Little Endian Byte Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-10. Byte Number and Lane Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-11. Big/Little Endian Program Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-12. Cycle Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-13. Upper Lword Lane Transfer--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-14. Upper Word Lane Transfer--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-15. Lower Word Lane Transfer--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-16. Upper Byte Lane Transfer--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-17. Lower Byte Lane Transfer--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-18. Serial EEPROM Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2-19. Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-20. Extra Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-21. New Capabilities Function Support Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 3-1. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2. Direct Slave Burst Mode Cycle Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-3. Data Bus TSIZ[0:1] Contents for Single Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-4. Data Bus TSIZ[0:1] Requirements for Single Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-5. DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3-6. Normal DMA with EOT Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3-7. Demand Mode DMA, Channel 0 and Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3-8. Any DMA Transfer Channel 0 and Channel 1 with EOT Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 4-1. Direct Slave Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-3. Local-to-PCI Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-4. Local-to-PCI I/O Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-5. Local-to-PCI Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-6. Local Bus Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-7. Burst and Bterm on the Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-8. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-9. PCI Bus Little Endian Byte Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-10. Byte Number and Lane Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-11. Big/Little Endian Program Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
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Preliminary Information
xv
Tables
4-12. Cycle Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-13. Upper Lword Lane Transfer--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-14. Upper Word Lane Transfer--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-15. Lower Word Lane Transfer--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-16. Upper Byte Lane Transfer--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-17. Lower Byte Lane Transfer--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-18. Serial EEPROM Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-19. Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-20. Extra Long Serial EEPROM Load Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-21. New Capabilities Function Support Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 5-1. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-2. DMA Local Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 7-1. Queue Starting Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7-2. Circular FIFO Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 9-1. Hot Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 11-1. Summary of New Registers (as Compared to the PCI 9054) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-2. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11-3. Local Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11-4. Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-5. DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11-6. Messaging Queue Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 12-1. Pins with Internal Pull-Up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2. Pins with No Internal Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-3. Pin Type Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-4. PCI System Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12-5. JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12-6. CompactPCI Hot Swap Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12-7. System Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-8. Serial EEPROM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-9. Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12-10. M Mode Local Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12-11. C Mode Local Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12-12. J Mode Local Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12-13. JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12-14. JTAG Infrared Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 13-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-2. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-3. Capacitance (Sample Tested Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-4. Package Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-5. Electrical Characteristics over Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13-6. AC Electrical Characteristics (Local Inputs) over Operating Range (M Mode) . . . . . . . . . . . . . . . . . . 13-4 13-7. AC Electrical Characteristics (Local Inputs) over Operating Range (C and J Modes) . . . . . . . . . . . . 13-5 13-8. AC Electrical Characteristics (Local Outputs) over Operating Range (M Mode) . . . . . . . . . . . . . . . . 13-6 13-9. AC Electrical Characteristics (Local Outputs) over Operating Range (C and J Modes) . . . . . . . . . . . 13-7 A-1. Available Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
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Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
REGISTERS
9-1. Hot Swap Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 10-1. VPD Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 11-1. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-2. (PCICR; PCI:04h, LOC:04h) PCI Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-3. (PCISR; PCI:06h, LOC:06h) PCI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-4. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-5. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-6. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-7. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Bus Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-8. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-9. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11-10. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime, and DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11-11. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-12. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-13. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-14. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-15. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-16. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-17. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-18. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-19. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-20. (CAP_PTR; PCI:34h, LOC:34h) New Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-21. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-22. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-23. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11-24. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11-25. (PMCAPID; PCI:40h, LOC:180h) Power Management Capability ID . . . . . . . . . . . . . . . . . . . . . . . 11-15 11-26. (PMNEXT; PCI:41h, LOC:181h) Power Management Next Capability Pointer . . . . . . . . . . . . . . . 11-15 11-27. (PMC; PCI:42h, LOC:182h) Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11-28. (PMCSR; PCI:44h, LOC:184h) Power Management Control/Status . . . . . . . . . . . . . . . . . . . . . . . 11-17 11-29. (PMCSR_BSE; PCI:46h, LOC:186h) PMCSR Bridge Support Extensions . . . . . . . . . . . . . . . . . . 11-17 11-30. (PMDATA; PCI:47h, LOC:187h) Power Management Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-31. (HS_CNTL; PCI:48h, LOC:188h) Hot Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-32. (HS_NEXT; PCI:49h, LOC:189h) Hot Swap Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-33. (HS_CSR; PCI:4Ah, LOC:18Ah) Hot Swap Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-34. (PVPDCNTL; PCI:4Ch, LOC:18Ch) PCI Vital Product Data Control . . . . . . . . . . . . . . . . . . . . . . . 11-19 11-35. (PVPD_NEXT; PCI:4Dh, LOC:18Dh) PCI Vital Product Data Next Capability Pointer. . . . . . . . . . 11-19 11-36. (PVPDAD; PCI:4Eh, LOC:18Eh) PCI Vital Product Data Address . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11-37. (PVPDATA; PCI:50h, LOC:190h) PCI VPD Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11-38. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus . . . 11-20 11-39. (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) . . . . . . . . . 11-20 11-40. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/DMA Arbitration. . . . . . . . . . . . . . . . . . . . . . 11-21
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
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Registers
11-41. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11-42. (LMISC1; PCI:0Dh, LOC:8Dh) Local Miscellaneous Control1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11-43. (PROT_AREA; PCI:0Eh, LOC:8Eh) Serial EEPROM Write-Protected Address Boundary . . . . . . 11-23 11-44. (LMISC2; PCI:0Fh, LOC:8Fh) Local Miscellaneous Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11-45. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11-46. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) and BREQo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11-47. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11-48. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master-to-PCI . . . . . . . . . . . . . . . 11-26 11-49. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master-to-PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11-50. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master-to-PCI I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11-51. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master-to-PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11-52. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11-53. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus . . 11-29 11-54. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) . . . . . . . . 11-29 11-55. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor . . . . . . . . . . . . . . . 11-30 11-56. (DMDAC; PCI:FCh, LOC:17Ch) Direct Master PCI Dual Address Cycle Upper Address . . . . . . . 11-30 11-57. (PCIARB; PCI:100h, LOC:1A0h) PCI Arbiter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11-58. (PABTADR; PCI:104h, LOC:1A4h) PCI Abort Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11-59. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11-60. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11-61. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11-62. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11-63. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11-64. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-65. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-66. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-67. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-68. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-69. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 11-70. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control, and Init Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 11-71. (PCIHIDR; PCI:70h, LOC:F0h) PCI Hardwired Configuration ID . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11-72. (PCIHREV; PCI:74h, LOC:F4h) PCI Hardwired Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11-73. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11-74. (DMAPADR0; (PCI:84h, LOC:104h when DMAMODE0[20]=0 or PCI:88h, LOC:108h when DMAMODE0[20]=1) DMA Channel 0 PCI Address . . . . . . . . . . . . 11-38 11-75. (DMALADR0; PCI:88h, LOC:108h when DMAMODE0[20]=0 or PCI:8Ch, LOC:10Ch when DMAMODE0[20]=1) DMA Channel 0 Local Address . . . . . . . . . . 11-38 11-76. (DMASIZ0; PCI:8Ch, LOC:10Ch when DMAMODE0[20]=0 or PCI:84h, LOC:104h when DMAMODE0[20]=1) DMA Channel 0 Transfer Size (Bytes) . . . . . 11-39 11-77. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer . . . . . . . . . . . . . . . . . . . . . 11-39 11-78. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
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PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Registers
11-79. (DMAPADR1;PCI:98h, LOC:118h when DMAMODE1[20]=0 or PCI:9Ch, LOC:11Ch when DMAMODE1[20]=1) DMA Channel 1 PCI Address. . . . . . . . . . . . 11-41 11-80. (DMALADR1;PCI:9Ch, LOC:11Ch when DMAMODE1[20]=0 or PCI:A0h, LOC:120h when DMAMODE1[20]=1) DMA Channel 1 Local Address. . . . . . . . . . . 11-41 11-81. (DMASIZ1; PCI:A0h, LOC:120h when DMAMODE1[20]=0 or PCI:98h, LOC:118h when DMAMODE1[20]=1) DMA Channel 1 Transfer Size (Bytes) . . . . . 11-41 11-82. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer . . . . . . . . . . . . . . . . . . . . . 11-41 11-83. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status. . . . . . . . . . . . . . . . . . . . . . 11-42 11-84. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status. . . . . . . . . . . . . . . . . . . . . . 11-42 11-85. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-86. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11-87. (DMADAC0; PCI:B4h, LOC:134h) DMA Channel 0 PCI Dual Address Cycle Upper Address . . . . 11-43 11-88. (DMADAC1; PCI:B8h, LOC:138h) DMA Channel 1 PCI Dual Address Cycle Upper Address . . . . 11-43 11-89. (OPQIS; PCI:30h, LOC:B0h) Outbound Post Queue Interrupt Status . . . . . . . . . . . . . . . . . . . . . . 11-44 11-90. (OPQIM; PCI:34h, LOC:B4h) Outbound Post Queue Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . 11-44 11-91. (IQP; PCI:40h) Inbound Queue Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11-92. (OQP; PCI:44h) Outbound Queue Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11-93. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11-94. (QBAR; PCI:C4h, LOC:144h) Queue Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11-95. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11-96. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11-97. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11-98. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11-99. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11-100. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11-101. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11-102. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11-103. (QSR; PCI:E8h, LOC:168h) Queue Status/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
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Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
TIMING DIAGRAMS
2-1. Initialization from Serial EEPROM (2K or 4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2-2. Local Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2-3. PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2-4. PCI Configuration Read to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2-5. Local Configuration Write to Configuration Register (M Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2-6. Local Configuration Read from Configuration Register (M Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 3-1. Direct Master Single Write to PCI Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 3-2. Direct Master Single Read from PCI Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3-3. Direct Master Single Write to PCI I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3-4. Direct Master Single Read from PCI I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3-5. Direct Master Burst Write to PCI Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3-6. Direct Master Burst Read from PCI Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3-7. Direct Master Burst Write with a Retry on PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 3-8. Direct Master Burst Read with a Retry on Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3-9. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Write . . . . . . . . . . . . . . . . . . . . . . . 3-38 3-10. Direct Slave Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3-11. Direct Slave Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3-12. Direct Slave Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3-13. Direct Slave Delay Burst Read 3-14. Direct Slave Single Read Ahead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3-15. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read Ahead Enabled . . . . . . . . . . 3-44 3-16. Direct Slave Burst Write and Read with Timer 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3-17. Direct Slave from PCI Bus to 32-Bit Device on Local Bus; Local Bus Latency and Pause Timers Set to 23 to Test LHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3-18. PCI Parity Error (Address Phase), SERR# Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3-19. PCI Parity PERR# Direct Slave Write Interrupts, First Data Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3-20. PCI Parity PERR# on Direct Slave Read Interrupts, First Data, DP0 . . . . . . . . . . . . . . . . . . . . . . . . 3-49 3-21. Direct Slave Burst Write 4 Data, Big Endian, Upper Bytes [31:24] . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 3-22. Direct Slave Burst Read 7, Big Endian, Lower Bytes [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 3-23. DMA Channel 0 Local-to-PCI (Memory Write Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 3-24. DMA Channel 0 PCI-to-Local (Memory Read Line Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53 3-25. DMA Channel 0 PCI-to-Local (Memory Read Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54 3-26. DMA Channel 1 PCI-to-Local (Memory Read Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 4-1. Initialization from Serial EEPROM (2K or 4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-2. Local Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4-3. PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4-4. PCI Configuration Read to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4-5. Local Configuration Write to Configuration Register (C Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4-6. Local Configuration Read from Configuration Register (C Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4-7. Local Configuration Write to Configuration Register (J Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4-8. Local Configuration Read from Configuration Register (J Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 5-1. Direct Master Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5-2. Direct Master Single Write and Single Read to PCI Memory and I/O Space 5-3. Direct Master Single Write and Single Read to and from PCI I/O Space 5-4. Direct Master Burst Write to PCI Memory Space . . . . . . . . . . . . . . . . . . . 5-27 . . . . . . . . . . . . . . . . . . . . . . 5-28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
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Timing Diagrams
5-5. TD-092.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5-6. Direct Master Burst Read from PCI Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5-7. TD-096.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5-8. Direct Master Burst Write to PCI I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5-9. Direct Master Burst Read from PCI I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5-10. Direct Master Burst Write with a Retry on PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5-11. Direct Master Burst Write followed by Direct Master Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5-12. Direct Master Memory Write of Four Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5-13. Direct Master Memory Read of Four Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5-14. Direct Master I/O Write of Four Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5-15. Direct Master I/O Read of Four Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5-16. Direct Master Single I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5-17. Direct Master Single I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5-18. Direct Master Memory Read of Four Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 5-19. Direct Master Memory Write of Six Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 5-20. Direct Master Memory Write of Seven Lwords 5-22. Direct Master Memory Write of Eight Lwords 5-24. Direct Master Memory Write of 12 Lwords 5-26. Direct Master Memory Write of 32 Lwords 5-28. Direct Master Memory Write of 40 Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5-21. Direct Master Memory Read of Seven Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 5-23. Direct Master Memory Read of Eight Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 5-25. Direct Master Memory Read of 12 Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 5-27. Direct Master Memory Read of 32 Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 5-29. Direct Master Single Read by Direct Master Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 5-30. Direct Master Burst Read with a PCI Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5-31. Direct Master Burst Write Four Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 5-32. Direct Master Burst Read Four Lwords from I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 5-33. Direct Master MWI 7, Transfer Eight Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5-34. Direct Master MWI 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5-35. TD-023.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5-36. Direct Master MWI 8, Transfer 16 Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 5-37. Direct Master MWI 16, Transfer Eight Lwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 5-38. Set Direct Master Write Mode to 8 for Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 5-39. Set Direct Master Write Mode to 8 for Write and Invalidate (Direct Master MWI 8) . . . . . . . . . . . . . 5-61 5-40. TD-028.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61 5-41. Set Direct Master Write Mode to 16 for Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5-42. TD-034.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5-43. Direct Master Single Write Read Memory, LBE = 1110b 5-44. Direct Master Single Write Read Memory, LBE = 1100b 5-45. Direct Master Single Write Read Memory, LBE = 1000b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
5-46. Direct Master Memory Single Write Read Big Endian, LBE = 0111b . . . . . . . . . . . . . . . . . . . . . . . . 5-66 5-47. Direct Master Memory Single Write Read Big Endian, LBE = 0011b . . . . . . . . . . . . . . . . . . . . . . . . 5-67 5-48. Direct Master Single Write Read Memory Big Endian Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5-49. TD-041.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5-50. Direct Master I/O Single Write Read Big Endian, LBE = 1110b . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69
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Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
5-51. TD-045.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 5-52. Direct Master Memory Read Programmable Command Code, CBE = 1100, 1110 . . . . . . . . . . . . . 5-70 5-53. TD-047.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70 5-54. Direct Master Memory Write Programmable Command Code, CBE = 1111 . . . . . . . . . . . . . . . . . . . 5-71 5-55. Direct Master Type 0, Configuration Device 2, Address 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 5-56. TD-050tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 5-57. Direct Master Type 1, Configuration Device 2, Address 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 5-58. TD-052.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 5-59. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, BREQ Enabled . . . . . . . . . . . . . . . . . . . 5-74 5-60. TD-054.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 5-61. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Read No Write Enabled . . . . . . . 5-75 5-62. TD-056.tif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75 5-63. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read No Write Enabled . . . . . . . . 5-76 5-64. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Read Write Flush Enabled . . . . . 5-77 5-65. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read Write Flush Enabled . . . . . . 5-78 5-66. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Delay Read Enabled . . . . . . . . . . . . . . . 5-79 5-67. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Read Ahead Enabled . . . . . . . . . 5-80 5-68. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read Ahead Enabled . . . . . . . . . . 5-81 5-69. Direct Slave Burst Read with Prefetch Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82 5-70. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Local Timer 8 Expired . . . . . . . . . . . . . . 5-83 5-71. PCI Memory Write with Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84 5-72. Direct Slave Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85 5-73. Direct Slave Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86 5-74. Direct Slave Burst 20 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87 5-75. Direct Slave Burst 20 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-88 5-76. Direct Slave Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89 5-77. DMA Channel 0 Local-to-PCI (Memory Write Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90 5-78. DMA Channel 0 PCI-to-Local (Memory Read Line Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91 5-79. DMA Channel 0 PCI-to-Local (Memory Read Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92 5-80. DMA Channel 1 PCI-to-Local (Memory Read Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93 5-81. DMA Channel 0 Local-to-PCI (Memory Write Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94 5-82. DMA Channel 0 PCI-to-Local (Memory Read Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95 5-83. DMA Channel 0 PCI-to-Local (Memory Read Line Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
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xxiv
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PREFACE
The information contained in this document is subject to change without notice. Although an effort has been made to keep the information accurate, there may be misleading or even incorrect statements made herein.
SUPPLEMENTAL DOCUMENTATION
The following is a list of additional documentation to provide the reader with further information: * PCI Local Bus Specification, Revision 2.1, PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PCI Local Bus Specification, Revision 2.2, December 18, 1998 PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PCI Hot-Plug Specification, Revision 1.0 PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PCI Bus Power Management Interface Specification, Revision 1.1, December 18, 1998 PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PICMG 2.1, R2.0, Hot Swap Specification, January 2001 PCI Industrial Computer Manufacturers Group (PICMG) c/o Virtual Inc., 401 Edgewater Place, Suite 500, Wakefield, MA 01880, USA Tel: 781 224-1100, Fax: 781 224-1239, http://www.picmg.org * Intelligent I/O (I2O) Architecture Specification, Revision 1.5, 1997 I2O Special Interest Group (I2O SIG) 404 Balboa Street, San Francisco, CA 94118, USA Tel: 415 750-8352, Fax: 415 751-4829, http://www.i2osig.org * IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 The Institute of Electrical and Electronics Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394, USA Tel: 732 562-3800, Fax: 732 562-1571, http://www.ieee.org
Note: In the text of this data book, shortened titles are given to the works listed above. The following table lists these abbreviations.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
xxv
Preface
Supplemental Documentation Abbreviations
Abbreviation PCI r2.1 PCI r2.2 Hot-Plug r1.0 PCI Power Mgmt. r1.1 PICMG 2.1, R2.0 I2O r1.5 IEEE Standard 1149.1-1990 PCI Local Bus Specification, Revision 2.1 PCI Local Bus Specification, Revision 2.2 PCI Hot-Plug Specification, Revision 1.0 PCI Bus Power Management Interface Specification, Revision 1.1 PICMG 2.1, R2.0, CompactPCI Hot Swap Specification Intelligent I/O (I2O) Architecture Specification, Revision 1.5 IEEE Standard Test Access Port and Boundary-Scan Architecture Document
TERMS AND DEFINITIONS
* Direct Master External Local Bus Master initiates Data write/read to/from the PCI Bus * Direct Slave External PCI Bus Master initiates Data write/read to/from the Local Bus
Data Assignment Conventions
Data Width 1 byte (8 bits) 2 bytes (16 bits) 4 bytes (32 bits) 8 bytes (64 bits) PCI 9056 Convention Byte Word Lword Qword
REVISION HISTORY
Date
01/2000 12/2000 01/2001 02/2002 02/2002
Revision
0.11 0.90 0.91 0.91a 0.91b Initial release Red Book. Initial release Blue Book.
Comments
Blue Book update. Incorporate PICMG 2.1, R2.0 Hot Swap Silicon. Blue Book update. Only affected pages list the revision and date change. Blue Book update. Only affected pages list the revision and date change. Revised pages 2-8, 2-9, 4-8--4-10, 11-3, 11-31, 12-1, 13-2, and 13-3. For corrections to the content on the listed pages, refer to the document, PCI 9056 Blue Book Revision 0.91 Correction.
xxviii
Preliminary Information
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
PCI 9056
32-Bit, 66 MHz PCI Bus Mastering I/O Accelerator
February 2002 Version 0.91b for PowerQUICC and Generic 32-Bit, 66 MHz Local Bus Designs
FEATURE SUMMARY
* PCI Bus Mastering I/O Accelerator between a 32-bit, 66 MHz PCI Bus and 32-bit, 66 MHz processor Local Bus * PCI r2.2-compliant * Supports Vital Product Data (VPD) * Supports PCI Power Management r1.1, including D3cold PME generation for PC 2001 modem and network communications adapter compliance PICMG 2.1, R2.0, Hot Swap Silicon * Programming Interface 0 (PI = 0) * BIAS Voltage Support * Early Power Support * Initially Not Respond Support PCI Hot-Plug Specification, Revision 1.0-compatible Direct connection to three processor Local Bus types * M Mode--Motorola MPC850, MPC860, PowerPC 801 * C Mode (non-multiplexed address/data)-- Intel i960, DSPs, custom ASICs and FPGAs, and others * J Mode (multiplexed address/data)-- Intel i960, IBM PowerPC 401, DSPs, PLX IOP 480, and others Asynchronous clock inputs for PCI and Local Buses Low-power CMOS 2.5V core, 3.3V I/O 3.3, 5.0V tolerant PCI and Local Bus operation Industrial Temperature Range operation IEEE 1149.1 JTAG boundary scan * Two Local Bus address spaces map to the PCI Bus--one to PCI memory and one to PCI I/O * Generates all PCI memory and I/O transaction types, including MWI and Type 0 and Type 1 configuration * Read Ahead, Programmable Read Prefetch Counter (all modes) * MPC850/MPC860 Delayed Read and IDMA support (M mode) Direct Slave--Transfer data between a Master on the PCI Bus and a 32-, 16-, or 8-bit Local Bus device * Two general-purpose address spaces to the Local Bus and one expansion ROM address space * Delayed Read, Delayed Write, Read Ahead, Posted Write, Programmable Read Prefetch counter * Programmable READY# timeout and recovery DMA--PCI 9056 services data transfer descriptors, mastering on both buses during transfer * Two independent channels * Block Mode--Single descriptor execution * Scatter/Gather Mode * Descriptors in PCI or Local Bus memory * Linear descriptor list execution * Dynamic DMA descriptor Ring Management with Valid bit semaphore control * Burst descriptor loading * Hardware EOT/Demand controls to stop/pause DMA in any mode * Programmable Local Bus burst lengths, including infinite burst
*
*
* *
*
*
* 256-pin, 17 x 17 mm, 1.00 mm ball pitch PBGA * * * *
* Three data transfer modes--Direct Master, Direct Slave, and DMA * Direct Master--Transfer data between a Master on the Local Bus and a PCI Bus device
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Preliminary Information
xxvii
Feature Summary
Feature Summary
*
*
Six independent, programmable FIFOs--Direct Master Read and Write, Direct Slave Read and Write, DMA Channel 0 and 1 Advanced features common to Direct Master, Direct Slave, and DMA * Zero wait state burst operation * 264 MB/s bursts on PCI Bus * 264 MB/s bursts on Local Bus * Deep FIFOs prolong fast PCI bursts * Unaligned transfers on both buses * On-the-fly Local Bus Endian conversion * Programmable Local Bus wait states * Parity checking on both buses
* Eight 32-bit Mailbox and two 32-bit Doorbell registers enable general-purpose messaging * PCI arbiter supports seven external masters * Reset and interrupt signal directions configurable for host and peripheral applications * Programmable Interrupt Generator * Serial EEPROM interface * * Store user-specified power-on/reset configuration register values Store Vital Product Data (VPD)
* Register compatible with PCI 9060, PCI 9080, PCI 9054, and PCI 9656
* I2OTM r1.5-Ready Messaging Unit
Configuration Registers PCI Bus Local Bus PCI Arbiter DMA I2O Runtime 32-Bit, 66 MHz PCI Bus
Serial EEPROM - User-specified register initialzation values - Vital Product Data
PCI Master (For Direct Master Xfers) PCI Bus Interface PCI Master (For DMA Ch 0/1 Xfers)
Direct Master Read Direct Master Write
Local Slave (For Direct Master Xfers) Local Master (For DMA Ch 0/1 Xfers)
Local Bus Interface - Dynamic Bus Width (8-, 16-, or 32-bit) - Endian Conversion - Muxed or non-Muxed Address/Data Buses
DMA Channel 0 DMA Channel 1
PCI Target (For Direct Slave Xfers)
Dir. Slave Read Direct Slave Read Direct Slave Write
Local Master (For Direct Slave Xfers)
Control Logic
I2O Messaging Interrupts
Direct Master Hot Swap
Direct Slave Serial EEPROM
DMA Power Management
PCI 9056 Block Diagram
xxviii
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
32-Bit, 66 MHz Local Bus
PCI Bus State Machines
FIFOs
Local Bus State Machines
1
1.1
INTRODUCTION
COMPANY AND PRODUCT BACKGROUND 1.2.1 High-Speed Data Transfers
technology provides moving data--Direct Data Pipe Architecture independent methods for Transfers and DMA.
* PCI Local Bus burst transfers at the maximum bus rates * Unaligned transfers on both buses * On-the-fly Local Bus Endian conversion * Programmable Local Bus wait states * Parity checking on both buses
The PLX solution enables hardware designers and software developers to maximize system input/output (I/O), lower development costs, minimize system design risk, and accelerate time to market. PLX PCI I/O Accelerator chips and I/O Processor devices are designed in a wide variety of embedded PCI communication systems, including switches, routers, media gateways, base stations, access multiplexors, and remote access concentrators. PLX customers include many of the leading communications equipment companies, including 3Com, Cisco Systems, Compaq Computer, Ericsson, Hewlett-Packard, Intel, IBM, Lucent Technologies, Marconi, Nortel Networks, and Siemens. Founded in 1986, PLX has developed products based on the PCI industry standard since 1994. PLX is publicly-traded (NASDAQ: PLXT) and headquartered in Sunnyvale, California, USA, with operations in the United Kingdom, Japan, and China.
1.2.1.1
Direct Transfers
Data Pipe Architecture technology Direct Transfers are used by a master on either the PCI or Local Bus to move data through the I/O accelerator to a device on the other bus. The master takes responsibility for moving the data either into the I/O accelerator on a write or out of the I/O accelerator on a read. The I/O accelerator is responsible for moving the data out to the target device on a write, or in from the target device on a read.
1.2.1.1.1 Direct Master
When a master on the local processor bus uses Direct Transfer, this is a Direct Master transfer. The I/O accelerator is a master on the PCI Bus. Data Pipe Architecture technology provides independent FIFOs for Direct Master Read and Write transfers. It also supports multiple independent Direct Master Local Bus address spaces for mapping to PCI addresses, as illustrated in Figure 1-1. Direct Master transfers support generation of all PCI memory and I/O transaction types, including Configuration Type 0 and Type 1 cycles for system configuration.
1.2
DATA PIPE ARCHITECTURE TECHNOLOGY
PLX I/O accelerators feature PLX proprietary Data Pipe Architecture(R) technology. This technology consists of powerful, flexible engines for high-speed data transfers, as well as intelligent messaging units for managing distributed I/O functions.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
1-1
Section 1--Introduction
PLX Technology, Inc. is the leading supplier of high-speed, interconnect silicon and software solutions for the networking and communications industry. These include high-speed silicon, reference design tools that minimize design risk, and software for managing data throughout the PCI Bus, as well as third-party development tool support through the PLX Partner Program, further extending our complete solution.
Regardless of the method chosen, Data Pipe Architecture technology data transfers support the following:
Section 1 Introduction
Data Pipe Architecture Technology
accelerator, the master is free to spend its time and resources elsewhere.
Target Device 0 I/O Accelerator Target Device 1 Read Direction Write Direction PCI Memory Map Local Memory Map Space 1 Master Space 0
Figure 1-1. Direct Master Address Mapping
1.2.1.1.2 Direct Slave
When a master on the PCI Bus uses Direct Transfer, this is a Direct Slave transfer. The I/O accelerator is a slave (technically, a target) on the PCI Bus. Data Pipe Architecture technology provides independent FIFOs for Direct Slave Read and Write transfers. It also supports multiple independent Direct Slave PCI address spaces for mapping to Local Bus addresses, as illustrated in Figure 1-2. Under software control, Direct Slave transfers support Local Bus data transfers of 16 and 32 bits. Direct Slave read transfers also support PCI delayed reads.
2. Because the I/O accelerator supports multiple DMA channels, each with its own FIFO, it can service multiple PCI and processor Local Bus masters simultaneously. During DMA transfers, the I/O accelerator masters each bus. Consequently, during DMA, there are no external masters to Retry. During DMA, if the I/O accelerator is retried on either bus, it can simply change context to another transfer and continue. Furthermore, DMA can run simultaneously with Direct Master and Direct Slave transfers, providing support for several simultaneous data transfers. Direct Master and Direct Slave transfers have higher priority than DMA. Data Pipe Architecture technology supports two DMA transfer modes--Block mode and Scatter/Gather mode.
1.2.1.2.1 Block Mode
Block mode is the simplest DMA mode. The master simply programs the description of a single transfer into the I/O accelerator and sets the Start bit. The I/O accelerator signals DMA completion to the master, either by setting a bit in one of its registers that the master polls or by asserting an interrupt.
Target Space 0 Master Space 1 Read Direction Write Direction PCI Memory Map Local Memory Map Device 0 I/O Accelerator Target Device 1
1.2.1.2.2 Scatter/Gather Mode
In most cases, however, one descriptor is not sufficient. The master typically generates a list of several descriptors in its memory before submitting them to the I/O accelerator. For these cases, Scatter/ Gather mode is used to enable I/O accelerator list processing with minimal master intervention. With Scatter/Gather mode, the master simply tells the I/O accelerator the location of the first descriptor in its list, sets the Start bit, then waits for the I/O accelerator to service the entire list. This off loads both data and DMA descriptor transfer responsibilities from the master. Data Pipe Architecture technology supports Scatter/ Gather mode descriptor lists in either PCI or Local Bus memory. It also supports linear and circular Ring mode descriptor lists.
Figure 1-2. Direct Slave Address Mapping
1.2.1.2
DMA
When a Master on either bus uses Data Pipe Architecture technology DMA transfers, instead of the Master moving data, it places a description of the entire transfer in I/O accelerator registers and allows the I/O accelerator to perform the entire data transfer with its DMA engine. This offers two main benefits: 1. Data movement responsibilities are off loaded from the master. A transfer descriptor is short and takes little effort on the master's part to load. Once the descriptor is loaded into the I/O
1-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI 9056 I/O Accelerator
Section 1 Introduction
1.2.1.2.3 Hardware DMA Controls-- EOT and Demand Mode
To optimize DMA transfers in datacom/telecom and other applications, Data Pipe Architecture technology supports hardware controls for data transfer. With End of Transfer (EOT), an EOT# signal is asserted to the I/O accelerator to end a transfer. Whenever EOT# is asserted, the I/O accelerator immediately aborts the current DMA transfer and writes back to the current DMA descriptor the actual number of bytes transferred. Data Pipe Architecture technology also supports unlimited bursting. EOT and unlimited bursting are especially useful in applications such as Ethernet adapter cards where the lengths of read packets are not known until the packets are read. With Demand mode, a hardware DREQ#/DACK# signal pair is used to pause and resume the DMA transfer. Data Pipe Architecture technology provides one DREQ#/DACK# signal pair for each DMA channel. Demand mode provides a means for a peripheral device with a FIFO to control DMA transfers. The peripheral device uses Demand mode to pause the transfer when the FIFO is full on a write or empty on a read. Demand mode also resumes the transfer when the FIFO condition changes to allow the data transfer to continue.
1.3
PCI 9056 I/O ACCELERATOR
The PCI 9056, a 32-bit 66 MHz PCI Bus Master I/O Accelerator, extends the PLX family of advanced general-purpose bus master devices to 66 MHz operation. (Refer to Table 1-3 for a detailed comparison of the PCI 9056 with other PLX bus mastering I/O accelerators.) The PCI 9056 register set is backward-compatible with the previous generation PCI 9054 and PCI 9080 I/O accelerators, and offers a robust PCI r2.2 implementation, enabling burst transfers up to 264 MB/s. It incorporates the industry-leading PLX Data Pipe Architecture technology, including programmable Direct Master and Direct Slave transfer modes, intelligent DMA engines, and PCI messaging functions.
1.3.1
Applications
1.2.2
Intelligent Messaging Unit
Data Pipe Architecture technology provides two methods for managing system I/O through messaging. The first method is provided through support for Intelligent I/O (I2O). As the device independent, industry standard method for I/O control, I2O is the easiest way to obtain interoperability of all PCI-based components in the system. I2O is the recommended
The PCI 9056 continues the PLX tradition of expanding its product capabilities to meet the leading edge requirements of I/O intensive embeddedprocessor applications. The PCI 9056 builds upon the industry-leading PLX PCI 9080 and PCI 9054 products, providing an easy upgrade path to 32-bit, 66 MHz PCI Bus operation and 32-bit, 66 MHz Local Bus operation. The PCI 9056 supports all legacy processors and designs using the M, C and J Local Bus interfaces. Additionally, the PCI 9056 adds several important new features that expand its applicability and performance.
1.3.1.1
High-Performance Motorola MPC850/MPC860 PowerQUICC Designs
A key application for the PCI 9056 is Motorola MPC850- or MPC860-based adapters for telecom
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
1-3
Section 1--Introduction
Ring mode uses a Valid bit in each descriptor to enable dynamic list management. In this case, the master and I/O accelerator continuously "walk" the descriptor list, the master in the lead filling invalid descriptors, setting the Valid bit when done, and the I/O accelerator following behind servicing valid descriptors, and finally resetting the Valid bit when done. The I/O accelerator supports write back to serviced descriptors, allowing status and actual transfer counts to be posted prior to resetting the Valid bit.
method for messaging (especially for systems that include PCI or CompactPCI expansion slots). The second method is provided through general-purpose mailbox and doorbell registers. When all PCI-based components are under direct control of the system designer (for example, an embedded system, such as a set-top box), it is often desirable to implement an application-specific messaging unit through general-purpose mailbox and doorbell registers.
Section 1 Introduction
PCI 9056 I/O Accelerator
and networking applications. These applications include high-performance communications, such as WAN/LAN controller cards, high-speed modem cards, Frame Relay cards, routers, and switches. The PCI 9056 simplifies these designs by providing an industry-leading enhanced direct-connect interface to the MPC850 or MPC860 processor. The flexible PCI 9056 3.3V, 5V tolerant I/O buffers, combined with Local Bus operation up to 66 MHz, are ideally suited for current and future PowerQUICC processors. The PCI 9056 supports the MPC850 and MPC860 IDMA channels for movement of data between the integrated MPC850 or MPC860 communication channels and the PCI Bus. In addition, the PCI 9056 makes use of the advanced Data Pipe Architecture technology, allowing unlimited burst capability, as illustrated in Figure 1-3.
This is a prime example of how the PCI 9056 provides superior general-purpose bus master performance and provides designers using the PowerQUICC processor with greater flexibility in implementing multiple simultaneous I/O transfers. The PCI 9056 has unlimited bursting capability, which enhances most MPC850 or MPC860 PowerQUICC designs.
1.3.1.2
High-Performance CompactPCI Adapter Cards
Another key application for the PCI 9056 is CompactPCI adapters for telecom and networking applications. These applications include high-performance communications, such as WAN/ LAN controller cards, high-speed modem cards, Frame Relay cards, telephony cards for telecom switches, and remote-access systems. Many processors have integrated communication channels that support ATM, T1/E1, Ethernet, and other high-speed communication standards for communications add-in cards. Today, CompactPCI is the standard choice for the system interconnect of these add-in cards. The PCI 9056 is the perfect choice for adding CompactPCI connection capabilities to a variety of processor platforms. The PCI 9056 has integrated key features to enable live insertion of Hot Swap CompactPCI adapters. The PCI 9056 Hot Swap Silicon includes the following features: * Compliant with PCI r2.2 * Tolerant of VCC from early power, including support for pin bounce, 2.5 and 3.3V appearing in any order, I/O cell stability within 4 ms, and low current drain during insertion * Tolerant of asynchronous reset * Tolerant of pre-charge voltage * I/O buffers meet modified V/I requirements in PICMG 2.1, R2.0 * Limited I/O pin leakage at precharge voltage * Incorporates the Hot Swap Control/Status register (HS_CSR) * Incorporates an Extended Capability Pointer (ECP) to the Hot Swap Control/Status register * Incorporates added resources for software control of the ejector switch, ENUM#, and the blue status LED which indicates insertion and removal to the user
MPC850 or MPC850 PowerQUICC
Memory
1
IDMA
2
DMA 0
32-Bit, 66 MHz M Mode Local Bus
PCI 9056 I/O Accelerator
DMA 1
ROM
32-Bit, 66 MHz PCI Bus
Figure 1-3. High-Performance MPC850 or MPC860 PowerQUICC Adapter Design
1. For PowerQUICC IDMA operation, the PCI 9056 transfers data to the PCI Bus under the control of the IDMA handshake protocol using Direct Master transfers (1). 2. Simultaneously, the PCI 9056 DMA can be operated bi-directionally, with the PCI 9056 as the master for both buses, to manage transfers of data between the Local Bus and the PCI Bus (2).
1-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI 9056 I/O Accelerator
Section 1 Introduction
* BIAS voltage support with integrated 10K ohm precharge resistors eliminates the need for an external resistor network * Early power support allows transition between the operating and powered down states without external circuitry * Programming Interface 0 (PI = 0) * Initially Not Respond Support Figure 1-4 illustrates a CompactPCI peripheral card that utilizes an MPC860 CPU for communication I/O and the PCI 9056 for PCI-based I/O. The PCI 9056, with its internal PCI arbiter, reset signal direction control, and Type 0 and Type 1 PCI configuration support, is an ideal choice for CompactPCI system cards.
Today, Power Management and Green PCs are major initiatives in traditional PCI applications. The PCI 9056 supports PCI power management, including generation of PME in the D3cold state. This is especially useful in applications such as modem cards that are responsible for waking up the system (as a result of an external event), such as a telephone line ringing. Figure 1-5 illustrates the PCI 9056 in a PCI adapter card application with a CPU, using the C or J Local Bus modes.
Section 1--Introduction
32-Bit CPU
Memory
PCI 9056 I/O Accelerator
Local Bus Using C or J Mode
COM 1 COM 2 COM N
32-Bit, 66 MHz PCI Bus
ROM
MPC860 SDRAM Flash
Local Bus
J1 Serial EEPROM
PCI 9056
32-Bit, 66 MHz PCI Bus
Figure 1-5. PCI 9056 PC Adapter Card with C or J Mode Processor
Figure 1-4. PCI 9056 CompactPCI Peripheral Card
The C and J Local Bus modes, in addition to supporting Intel's i960 processors, have been adopted by designers of a wide variety of devices, ranging from DSPs to custom ASICs, because of their high-speed, low overhead, and relative simplicity. For applications using I/O types not supported directly by the processor (such as, SCSI for storage applications), the PCI 9056 provide a high-speed interface between the processor and PCI-based I/O chips. Furthermore, its Local Bus interface supports processors that do not include integrated I/O. Typically, a PCI-to-PCI bridge chip is used to isolate the add-in card's local PCI Bus and its I/O chips from the system bus. Figure 1-6 illustrates a typical PCI add-in card with local PCI I/O using the PCI 9056 and a PCI-to-PCI bridge interfacing to the system PCI Bus. The PCI 9056 internal PCI arbiter provides arbitration services to the devices on the local PCI Bus.
1.3.1.3
High-Performance PC Adapter Cards
The PCI 9056 is also designed for traditional PCI adapter card applications requiring 32-bit, 66 MHz PCI operation and bandwidth. Specific applications include high-performance communications, networking, disk control, and data encryption adapters. As such, the PCI 9056 enables easy migration of existing 32-bit, 33 MHz PCI I/O accelerator designs to 32-bit, 66 MHz capability.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
1-5
Section 1 Introduction
PCI 9056 I/O Accelerator
CPU
Memory Controller
SDRAM
Flash
32-Bit, 66 MHz Local Bus
While the support requirements of these embedded host designs share many similarities with peripheral card designs (such as, their requirement for intelligent management of high-performance I/O), there are three significant differences. First, the host is responsible for configuring the system PCI Bus. The PCI 9056 supports PCI Configuration Type 0 and Type 1 cycles to accomplish this. Second, the host is responsible for providing PCI Bus arbitration services. The PCI 9056 includes an internal PCI arbiter that supports seven external PCI masters in addition to the PCI 9056. This is sufficient for a standard 33 MHz CompactPCI backplane with seven peripheral slots and one system slot. Third, for hosts, the directions of the reset and interrupt signals reverse. The PCI 9056 includes a strapping option for reversing the directions of the PCI and Local Bus reset and interrupt signals. In one setting, the directions are appropriate for a peripheral. In the other setting, they are appropriate for a host. Figure 1-8 illustrates the PCI 9056 in an embedded host system. Figure 1-9 illustrates the PCI 9056 and IOP 480 in an embedded host system.
PCI I/O
PCI I/O
PCI Arbiter
PCI-to-PCI Bridge
32-Bit, 66 MHz Local PCI Bus
PCI 9056
Serial EEPROM
32-Bit, 66 MHz System PCI Bus
Figure 1-6. PCI 9056 PC Adapter Card with Local PCI I/O and PCI-to-PCI Bridge
The PCI 9056 directly interfaces to the PLX IOP 480, which includes an integrated PowerPC 401 processor, and PCI Bus. The IOP 480 can control the local PCI Bus while the PCI 9056 provides 32-bit, 66 MHz, mastering on the system PCI Bus, as illustrated in Figure 1-7.
Memory ROM
I/O
32-Bit, 66 MHz J Mode Local Bus
I/O Chips (Datacom, Telecom, Storage, etc.)
IOP 480
PCI 9056
32-Bit, 33 MHz PCI Bus
CPU
PCI I/O
I/O
I/O
PCI 9056
32-Bit, 66 MHz PCI Bus
Local Bus
Memory
PCI Arbiter
I/O
Figure 1-7. PCI 9056 PC Adapter Card with Local PCI I/O and IOP 480
32-Bit, 66 MHz PCI Bus
PCI I/O
Expansion Slot
1.3.1.4
High-Performance Embedded Host Designs
Figure 1-8. PCI 9056 Embedded Host System with Generic Host CPU
I/O intensive embedded host designs are another major application of the PCI 9056. These applications include network switches and routers, printer engines, set-top boxes, CompactPCI system cards, and industrial equipment.
1-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI 9056 Major Features
Section 1 Introduction
I/O Chips (Datacom, Telecom, Storage, etc.)
Memory
I/O
I/O
Subsystem ID and Subsystem Vendor ID. Contains Subsystem ID and Subsystem Vendor ID in the PCI Configuration register space, in addition to System and Vendor IDs. The PCI 9056 also contains a permanent Vendor ID (10B5h) and Device ID (9056h). RST# Timing. Supports response to first configuration accesses after de-assertion of RST# under 225 clocks.
PCI 9056
PCI Arbiter
32-Bit, 66 MHz J Mode Local Bus
IOP 480
32-Bit, 66 MHz PCI Bus
PCI I/O
32-Bit, 33 MHz PCI Bus
PCI I/O PCI I/O
PCI I/O
PCI Expansion Slot
Clocks. The PCI and Local Bus clocks are independent and asynchronous. The Local Bus interface runs from an external clock to provide the necessary internal clocks. Local Bus Direct Interface. 32-bit, 66 MHz Local Bus interface supports direct connection to the Motorola 801 PowerPC and MPC850/MPC860 PowerQUICC families, the Intel i960 family, the IBM PowerPC 401 family, the PLX IOP 480, Texas Instruments DSPs, and other similar bus-protocol devices. Local Bus Types. Local bus type selected through a pin strapping option, as listed in the following table.
Table 1-1. Local Bus Types
Mode
M C J
Figure 1-9. PCI 9056 Embedded Host System with IOP 480
1.4 1.4.1
PCI 9056 MAJOR FEATURES Interfaces
The PCI 9056 is a PCI Bus Master interface chip that connects a 32-bit, 66 MHz PCI Bus to one of three 32-bit, 66 MHz Local Bus types. PCI r2.1 and r2.2 Compliant. Compliant with PCI r2.1 and PCI r2.2, including 66 MHz operation. New Capabilities Structure. Supports New Capabilities registers to define additional capabilities of the PCI functions. VPD Support. Supports the Vital Product Data (VPD) PCI extension through its serial EEPROM interface, providing an alternate to Expansion ROM for VPD access. Power Management. Supports all five power states for PCI Power Management functions (D0, D1, D2, D3hot, and D3cold) and Power Management Event interrupt (PME#) generation in all five states, including D3cold. PICMG 2.1, R2.0 Hot Swap Silicon. Compliant with PICMG 2.1, R2.0, including support for Programming Interface (PI = 0), BIAS Voltage and Early Power Support, and an option to Initially Not Respond while the chip is initializing. PCI Hot-Plug Hot-Plug r1.0. Compliant. Compliant with
Description
32-bit address/32-bit data, non-multiplexed direct connect interface to MPC850 or MPC860 PowerQUICC 32-bit address/32-bit data, non-multiplexed 32-bit address/32-bit data, multiplexed
1.4.2
Data Transfer
PCI Local Burst Transfers up to 264 MB/s. Six Programmable FIFOs for Zero Wait State Burst Operation. The following table enumerates the FIFO depth.
Table 1-2. FIFO Depth
FIFO
Direct Master Read Direct Master Write Direct Slave Read Direct Slave Write DMA Channel 0 DMA Channel 1
Depth
32 Lwords 64 Lwords 32 Lwords 64 Lwords 64 Lwords 64 Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
1-7
Section 1--Introduction
Section 1 Introduction
PCI 9056 Major Features
Unaligned Transfer Support. Capable of transferring data on any byte-boundary combination of the PCI and Local Address Bus addresses. Big/Little Endian Conversion. Supports dynamic switching between Big Endian (Address Invariance) and Little Endian (Data Invariance) operations for Direct Slave, Direct Master, DMA, and internal register accesses on the Local Bus. Supports on-the-fly Endian conversion of Local Bus data transfers. The Local Bus can be Big/Little Endian by using the BIGEND# input pin or programmable internal register configuration. When BIGEND# is asserted, it overrides the internal register configuration during Direct Master, and internal register accesses on the Local Bus.
Note: The PCI Bus is always Little Endian.
C and J Mode Data Transfers. Communicates with these processors, using four possible data transfer modes: * Configuration Register Access * Direct Master Operation * Direct Slave Operation * DMA Operation Direct Master. Supports PCI accesses from a Local Bus master. Burst transfers are supported for memory-mapped devices. Single transfers are supported for Memory- and I/O-Mapped devices. Also supports PCI Bus interlock (LOCK#) cycles. Direct Slave. Supports Burst Memory-Mapped and single I/O-Mapped accesses to the Local Bus. Supports 8-, 16-, and 32-bit Local Bus data transfers. The Read and Write FIFOs enable high-performance bursting. Three PCI-to-Local Address Spaces. Supports three PCI-to-Local Address spaces in Direct Slave mode-- Space 0, Space 1, and Expansion ROM. These spaces allow any PCI Bus master to access the Local Bus memory spaces with programmable wait states, bus width, burst capabilities, and so forth. Read Ahead Mode. Supports Read Ahead mode, where prefetched data can be read from the internal Read FIFO instead of the external bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4). This feature allows for increased bandwidth and reduced data latency. Programmable Prefetch Counter. Includes programmable controls to prefetch data during Direct Master and Direct Slave accesses. To perform burst reads, prefetching must be enabled. The prefetch size can be programmed to match the master burst length, or can be used as Read Ahead mode data. Reads single data (8, 16, or 32 bit) if the Master initiates a single cycle; otherwise, prefetches the programmed size. Posted Memory Writes. Supports the Posted Memory Writes (PMW) for maximum performance and to avoid potential deadlock situations.
Keep Bus Mode (M Mode). Supports program control to retain the PCI Bus by generating wait state(s) if the Direct Slave Write FIFO becomes full. Can also be programmed to retain the Local Bus (BB# asserted) if the Direct Slave Write FIFO becomes empty or the Direct Slave Read FIFO becomes full. The Local Bus is dropped in either case when the Local Bus Latency Timer is enabled and expires. Keep Bus Mode (C and J Modes). The PCI 9056 can be programmed to retain the PCI Bus by generating one or more wait states if the Direct Slave Write FIFO becomes full. The PCI 9056 can also be programmed to retain the Local Bus (LHOLD asserted) if the Direct Slave Write FIFO becomes empty or the Direct Slave Read FIFO becomes full. The Local Bus is dropped in either case when the Local Bus Latency Timer is enabled and expires. M Mode Data Transfers. Communicates with the MPC850 or MPC860, using five possible data transfer modes: * Configuration Register Access * Direct Master Operation * Direct Slave Operation * DMA Operation * IDMA/SDMA Operation
1-8
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Compatibility with Other PLX Chips
Section 1 Introduction
Two DMA Channels with Independent FIFOs. Provides two independently programmable DMA controllers with independently programmable FIFOs. Each channel supports Block and Scatter/Gather DMA modes, including ring management, as well as EOT mode. Supports Demand mode DMA for both channels. PCI Dual-Address Cycle (DAC) Support (32-bit Address Space). Supports PCI Dual Address Cycle beyond the low 4-GB Address space. PCI DAC can be used during PCI 9056 PCI Bus Master operation (DMA and Direct Master).
1.4.5
Electrical/Mechanical
Packaging. Available in a 256-pin, 17 x 17 mm PBGA package. 2.5V Core/3.3V I/O. Low power CMOS 2.5V core with 3.3V I/O. 5V Tolerant Operation. Provides 3.3V signaling with 5V I/O tolerance on both the PCI and Local Buses. Industrial Temperature Range Operation. The PCI 9056 works in a -40 to +85 C temperature range. JTAG. Supports IEEE 1149.1 JTAG boundary scan.
Section 1--Introduction
1.4.3
Messaging Unit
1.4.6
Miscellaneous
I2O-Ready Messaging Unit. Incorporates the I2O-Ready Messaging Unit, which enables the adapter or embedded system to communicate with other I2O-supported devices. The I2O Messaging Unit is fully compatible with the PCI extension of I2O r1.5. Mailbox Registers. Includes eight 32-bit Mailbox registers that may be accessed from the PCI or Local Bus. Doorbell Registers. Includes two 32-bit doorbell registers. One asserts interrupts from the PCI Bus to the Local Bus. The other asserts interrupts from the Local Bus to the PCI Bus.
Serial EEPROM Interface. Includes a serial EEPROM interface (optional only if using a Local processor) that can be used to load configuration information. This is useful for loading information that is unique to a particular adapter (such as, the Network or Vendor ID). Interrupt Generator. Can assert PCI and Local interrupts from external and internal sources.
1.5
COMPATIBILITY WITH OTHER PLX CHIPS Pin Compatibility
1.5.1 1.4.4 Hosting Features
Type 0 and Type 1 Configuration. In Direct Master mode, supports Type 0 and Type 1 PCI Configuration cycles. Internal PCI Arbiter. Includes integrated PCI arbiter that supports seven external masters in addition to the PCI 9056. Reset and Interrupt Signal Directions. Includes a strapping option to reverse the directions of the PCI and Local Bus reset and interrupt signals.
The PCI 9056 is not pin compatible with other PLX chips.
1.5.2
Register Compatibility
All registers implemented in the PCI 9060, PCI 9080, PCI 9054, and PCI 9656 are implemented in the PCI 9056. The PCI 9056 includes many new bit definitions and several new registers. (Refer to Section 11 for details.) The PCI 9056 is not register-compatible with the PCI 9050.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
1-9
Section 1 Introduction
Compatibility with Other PLX Chips
1.5.3
PCI 9056 Comparison with Other PLX Chips
Table 1-3. Bus Master I/O Accelerator PLX Product Comparison
Features PCI 9054-AB50PI PCI 9054-AB50BI Interfaces
Host Bus Type Processor Local Bus Type(s): A = Address Bus D = Data Bus Mux = Multiplexed A/D Buses Non-Mux = Non-Multiplexed A/D Buses Maximum Processor Local Bus Speed Core Voltage I/O Ring Voltage 3.3V PCI Bus Signalling 5V PCI Bus Signalling 3.3V Tolerant Local Bus 5V Tolerant Local Bus 32-Bit, 33 MHz PCI r2.2 C: Generic, 32-Bit A, 32-Bit D, non-mux J: Generic, 32-Bit A, 32-Bit D, mux M: PowerPC(R) PowerQUICC(R), 32-Bit A, 32-Bit D, non-mux 50 MHz 3.3V 3.3V
! ! ! !
PCI 9056-AA66BI
PCI 9656-AA66BI
32-Bit, 66 MHz PCI r2.2 C: Generic, 32-Bit A, 32-Bit D, non-mux J: Generic, 32-Bit A, 32-Bit D, mux M: PowerPC(R) PowerQUICC(R), 32-Bit A, 32-Bit D, non-mux 66 MHz 2.5V 3.3V
! ! ! !
64-Bit, 66 MHz PCI r2.2 C: Generic, 32-Bit A, 32-Bit D, non-mux J: Generic, 32-Bit A, 32-Bit D, mux M: PowerPC(R) PowerQUICC(R), 32-Bit A, 32-Bit D, non-mux 66 MHz 2.5V 3.3V
! ! ! !
PICMG 2.1, R2.0
Programming Interface (PI = 0)
Programming Interface (PI = 0) Bias Voltage Support Early Power Support Initially Not Respond Support
Programming Interface (PI = 0) Bias Voltage Support Early Power Support 64-Bit Initialization
Package Size/Type(s): Pin/Ball Count External Dimensions (mm) Pin/Ball Pitch (mm) Package Type Industrial Temperature Range Operation
176-Pin, 26 x 26, .5 PQFP 225-Pin, 27 x 27, 1.5 PBGA
256-Pin, 17 x 17, 1.00 PBGA
272-Pin, 27 x 27, 1.27 PBGA
!
!
!
Data Transfer
Direct Slave Address Spaces Direct Slave Read FIFO Depth Direct Slave Write FIFO Depth Delayed Read Support Programmable READY# Timeout Direct Master Address Spaces Direct Master Read FIFO Depth Direct Master Write FIFO Depth Two General-Purpose One Expansion ROM 16 Lwords (64 bytes) 32 Lwords (128 bytes)
!
Two General-Purpose One Expansion ROM 32 Lwords (128 bytes) 64 Lwords (256 bytes)
! !
Two General-Purpose One Expansion ROM 16 Qwords (128 bytes) 32 Qwords (256 bytes)
! !
-- 1 16 Lwords (64 bytes) 32 Lwords (128 bytes)
1 32 Lwords (128 bytes) 64 Lwords (256 bytes)
1 16 Qwords (128 bytes) 32 Qwords (256 bytes)
1-10
Preliminary Information
PCI 9056 Data Book, Version 0.91a (c) 2002 PLX Technology, Inc. All rights reserved.
Compatibility with Other PLX Chips
Section 1 Introduction
Table 1-3. Bus Master I/O Accelerator PLX Product Comparison (Continued)
Features PCI 9054-AB50PI PCI 9054-AB50BI PCI 9056-AA66BI PCI 9656-AA66BI
Data Transfer (Continued)
DMA Channels DMA Channel 0 FIFO Depth DMA Channel 1 FIFO Depth DMA Demand Mode Hardware Control DMA EOT Mode Hardware Control DMA Block Mode DMA Scatter/Gather Mode DMA Ring Management Mode Programmable Prefetch Counter Dual Address Cycle Generation Big Endian/Little Endian Conversion 2 32 Lwords (128 bytes) Bi-directional 16 Lwords (64 bytes) Bi-directional
!
2 64 Lwords (256 bytes) Bi-directional 64 Lwords (256 bytes) Bi-directional
! ! ! ! ! ! ! !
2 32 Qwords (256 bytes) Bi-directional 32 Qwords (256 bytes) Bi-directional
(Channel 0 Only)
! ! !
! ! ! ! ! ! !
--
!
--
!
Control
Mailbox Registers Doorbell Registers I2O Messaging Unit PCI Arbiter PCI Type 0 and Type 1 Configuration PCI Power Management D3cold PME Generation PCI r2.2 VPD Support Serial EEPROM Support JTAG Boundary Scan Register Compatibility Eight 32-Bit Two 32-Bit
!
Eight 32-Bit Two 32-Bit
!
Eight 32-Bit Two 32-Bit
!
r1.5 --
!
r1.5
!
r1.5
!
Seven external masters
! !
Seven external masters
! !
-- -- -- 2K bit, 4K bit Microwire devices with sequential read support -- --
r1.1
! !
r1.1
! !
2K bit, 4K bit Microwire devices with sequential read support
!
2K bit, 4K bit Microwire devices with sequential read support
!
Backward compatible with PCI 9054
Backward compatible with PCI 9054
PCI 9056 Data Book, Version 0.91a (c) 2002 PLX Technology, Inc. All rights reserved.
Preliminary Information
1-11
1--Introduction
!
2
2.1
M MODE BUS OPERATION
PCI BUS CYCLES 2.1.2.1 DMA Master Command Codes
The PCI 9056 DMA controllers can assert the Memory Command cycles listed in Table 2-2.
Table 2-2. DMA Master Command Codes
Command Type
Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate
The PCI 9056 is compliant with PCI r2.2. Refer to PCI r2.2 for specific PCI Bus functions.
2.1.1
Direct Slave Command Codes
As a Target, the PCI 9056 allows access to the PCI 9056 internal registers and the Local Bus, using the commands listed in Table 2-1. All Read or Write accesses to the PCI 9056 can be Byte, Word, or Long-Word (Lword) accesses, defined as 32 bit. All memory commands are aliased to basic memory commands. All I/O accesses to the PCI 9056 are decoded to an Lword boundary. Byte enables are used to determine which bytes are read or written. An I/O access with illegal byte enable combinations is terminated with a Target Abort.
Table 2-1. Direct Slave Command Codes
Command Type
I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write and Invalidate
Code (C/BE[3:0]#)
0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh)
2.1.2.2
Code (C/BE[3:0]#)
0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1010 (Ah) 1011 (Bh) 1100 (Ch) 1110 (Eh) 1111 (Fh)
For Direct Master Local-to-PCI Bus accesses, the PCI 9056 asserts the cycles listed in Table 2-3 through Table 2-5.
Table 2-3. Local-to-PCI Memory Access
Command Type
Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate
Code (C/BE[3:0]#)
0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh)
2.1.2
PCI Master Command Codes
Table 2-4. Local-to-PCI I/O Access
Command Type
I/O Read I/O Write
The PCI 9056 can access the PCI Bus to perform DMA or Direct Master Local-to-PCI Bus transfers. During a Direct Master or DMA transfer, the command code assigned to the PCI 9056 internal register location (CNTRL[15:0]) is used as the PCI command code (except for Memory Write and Invalidate mode for DMA cycles where DMPBAM[9]=1).
Notes: Programmable internal registers determine PCI command codes when the PCI 9056 is the Master. DMA cannot perform I/O or Configuration accesses.
Code (C/BE[3:0]#)
0010 (2h) 0011 (3h)
Table 2-5. Local-to-PCI Configuration Access
Command Type
Configuration Memory Read Configuration Memory Write
Code (C/BE[3:0]#)
1010 (Ah) 1011 (Bh)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-1
Section 2--M Bus Op
Direct Master Local-to-PCI Command Codes
Section 2 M Mode Bus Operation
Local Bus Cycles
2.1.3
PCI Arbitration
The PCI 9056 asserts REQ# to request the PCI Bus. The PCI 9056 can be programmed using the PCI Request Mode bit (MARBR[23]) to de-assert REQ# when it asserts FRAME# during a Bus Master cycle, or to keep REQ# asserted for the entire Bus Master cycle. The PCI 9056 always de-asserts REQ# for a minimum of two PCI clocks after a bus ownership that sustains a Target disconnect. The Direct Master Write Delay bits (DMPBAM[15:14]) can be programmed to delay the PCI 9056 from asserting PCI REQ# during a Direct Master Write cycle. DMPBAM can be programmed to wait 0, 4, 8, or 16 PCI Bus clocks after the PCI 9056 has received its first Write data from the Local Bus Master, and is ready to begin the PCI Write transaction. This function is useful in applications where a Local Master is bursting and a Local Bus clock is slower than the PCI Bus clock. This allows Write data to accumulate in the PCI 9056 Direct Master Write FIFO, which provides for better use of the PCI Bus.
is de-asserted (no other device is acting as the Local Bus Master). The PCI 9056 continues to assert BB# while acting as the Local Bus Master (that is, it holds the bus until instructed to release BB#) when the Local Bus Latency Timer is enabled and expires (MARBR[7:0]) or the transaction is complete.
Note: The Local Bus Pause Timer applies only to DMA operation. It does not apply to Direct Slave operation.
2.2.2
Direct Master
Local Bus cycles can be single or Burst cycles. As a Local Bus Target, the PCI 9056 allows access to the PCI 9056 internal registers and the PCI Bus. Local Bus Direct Master accesses to the PCI 9056 must be for a 32-bit non-pipelined bus. Non-32-bit Direct Master accesses to the PCI 9056 require simple external logic (latch array to combine data into a 32-bit bus).
2.2.3
Direct Slave
2.2
LOCAL BUS CYCLES
The PCI Bus Master reads from and writes to the Local Bus (the PCI 9056 is a PCI Bus Target and a Local Bus Master).
The PCI 9056 interfaces a PCI Host bus to several Local Bus types, as listed in Table 2-6. It operates in one of three modes (selected through the MODE[1:0] pins), corresponding to the three bus types----M, C, and J.
Table 2-6. Local Bus Types
MODE1
1 1 0 0
2.2.4
Wait State Control
The TA# signal overwrites the programmable wait state counter, and can be used to introduce additional wait states. The following figure illustrates the PCI 9056 wait states for M mode.
PCI Bus
Accessing PCI 9056 from PCI Bus
MODE0
1 0 0 1
Bus Mode
M Reserved C J --
Bus Type
32-bit non-multiplexed
Local Bus
Accessing PCI 9056 from Local Bus
32-bit non-multiplexed 32-bit multiplexed
PCI 9056 de-asserts TRDY# when waiting on the Local Bus PCI Bus de-asserts IRDY# or simply ends the cycle when it is not ready PCI 9056 accessing PCI Bus PCI 9056 can be programmed to de-assert IRDY# when its Direct Master Read FIFO is full PCI Bus de-asserts TRDY# when it is not ready
PCI 9056 generates READY# when data is valid on the following clock edge Local Processor generates wait states with WAIT#
In M mode, the PCI 9056 provides a direct connection to the MPC850 or MPC860 address and data lines, regardless of the PCI 9056 Little Endian or Big Endian modes.
PCI 9056
PCI 9056 accessing Local Bus PCI 9056 generates wait states with WAIT# (programmable) Local Bus can respond to PCI 9056 requests with READY#
2.2.1
Local Bus Arbitration
The PCI 9056 asserts BR# to request the Local Bus. It owns the Local Bus when BG# is asserted. Upon receiving BG#, the PCI 9056 waits for BB# to de-assert. The PCI 9056 then asserts BB# at the next rising edge of the Local clock after acknowledging BB#
Figure 2-1. Wait States
Note: Figure 2-1 represents a sequence of Bus cycles.
2-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus Cycles
Section 2 M Mode Bus Operation
2.2.4.1
Wait States--Local Bus
In Direct Master mode, when accessing the PCI 9056 registers, the PCI 9056 acts as a Local Bus Slave. The PCI 9056 asserts external wait states with the TA# signal. In Direct Slave and DMA modes, the PCI 9056 acts as a Local Bus Master. The Internal Wait States bit(s) (LBRD0[21:18, 5:2], LBRD1[5:2], DMAMODE0[5:2], and/or DMAMODE1[5:2]) can be used to program the number of internal wait states between the first address-to-data (and subsequent data-to-data in Burst mode). In Direct Slave and DMA modes, if TA# is enabled and active, it continues the Data transfer, regardless of the wait state counter.
On the Local Bus, BTERM# is not supported, but the Bterm bit can be used to gain maximum performance and data throughput. * If the Burst Mode bit is enabled, but the Bterm Mode bit is disabled, then the PCI 9056 bursts four Lwords. BDIP# is de-asserted at the last Lword transfer before its completion (LA[2:3]=11) and a new TS# is asserted at the first Lword (LA[2:3]=00) of the next burst. * If the Burst Mode and Bterm Mode bits are both enabled, then the PCI 9056 bursts until the transfer counter counts to "0", the Local Latency Timer is enabled and expires, the EOT function is introduced, or DREQ0# is de-asserted during DMA transactions. For Direct Slave transactions, the PCI 9056 bursts until BI# is asserted, implying a new TS# is required, or the Local Latency Timer is enabled and expires. The PCI 9056 does not release bus ownership during BI# assertion. BDIP# output is supported in Burst Forever mode with a different behavior then MPC860 protocol. Refer to Section 2.2.5.2.
Notes: If Address Increment is disabled, the DMA transaction bursts beyond four Lwords. If the Bterm Mode bit is disabled, the PCI 9056 performs the following: * * * 32-bit Local Bus--Bursts up to four Lwords 16-bit Local Bus--Bursts up to four Lwords 8-bit Local Bus--Bursts up to four Lwords
2.2.4.2
Wait States--PCI Bus
To insert PCI Bus wait state(s), the PCI Bus Master throttles IRDY# and the PCI Bus Slave throttles TRDY#.
2.2.5
Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode)
Note: In the following sections, Bterm refers to the PCI 9056 internal register bit, and BTERM# refers to the PCI 9056 external signal.
In every case, it transfers 16 bytes of data.
2.2.5.1
Burst and Bterm Modes
2.2.5.2
Burst-4 Lword Mode
Table 2-7. Burst and Bterm on the Local Bus
Mode
Single Cycle
Burst
0 0
Bterm
0 1 0
Result
One TS# per data (default). One TS# per data. One TS# per four data (recommended for MPC850 or MPC860). Direct Slave or DMA-- One TS# per Burst data or until BI# is asserted. (Refer to Section 2.2.5.2.1.)
Burst-4
1
If the Burst Mode bit is enabled and the Bterm Mode bit is disabled, bursting can start only on a 16-byte boundary and continue up to the next 16-byte address boundary. After data before the boundary is transferred, the PCI 9056 asserts a new Address cycle (TS#).
Table 2-8. Burst-4 Lword Mode
Bus Width
32 bit 16 bit
Burst
Four Lwords or up to a quad Lword boundary (LA3, LA2 = 11) Eight words or up to a quad Lword boundary (LA2, LA1 = 11) Sixteen bytes or up to a quad Lword boundary (LA1, LA0 = 11)
Burst Forever
1
1
Note: BI# is supported in Burst-4 mode. Refer to the MPC850 or MPC860 data manual.
8 bit
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-3
Section 2--M Bus Op
Section 2 M Mode Bus Operation
Local Bus Cycles
2.2.5.2.1 Continuous Burst Mode (Bterm "Burst Terminate" Mode)
If both the Burst and Bterm Mode bits are enabled, the PCI 9056 can operate beyond the Burst-4 Lword mode. Bterm mode enables the PCI 9056 to perform long bursts to special external M mode interface devices that can accept bursts of longer than four Lwords. The PCI 9056 asserts one Address cycle and continues to burst data. The external address is incremented during bursts. If a device requires a new Address cycle, it can assert BI# input anywhere after the first Data phase to cause the PCI 9056 to assert a new Address cycle (TS#). The BI# input acknowledges the current Data transfer and requests that a new Address cycle be asserted (TS#), for the next Data transfer. If the Bterm Mode bit is enabled, the PCI 9056 de-asserts BURST# only if its Read FIFO is full, its Write FIFO is empty, or if a transfer is complete. If the transfer starts on a non-Qword-aligned address, the PCI 9056 single cycles the data until the next Qwordaligned address and bursts forever the remainder of the data. The PCI 9056 supports the BDIP# signal for continuous bursts greater than four Lwords, which differs from MPC850 and MPC860 protocol. When Bterm and Burst functions are enabled for Direct Slave and/or DMA transactions, and Slow Terminate mode is enabled for DMA, the PCI 9056 asserts the BDIP# signal low until the last Burst Data transfer. On the last Data transfer, the PCI 9056 de-asserts BDIP#, indicating the last transfer of the Burst transaction. During Burst Forever Write transactions, the PCI 9056 passes all bytes from the PCI Bus to the Local Bus, if C/BE# begins to toggle on the nonquad-aligned address by keeping TSIZ[0:1] at a constant value of 0 and issues TS# for the toggled address. However, if C/BE# toggles on the Qword-aligned address, the PCI 9056 begins the Local Bus Burst and toggles TSIZ[0:1], along with TS#, for all data that follows when a burst resumes. It is recommended to keep all bytes enabled during a PCI Write Burst transaction.
Start Address in a Direct Slave or DMA transfer is not aligned to a Qword or Lword boundary. It then starts to burst on the Qword boundary if there is remaining data that is not a whole Lword during DMA (for example, it results in a single cycle at the end).
2.2.6
Local Bus Read Accesses
For all single cycle Local Bus Read accesses, the PCI 9056 reads only bytes corresponding to byte enables requested by the Direct Master. For all Burst Read cycles, the PCI 9056 passes all the bytes and can be programmed to: * Prefetch * Perform Read Ahead mode * Generate internal wait states * Enable external wait control (TA# input) * Enable type of Burst mode to perform
2.2.7
Local Bus Write Accesses
For Local Bus writes, only bytes specified by a PCI Bus master or the PCI 9056 DMA controller are written.
2.2.8
Direct Slave Accesses to 8- or 16-Bit Local Bus
Direct Slave PCI accesses to an 8- or 16-bit Local Bus results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each transfer, byte enables are encoded to provide the Transfer Size bits (TSIZ[0:1]).
2.2.9
Local Bus Data Parity
2.2.5.3
Partial Lword Accesses
Lword accesses, in which not all byte enables are asserted, are broken into single Cycle accesses. Burst start addresses can be any Qword boundary. The PCI 9056 first performs a single cycle, if the Burst
Generation or use of Local Bus data parity is optional. Signals on the data parity pins do not affect operation of the PCI 9056. The PCI Bus parity checking and generation is independent of the Local Bus parity checking and generation. PCI Bus parity checking may result in assertion of PERR#, a PCI Bus system error (SERR#), or other means of PCI Bus transfer termination as a result of the parity error on the PCI data address, command code, and byte enables. The Local Bus Parity Check is passive and only provides parity information to the Local processor during Direct Master, Direct Slave, and DMA transfers. There is one data parity pin for each byte lane of the PCI 9056 data bus (DP[0:3]). "Even data parity" is
2-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Big Endian/Little Endian
Section 2 M Mode Bus Operation
asserted for each lane during Local Bus reads from the PCI 9056 and during PCI 9056 Master writes to the Local Bus. Even data parity is checked during Local Bus writes to the PCI 9056 and during PCI 9056 reads from the Local Bus. Parity is checked for each byte lane with an asserted byte enable. If a parity error is detected, TEA# is asserted in the Clock cycle following the data being checked. Parity is checked for Direct Slave reads, Direct Master writes, and DMA Local Bus reads. The PCI 9056 sets a status bit and asserts an interrupt (TEA#) in the clock cycle following data being checked if a parity error is detected. However, the Data Parity Error Status bit and interrupt are never set or asserted unless the TA# signal is active and asserted low. This applies only when the TA# signal is disabled in the PCI 9056 register. A workaround for this is to disable the TA# Enable bit and externally pull TA# low.
2.3.2
Local Bus Big/Little Endian Mode
The PCI 9056 Local Bus can be programmed to operate in Big or Little Endian mode.
Table 2-10. Byte Number and Lane Cross-Reference
Byte Number Big Endian
3 2 1 0
Little Endian
0 1 2 3
Byte Lane
LD[24:31] LD[16:23] LD[8:15] LD[0:7]
Table 2-11. Big/Little Endian Program Mode
BIGEND# Pin
0 0 1 1
BIGEND Register (1=Big, 0=Little)
0 1 0 1
Endian Mode
Big Big Little Big
2.3 2.3.1
BIG ENDIAN/LITTLE ENDIAN PCI Bus Little Endian Mode
Table 2-12 lists register bits associated with the following cycles.
Table 2-12. Cycle Reference
Cycle
Local access to the Configuration registers Direct Master, Memory, and I/O Direct Slave
PCI Bus is a Little Endian bus (that is, the address is invariant and data is Lword-aligned to the lowermost byte lane).
Table 2-9. PCI Bus Little Endian Byte Lanes
Byte Number
0 1 2 3
Register Bits
BIGEND[0] BIGEND[1] BIGEND[2], Space 0, and BIGEND[3], Expansion ROM
Byte Lane
AD[7:0] AD[15:8] AD[23:16] AD[31:24]
In Big Endian mode, the PCI 9056 transposes data byte lanes. Data is transferred as listed in Table 2-13 through Table 2-17.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-5
Section 2--M Bus Op
Section 2 M Mode Bus Operation
Big Endian/Little Endian
2.3.2.1
32-Bit Local Bus-- Big Endian Mode
2.3.2.2
16-Bit Local Bus-- Big Endian Mode
Data is Lword-aligned to the uppermost byte lane (Data Invariance).
Table 2-13. Upper Lword Lane Transfer-- 32-Bit Local Bus
Burst Order
First transfer
For a 16-bit Local Bus, the PCI 9056 can be programmed to use the upper or lower word lanes.
Table 2-14. Upper Word Lane Transfer-- 16-Bit Local Bus
Burst Order
First transfer
Byte Lane
Byte 3 appears on Local Data [24:31] Byte 2 appears on Local Data [16:23] Byte 1 appears on Local Data [8:15] Byte 0 appears on Local Data [0:7]
Byte Lane
Byte 0 appears on Local Data [24:31] Byte 1 appears on Local Data [16:23]
Second transfer
Byte 2 appears on Local Data [24:31] Byte 3 appears on Local Data [16:23]
Little Endian 31 BYTE 3 BYTE 2 BYTE 1 BYTE 0 0
Table 2-15. Lower Word Lane Transfer-- 16-Bit Local Bus
Burst Order
First transfer
Byte Lane
Byte 0 appears on Local Data [8:15] Byte 1 appears on Local Data [0:7]
Second transfer
Byte 2 appears on Local Data [8:15] Byte 3 appears on Local Data [0:7]
31 BYTE 0 BYTE 1 BYTE 2 BYTE 3
0
31 BYTE 3
Little Endian BYTE 2 BYTE 1
First Cycle
0 BYTE 0
Big Endian
Figure 2-2. Big/Little Endian--32-Bit Local Bus
15
Second Cycle
0 BYTE 0 BYTE 1 0 Big Endian
31 BYTE 0 15 Big Endian BYTE 1
15 16 0
Figure 2-3. Big/Little Endian--16-Bit Local Bus
2-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 2 M Mode Bus Operation
2.3.2.3
8-Bit Local Bus-- Big Endian Mode
2.3.2.4
Local Bus Big/Little Endian Mode Accesses
For an 8-bit Local Bus, the PCI 9056 can be programmed to use upper or lower byte lanes.
Table 2-16. Upper Byte Lane Transfer-- 8-Bit Local Bus
Burst Order
First transfer Second transfer Third transfer Fourth transfer
For each of the following transfer types, the PCI 9056 Local Bus can be independently programmed to operate in Little Endian or Big Endian mode: * Local Bus accesses to the PCI 9056 Configuration registers * Direct Slave PCI accesses to Local Address Space 0 * Direct Slave PCI accesses to Local Address Space 1 * Direct Slave PCI accesses to the Expansion ROM * DMA Channel 0 accesses to the Local Bus * DMA Channel 1 accesses to the Local Bus * Direct Master accesses to the PCI Bus For Local Bus accesses to the Internal Configuration registers and Direct Master accesses, use BIGEND# to dynamically change the Endian mode.
Notes: The PCI Bus is always Little Endian. Only byte lanes are swapped, not individual bits.
Byte Lane
Byte 0 appears on Local Data [24:31] Byte 1 appears on Local Data [24:31] Byte 2 appears on Local Data [24:31] Byte 3 appears on Local Data [24:31]
Table 2-17. Lower Byte Lane Transfer-- 8-Bit Local Bus
Burst Order
First transfer Second transfer Third transfer Fourth transfer
Byte Lane
Byte 0 appears on Local Data [0:7] Byte 1 appears on Local Data [0:7] Byte 2 appears on Local Data [0:7] Byte 3 appears on Local Data [0:7]
31 BYTE 3
Little Endian BYTE 2 BYTE 1
Second Cycle
2.4
0 BYTE 0
First Cycle
SERIAL EEPROM
Functional operation described can be modified through the PCI 9056 programmable internal registers.
Fourth Cycle
Third Cycle
7 BYTE 0
0 0
2.4.1
Vendor and Device ID Registers
Three Vendor and Device ID registers are supported: * PCIIDR--Contains normal Device and Vendor IDs. Can be loaded from the serial EEPROM or by the Local processor(s). * PCISVID--Contains Subsystem and Subvendor IDs. Can be loaded from the serial EEPROM or by the Local processor(s). * PCIHIDR--Contains hardwired PLX Vendor and Device IDs.
15 23
16 7 BYTE 0 31 24 7 0 BYTE 0 Big Endian 7 0
8 7 BYTE 0 0
Figure 2-4. Big/Little Endian--8-Bit Local Bus
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-7
Section 2--M Bus Op
Section 2 M Mode Bus Operation
Serial EEPROM
2.4.1.1
Serial EEPROM Initialization
During serial EEPROM initialization, the PCI 9056 responds to Direct Slave accesses with a Retry. During serial EEPROM initialization, the PCI 9056 responds to a Local processor access by delaying acknowledgement of the cycle (TA#).
2.4.1.2
Local Initialization
Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of this section.
2.4.2
Serial EEPROM Operation
After reset, the PCI 9056 attempts to read the serial EEPROM to determine its presence. An active Start bit set to 0 indicates a serial EEPROM is present. The PCI 9056 supports 2K bit (FM93CS56L or compatible) or 4K bit (FM93CS66L or compatible) devices. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The first Lword is then checked to verify that the serial EEPROM is programmed. If the first Lword (33 bits) is all ones (1), a blank serial EEPROM is present. If the first Lword (33 bits) is all zeros, no serial EEPROM is present. For both conditions, the PCI 9056 reverts to the default values. (Refer to Table 2-18.) The Programmed Serial EEPROM Present bit is set (CNTRL[28]=1) if the serial EEPROM is programmed (real or random data if a serial EEPROM is detected). The 3.3V serial EEPROM clock (EESK) is derived from the PCI clock. The PCI 9056 generates the serial EEPROM clock by internally dividing the PCI clock by 268. For a 66.6 MHz PCI Bus, EESK is 248.7 kHz; for a 33.3 MHz PCI Bus, EESK is 124.4 kHz. The serial EEPROM can be read or written from the PCI or Local Buses. The Serial EEPROM Control Register bits (CNTRL[31, 27:24]) control the PCI 9056 pins that enable reading or writing of serial EEPROM data bits. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The PCI 9056 provides the ability to manually access the serial EEPROM interface by using CNTRL[31,
2-8
Preliminary Information
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 2 M Mode Bus Operation
27:24] (EESK, EECS, and EEDI/EEDO, controlled by software). Bit 24 is used to generate EESK (clock), bit 25 controls the chip select, and bit 31 enables the EEDO input buffer. Bit 27, when read, returns the value of EEDO. Setting bits [31, 25, 24] to 1 causes the EEDI output to go high. A pull-up resistor is required on EEDO to go high when bit 31 is set. When reading the serial EEPROM, bit 31 must be set to 1. To perform the read, the basic approach is to set the EECS and EEDO bits (bits 25 and 31, respectively) to the desired level and then toggle EESK high and low until done. For example, reading the serial EEPROM at location 0 involves the following steps: 1. Clear EESK, EEDO and EECS bits. 2. Set EECS high. 3. Toggle EESK high, then low. 4. Set EEDO bit high (start bit). 5. Toggle EESK high, then low. 6. Repeat step 5. 7. Clear EEDO.
Table 2-18. Serial EEPROM Guidelines
Local Processor
None
8. Toggle EESK high, then low. 9. Toggle EESK bit high, then low 8 times (clock in serial EEPROM Address 0). 10. Set bit 31 to float the EEDO pin for reading. 11. Toggle EESK high, then low 16 times (clock in one word from serial EEPROM). 12. After each clock pulse, read bit 27 and save. 13. Clear EECS bit. 14. Toggle EESK high, then low. 15. Read is now complete. The serial EEPROM can also be read or written, using the VPD function. (Refer to Section 10.) The PCI 9056 has two serial EEPROM load options: * Long Load Mode--Default. The PCI 9056 loads 17 Lwords from the serial EEPROM if the Extra Long Load from the Serial EEPROM bit is clear (LBRD0[25]=0)
Section 2--M Bus Op
2-9
* Extra Long Load Mode--The PCI 9056 loads 23 Lwords from the serial EEPROM if the Extra Long Load from the Serial EEPROM bit is set (LBRD0[25]=1) during a Long Load
Serial EEPROM
None
System Boot Condition
The PCI 9056 uses default values. The EEDI/EEDO pin must be pulled low--a 1K ohm resistor is required (rather than pulled high, which is typically done for this pin). If the PCI 9056 detects all zeros, it reverts to default values. Boot with serial EEPROM values. The Local Init Status bit (LMISC1[2]) must be set by the serial EEPROM. A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO. The PCI 9056 detects a blank device and reverts to default values. A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO. Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of this table entry.
None
Programmed
None Present
Blank None
Present
Programmed
Load serial EEPROM, but the Local processor can reprogram the PCI 9056. Either the Local processor or the serial EEPROM must set the Local Init Status bit (LMISC1[2]=done). A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO. The PCI 9056 detects a blank serial EEPROM and reverts to default values. A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO.
Notes: In some systems, the Local processor may be overly late to reconfigure the PCI 9056 registers before the BIOS configures them. The serial EEPROM can be programmed through the PCI 9056 after the system boots in this condition.
Present
Blank
Note: If the serial EEPROM is missing and a Local Processor is present with blank Flash, the condition None/None (as seen in Table
2-18) applies, until the Processor's Flash is programmed.
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Preliminary Information
Section 2 M Mode Bus Operation
Serial EEPROM
2.4.2.1
Long Serial EEPROM Load
The registers listed in Table 2-19 are loaded from the serial EEPROM after a reset is de-asserted if the Extra Long Load from Serial EEPROM bit is not set (LBRD0[25]=0). The serial EEPROM is organized in words (16 bit). The PCI 9056 first loads the Most Significant Word bits (MSW[31:16]), starting from the Most Significant bit (MSB[31]). The PCI 9056 then loads the Least Significant Word bits (LSW[15:0]), starting again from the Most Significant bit (MSB[15]). Therefore, the PCI 9056 loads the Device ID, Vendor ID, Class Code, and so forth.
The serial EEPROM values can be programmed using an EEPROM programmer. The values can also be programmed using the PCI 9056 VPD function (refer to Section 10) or through the Serial EEPROM Control register (CNTRL). The CNTRL register allows programming of the serial EEPROM, one bit at a time. To read back the value from the serial EEPROM, the CNTRL[27] bit (refer to Section 2.4.2) or the VPD function should be utilized. With full utilization of VPD, the designer can perform reads and writes from/to the serial EEPROM, 32 bits at a time. Values should be programmed in the order listed in Table 2-19. The 34, 16-bit words listed in the table are stored sequentially in the serial EEPROM.
2-10
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 2 M Mode Bus Operation
Table 2-19. Long Serial EEPROM Load Registers
Serial EEPROM Offset
0h 2h 4h 6h 8h Ah Ch Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h Device ID Vendor ID Class Code Class Code / Revision Maximum Latency / Minimum Grant Interrupt Pin / Interrupt Line Routing MSW of Mailbox 0 (User Defined) LSW of Mailbox 0 (User Defined) MSW of Mailbox 1 (User Defined) LSW of Mailbox 1 (User Defined) MSW of Range for PCI-to-Local Address Space 0 LSW of Range for PCI-to-Local Address Space 0 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 MSW of Mode/DMA Arbitration Register LSW of Mode/DMA Arbitration Register MSW of Local Miscellaneous Control Register 2 / MSW of Serial EEPROM Write-Protected Address LSW of Local Miscellaneous Control Register 1/ LSW of Local Bus Big/Little Endian Descriptor Register MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM MSW of Bus Region Descriptors for PCI-to-Local Accesses LSW of Bus Region Descriptors for PCI-to-Local Accesses MSW of Range for Direct Master-to-PCI LSW of Range for Direct Master-to-PCI MSW of Local Base Address for Direct Master-to-PCI Memory LSW of Local Base Address for Direct Master-to-PCI Memory MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration MSW of PCI Base Address (Remap) for Direct Master-to-PCI LSW of PCI Base Address (Remap) for Direct Master-to-PCI MSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration LSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration
Description
Register Bits Affected
PCIIDR[31:16] PCIIDR[15:0] PCICCR[23:8] PCICCR[7:0] / PCIREV[7:0] PCIMLR[7:0] / PCIMGR[7:0] PCIIPR[7:0] / PCIILR[7:0] MBOX0[31:16] MBOX0[15:0] MBOX1[31:16] MBOX1[15:0] LAS0RR[31:16] LAS0RR[15:0] LAS0BA[31:16] LAS0BA[15:0] MARBR[31:16] MARBR[15:0] LMISC2[7:0] / PROT_AREA[7:0] LMISC1[7:0] / BIGEND[7:0] EROMRR[31:16] EROMRR[15:0] EROMBA[31:16] EROMBA[15:0] LBRD0[31:16] LBRD0[15:0] DMRR[31:16] DMRR[15:0] DMLBAM[31:16] DMLBAM[15:0] DMLBAI[31:16] DMLBAI[15:0] DMPBAM[31:16] DMPBAM[15:0] DMCFGA[31:16] DMCFGA[15:0]
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-11
Section 2--M Bus Op
Section 2 M Mode Bus Operation
Serial EEPROM
2.4.2.2
Extra Long Serial EEPROM Load
bit (MSB[15]). Therefore, the PCI 9056 loads Device ID, Vendor ID, class code, and so forth. The serial EEPROM values can be programmed using a Data I/O programmer. The values can also be programmed using the PCI 9056 VPD function or through the Serial EEPROM Control register (CNTRL). Values should be programmed in the order listed in Table 2-20. The 46 16-bit words listed in Table 2-19 and Table 2-20 should be stored sequentially in the serial EEPROM.
The registers listed in Table 2-19 and Table 2-20 are loaded from serial EEPROM after a reset is de-asserted if the Extra Long Load from Serial EEPROM bit is set (LBRD0[25]=1). The serial EEPROM is organized in words (16 bit). The PCI 9056 first loads the Most Significant Word bits (MSW[31:16]), starting from the Most Significant bit (MSB[31]). It then loads the Least Significant Word bits (LSW[15:0]), restarting from the Most Significant
Table 2-20. Extra Long Serial EEPROM Load Registers
Serial EEPROM Offset
44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah Subsystem ID Subsystem Vendor ID MSW of Range for PCI-to-Local Address Space 1 (1 MB) LSW of Range for PCI-to-Local Address Space 1 (1 MB) MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 MSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses LSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses MSW of Hot Swap Control/Status LSW of Hot Swap Control / Hot Swap Next Capability Pointer PCI Arbiter Control Reserved
Description
Register Bits Affected
PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS1BA[31:16] LAS1BA[15:0] LBRD1[31:16] LBRD1[15:0] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] PCIARB[3:0] Reserved
2-12
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 2 M Mode Bus Operation
2.4.2.3
New Capabilities Function Support
2.4.3
Internal Register Access
The New Capabilities Function Support includes PCI Power Management, Hot Swap, and VPD features, as listed in Table 2-21.
Table 2-21. New Capabilities Function Support Features
New Capability Function
First (Power Management) Second (Hot Swap)
The PCI 9056 provides several internal registers, which allow for maximum flexibility in the bus interface design and performance. These registers are accessible from the PCI and Local Buses (refer to Figure 2-6) and include the following: * PCI and Local Configuration registers * DMA registers * Mailbox registers * PCI-to-Local and Local-to-PCI Doorbell registers * Messaging Queue registers (I2O) * Power Management registers * Hot Swap registers * VPD registers
PCI Bus Master Local Bus Master
PCI Register Offset Location
40h, if the New Capabilities Function Support bit (PCISR[4]) is enabled (PCISR[4] is enabled, by default). 48h, which is pointed to from PMNEXT[7:0]. 4Ch, which is pointed to from HS_NEXT[7:0]. Because PVPD_NEXT[7:0] defaults to zero (0), this indicates that VPD is the last New Capability Function Support feature of the PCI 9056.
Third (VPD)
PCI 9056
PCI Configuration Registers Local Configuration Registers DMA Registers Mailbox Registers
2.4.2.4
Recommended Serial EEPROMs
The PCI 9056 is designed to use either a 2K bit (FM93CS56L or compatible) or 4K bit (FM93CS66L or compatible) device.
PCI Interrupt
Set Clear
PCI-to-Local Doorbell Register Local-to-PCI Doorbell Register Messaging Queue Registers
4096
100h
Set
2048 VPD 1536 Empty 704 Extra Long 544 Long Load 0 # of bits
80h
Power Management Registers Hot Swap Registers VPD Registers
60h (PROT_AREA register default)
2Eh
Figure 2-6. PCI 9056 Internal Register Access
22h
0 # of words
Figure 2-5. Serial EEPROM Memory Map
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-13
Local Interrupt
Note: The PCI 9056 does not support serial EEPROMs that do not support sequential reads (such as the FM93C56L).
Clear
Section 2--M Bus Op
Section 2 M Mode Bus Operation
Serial EEPROM
2.4.3.1
PCI Bus Access to Internal Registers
2.4.3.2
Local Bus Access to Internal Registers
The PCI 9056 PCI Configuration registers can be accessed from the PCI Bus with a Configuration Type 0 cycle. All other PCI 9056 internal registers can be accessed by a Memory cycle, with the PCI Bus address that matches the base address specified in PCI Base Address 0 (PCIBAR0[31:8]) for the PCI 9056 Memory-Mapped Configuration register. These registers can also be accessed by an I/O cycle, with the PCI Bus address matching the base address specified in PCI Base Address 1 for the PCI 9056 I/ O-Mapped Configuration register (PCIBAR1). All PCI Read or Write accesses to the PCI 9056 registers can be Byte, Word, or Lword accesses. All PCI Memory accesses to the PCI 9056 registers can be Burst or Non-Burst accesses. The PCI 9056 responds with a PCI disconnect for all Burst I/O accesses (PCIBAR1[31:8]) to the PCI 9056 Internal registers.
The Local processor can access all PCI 9056 internal registers through an external chip select. The PCI 9056 responds to a Local Bus access when the PCI 9056 Configuration Chip Select input (CCS#) is asserted low. Figure 2-7 illustrates how the Configuration Chip Select logic works.
Notes: CCS# must be decoded while TS# is low. Accesses must be for a 32-bit non-pipelined bus.
Local Read or Write accesses to the PCI 9056 internal registers can be Byte, Word, or Lword accesses. The Local Bus width must be 32-bit to access the internal registers. Eight and 16-bit data buses require external latches to form a 32-bit data path for Local Bus access to internal registers. Local accesses to the PCI 9056 internal registers can be Burst or Non-Burst accesses. The PCI 9056 TA# signal indicates that Data transfer is complete.
Address Mode Pin PCI 9056
CCS# (PCI 9056 Chip Select)
PCI 9056 Internal Register Chip Select
Figure 2-7. Address Decode Mode
2-14
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 2 M Mode Bus Operation
2.4.4
Serial EEPROM and Configuration Initialization Timing Diagrams
Note: In the timing diagrams that follow, the "_" symbol at the end of the signal names represents the "#" symbol.
0us
10us
20us
30us
EESK LRESET# EECS EEDI EEDO
1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 0 D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 BITS [31:16] CONFIGURATION REGISTER 0 HEX D0
INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----|
EEDO
D15 D14 D13 D12D11 D10 D9 D8 D7 D6
D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] OF CONFIGURATION REGISTER 8 HEX
BITS [15:0] CONFIGURATION REGISTER 0 HEX
CONTINUES
EESK (continues) EECS EEDO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EESK, EEDO, EECS STATUS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ
CONTINUES
Timing Diagram 2-1. Initialization from Serial EEPROM (2K or 4K Bit)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-15
Section 2--M Bus Op
EESK
Section 2 M Mode Bus Operation
Serial EEPROM
Timing Diagram 2-2. Local Interrupt Asserting PCI Interrupt
2-16
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 2 M Mode Bus Operation
Timing Diagram 2-3. PCI Configuration Write to PCI Configuration Register
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-17
Section 2--M Bus Op
Section 2 M Mode Bus Operation
Serial EEPROM
Timing Diagram 2-4. PCI Configuration Read to PCI Configuration Register
2-18
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 2 M Mode Bus Operation
Timing Diagram 2-5. Local Configuration Write to Configuration Register (M Mode)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
2-19
Section 2--M Bus Op
Section 2 M Mode Bus Operation
Serial EEPROM
Timing Diagram 2-6. Local Configuration Read from Configuration Register (M Mode)
2-20
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
3
M MODE FUNCTIONAL DESCRIPTION
set (CNTRL[30]=1), or the PCI 9056 initiates an external reset.
The functional operation described in this chapter can be modified through the PCI 9056 programmable internal registers.
3.1.2.2 3.1 3.1.1 3.1.1.1 RESET OPERATION Adapter Mode PCI Bus Input RST#
Local LRESET#
When the Local LRESET# pin is asserted by an external source, the Local Bus interface circuitry, the configuration registers, and the PCI 9056 are reset. The PCI 9056 drives the Local LRESET# pin after it detects a reset for 62 clocks.
The PCI Bus RST# input pin is a PCI Host reset. It causes all PCI Bus outputs to float, resets the entire PCI 9056 and causes the Local LRESET# signal to be asserted.
3.1.2.3
Software Reset
When the Software Reset bit is set (CNTRL[30]=1), the following occurs: * PCI Master logic is held reset * PCI 9056 PCI Configuration registers held in reset * FIFOs are reset * PCI RST# pin is asserted Only the PCI Configuration registers are in reset. A software reset can only be cleared from another Host on the Local Bus, and the PCI 9056 remains in this reset condition until a Local Host clears the bit.
Note: The PCI Bus cannot clear this reset bit because the PCI Bus is in a reset state.
3.1.1.2
Software Reset
3.1.2.4
Power Management Reset
Note: The Local Bus cannot clear this reset bit because the Local Bus is in a reset state, even if the Local processor does not use LRESET# to reset.
Power Management reset is not applicable for Host mode.
3.1.1.3
Power Management Reset
3.2
PCI 9056 INITIALIZATION
When the power management reset is asserted (transition from D3 to any other state), the PCI 9056 resets as if a PCI reset was asserted. (Refer to Section 8, "PCI Power Management.")
The PCI 9056 Configuration registers can be programmed by an optional serial EEPROM and/or by a Local processor, as listed in Table 2-18, "Serial EEPROM Guidelines," on page 2-9. The serial EEPROM can be reloaded by setting the Reload Configuration Registers bit (CNTRL[29]). The PCI 9056 retries all PCI cycles until the Local Init Status bit is set to "done" (LMISC1[2]=1).
Note: The PCI Host processor can also access Internal Configuration registers after the Local Init Status bit is set.
3.1.2 3.1.2.1
Host Mode PCI Reset
The PCI Bus RST# output is driven when the Local LRESET# signal is asserted, the Software Reset bit is
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-1
Section 3--M Func Desc
A Host on the PCI Bus can set the PCI Adapter Software Reset bit (CNTRL[30]=1) to reset the PCI 9056 and assert LRESET# output. All Local Configuration registers are reset; however, the PCI Configuration DMA and Shared Runtime registers and the Local Init Status bit (LMISC1[2]) are not reset. When the Software Reset bit (CNTRL[30]) is set, the PCI 9056 responds to PCI accesses, but not to Local Bus accesses. The PCI 9056 remains in this reset condition until the PCI Host clears the bit. The serial EEPROM is reloaded, if the Reload Configuration Registers bit is set (CNTRL[29]=1).
Section 3 M Mode Functional Description
Response to FIFO Full or Empty
If a PCI Host is present, the Master Enable, Memory Space, and I/O Space bits (PCICR[2:0], respectively) are programmed by that Host after initialization completes (LMISC1[2]=1).
3.4.1
Direct Master Operation (Local Master-to-Direct Slave)
3.3
RESPONSE TO FIFO FULL OR EMPTY
The PCI 9056 supports a direct access to the PCI Bus by the Local processor or an intelligent controller. Master mode must be enabled in the PCI Command register. The following registers define Local-to-PCI accesses: * Direct Master Memory and I/O Range (DMRR) * Local Base Address for Direct Master-to-PCI Memory (DMLBAM) * Local Base Address for Direct Master-to-PCI I/O and Configuration (DMLBAI) * PCI Base Address (DMPBAM) * Direct Master Configuration (DMCFGA) * Direct Master PCI Dual Address Cycles (DMDAC) * Master Enable (PCICR) * PCI Command Code (CNTRL)
Table 3-1 lists the PCI 9056 response to full and empty FIFOs.
3.4
DIRECT DATA TRANSFER MODES
The PCI 9056 supports three direct transfer modes: * Direct Master--Local CPU accesses PCI memory or I/O * Direct Slave--PCI Master accesses Local memory or I/O * DMAPCI 9056 DMA controller reads/writes PCI memory to/from Local memory
Table 3-1. Response to FIFO Full or Empty
Mode
Direct Master Write
Direction
Local-to-PCI
FIFO
Full Empty Full Empty Full Empty Full Empty Full Empty Full Empty Normal
PCI Bus
De-assert REQ# (off the PCI Bus) De-assert REQ# or throttle IRDY# Normal Disconnect or throttle TRDY#3 Normal Normal Throttle TRDY#3 Normal De-assert REQ# De-assert REQ# Normal
2
Local Bus
De-assert TA#, RETRY#1 Normal Normal De-assert TA# Normal De-assert BB#4 De-assert BB#4 Normal De-assert BB#4 Normal Normal De-assert BB#4
Direct Master Read
PCI-to-Local
Direct Slave Write
PCI-to-Local
Direct Slave Read
Local-to-PCI
Local-to-PCI DMA PCI-to-Local
1. Issue
RETRY# depends upon the Direct Master Write FIFO Almost Full RETRY# Output Enable bit (LMISC1[6]). 2. Throttle IRDY# depends upon the Direct Master PCI Read Mode bit (DMPBAM[4]). 3. Throttle TRDY4 depends upon the Direct Slave PCI Write Mode bit (LBRD0[27]). 4. BB# de-assert depends upon the Local Bus Direct Slave Release Bus Mode bit (MARBR[21]).
3-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
Section 3 M Mode Functional Description
PCI Bus Master
Local Processor
1
Initialize Local Direct Master Access Registers
Local Range for Direct Master-to-PCI Local Base Address for Direct Master-to-PCI Memory PCl Base Address (Remap) for Direct Master-to-PCI Local Base Address for Direct Master-to-PCI I/O Configuration
I/O or Configuration 0 = I/O 1 = Configuration
PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration PCI Command Register
3
PCI Bus Access
2 FIFOs
64-Lword Deep Write 32-Lword Deep Read Local Base Address for Direct Masterto-PCI Memory Space Local Bus Access
Local Memory PCI Address Space
PCI Base Address Memory Command
Range
Local Base Address for Direct Master-toPCI I/O Configuration
I/O Command
Figure 3-1. Direct Master Access to the PCI Bus
3.4.1.1
Direct Master Memory and I/O Decode
The Direct Master Range register and the Local Base Address register specifies the Local Address bits to use for decoding a Local-to-PCI access (Direct Master). The range of Memory or I/O space must be a power of 2 and the Range register value must be the 2's complement of the range value. In addition, the Local Base Address must be a multiple of the range value. Any Local Master Address starting from the Direct Master Local Base Address (Memory or I/O) to the range value is recognized as a Direct Master access by the PCI 9056. All Direct Master cycles are then
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
decoded as PCI Memory, I/O, or Configuration Type 0 or Type 1. Moreover, a Direct Master Memory or I/O cycle is remapped according to the Remap register value. The Remap Register value must be a multiple of the Direct Master Range value (not the Range register value). The PCI 9056 can only accept Memory cycles from a Local processor. The Local Base Address and/or the range determine whether PCI Memory or PCI I/O transactions occur.
3.4.1.2
Direct Master FIFOs
For Direct Master Memory access to the PCI Bus, the PCI 9056 has a 64-Lword (256-byte) Write FIFO and a
Preliminary Information
3-3
Section 3--M Func Desc
Range
Section 3 M Mode Functional Description
Direct Data Transfer Modes
32-Lword (128-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus and allows high-performance bursting on the PCI and Local Buses. In a Direct Master write, the Local processor (Master) writes data to the PCI Bus (Slave). In a Direct Master read, the Local processor (Master) reads data from the PCI Bus (Slave). The FIFOs that function during a Direct Master write and read are illustrated in Figure 3-2 and Figure 3-3.
the PCI 9056 appear as Direct Master operations. (Refer to Section 3.4.2 for further information.) Transactions are initiated by the MPC850 or MPC860 (a Local Bus Master) when the memory address on the Local Bus matches the Memory space decoded for Direct Master operations. Upon a Local Bus Read, the PCI 9056 becomes a PCI Bus Master, arbitrates for the PCI Bus, and reads data from the PCI Slave device directly into the Direct Master Read FIFO. When sufficient data is placed into the FIFO, it asserts the Transfer Acknowledge (TA#) signal onto the Local Bus to indicate that the requested data is on the Local Bus. The Local processor can read or write to PCI memory. The PCI 9056 converts the Local Read/Write access. The Local Address space starts from Direct Master Local Base Address up to the range. Remap (PCI Base Address) defines the PCI starting address. The PCI 9056 supports single and Burst cycles performed by the MPC850 or MPC860 processor. An MPC850 or MPC860 single cycle causes a single cycle PCI transaction. An MPC850 or MPC860 Burst cycle asserts a Burst cycle PCI transaction. Bursts are limited to 16 bytes (four Lwords) in the MPC850 or MPC860 bus protocol. The PCI 9056 supports bursts beyond the 16-byte boundary (Continuous Burst) when the BDIP# input signal remains asserted beyond a 16-byte boundary by an external Local Bus Master. To finish, the continuing burst and external Master should de-assert the BDIP# signal on the last Data phase. Writes--Upon a Local Bus Write, the Local Bus Master writes data to the Direct Master Write FIFO. When the first data is in the FIFO, the PCI 9056 becomes the PCI Bus Master, arbitrates for the PCI Bus, and writes data to the PCI Slave device. The PCI 9056 continues to accept writes and returns TA# until the Write FIFO is full. It then holds off TA# until space becomes available in the Write FIFO. A programmable Direct Master "almost full" status output is provided (MDREQ#/DMPAF). The PCI 9056 asserts RETRY# whenever the Direct Master Write FIFO is full, implying that the Local Master can relinquish the bus and finish the Write operation at a later time (LMISC1[6]).
Slave
Master
Slave
LA, TS#, TSIZ, LD, RD/WR#, BURST#, BI#, BDIP#
Master
REQ#
TA#
PCI Bus
GNT# FRAME#, C/BE# AD (addr) IRDY# DEVSEL#, TRDY# AD (data)
PCI 9056
RETRY#, TEA# (Optional)
Figure 3-2. Direct Master Write
Slave
Master
Slave
TS#, BI#, RD/WR#, TSIZ, BURST#, BDIP#
Master
REQ# GNT#
IRDY# DEVSEL#, TRDY#, AD (data)
PCI 9056
LD, TA# RETRY#, TEA# (Optional)
Figure 3-3. Direct Master Read
Note: Figures 3-2 and 3-3 represent a sequence of Bus cycles.
3.4.1.3
Direct Master Memory Access
The MPC850 or MPC860 transfers data through a single or burst Read/Write Memory transaction, or through SDMA channels to the PCI 9056 and PCI Bus. The MPC850 or MPC860 IDMA/SDMA accesses to
Local Bus
PCI Bus
FRAME#, C/BE#, AD (addr)
Local Bus
3-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
Section 3 M Mode Functional Description
MPC850 or MPC860 single cycle Write transactions result in PCI 9056 transfers of one Lword of data onto a 32-bit PCI Bus. MPC850 or MPC860 Burst Cycle Write transactions of four Lwords result in PCI 9056 Burst transfers of four Lwords to a 32-bit PCI Bus. A Local processor (MPC850 or MPC860), with no burst limitations and a Burst Cycle Write transaction of two Lwords, results in PCI 9056 burst transfers of two Lwords to a 32-bit PCI Bus. Three Lword (or more) Burst cycles of any type result in the PCI 9056 bursting data onto the PCI Bus. Reads--The PCI 9056 holds off TA# while gathering an Lword from the PCI Bus. Programmable Prefetch modes are available if prefetch is enabled to prefetch, 4, 8, 16, or continuous data until the Direct Master cycle ends. The Read cycle is terminated when the Local BDIP# input is de-asserted. Unused Read data is flushed from the FIFO. The PCI 9056 does not prefetch Read PCI data for single cycle Direct Master reads (Local BURST# input is not asserted during the first Data phase). In this case, for the 32-bit PCI Bus, the PCI 9056 reads a single PCI Lword unless Direct Master Read Ahead mode is enabled. For single cycle Direct Master reads, the PCI 9056 passes the corresponding PCI Bus byte enables from the Local Bus address and the TSIZ[0:1] signal. For Burst Cycle reads, the PCI 9056 reads entire Lwords (all PCI Bus byte enables are asserted). If the Direct Master Prefetch Limit bit is enabled (DMPBAM[11]=1), the PCI 9056 terminates a read prefetch at 4-KB boundaries and restarts it as a new PCI Read Prefetch cycle at the start of a new boundary. If the bit is disabled, the prefetch crosses the 4-KB boundaries.
Local Burst accesses are broken into single PCI I/O (address/data) cycles. The PCI 9056 does not prefetch Read data for I/O and Configuration reads. For Direct Master I/O or Configuration cycles, the PCI 9056 asserts the same PCI Bus byte enables as set on the Local Bus.
3.4.1.5
Direct Master I/O
If the Configuration Enable bit is cleared (DMCFGA[31]=0), a single I/O access is made to the PCI Bus. The Local Address, Remapped Decode Address bits, and Local byte enables are encoded to provide the address and are output with an I/O Read or Write command during a PCI Address cycle. For writes, data is loaded into the Write FIFO and TA# is returned to the Local Bus. For reads, the PCI 9056 holds off TA# while receiving an Lword from the PCI Bus.
3.4.1.6
Direct Master Delayed Write Mode
The PCI 9056 only utilizes the delay counter and accumulates data in the Direct Master Write FIFO for burst transactions on the Local Bus. Otherwise, an immediate single cycle PCI transfer occurs.
3.4.1.7
Direct Master Read Ahead Mode
3.4.1.4
Direct Master I/O Configuration Access
When a Local Direct Master I/O access to the PCI Bus occurs, the PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration Enable bit (DMCFGA[31]) determines whether an I/O or Configuration access is to be made to the PCI Bus.
The PCI 9056 also supports Direct Master Read Ahead mode (DMPBAM[2]), where prefetched data can be read from the internal FIFO of the PCI 9056 instead of from the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4) for 32-bit Direct Slave transfers. Read Ahead mode functions can be used with or without Delayed Read mode.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-5
Section 3--M Func Desc
The PCI 9056 supports Direct Master Delayed Write mode transactions, where posted Write data accumulates in the Direct Master Write FIFO before the PCI 9056 requests the PCI Bus. Direct Master Delayed Write mode is programmable to delay REQ# assertion for the number of PCI clocks specified in DMPBAM[15:14]. This feature is useful for gaining higher throughput during Direct Master Write Burst transactions for conditions in which the Local clock frequency is slower than the PCI clock frequency.
Section 3 M Mode Functional Description
Direct Data Transfer Modes
A Local Bus single cycle Direct Master transaction, with Read Ahead Mode (DMPBAM[2]) enabled results in the PCI 9056 processing continuous PCI Bus Read burst data with all bytes enabled (C/BE# = 0h).
Local Bus
Local Read request Read Ahead mode is set in Internal Registers
available to the Local Bus). In this mode, it is required that a Local Processor returns and reads at least one data. Otherwise, the PCI 9056 indefinitely retries a Local Bus.
PCI 9056
PCI Bus
PCI 9056 prefetches data from PCI Bus device
3.4.1.9
Direct Master Configuration (PCI Configuration Type 0 or Type 1 Cycles)
Read data Local Bus Master Read returns with "Sequential Address" Prefetched data is stored in the internal FIFO PCI 9056 returns prefetched data immediately from internal FIFO without reading again from the PCI Bus
PCI 9056 prefetches more data if FIFO space is available
Read data
PCI 9056 prefetches more data from Local memory
If the Configuration Enable bit is set (DMCFGA[31]=1), and a Direct Master access is made to the Local Bus address programmed in DMLBAM, a Configuration access is made to the PCI Bus. In addition to enabling configuration of this bit, the user must provide all register information. The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/Write cycle must be performed before accessing other registers or devices. If the PCI Configuration Address register selects a Type 0 command, register bits [10:0] are copied to address bits [10:0]. Bits [15:11] (device number) are translated into a single bit being set in the PCI Address bits [31:11]. The PCI Address bits [31:11] can be used as a device select. For a Type 1 command, bits [23:0] are copied from the register to PCI address bits [23:0]. The PCI Address bits [31:24] are set to 0. A configuration Read or Write command code is output with the address during the PCI Address cycle. (Refer to the DMCFGA register.) For writes, Local data is loaded into the Write FIFO and TA# is returned. For reads, the PCI 9056 holds off TA# while gathering an Lword from the PCI Bus.
Figure 3-4. Direct Master Read Ahead Mode
Note: Figure 3-4 represents a sequence of Bus cycles.
3.4.1.8
RETRY# Capability
3.4.1.8.1 Direct Master Write FIFO Full
The PCI 9056 supports the Direct Master Write FIFO full condition. When enabled (LMISC1[6]=1), the PCI 9056 asserts the RETRY# signal to the Local Bus Master to relinquish ownership of the bus and return to finish the initial write at a later time. In a Direct Master Write FIFO full condition, the PCI 9056 asserts the RETRY# signal. Otherwise, the Direct Master Write transfer goes through successfully.
3.4.1.9.1 Direct Master Configuration Cycle Example
To perform a Configuration Type 0 cycle to PCI device on AD[21]: 1. The PCI 9056 must be configured to allow Direct Master access to the PCI Bus. The PCI 9056 must also be set to respond to I/O Space accesses. These bits must be set (PCICR[2:0]=111b). In addition, Direct Master memory and I/O access must be enabled (DMPBAM[1:0]=11).
3.4.1.8.2 Direct Master Delayed Read
The PCI 9056 supports Direct Master Delayed Read transactions. When the M Mode Direct Master Deferred Read Enable bit is set (LMISC1[4]=1), the PCI 9056 asserts RETRY# and prefetches Read data every time the Local Master requests a read. During a PCI data prefetch, the Local Master is capable of doing other transactions and free to return for requested data at a later time. When Delayed Direct Master Read mode is disabled, the Local Master must retain the Local Bus and wait for the requested data (TA# is not asserted until data is
3-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
Section 3 M Mode Functional Description
2. The Local Memory map selects the Direct Master range. For this example, use a range of 1 MB: 1 MB = 220 = 00100000h 3. The value to program into the Range register is the 2's complement of 00100000h (FFF00000h): DMRR = FFF00000h 4. The Local Memory map determines the Local Base Address for the Direct Master-to-PCI I/O Configuration register. For this example, use 40000000h: DMLBAI = 40000000h 5. The PCI Address (Remap) for Direct Master-to-PCI Memory register must enable the Direct Master I/O access. The Direct Master I/O Access Enable bit must be set (DMPBAM[1]=1). 6. The user must know which PCI device and PCI Configuration register the PCI Configuration cycle is accessing. This example assumes the IDSEL signal of the Target PCI device is connected to AD[21] (logical device #10=0Ah). It also assumes access is to PCIBAR0 (the fourth register, counting from 0. Use Table 11-2 for reference). Set DMCFGA[31, 23:0] as follows:
Bit
1:0
After these registers are configured, a simple Local Master Memory cycle to the I/O Base Address is necessary to generate a PCI Configuration Read or Write cycle. An offset to the Base Address is not necessary because the register offset for the read or write is specified in the Configuration register. The PCI 9056 takes the Local Bus Master Memory cycle and checks for the Configuration Enable bit (DMCFGA[31]). If set, the PCI 9056 converts the current cycle to a PCI Configuration cycle, using the DMCFGA register and the Write/Read signal (RD/WR#). The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/Write cycle must be performed before accessing other registers or devices.
3.4.1.10
Direct Master PCI Dual Address Cycle
Description
Configuration Type 0. Register Number. Fourth register. Must program a "4" into this value, beginning with bit 2. Function Number. Device Number n-11, where n is the value in AD[n]=21-11 = 10. Bus Number. Configuration Enable.
Value
00b
7:2
000100b
10:8 15:11 23:16 31
000b 01010b 00000000b 1
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-7
Section 3--M Func Desc
The PCI 9056 supports PCI Dual Address Cycle (DAC) when it is a PCI Bus Master using the DMDAC register for Direct Master transactions. The DAC command is used to transfer a 32-bit address to devices that support 32-bit addressing when the address is not in the low 4-GB address space. The PCI 9056 performs the address portion of a DAC in two PCI clock periods, where the first PCI address is a Lo-Addr with the command (C/BE[3:0]#) "D" and the second PCI address will be a Hi-Addr with the command (C/BE[3:0]#) "6" or "7", depending upon it being a PCI Read or a PCI Write cycle. Whenever the DMDAC register contains a value of 0x00000000, the PCI 9056 performs a Single Address Cycle (SAC) on the PCI Bus. (Refer to Figure 3-5.)
Section 3 M Mode Functional Description
Direct Data Transfer Modes
Figure 3-5. Dual Address Timing
3.4.1.11 PCI Master/Target Abort
The PCI 9056 PCI Master/Target Abort logic enables a Local Bus Master to perform a Direct Master Bus poll of devices to determine whether devices exist (typically when the Local Bus performs Configuration cycles to the PCI Bus). When a PCI Master device attempts to access and does not receive DEVSEL# within six PCI clocks, it results in a Master Abort. The Local Bus Master must clear the Received Master Abort bit or Target Abort bit (PCISR[13 or 11]=0, respectively) and continue by processing the next task. If a PCI Master/Target Abort, or Retry Timeout is encountered during a transfer, the PCI 9056 asserts TEA# if enabled [INTCSR[1:0]=1, which can be used as a Non-Maskable Interrupt (NMI)]. If a Local Bus Master is waiting for TA#, it is asserted along with TEA#. The interrupt handler of the Local Bus Master can take the appropriate application-specific action. It can then clear the Target Abort bit (PCISR[11]) to clear the TEA# interrupt and re-enable Direct Master transfers. If a Local Bus Master is attempting a Burst read from a nonresponding PCI device (Master/Target Abort), it receives TA# and BI# for the first cycle only. In addition, the PCI 9056 asserts TEA# if the Enable Local Bus TEA# bits are enabled (INTCSR[1:0], which can be used as an NMI). If the Local processor cannot terminate its Burst cycle, it may cause the Local processor to hang. The Local Bus must then be reset from the PCI Bus. If the Local Bus Master cannot terminate its cycle with TEA# output, it should not perform Burst cycles when attempting to determine whether a PCI device exists. If a PCI Master/Target Abort is encountered during a Direct Master transfer, the PCI 9056 stores the PCI
Abort address into the PCI Abort Address register bits (PABTADR[31:0]).
3.4.1.12 Direct Master Memory Write and Invalidate
The PCI 9056 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for Direct Master transfers, as well as for DMA transfers. (Refer to Section 3.5.4.) The PCI 9056 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers. Direct Master Memory Write and Invalidate transfers are enabled when the Invalidate Enable and the Memory Write and Invalidate Enable bits are set (DMPBAM[9]) and (PCICR[4], respectively). In Memory Write and Invalidate mode, if the start address of the Direct Master transfer is on a cache line boundary, the PCI 9056 waits until the number of Lwords required for the specified cache line size are written from the Local Bus before starting a PCI Memory Write and Invalidate access. This ensures a complete cache line write can complete in one PCI Bus ownership. If the start address is not on a cache line boundary, the PCI 9056 starts a normal PCI Write access (PCI command code = 7h). The PCI 9056 does not terminate a normal PCI Write at an MWI cache boundary. The normal PCI Write transfer continues until the Data transfer is complete. If a Target disconnects before a cache line is completed, the PCI 9056 completes the remainder of that cache line, using normal writes.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
3-8
Preliminary Information
Direct Data Transfer Modes
Section 3 M Mode Functional Description
3.4.2 3.4.2.1
IDMA/SDMA Operation IDMA Operation
3.4.2.2
SDMA Operation
The PCI 9056 supports the MPC850 or MPC860 Independent DMA (IDMA) mode, using the MDREQ# signal and operating in Direct Master mode. In M mode, this signal is connected to the MPC850 or MPC860 DREQ0# and/or DREQ1# input pins. After programming the MPC850 or MPC860 IDMA channel, the PCI 9056 uses Direct Master mode to transfer data between the PCI Bus and the MPC850 or MPC860 internal dual-port RAM (or external memory). The data count is controlled by the IDMA Byte counter and throttled by the PCI 9056 MDREQ# signal. When the PCI 9056 FIFO is nearly full, MDREQ# is de-asserted to the MPC850 or MPC860, indicating that it should inhibit transferring further data (the FIFO threshold count in the PCI 9056 must be set to a value of at least five Lwords below the full capacity of the FIFO-- 27 Lwords) (DMPBAM[10, 8:5]). The Retry function can be used to communicate to the Local Bus Master that it should relinquish ownership of the Local Bus.
Note: The Direct Master Write FIFO Almost Full RETRY# Output Enable bit (LMISC1[6]) can be disabled to prevent assertion of the RETRY# signal.
The PCI 9056 supports the MPC850 or MPC860 Serial DMA (SDMA) mode, using Direct Master mode. No handshake signals are required to perform the SDMA operation. The Retry function can be used to communicate to the Local Bus Master it should relinquish ownership of the Local Bus. The Direct Master Write FIFO Almost Full RETRY# Output Enable bit (LMISC1[6]) can be disabled to prevent assertion of the RETRY# signal.
Note: The Direct Master Write FIFO can be programmed to identify the full status condition (DMPBAM[10, 8:5]). The FIFO Full Status Flag is in MARBR[30].
3.4.3
Direct Slave Operation (PCI Master-to-Local Bus Access)
* Space 1 * Expansion ROM Expansion ROM is intended to support a bootable ROM device for the Host. Writes--Upon a PCI Bus Write, the PCI Bus Master writes data to the Direct Slave Write FIFO. When the first data is in the FIFO, the PCI 9056 becomes the Local Bus Master, arbitrates for the Local Bus, and writes data to a Local Slave device. The PCI 9056 continues to accept writes and returns TRDY# until the Write FIFO is full. It then holds off TRDY# until space becomes available in the Write FIFO or asserts STOP#, and Retries the PCI Bus Master, dependent upon the register bit setting (LBRD0[27]). A 32-bit PCI Bus Master single cycle Write transaction results in PCI 9056 transfers of one Lword of data onto a Local Bus.
After the IDMA has transferred all required bytes [MPC850 or MPC860 Byte counter decrements to zero (0)], the MPC850 or MPC860 generate an internal interrupt, which in turn should execute the code to disable the IDMA channel (the MDREQ# input signal may still be asserted by the PCI 9056). The SDACK[1:0] signal from the MPC850 or MPC860 is not used by the PCI 9056 (no connection). Refer to Section 3.4.1 for more information about Direct Master Data transfers.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-9
Section 3--M Func Desc
In IDMA reads (PCI 9056 to the Local Bus), the MDREQ# signal is asserted (indicating data is available), although the Read FIFO is empty. Any Local Bus read of the PCI Bus causes the PCI 9056 to become a PCI Bus Master and fills the Direct Master Read FIFO buffer. When sufficient data is in the FIFO, the PCI 9056 completes the Local Bus cycle by asserting Transfer Acknowledge (TA#).
The PCI 9056 supports Burst Memory-Mapped Transfer accesses and I/O-Mapped, Single-Transfer PCI-to-Local Bus accesses through a 32-Lword (128-byte) Direct Slave Read FIFO and a 64-Lword (256-byte) Direct Slave Write FIFO. The PCI Base Address registers are provided to set up the location of the adapter in the PCI memory and the I/O space. In addition, Local mapping registers allow address translation from the PCI Address Space to the Local Address Space. Three spaces are available: * Space 0
Section 3 M Mode Functional Description
Direct Data Transfer Modes
Reads--The PCI 9056 holds off TRDY# while gathering an Lword from the Local Bus, unless the Delayed Read Mode bit is enabled (MARBR[24]=1). (Refer to Section 3.4.3.2.) Programmable Prefetch modes are available, if prefetch is enabled--prefetch, 0-16, or continuous--until the Direct Slave read ends. The Read cycles are terminated on the following clock after FRAME# is de-asserted or the PCI 9056 issues a Retry or disconnect. For the highest data transfer rate, the PCI 9056 supports posted writes and can be programmed to prefetch data during a PCI Burst read. The Prefetch size, when enabled, can be from one to 16 Lwords or until the PCI Bus stops requesting. When the PCI 9056 prefetches, if enabled, it drops the Local Bus after reaching the prefetch counter limit. In Continuous Prefetch mode, the PCI 9056 prefetches as long as FIFO space is available, and stops prefetching when the PCI Bus terminates the request. If Read prefetching is disabled, the PCI 9056 disconnects after one Read transfer. In addition to Prefetch mode, the PCI 9056 supports Read Ahead mode. (Refer to Section 3.4.3.3.) Only 32-bit PCI Bus single cycle Direct Slave Read transactions result in the PCI 9056 passing requested PCI bytes (C/BE#) to a Local Bus Target device by way of TSIZ[0:1] assertion back to a PCI Bus Master. This transaction results in the PCI 9056 reading one Lword or partial Lword data. For other types of Read transactions (Burst transfers or Unaligned), the PCI 9056 reads multiple Local Bus data with all bytes asserted (TSIZ[0:1] =0h). Each Local space can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width. The PCI 9056 has an internal wait state generator and external wait state input, TA#. TA# can be disabled or enabled with the Internal Configuration registers. With or without wait state(s), the Local Bus, independent of the PCI Bus, can perform the following: * Burst as long as data is available (Continuous Burst mode) * Burst four Lwords at a time (recommended) * Perform continuous single cycles
A Burst cycle from the PCI Bus through the PCI 9056 asserts an MPC850 or MPC860 Burst transaction, if the following is true: * The address is quad-Lword-aligned, * A FIFO contains at least four Lwords, and * All PCI Bus byte enables are set for writes only and ignored for reads
3.4.3.1
Direct Slave Lock
The PCI 9056 supports direct PCI-to-Local-Bus exclusive accesses (locked atomic operations). A PCI-locked operation to the Local Bus results in the entire address Space 0, Space 1, and Expansion ROM space being locked until they are released by the PCI Bus Master. Locked operations are enabled or disabled with the Direct Slave LOCK# Enable bit (MARBR[22]).
3.4.3.2
Direct Slave Delayed Read Mode
The PCI 9056 can be programmed through the Delayed Read Mode bit (MARBR[24]=1) to perform delayed reads. PCI Bus single cycle aligned or unaligned 32-bit Direct Slave Delayed Read transactions always result in 1-Lword single cycle transfers on the Local Bus with the corresponding Local Address and TSIZ[0:1] asserted to reflect the PCI byte enables (C/BE#), unless the PCI Read No Flush Mode bit is enabled (MARBR[28]=1). (Refer to Section 3.4.3.3 for further information.) This causes the PCI 9056 to Retry all PCI Bus Read requests that follow, until the original PCI byte enables (C/BE#) are matched. In addition to delayed reads, the PCI 9056 supports the following Delayed Read mode functions: * No writes while a read is pending (PCI Retry for writes) * Write and flush pending read
3-10
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
Section 3 M Mode Functional Description
3.4.3.4
PCI Bus
Direct Slave Delayed Write Mode
PCI 9056
Local Bus
PCI Read request
PCI 9056 instructs PCI Host to "Retry" Read cycle later PCI Bus is free to perform other cycles during this time PCI Host returns to fetch Read data again Read data is now ready for host
Delayed Read mode is set in Internal Registers PCI 9056 requests Read data from Local Bus Local memory returns requested data to PCI 9056
Data is stored in 32-Lword Internal FIFO
PCI 9056 returns prefetched data immediately
The PCI 9056 supports Direct Slave Delayed Write mode transactions, where posted Write data accumulates in the Direct Slave Write FIFO before the PCI 9056 requests a Write transaction (TS# assertion) to be performed on the Local Bus. The Direct Slave Delayed Write mode is programmable to delay the TS# assertion in the amount of Local clocks (LMISC2[4:2]). This feature is useful for gaining higher throughput during Direct Slave Write burst transactions for conditions in which the PCI clock frequency is slower than the Local clock frequency.
3.4.3.5
Figure 3-6. Direct Slave Delayed Read
Note: Figure 3-6 represents a sequence of Bus cycles.
Direct Slave Local Bus TA# Timeout Mode
3.4.3.3
Direct Slave Read Ahead Mode
The PCI 9056 also supports Direct Slave Read Ahead mode (MARBR[28]), where prefetched data can be read from the internal FIFO of the PCI 9056 instead of from the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4) for 32-bit Direct Slave transfers.
PCI Bus
PCI Read request
PCI 9056
Read Ahead mode is set in Internal Registers
Local Bus
PCI 9056 prefetches data from Local Bus device
3.4.3.6
Direct Slave Transfer
Read data PCI Bus Master Read returns with "Sequential Address" Prefetched data is stored in the internal FIFO PCI 9056 returns prefetched data immediately from internal FIFO without reading again from the Local Bus
PCI 9056 prefetches more data if FIFO space is available
A PCI Bus Master addressing the Memory space decoded for the Local Bus initiates transactions. Upon a PCI Read/Write, the PCI 9056 becomes a Local Bus Master and arbitrates for the Local Bus. The PCI 9056 then reads data into the Direct Slave Read FIFO or writes data to the Local Bus. The Direct Slave or Direct Master preempts DMA; however, the Direct Slave does not preempt the Direct Master. (Refer to Section 3.4.4.1) The PCI 9056 can be programmed to retain the PCI Bus by generating a wait state(s) and de-asserting TRDY#, if the Write FIFO becomes full. The PCI 9056 can also be programmed to retain the Local Bus and continue asserting BB#, if the Direct Slave Write FIFO
Read data
PCI 9056 prefetches more data from Local memory
Figure 3-7. Direct Slave Read Ahead Mode
Note: Figure 3-7 represents a sequence of Bus cycles.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-11
Section 3--M Func Desc
The PCI 9056 supports Direct Slave Local Bus TA# Timeout mode transactions, where the PCI 9056 asserts an internal TA# signal to recover from stalling the Local and PCI Buses. The Direct Slave Local Bus TA# Timeout mode transaction is programmable to select the amount of Local clocks before TA# times out (LMISC2[1:0]). If a Local Slave stalls with a TA# assertion during Direct Slave Write transactions, the PCI 9056 empties the Write FIFO by dumping the data into the Local Bus and does not pass an error condition to the PCI Bus Initiator. During Direct Slave Read transactions, the PCI 9056 issues a Direct Slave Abort to the PCI Bus Initiator every time the Direct Slave Local Bus TA# Timeout is detected.
Section 3 M Mode Functional Description
Direct Data Transfer Modes
becomes empty or the Direct Slave Read FIFO becomes full. In either case, the Local Bus is dropped when the Local Bus Latency Timer is enabled and expires (MARBR[7:0]). For Direct Slave writes, the PCI Bus writes data to the Local Bus. Direct Slave is the "Command from the PCI Host," which has the highest priority. For Direct Slave reads, the PCI Bus Master reads data from the Local Bus Slave. The PCI 9056 supports on-the-fly Endian conversion for Space 0, Space 1, and Expansion ROM space. The Local Bus can be Big/Little Endian (Address/Data Invariance) by using the programmable internal register configuration.
Note: The PCI Bus is always Little Endian.
Master
FRAME#, C/BE#, AD (addr) IRDY#
Slave
Master
Slave
PCI 9056
TRDY#, AD (data)
BR# BG# BB#, LA, TS#, RD/WR# , BURST# TA#, LD
Figure 3-9. Direct Slave Read
Note: Figures 3-8 and 3-9 represent a sequence of Bus cycles.
During Direct Slave transactions, the MPC850 or MPC860 user has the option to use the PCI 9056 for maximum Burst transfers, using the BTERM# Input Enable bit(s) (LBRD0[23, 7], LBRD1[7], DMAMODE0[7], and/or DMAMODE1[7]). In Direct Slave transfers, each Direct Slave space (Space 0, Space 1, and Expansion ROM) has its own BTERM# Input Enable bit (the BTERM# input signal becomes the BI# signal in M mode). Space 0 is in LBRD0[7], Space 1 is in LBRD1[7], and Expansion ROM is in LBRD0[23].
Master
FRAME#, C/BE#, AD (addr) IRDY#, AD (data)
When the Bterm Mode bit is enabled, the PCI 9056 continues to burst on the Local Bus until the BI# signal is asserted for one CLK cycle any time after the first Data phase, implying a new Address cycle (TS#) is needed if there is more data to transfer. If the BI# signal is asserted on the first Data phase, the Burst transfer is broken into single cycle transactions. When the Bterm Mode bit is enabled and the BI# signal asserted for one CLK cycle any time after the first Data phase, this implies that a new Address cycle (TS#) is needed for more data to transfer. This can be used when crossing memory banks. Regardless of the Bterm mode setting, if the BI# signal is asserted on the first Data phase, single cycle transfers are performed until the Qword boundary is reached.
Slave
Master
Slave
PCI 9056
BR# BG# BB#, LA, TS#, RD/WR# LD, BURST# TA#
Figure 3-8. Direct Slave Write
Local Bus
PCI Bus
DEVSEL#, TRDY#
3-12
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus
PCI Bus
DEVSEL#
Direct Data Transfer Modes
Section 3 M Mode Functional Description
Table 3-2. Direct Slave Burst Mode Cycle Detection
Burst Enable Bit BTERM# Input Enable Bit
3.4.3.7
Direct Slave PCI-to-Local Address Mapping
BI# Signal
Result
Burst 16 bytes (MPC850 or MPC860 compatible) Single cycle Burst until BI# is asserted for one CLK cycle Single cycle
Note: In I2O mode (QSR[0]=1), Memory-Mapped Local Configuration registers and Space 1 share the PCIBAR0 Base Address (refer to Section 7.1.10 for further details).
1
0
Not asserted
1
0
Asserted during first Data phase Asserted after first Data phase X
Three Local Address spaces--Space 0, Space 1, and Expansion ROM--are accessible from the PCI Bus. Each is defined by a set of three registers: * Local Address Range (LAS0RR, LAS1RR, and/or EROMRR) * Local Base Address (LAS0BA, LAS1BA, and/or EROMBA) * PCI Base Address (PCIBAR2, PCIBAR3, and/or PCIERBAR) A fourth register, the Bus Region Descriptor register(s) for PCI-to-Local Accesses (LBRD0 and/or LBRD1), defines the Local Bus characteristics for the Direct Slave regions. (Refer to Figure 3-10.) Each PCI-to-Local Address space is defined as part of reset initialization, as described in Section 3.4.3.7.1. These Local Bus characteristics can be modified at any time before actual data transactions.
1 0
1 X
Caution: The MPC850 and MPC860 do not support bursting more than 16 bytes. The BTERM# Input Enable bits should be set only for Local Bus Masters that support continuous bursting. Note: "X" is "Don't Care."
During burst forever, extended M mode protocol, the PCI 9056 supports BDIP# signal. The BDIP# signal is asserted at the beginning of a Burst transaction and remains active until the last data of the Transfer packet. The BDIP# signal is de-asserted on the last Data Transfer phase, indicating the end of transfer. The PCI 9056 supports Local Bus error conditions using TEA#. TEA# may be asserted by a device on the Local Bus, either before or simultaneously with TA#. In either case, the PCI 9056 tries to complete the current transaction by transferring data and then asserting TS# for every address that follows, waiting for another TA# or TEA# to be issued (used to flush Direct Slave FIFOs). After acknowledging TEA# is asserted, the PCI 9056 asserts PCI SERR# and sets an error flag, using the Signaled System Error bit (PCISR[14]=1). When set, this indicates a catastrophic error occurred on the Local Bus. SERR# may be masked off by resetting the TEA# Input Interrupt Mask bit (LMISC1[5]=0). The PCI 9056 Local Bus Latency Timer (MARBR[7:0]) can be used to better utilize the Local Bus.
3.4.3.7.1 Direct Slave Local Bus Initialization
Section 3--M Func Desc
Range--Specifies which PCI Address bits to use for decoding a PCI access to Local Bus space. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. Remap PCI-to-Local Addresses into a Local Address Space--Bits in this register remap (replace) the PCI Address bits used in decode as the Local Address bits. Local Bus Region Descriptor--Specifies the Local Bus characteristics.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-13
Section 3 M Mode Functional Description
Direct Data Transfer Modes
3.4.3.7.2 Direct Slave PCI Initialization
After a PCI reset, the software determines how much address space is required by writing all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9056 returns zeroes (0) in the Don't Care Address bits, effectively specifying the address
space required. The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 3-10.)
PCI Bus Master
Local Processor 1
Initialize Local Direct Access Registers
2
Initialize PCI Base Address Registers
Range for PCI-to-Local Address Space 0/1 Local Base Address (Remap) for PCI-to-Local Address Space 0/1 Bus Region Descriptors for PCI-to-Local Accesses
Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses
Local Bus Hardware Characteristics
PCI Base Address to Local Address Space 0/1 PCI Base Address to Local Expansion ROM
3
PCI Bus Access
4 FIFOs
64-Lword Deep Write 32-Lword Deep Read Local Bus Access
PCI Address Space
PCI Base Address Local Base Address
Local Memory
Range
Figure 3-10. Local Bus Direct Slave Access
3-14
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
Section 3 M Mode Functional Description
3.4.3.7.3 Direct Slave Transfer Size
The TSIZ[0:1] pins correspond to the data-transfer size on the Local Bus, as listed in the following tables.
Table 3-3. Data Bus TSIZ[0:1] Contents for Single Write Cycles
Address LA30
1 1 1 1 0 0 0 0 0 1 1 0 1 0
Transfer Size
0 Byte 0 0 0 Word Lword 1 1 0
TSIZ [0:1]
External Data Bus Pattern For 32-, 16-, and 8-Bit Port Sizes LD[0:7]
OP0 OP1 OP2 OP3 OP0 OP2 OP0
LA31
0 1 0 1 0 0 0
LD[8:15]
-- OP1 -- OP3 OP1 OP3 OP1
LD[16:23]
-- -- OP2 -- -- OP2 OP2
LD[24:31]
-- -- -- OP3 -- OP3 OP3
Table 3-4. Data Bus TSIZ[0:1] Requirements for Single Read Cycles
Address LA30
0 0 1 1 0 1 0
Transfer Size
TSIZ [0:1]
0 1 1 1 1 0 0 0 0 0 0
32-Bit Port Size LD[0:7]
OP0 -- -- -- OP0 -- OP0
16-Bit Port Size LD[24:31]
-- -- -- OP3 -- OP3 OP3
8-Bit Port Size LD[0:7]
OP0 OP1 OP2 OP3 OP0
LA31
0 1 0 1 0 0 0
LD[8:15]
-- OP1 -- -- OP1 -- OP1
LD[16:23]
-- -- OP2 -- -- OP2 OP2
LD[0:7]
OP0 -- OP2 -- OP0 OP2 OP0
LD[8:15]
-- OP1 -- OP3 OP1 OP3 OP1
Byte
Word Lword
1 1 0
OP0
3.4.3.7.3.1
Direct Slave Transfer Size Example
b. PCI Initialization software writes all ones (1) to the PCI Base Address, then reads it back again. * The PCI 9056 returns a value of FFF00000h. The PCI software then writes to the PCI Base Address register(s). PCI Base Address--789XXXXXh (PCI Base Address for Access to the Local Address Space registers, PCIBAR2 and PCIBAR3).
A 1 MB Local Address Space, 12300000h through 123FFFFFh, is accessible from the PCI Bus at PCI addresses 78900000h through 789FFFFFh. a. Local initialization software sets the Range and Local Base Address registers as follows: * * Range--FFF00000h (1 MB, decode the upper 12 PCI Address bits) Local Base Address (Remap)--123XXXXXh (Local Base Address for PCI-to-Local accesses [Space Enable bit(s) must be set to be recognized by the PCI Host (LAS0BA[0]=1 and/or LAS1BA[0]=1)]
*
For a PCI Direct access to the Local Bus, the PCI 9056 has a 64-Lword (256-byte) Write FIFO and a 32-Lword (128-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus. The PCI 9056 can be programmed to return a Retry response or to throttle TRDY# for any PCI Bus transaction attempting to write to the PCI 9056 Local Bus when the FIFO is full.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-15
Section 3--M Func Desc
OP2
Section 3 M Mode Functional Description
Direct Data Transfer Modes
For PCI Read transactions from the Local Bus, the PCI 9056 holds off TRDY# while gathering data from the Local Bus. For Read accesses mapped to PCI Memory space, the PCI 9056 prefetches up to 16 Lwords (has Continuous Prefetch mode) from the Local Bus. Unused Read data is flushed from the FIFO. For Read accesses mapped to PCI I/O space, the PCI 9056 does not prefetch Read data. Rather, it breaks each read of a Burst cycle into a single Address/Data cycle on the Local Bus. The Direct Slave Retry Delay Clocks bits (LBRD0[31:28]) can be used to program the period of time in which the PCI 9056 holds off TRDY#. The PCI 9056 issues a Retry to the PCI Bus Transaction Master when the programmed time period expires. This occurs when the PCI 9056 cannot gain control of the Local Bus and return TRDY# within the programmed time period.
3.4.4
Deadlock Conditions
Deadlock can occur when a PCI Bus Master must access the PCI 9056 Local Bus at the same time a Master on the PCI 9056 Local Bus must access the PCI Bus. There are two types of deadlock: * Partial Deadlock--A Local Bus Master is performing a Direct Bus Master access to a PCI Bus device other than the PCI Bus device concurrently trying to access the Local Bus * Full Deadlock--A Local Bus Master is performing a Direct Bus Master access to the same PCI Bus device concurrently trying to access the Local Bus This applies only to Direct Master and Direct Slave accesses through the PCI 9056. Deadlock does not occur in transfers through the PCI 9056 DMA channels or the PCI 9056 internal registers (such as mailboxes). For partial deadlock, the PCI access to the Local Bus times out [the Direct Slave Retry Delay Clock (LBRD0[31:28]), which is programmable through the Local Bus Region Descriptor register] and the PCI 9056 responds with a PCI Retry. PCI r2.2 requires that a PCI Master release its request for the PCI Bus (de-assert REQ#) for a minimum of two PCI clocks after receiving a Retry. This allows the PCI Bus arbiter to grant the PCI Bus to the PCI 9056 so that it can complete its Direct Master access and free up the Local Bus. Possible solutions are described in the following sections for cases in which the PCI Bus arbiter does not function as described (PCI Bus architecture dependent), waiting for a time out is undesirable, or a full deadlock condition exists. When a full deadlock occurs, the only solution is to back off the Local Bus Master.
3.4.3.8
Direct Slave Priority
Direct Slave accesses have a higher priority than DMA accesses, thereby preempting DMA transfers. During a DMA transfer, if the PCI 9056 detects a pending Direct Slave access, it releases the Local Bus within two Data transfers. The PCI 9056 resumes operation after the Direct Slave access completes. When the PCI 9056 DMA controller owns the Local Bus, its BR# output and BG# input are asserted. When a Direct Slave access occurs, the PCI 9056 releases the Local Bus within two Lword transfers by de-asserting BB# and floating the Local Bus outputs. After the PCI 9056 acknowledges that BG# is de-asserted, it requests the Local Bus for a Direct Slave transfer by asserting BR#. When the PCI 9056 receives BG#, it drives the bus and performs the Direct Slave transfer. Upon completing a Direct Slave transfer, the PCI 9056 releases the Local Bus by de-asserting BB# and floating the Local Bus outputs. After the PCI 9056 acknowledges that BG# is de-asserted and the Local Bus Pause Timer is set to zero (0), it requests a DMA transfer from the Local Bus by re-asserting BR#. When it receives BG#, it drives the bus and continues the DMA transfer.
3-16
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Section 3 M Mode Functional Description
3.4.4.1
Backoff
The PCI 9056 Local RETRY# signal indicates whether a possible deadlock condition exists. The PCI 9056 starts the Backoff Timer (programmable through registers) when it detects one of the following conditions: * A PCI Bus Master is attempting to access memory or an I/O device on the Local Bus and is not gaining access (for example, BG# is not received). * A Local Bus Master is performing a Direct Bus Master Read access to the PCI Bus. Or, a Local Bus Master is performing a Direct Bus Master Write access to the PCI Bus and the PCI 9056 Direct Master Write FIFO cannot accept another Write cycle. If the Local Bus Backoff Enable bit is enabled (EROMBA[4]=1), the Backoff Timer expires, and the PCI 9056 has not received BG#, the PCI 9056 asserts RETRY#. External bus logic can use this signal to perform backoff. The Backoff cycle is device/bus architecture dependent. The external logic (arbiter) can assert the necessary signals to cause the Local Bus Master to release the Local Bus (backoff). After the Local Bus Master backs off, it can grant the bus to the PCI 9056 by asserting BG#. Once RETRY# is asserted, TA# for the current Data cycle is never asserted (the Local Bus Master must perform a backoff). When the PCI 9056 detects BG#, it proceeds with the PCI Master-to-Local-Bus access. When this access completes and the PCI 9056 releases the Local Bus, external logic can then release the backoff and the Local Bus Master can resume the cycle interrupted by the Backoff cycle. The PCI 9056 Write FIFO retains all data acknowledged (that is, last data for which TA# was asserted). After the backoff condition ends, the Local Bus Master restarts the last cycle with TS#. For writes, data following TS# should be the data the PCI 9056 did not acknowledge prior to the Backoff cycle (for example, the last data for which TA# is not asserted). All PCI Read cycles completed before the Local Bus was backed off remain in the Direct Master Read FIFO. Therefore, if the Local Bus Master returns with the same last cycle, the cycle is acknowledged with the data currently in the FIFO (the FIFO data is not
read twice). A new PCI read is performed, if the resumed Local Bus cycle is not the same as the Backed Off cycle.
3.4.4.1.1 Software/Hardware Solution for Systems without Backoff Capability
For adapters that do not support backoff, a possible deadlock solution is as follows. PCI Host software, external Local Bus hardware, general-purpose output USERo and general-purpose input USERi can be used to prevent deadlock. USERo can be asserted to request that the external arbiter not grant the bus to any Local Bus Master except the PCI 9056. Status output from the Local arbiter can be connected to the general purpose input USERi to indicate that no Local Bus Master owns the Local Bus, or the PCI Host to determine that no Local Bus Master that currently owns the Local Bus can read input. The PCI Host can then perform Direct Slave access. When the Host finishes, it de-asserts USERo.
3.4.4.1.2 Preempt Solution
For devices that support preempt, USERo can be used to preempt the current Local Bus Master device. When USERo is asserted, the current Local Bus Master device completes its current cycle and releases the Local Bus, de-asserting BB#.
3.4.4.2
Software Solutions to Deadlock
Both PCI Host and Local Bus software can use a combination of mailbox registers, doorbell registers, interrupts, direct Local-to-PCI accesses and direct PCI-to-Local accesses to avoid deadlock.
3.5
DMA OPERATION
DMA
The PCI 9056 supports two independent channels capable of transferring data from the: * Local-to-PCI Bus * PCI-to-Local Bus
Each channel consists of a DMA controller and a dedicated, bidirectional FIFO. Both channels support Block transfers, and Scatter/Gather transfers, with or without End of Transfer (EOT#). Only DMA Channel 0 supports Demand mode DMA transfers. Master mode must be enabled with the Master Enable bit
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-17
Section 3--M Func Desc
Section 3 M Mode Functional Description
DMA Operation
(PCICR[2]) before the PCI 9056 can become a PCI Bus Master. In addition, both DMA channels can be programmed to: * Operate in 8-, 16-, or 32-bit Local Bus width * Use zero to 15 internal wait states (Local Bus) * Enable/disable internal wait states (Local Bus) * Enable/disable Local Bus Burst capability * Limit Local Bus bursts to four (BTERM# enable/ disable) * Hold Local address constant (Local Slave is FIFO) or increment * Perform PCI Memory Write and Invalidate (command code = Fh) or normal PCI Memory Write (command code = 7h) * Pause Local transfer with/without BLAST# (DMA Fast/Slow termination) * Assert PCI interrupt (INTA#) or Local interrupt (LINTo#) when DMA transfer is complete or Terminal Count is reached during Scatter/Gather DMA mode transfers * Operate in DMA Clear Count mode (only if the descriptor is in Local memory) The PCI 9056 also supports PCI Dual Address with the upper 32-bit register(s) (DMADAC0 and/or DMADAC1). The Local Bus Latency Timer determines the number of Local clocks the PCI 9056 can burst data before relinquishing the Local Bus. The Local Bus Pause Timer sets how soon the DMA channel can request the Local Bus.
3.5.2
Block DMA Mode
The Host processor or the Local processor sets the Local and PCI starting addresses, transfer byte count, and transfer direction. The Host or Local processor then sets the DMA Start bit (DMACSR0[1] and/or DMACSR1[1]) to initiate a transfer. The PCI 9056 requests the PCI and Local Buses and transfers data. Once the transfer completes, the PCI 9056 sets the Channel Done bit(s) (DMACSR0[4]=1 and/or DMACSR1[4]=1) and, if enabled, asserts an interrupt(s) (DMAMODE0[10] and/or DMAMODE1[10]) to the Local processor or the PCI Host (programmable). The Channel Done bit(s) can be polled, instead of interrupt generation, to indicate the DMA transfer status. DMA registers are accessible from the PCI and Local Buses. (Refer to Figure 3-11.) During DMA transfers, the PCI 9056 is a Master on both the PCI and Local Buses. For simultaneous access, Direct Slave or Direct Master has a higher priority than DMA. The PCI 9056 releases the PCI Bus, if one of the following conditions occur (refer to Figure 3-12 and Figure 3-13): * FIFO is full (PCI-to-Local Bus) * FIFO is empty (Local-to-PCI Bus) * Terminal count is reached * PCI Bus Latency Timer expires (PCILTR[7:0])-- normally programmed by the Host PCI BIOS--and PCI GNT# de-asserts * PCI Host asserts STOP#
3.5.1
DMA PCI Dual Address Cycle
The PCI 9056 releases the Local Bus, if one of the following conditions occurs: * FIFO is empty (PCI-to-Local Bus) * FIFO is full (Local-to-PCI Bus) * Terminal count is reached * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * Special cycle BI# input is asserted * Direct Slave request is pending
The PCI 9056 supports PCI Dual Address Cycles (DAC) when it is a PCI Bus Master using the DMADAC0 and/or DMADAC1 register(s) for Block DMA transactions. Scatter/Gather DMA can utilize the DAC function by way of the DMADAC0 and/or DMADAC1 register(s) or DMAMODE0[18] and/or DMAMODE1[18]. The DAC command is used to transfer a 32-bit address to devices that support 32-bit addressing when the address is above the 4-GB address space. The PCI 9056 performs a DAC within two PCI clock periods, when the first PCI address is a Lo-Addr, with the command (C/BE[3:0]#) "D", and the second PCI address is a Hi-Addr, with the command (C/BE[3:0]#) "6" or "7", depending upon whether it is a PCI Read or PCI Write cycle.
3-18
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Section 3 M Mode Functional Description
During DMA transactions, users have the option of using the Burst Forever BTERM# Input Enable bit(s) (DMAMODE0[7] and/or DMAMODE1[7]), if the External Memory Controller is provided. Used in conjunction with the Fast/Slow Terminate Mode Select bit(s) (DMAMODE0[15] and/or DMAMODE1[15]).
Set DMA Mode to Block
Mode Register
PCI Host Memory
Set up Transfer Parameters
Single Address--PCI Address Register Dual Address--PCI Addresses Register Local Address Register Transfer Size (byte count) Register Descriptor Pointer Register (set direction only)
Memory Block to Transfer
Local Memory
Memory Block to Transfer
Command/Status Register
Set Enable and Start bits in DMA Command/Status Register(s) (DMACSR0 and/or DMACSR1) to Initiate DMA Transfer
Figure 3-11. Block DMA Mode Initialization (Single Address or Dual Address PCI)
Slave
DMA Start
Master
(DMALADR1 & DMASIZ1)
Master
DMA Start
Slave
Slave
DMA Start
Master
(DMALADR1 & DMASIZ1)
Master
DMA Start
(DMALADR1 & DMASIZ1)
Slave
(DMALADR1 & DMASIZ1)
REQ# GNT# FRAME#, C/BE#, AD (addr)
BR# BG# BB#, LA, TS#, RD/WR#
PCI Bus
Local Bus
PCI Bus
IRDY# DEVSEL#, TRDY#, AD (data)
PCI 9056
REQ# GNT# IRDY# DEVSEL#, TRDY# AD (addr & data)
PCI 9056
LD, TA#
BR# BG# BB#, LA, TS#, RD/WR#, BURST# TA#
Figure 3-12. DMA, PCI-to-Local Bus
Figure 3-13. DMA, Local-to-PCI Bus
Note: Figures 3-12 and 3-13 represent a sequence of Bus cycles.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Local Bus
3-19
Section 3--M Func Desc
Section 3 M Mode Functional Description
DMA Operation
Table 3-5. DMA
BTERM# Input Enable Bit(s)
Enabled (1)
3.5.2.1
Fast/Slow Terminate Mode Select Bit(s)
Disabled (1)
Block DMA PCI Dual Address Cycle
PCI 9056 BDIP# Output
BDIP# is not asserted. Burst forever or until BI# asserts for one CLK cycle. BDIP# is asserted until the last Data transfer, or until BI# asserts for one CLK cycle Burst forever. (Refer to Section 2.2.5.2.1.) BDIP# is not asserted. Burst forever. BDIP# is asserted by the PCI 9056. Burst up to 16 bytes (MPC850 or MPC860 compatible).
Enabled (1)
Enabled (0)
The PCI 9056 supports the DAC feature in Block DMA mode. Whenever the DMADAC0 and/or DMADAC1 register(s) contain a value of 0x00000000, the PCI 9056 performs a Single Address Cycle (SAC) on the PCI Bus. Any other value causes a Dual Address to appear on the PCI Bus. (Refer to Figure 3-14.)
3.5.3
Scatter/Gather DMA Mode
Disabled (0) Disabled (0)
Disabled (1) Enabled (0)
In Scatter/Gather DMA mode, the Host processor or Local processor sets up descriptor blocks in Local or Host memory composed of PCI and Local addresses, transfer count, transfer direction, and address of next descriptor block. (Refer to Figure 3-15 and Figure 3-16.) The Host or Local processor then: * Enables the Scatter/Gather mode bit(s) (DMAMODE0[9]=1 and/or DMAMODE1[9]=1) * Sets up the address of initial descriptor block in the PCI 9056 Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) * Initiates the transfer by setting a control bit(s) (DMACSR0[1:0] and/or DMACSR1[1:0]) The PCI 9056 supports zero wait state Descriptor Block bursts from the Local and PCI Bus when the Local Burst Enable bit(s) is enabled (DMAMODE0[8]=1 and/or DMAMODE1[8]=1). The PCI 9056 loads the first descriptor block and initiates the Data transfer. The PCI 9056 continues to load descriptor blocks and transfer data until it detects the End of Chain bit(s) is set (DMADPR0[1]=1 and/or DMADPR1[1]=1) (these bits are part of each descriptor). When the End of Chain bit(s) is detected, the PCI 9056 completes the current descriptor block and sets the DMA Done bit(s) (DMACSR0[4] and/or DMACSR1[4]). If the End of Chain bit(s) is detected, the PCI 9056 asserts a PCI interrupt (INTA#) and/or Local interrupt (LINTo#). The PCI 9056 can also be programmed to assert PCI or Local interrupts after each descriptor is loaded, then finish transferring. If Scatter/Gather descriptors are in Local memory, the DMA controller can be programmed to clear the transfer size at completion of each DMA, using the
Table 3-6. Normal DMA with EOT Function
BTERM# Enable Bit(s) Fast/Slow Terminate Mode Select Bit(s)
PCI 9056 BDIP# Output
BDIP# is not asserted. Immediate transfer terminated by EOT#.
Enabled (1)
Disabled (1)
BDIP# is asserted until the last Data transfer, or until BI# asserts for one CLK cycle. (Refer to Section 2.2.5.2.1.) BDIP# is asserted until the last Data transfer, or until BI# asserts for one CLK cycle Burst forever. (Refer to Section 2.2.5.2.1.) BDIP# is not asserted. Immediate transfer terminated by EOT#. BDIP# is asserted by the PCI 9056. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible).
Enabled (1)
Enabled (0)
Disabled (0) Disabled (0)
Disabled (1) Enabled (0)
Note: If the Burst Enable bit is set to 0, the PCI 9056 performs single cycle transfers on the Local Bus.
3-20
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Section 3 M Mode Functional Description
DMA Clear Count Mode bit(s) (DMAMODE0[16] and/ or DMAMODE1[16]).
Notes: In Scatter/Gather DMA mode, the descriptor includes the PCI and Local Address Space, transfer size, and next descriptor pointer. It also includes a DAC value, if the DAC Chain Load bit(s) is enabled (DMAMODE0[18]=1 and/or DMAMODE1[18]=1). Otherwise, the register (DMADAC0 and/or DMADAC1) values are used.
The Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) contains end of chain (bit 1), direction of transfer (bit 3), next descriptor address (bits [31:4]), interrupt after terminal count (bit 2), and descriptor location (bit 0) bits. The Local Bus width must be the same as Local Memory Bus width. A DMA descriptor can be on the Local memory or the PCI memory, or both (for example, one descriptor on Local memory, another descriptor on PCI memory and vice-versa).
Figure 3-14. Dual Address Timing
PCI Bus
Local Bus
Set up Scatter/Gather DMA for PCI-to-Local PCI 9056 retrieves Scatter/Gather data from Local memory PCI 9056 writes data to Local Bus
PCI Bus
Set up Scatter/Gather DMA for Local-to-PCI PCI 9056 retrieves Scatter/Gather data from PCI memory PCI 9056 writes data to PCI Bus PCI 9056 writes data to PCI Bus PCI 9056 retrieves S catter/Gather data from PCI memory PCI 9056 writes data to PCI Bus PCI 9056 writes data to PCI Bus
Local Bus
PCI 9056 initiates read from PCI Bus PCI 9056 initiates read from PCI Bus
PCI 9056 initiates read from Local Bus
PCI 9056 initiates read from PCI Bus PCI 9056 initiates read from PCI Bus
PCI 9056 retrieves Scatter/Gather data from Local memory PCI 9056 writes data to Local Bus PCI 9056 writes data to Local Bus
PCI 9056 initiates read from Local Bus PCI 9056 initiates read from Local Bus
Read and Write cycles continue...
Read and Write cycles continue...
Figure 3-15. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus)
Figure 3-16. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus)
Note: Figures 3-15 and 3-16 represent a sequence of Bus cycles.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-21
Section 3--M Func Desc
PCI 9056
PCI 9056 writes data to Local Bus
PCI 9056
PCI 9056 initiates read from Local Bus
Section 3 M Mode Functional Description
DMA Operation
3.5.3.1
Scatter/Gather DMA PCI Dual Address Cycle
The PCI 9056 supports the DAC feature in Scatter/ Gather DMA mode for Data transfers only. The descriptor blocks should reside below the 4-GB Address space. The PCI 9056 offers three different options of how PCI DAC Scatter/Gather DMA is utilized. Assuming the descriptor blocks are located on the PCI Bus: * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 0. The PCI 9056 performs a Single Address Cycle (SAC) four-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. (Refer to Figure 3-17.) * DMADAC0 and/or DMADAC1 contain(s) an 0x00000000 value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9056 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. (Refer to Figure 3-18.) * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9056 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. The fifth descriptor overwrites the value of the DMADAC0 and/or DMADAC1 register(s). (Refer to Figure 3-18.)
count) is ignored. When the Valid Mode Enable bit(s) is set to 1 (DMAMODE0[20]=1 and/or DMAMODE1 [20]=1), the DMA descriptor proceeds only when the Valid bit is set. If the Valid bit is set, the transfer count is 0, and the descriptor is not the last descriptor, then the DMA controller moves on to the next descriptor in the chain. When the Valid Stop Control bit(s) is set to 0 (DMAMODE0[21]=0 and/or DMAMODE1[21]=0), the DMA Scatter/Gather controller continuously polls the descriptor with the Valid bit set to 0 (invalid descriptor) until the Valid bit is read to be a 1. When the Valid Stop Control bit(s) is set to 1 (DMAMODE0 [21]=1 and/or DMAMODE1[21]=1), the DMA Scatter/ Gather controller pauses if a Valid bit with a value of 0 is detected. In this case, the PCI 9056 must restart the DMA controller by setting bit 1 of the DMA Control/Status register(s) (DMACSR0[1] and/or DMACSR1[1]). The DMA Clear Count mode bit(s) (DMAMODE0[16] and/or DMAMODE1[16]) must be enabled for the Ring Management Valid bit to be cleared at the completion of each descriptor.
3.5.4
DMA Memory Write and Invalidate
3.5.3.2
DMA Clear Count Mode
The PCI 9056 supports DMA Clear Count mode (Write-Back feature, DMAMODE0[16] and/or DMAMODE1[16]). This feature allows users to control the Data transfer blocks during Scatter/Gather DMA operations. The PCI 9056 clears the Transfer Size descriptor to zero (0) by writing to a descriptor memory location at the end of each transfer chain. This feature is available for DMA descriptors located on the Local and PCI Buses.
The PCI 9056 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for DMA transfers, as well as Direct Master transfers. (Refer to Section 3.4.1.12.) The PCI 9056 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers. DMA Memory Write and Invalidate transfers are enabled when the DMA controller Memory Write and Invalidate Enable bit(s) (DMAMODE0[13] and/or DMAMODE1[13]) and the Memory Write and Invalidate Enable bit (PCICR[4]) are set. In Memory Write and Invalidate mode, the PCI 9056 waits until the number of Lwords required for specified cache line size are read from the Local Bus before starting the PCI access. This ensures a complete cache line write can complete in one PCI Bus ownership. If a target disconnects before a cache line completes, the PCI 9056 completes the remainder of that cache line, using normal writes before resuming Memory Write and
3.5.3.3
DMA Descriptor Ring Management (Valid Mode)
In Scatter/Gather DMA mode, when the Valid Mode Enable bit(s) is set to 0 (DMAMODE0[20]=0 and/or DMAMODE1[20]=0), the Valid bit (bit 31 of transfer
3-22
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Section 3 M Mode Functional Description
Invalidate transfers. If a Memory Write and Invalidate cycle is in progress, the PCI 9056 continues to burst if another cache line is read from the Local Bus before the cycle completes. Otherwise, the PCI 9056 terminates the burst and waits for the next cache line to be read from the Local Bus. If the final transfer is not a complete cache line, the PCI 9056 completes the DMA transfer, using normal writes. EOT# signal assertion, in any DMA transfer type, or DREQ0# and/or DREQ1# signal de-assertion in Demand Mode before the cache line is read from the Local Bus, results in the PCI 9056 performing a normal PCI Memory Write to data read into a DMA FIFO.
3.5.5
DMA Priority
The DMA Channel Priority bits (MARBR[20:19]) can be used to specify the following priorities: * Rotating (MARBR[20:19]=00) * DMA Channel 0 (MARBR[20:19]=01) * DMA Channel 1 (MARBR[20:19]=10)
3.5.4.1
DMA Abort
DMA transfers can be aborted, in addition to the EOT# signal, as follows: 1. Clear the DMA Channel Enable bit(s) (DMACSR0[0]=0 and/or DMACSR1[0]=0). 2. Abort DMA by setting the Channel Abort bit(s) (DMACSR0[2]=1 and/or DMACSR1[2]=1). 3. Wait until the Channel Done bit(s) is set (DMACSR0[4]=1 and/or DMACSR1[4]=1).
Note: One to two Data transfers occur after the Abort bit is set. Aborting when no DMA cycles are in progress causes the next DMA to abort.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-23
Section 3--M Func Desc
Section 3 M Mode Functional Description
DMA Operation
1
Set DMA Mode to Scatter/Gather
3
Local or Host Memory PCI Memory
Mode Register
First PCI Address First Local Address First Transfer Size (byte count) Next Descriptor Pointer First Memory Block to Transfer
2
Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s)
PCI Address Local Address Transfer Size (byte count) Next Descriptor Pointer Command/Status Register 4 Set Enable and Start Bits in DMA Command/Status Register(s) (DMACSR0 and/or DMACSR1) to Initiate DMA Transfer End of Chain Specification Bit Local Memory Next Memory Block to Transfer
First Memory Block to Transfer
Next Memory Block to Transfer
Figure 3-17. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0 and/or DMADAC1) Register Dependent]
Local or Host Memory PCI Memory
1
Set DMA Mode to Scatter/Gather
3
Mode Register
PCI Address Low First Local Address First Transfer Size (byte count) Next Descriptor Pointer PCI Address High First Memory Block to Transfer
2
Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s)
PCI Address Low Local Address Transfer Size (byte count) Next Descriptor Pointer
Next Memory Block to Transfer
Command/Status Register 4 Set Enable and Start Bits in DMA Command/Status Register(s) (DMACSR0 and/or DMACSR1) to Initiate DMA Transfer
PCI Address High
Local Memory
End of Chain Specification Bit
First Memory Block to Transfer
Next Memory Block to Transfer
Figure 3-18. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18] and/or DMAMODE1[18]) Descriptor Dependent (PCI Address High Added)]
3-24
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Section 3 M Mode Functional Description
3.5.6
DMA Channel 0 and Channel 1 Interrupts
A DMA channel can assert a PCI Bus or Local Bus interrupt when done (transfer complete) or after a transfer is complete for the current descriptor in Scatter/ Gather DMA mode. The DMA Channel Interrupt Select bit(s) determine whether to assert a PCI (DMAMODE0[17]=1 and/or DMAMODE1[17]=1) or Local (DMAMODE0[17]=0 and/or DMAMODE1[17]=0) interrupt. The PCI or Local processor can read the DMA Channel 0 Interrupt Active bits to determine whether a DMA Channel 0 (INTCSR[21]) or DMA Channel 1 (INTCSR[22]) interrupt is pending. The Channel Done bit(s) (DMACSR0[4] and/or DMACSR1[4]) can be used to determine whether an interrupt is: * DMA Done interrupt * Transfer complete for current descriptor interrupt
The Done Interrupt Enable bit(s) (DMAMODE0[10] and/or DMAMODE1[10]) enable a Done interrupt. In Scatter/Gather DMA mode, a bit in the Next Descriptor Pointer register of the channel (loaded from Local memory) specifies whether to assert an interrupt at the end of the transfer for the current descriptor. A DMA Channel interrupt is cleared by the Channel Clear Interrupt bit(s) (DMACSR0[3]=1 and/or DMACSR1[3]=1).
3.5.7
DMA Data Transfers
The PCI 9056 DMA controller can be programmed to transfer data from the Local-to-PCI Bus or from the PCI-to-Local Bus.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-25
Section 3--M Func Desc
Section 3 M Mode Functional Description
DMA Operation
3.5.7.1
Local-to-PCI Bus DMA Transfer
PCI Interrupt Generation (Programmable)
Local Interrupt Generation (Programmable) Unload FIFO with PCI Bus Write Cycles
*
Done
FIFO
PCI Bus Arbitration Local Bus Arbitration
Load FIFO with Local Bus Read Cycles
*
Done
PCI Bus Arbitration:
Local Bus Arbitration:
*
Releases control of PCI Bus whenever FIFO becomes empty, PCI Bus Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending. GNT# Rearbitrates for control of PCI Bus when preprogrammed number of entries in FIFO becomes available, or after two PCI clocks if disconnect is received. REQ# BG# BR#, BB#
* *
Releases control of Local Bus whenever FIFO becomes full, terminal count is reached, Local Bus Latency Timer is enabled and expires, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of empty entries in FIFO becomes available. If Local Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires.
*
Figure 3-19. Local-to-PCI Bus DMA Data Transfer Operation
3.5.7.2
PCI-to-Local Bus DMA Transfer
Local Interrupt Generation (Programmable)
PCI Interrupt Generation (Programmable)
*
Done Load FIFO with PCI Bus Read Cycles
*
FIFO
PCI Bus Arbitration Local Bus Arbitration
Unload FIFO with Local Bus Write Cycles
Done
PCI Bus Arbitration:
Local Bus Arbitration:
*
Releases control of PCI Bus whenever FIFO becomes full, terminal count is reached, PCI Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending. Rearbitrates for control of PCI Bus when preprogrammed number of empty entries in FIFO becomes available, or after two PCI clocks if disconnect is received. GNT# REQ# BG# BR#, BB#
* *
Releases control of Local Bus whenever FIFO becomes empty, Local Bus Latency Timer is enabled and expires, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of entries becomes available in FIFO or PCI terminal count is reached. If Local Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires.
*
Figure 3-20. PCI-to-Local Bus DMA Data Transfer Operation
3-26
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Section 3 M Mode Functional Description
3.5.7.3
DMA Local Bus Error Condition
The PCI 9056 supports Local Bus error conditions with the TEA# signal. TEA# may be asserted by a device on the Local Bus, either before or simultaneously with TA#. In either case, the PCI 9056 attempts to finish the current transaction by transferring data and then asserting TS# for every address that follows, waiting for another TA# or TEA# to be issued to flush the FIFOs. After sensing TEA# is asserted, the PCI 9056 asserts PCI SERR# and sets the Signaled System Error bit (PCISR[14], indicating a catastrophic error occurred on the Local Bus. SERR# may be masked by resetting the TEA# Input Interrupt Mask bit (LMISC1[5]=0). The PCI 9056 Local Bus Latency Timer (MARBR[7:0]), as well as the Local Bus Pause Timer (MARBR[15:8]), can be used to better utilize the Local Bus.
If BDIP# output is not required to be driven by the PCI 9056 for a DMA transfer (bit [15]=1), the DMA controller releases the data bus after it receives an external TA# or the internal wait state counter decrements to 0 for the current Lword. When the PCI 9056 is in Demand Mode DMA Local-to-PCI Fast Terminate mode (DMAMODE0[15] and/or DMAMODE1[15]) unaligned DMA transfers, it monitors PCI address increments to guarantee Qword PCI data, 32-bit data completion when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer, Demand Mode DMA pause. Due to the nature of unaligned transfers, the PCI 9056 retains partial data, and seven or fewer bytes remaining in the DMA FIFO are not transferred when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer. When DREQ0# and/or DREQ1# resumes, the data is transferred to the PCI Bus. If the DREQ0# and/or DREQ1# assertion does not resume for ongoing transfers, the EOT# signal assertion (along with DREQ0# and/or DREQ1# de-assertion) should be used to ensure the partial data successfully transfers to the PCI Bus. These same conditions for DMA PCI-to-Local cause the PCI 9056 to immediately pause the DMA transfer on the Local Bus at Lword boundary. EOT# assertion (along with DREQ0# and/or DREQ1# de-assertion) causes the PCI 9056 to immediately terminate the ongoing Data transfer and flush the DMA FIFO. If BDIP# output must be driven by the PCI 9056 for the DMA transfer (bit [15]=0), the DMA controller continues transferring data up to the nearest 16-byte boundary. If DREQ0# and/or DREQ1# is de-asserted, or the Local Latency Timer expired (MARBR register) during the Address phase of the first transfer in PCI 9056 Local Bus ownership (TS#, BG# asserted), the DMA controller completes a 16-byte transfer. If DREQ0# and/or DREQ1# is de-asserted, or the Local Latency Timer expired (MARBR register) during a Data-Transfer phase, one Lword before the last 16-byte transfer, the PCI 9056 finishes the transfer and performs an additional 16-byte transfer to satisfy BDIP# de-assertion protocol. (Refer to Table 3-7.)
3.5.7.4
DMA Unaligned Transfers
For unaligned Local-to-PCI transfers, the PCI 9056 reads a partial Lword from the Local Bus. It continues to perform a single cycle read (Lwords) from the Local Bus until the nearest 16-byte boundary. If the Burst Mode bit is enabled, the PCI 9056 bursts thereafter. Lwords are assembled, aligned to the PCI Bus address, and loaded into the FIFO until the nearest 16-byte boundary. For PCI-to-Local transfers, Lwords are read from the PCI Bus and loaded into the FIFO. On the Local Bus, Lwords are assembled from the FIFO, aligned to the Local Bus address and single cycle written to the Local Bus until the nearest 16-byte boundary. If burst functionality is enabled, the PCI 9056 bursts thereafter.
3.5.8
Demand Mode DMA, Channel 0 and Channel 1
The Fast/Slow Terminate Mode Select bit(s) (DMAMODE0[15] and/or DMAMODE1[15]) determines the number of Lwords to transfer after the DMA controller DREQ0# and/or DREQ1# input is de-asserted.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-27
Section 3--M Func Desc
Section 3 M Mode Functional Description
DMA Operation
Table 3-7. Demand Mode DMA, Channel 0 and Channel 1
BTERM# Input Enable Bit(s) Fast/Slow Terminate Mode Select Bit(s)
(Refer to Section 2.2.5.2.1.) EOT# assertion (along with DREQ0# and/or DREQ1# de-assertion) causes the PCI 9056 to terminate the ongoing Data transfer and flush the DMA FIFO.
PCI 9056 BDIP# Output
BDIP# is not asserted. Immediate transfer terminated by EOT#, or until BI# asserts for one CLK cycle. (Refer to Section 2.2.5.2.1.) BDIP# is asserted by the PCI 9056 until the last Data transfer, or until BI# asserts for one CLK cycle. (Refer to Section 2.2.5.2.1.) BDIP# is not asserted. Immediate transfer terminated by EOT#, or until BI# asserts for one CLK cycle. (Refer to Section 2.2.5.2.1.) BDIP# is asserted by the PCI 9056. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible).
3.5.9
End of Transfer (EOT#) Input
Enabled (1)
Disabled (1)
The DMA EOT# Enable bit(s) (DMAMODE0[14] and/or DMAMODE1[14]) determines the number of Lwords to transfer after a DMA controller asserts EOT# input. EOT# input should be asserted only when the PCI 9056 owns a bus. (Refer to Table 3-8.) If BDIP# output is not required to be driven by the PCI 9056 for the DMA transfer (DMAMODE0[15]=1 and/or DMAMODE1[15]=1), and the DMA EOT# Enable bit(s) is set (DMAMODE0[14]=1 and/or DMAMODE1[14]=1), the DMA controller releases the data bus and terminates DMA after receiving an external TA# signal. Or, the internal wait state counter decrements to 0 for the current Lword when EOT# is asserted. If BDIP# output must be driven by the PCI 9056 for the DMA transfer (DMAMODE0[15]=0 and/or DMAMODE1[15]=0), the DMA controller transfers data up to the nearest 16-byte boundary if EOT#, (DMAMODE0[14]=1 and/or DMAMODE1[14]=1) is asserted and enabled. When the BTERM# Enable bit is disabled, Fast/Slow Terminate is enabled, and EOT# is asserted during the Data-Transfer phase of the last four bytes of a 16-byte transfer, the PCI 9056 completes the transfer and performs an additional 16-byte transfer to satisfy the BDIP# de-assertion protocol. Otherwise, it completes the current 16-byte transfer. When the BTERM# Enable bit is enabled, or the BTERM# Enable bit is disabled and Fast/Slow Terminate is disabled, the DMA controller terminates a transfer on an Lword boundary after EOT# is asserted. For an 8-bit bus, the PCI 9056 terminates after transferring the last byte for the Lword. For a 16-bit bus, the PCI 9056 terminates after transferring the last word for the Lword. In Single Cycle mode (burst disabled), the transfer is terminated at the next Lword boundary after EOT# occurs. The exception to this is when EOT# occurs on the last four bytes of the Transfer Count setting.
Enabled (1)
Enabled (0)
Disabled (0)
Disabled (1)
Disabled (0)
Enabled (0)
When the PCI 9056 is in Demand Mode DMA Local-to-PCI Slow Terminate mode (DMAMODE0[15] and/or DMAMODE1[15]) unaligned DMA transfers, it monitors PCI address increments to guarantee a Qword PCI data, 32-bit data completion when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer, Demand Mode DMA pause. Due to the nature of unaligned transfers, the PCI 9056 retains partial Qword data, seven or fewer bytes remain in the DMA FIFO and are not transferred when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer. When DREQ0# and/or DREQ1# resumes, the data is transferred to the PCI Bus. If DREQ0# and/or DREQ1# assertion is never resumed for ongoing transfers, the EOT# signal assertion (along with DREQ0# and/or DREQ1# de-assertion) should be used to ensure the partial data successfully transfers to the PCI Bus. These same conditions for DMA PCI-to-Local cause the PCI 9056 to pause the DMA transfer on the Local Bus at the Qword Address or Lword Data boundary, dependent upon BTERM# Input Enable bit.
3-28
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Section 3 M Mode Functional Description
During the descriptor loading on the Local Bus, EOT# assertion causes a complete descriptor load and no subsequent Data transfer; however, this is not recommended. This has no effect when the descriptor is loaded from the PCI Bus.
Table 3-8. Any DMA Transfer Channel 0 and Channel 1 with EOT Functionality
BTERM# Enable Bit(s) Fast/Slow Terminate Mode Select Bit(s)
Master (that is, it holds the bus until instructed to release BB#) under the following conditions: * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * Direct Slave access is pending * EOT# input is received (if enabled) The DMA controller releases control of the PCI Bus when one of the following conditions occurs: * FIFOs are full or empty * PCI Bus Latency Timer expires (PCILTR[7:0])-- and loses the PCI GNT# signal * Target disconnect response is received The DMA controller de-asserts PCI REQ# for a minimum of two PCI clocks.
PCI 9056 BDIP# Output
BDIP# is not asserted. Transfer is immediately terminated by EOT# or paused by DREQ# at Lword boundary, or until BI# asserts for one CLK cycle. (Refer to Section 2.2.5.2.1.) BDIP# is asserted by the PCI 9056 until last Data transfer. Transfer is immediately terminated by EOT# or paused by DREQ# at Lword boundary. BDIP# is not asserted. Transfer is immediately terminated by EOT# or paused by DREQ# at Lword boundary. BDIP# is asserted by the PCI 9056. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible).
Enabled (1)
Disabled (1)
3.5.11 Local Bus Latency and Pause Timers
The Local Bus Latency and Pause Timers are programmable with the Mode/DMA Arbitration register (MARBR[7:0, 15:8], respectively). If the Local Bus Latency Timer is enabled and expires, the PCI 9056 completes an Lword transfer up to the nearest 16-byte boundary and releases the Local Bus, de-asserting BB#. After the programmable Pause Timer expires, it arbitrates for the bus by asserting BR#. When it receives BG#, it asserts BB# and continues to transfer until the FIFO is empty for a Local-to-PCI transfer or full for a PCI-to-Local transfer. The DMA transfer can be paused by writing a 0 to the Channel Enable bit. To acknowledge the disable, the PCI 9056 gets at least one data from the bus before it stops. However, this is not recommended during a burst. The DMA Local Bus Timer starts after the Local Bus is granted to the PCI 9056 and the Local Pause Timer starts after BB# is de-asserted.
Enabled (1)
Enabled (0)
Disabled (0)
Disabled (1)
Disabled (0)
Enabled (0)
3.5.10 DMA Arbitration
The PCI 9056 asserts BR# when it needs to be the Local Bus Master. Upon receiving BG#, the PCI 9056 waits for BB# to be de-asserted. The PCI 9056 then asserts BB# at the next rising edge of the Local clock after sensing that BB# is de-asserted (no other device is acting as Local Bus Master). The PCI 9056 continues to assert BB# while acting as the Local Bus
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-29
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
3.6
M MODE TIMING DIAGRAMS
Note: In the timing diagrams that follow, the "_" symbol at the end of the signal names represents the "#" symbol.
3.6.1
M Mode Direct Master Timing Diagrams
Timing Diagram 3-1. Direct Master Single Write to PCI Memory Space
3-30
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-2. Direct Master Single Read from PCI Memory Space
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-31
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-3. Direct Master Single Write to PCI I/O Space
3-32
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-4. Direct Master Single Read from PCI I/O Space
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-33
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-5. Direct Master Burst Write to PCI Memory Space
3-34
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-6. Direct Master Burst Read from PCI Memory Space
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-35
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-7. Direct Master Burst Write with a Retry on PCI Bus
3-36
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-8. Direct Master Burst Read with a Retry on Local Bus
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-37
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
3.6.2
M Mode Direct Slave Timing Diagrams
Timing Diagram 3-9. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Write
3-38
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-10. Direct Slave Burst Write
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-39
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-11. Direct Slave Burst Read
3-40
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-12. Direct Slave Single Write
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-41
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-13. Direct Slave Delay Burst Read
3-42
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-14. Direct Slave Single Read Ahead
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-43
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-15. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read Ahead Enabled
3-44
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-16. Direct Slave Burst Write and Read with Timer 8
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-45
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-17. Direct Slave from PCI Bus to 32-Bit Device on Local Bus; Local Bus Latency and Pause Timers Set to 23 to Test LHOLD
3-46
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-18. PCI Parity Error (Address Phase), SERR# Asserted
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-47
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-19. PCI Parity PERR# Direct Slave Write Interrupts, First Data Phase
3-48
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-20. PCI Parity PERR# on Direct Slave Read Interrupts, First Data, DP0
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-49
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-21. Direct Slave Burst Write 4 Data, Big Endian, Upper Bytes [31:24]
3-50
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-22. Direct Slave Burst Read 7, Big Endian, Lower Bytes [7:0]
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-51
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
3.6.3
M Mode DMA Timing Diagrams
Timing Diagram 3-23. DMA Channel 0 Local-to-PCI (Memory Write Command)
3-52
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-24. DMA Channel 0 PCI-to-Local (Memory Read Line Command)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-53
Section 3--M Func Desc
Section 3 M Mode Functional Description
M Mode Timing Diagrams
Timing Diagram 3-25. DMA Channel 0 PCI-to-Local (Memory Read Command)
3-54
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Mode Timing Diagrams
Section 3 M Mode Functional Description
Timing Diagram 3-26. DMA Channel 1 PCI-to-Local (Memory Read Command)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
3-55
Section 3--M Func Desc
4
4.1
C AND J MODES BUS OPERATION
PCI BUS CYCLES 4.1.2.1 DMA Master Command Codes
The PCI 9056 DMA controllers can assert the Memory Command cycles listed in Table 4-2.
Table 4-2. DMA Master Command Codes
Command Type
Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate
The PCI 9056 is compliant with PCI r2.2. Refer to PCI r2.2 for specific PCI Bus functions.
4.1.1
Direct Slave Command Codes
As a Target, the PCI 9056 allows access to the PCI 9056 internal registers and the Local Bus, using the commands listed in Table 4-1. All Read or Write accesses to the PCI 9056 can be Byte, Word, or Long-Word (Lword) accesses, defined as 32 bit. All memory commands are aliased to basic memory commands. All I/O accesses to the PCI 9056 are decoded to an Lword boundary. Byte enables are used to determine which bytes are read or written. An I/O access with illegal byte enable combinations is terminated with a Target Abort.
Table 4-1. Direct Slave Command Codes
Command Type
I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write and Invalidate
Code (C/BE[3:0]#)
0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh)
4.1.2.2
Direct Master Local-to-PCI Command Codes
Code (C/BE[3:0]#)
0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1010 (Ah) 1011 (Bh) 1100 (Ch) 1110 (Eh) 1111 (Fh)
For Direct Master Local-to-PCI Bus accesses, the PCI 9056 asserts the cycles listed in Table 4-3 through Table 4-5.
Table 4-3. Local-to-PCI Memory Access
Command Type
Memory Read Memory Write Memory Read Multiple PCI Dual Address Cycle Memory Read Line Memory Write and Invalidate
Code (C/BE[3:0]#)
0110 (6h) 0111 (7h) 1100 (Ch) 1101 (Dh) 1110 (Eh) 1111 (Fh)
4.1.2
PCI Master Command Codes
Table 4-4. Local-to-PCI I/O Access
Command Type
I/O Read I/O Write
Table 4-5. Local-to-PCI Configuration Access
Command Type
Configuration Memory Read Configuration Memory Write
Code (C/BE[3:0]#)
1010 (Ah) 1011 (Bh)
Notes: Programmable internal registers determine PCI command codes when the PCI 9056 is the Master. DMA cannot perform I/O or Configuration accesses.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-1
Section 4--C, J Bus Op
The PCI 9056 can access the PCI Bus to perform DMA or Direct Master Local-to-PCI Bus transfers. During a Direct Master or DMA transfer, the command code assigned to the PCI 9056 internal register location (CNTRL[15:0]) is used as the PCI command code (except for Memory Write and Invalidate mode for DMA cycles where DMPBAM[9]=1).
Code (C/BE[3:0]#)
0010 (2h) 0011 (3h)
Section 4 C and J Modes Bus Operation
Local Bus Cycles
4.1.3
PCI Arbitration
4.2.1
Local Bus Arbitration
The PCI 9056 asserts REQ# to request the PCI Bus. The PCI 9056 can be programmed using the PCI Request Mode bit (MARBR[23]) to de-assert REQ# when it asserts FRAME# during a Bus Master cycle, or to keep REQ# asserted for the entire Bus Master cycle. The PCI 9056 always de-asserts REQ# for a minimum of two PCI clocks after a bus ownership that sustains that sustains a Target disconnect. The Direct Master Write Delay bits (DMPBAM[15:14]) can be programmed to delay the PCI 9056 from asserting PCI REQ# during a Direct Master Write cycle. DMPBAM can be programmed to wait 0, 4, 8, or 16 PCI Bus clocks after the PCI 9056 has received its first Write data from the Local Bus Master and is ready to begin the PCI Write transaction. This function is useful in applications where a Local Master is bursting and a Local Bus clock is slower than the PCI Bus clock. This allows Write data to accumulate in the PCI 9056 Direct Master Write FIFO, which provides for better use of the PCI Bus.
The PCI 9056 asserts LHOLD to request the Local Bus. It owns the Local Bus when LHOLD and LHOLDA are asserted. When the PCI 9056 acknowledges BREQi assertion during DMA or Direct Slave Write transfers, it releases the Local Bus within two Lword transfers by de-asserting LHOLD and floating the Local Bus outputs if either of the following conditions exist: * BREQi is asserted and enabled * Gating is enabled and the Local Bus Latency Timer is enabled and expires (MARBR[27, 7:0], respectively) The Local Arbiter can now grant the Local Bus to another Local Master. After the PCI 9056 acknowledges that LHOLDA is de-asserted and the Local Bus Pause Timer is zero, it re-asserts LHOLD to request the Local Bus. When the PCI 9056 receives LHOLDA, it drives the bus and continues the transfer.
Note: The Local Bus Pause Timer applies only to DMA operation. It does not apply to Direct Slave operation.
4.2
LOCAL BUS CYCLES 4.2.2 Direct Master
Local Bus cycles can be single or Burst cycles. The BLAST# signal is used to determine whether a single or Burst cycle is to be performed. If BLAST# is asserted at the beginning of the first Data phase, the PCI 9056 performs a single PCI Bus cycle. Otherwise, the PCI 9056 performs a Burst PCI Bus cycle and BLAST# is used to end the cycle. As a Local Bus Target, the PCI 9056 allows access to the PCI 9056 internal registers and the PCI Bus. Non-32-bit Direct Master accesses to the PCI 9056 require simple external logic (latch array to combine data into a 32-bit bus). Local Bus Direct Master accesses to the PCI 9056 must be for a 32-bit non-pipelined bus.
The PCI 9056 interfaces a PCI Host bus to several Local Bus types, as listed in Table 4-6. It operates in one of three modes (selected through the MODE[1:0] pins), corresponding to the three bus types--M, C, and J.
Table 4-6. Local Bus Types
MODE1
1 1 0 0
MODE0
1 0 0 1
Bus Mode
M Reserved C J --
Bus Type
32-bit non-multiplexed
32-bit non-multiplexed 32-bit multiplexed
4.2.3
Direct Slave
The PCI Bus Master reads from and writes to the Local Bus (the PCI 9056 is a PCI Bus Target and a Local Bus Master).
4-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus Cycles
Section 4 C and J Modes Bus Operation
4.2.4
Wait State Control
4.2.4.1
Wait States--Local Bus
If READY# mode is disabled, the external READY# input signal has no effect on wait states for a Local access. Wait states between Data cycles are asserted internally by a wait state counter. The wait state counter is initialized with its Configuration register value at the start of each data access. If READY# mode is enabled, it has no effect until the wait state counter reaches 0. READY# then controls the number of additional wait states. BTERM# input is not sampled until the wait state counter reaches 0. BTERM# overrides READY# when BTERM# is enabled and asserted. The following figure illustrates the PCI 9056 wait states for C and J modes.
PCI Bus
Accessing PCI 9056 from PCI Bus
In Direct Master mode and when accessing the PCI 9056 registers, the PCI 9056 acts as a Local Bus Slave. The PCI 9056 asserts wait states by delaying the READY# signal. The Local processor asserts wait states with the WAIT# signal. In Direct Slave and DMA modes, the PCI 9056 acts as a Local Bus Master. The PCI 9056 inserts internal wait states with the WAIT# signal. The Local processor asserts external wait states by delaying the READY# signal. The Internal Wait State bit(s) (LBRD0[21:18, 5:2], LBRD1[5:2], DMAMODE0[5:2], and/or DMAMODE1 [5:2]) can be used to program the number of internal wait states between the first address-to-data (and subsequent data-to-data in Burst mode). During Direct Master accesses, WAIT# signal must be asserted during the ADS phase for the PCI 9056 to sample the wait state phase. In Direct Slave and DMA modes, the READY# signal has no effect until the wait state counter (LBRD0[21:18, 5:2], LBRD1[5:2], DMAMODE0[5:2], and/or DMAMODE1[5:2]) reaches zero. READY# then controls the number of wait states by being de-asserted in the middle of the Data transaction.
Local Bus
Accessing PCI 9056 from Local Bus
PCI 9056 de-asserts TRDY# when waiting on the Local Bus PCI Bus de-asserts IRDY# or simply ends the cycle when it is not ready PCI 9056 accessing PCI Bus PCI 9056 can be programmed to de-assert IRDY# when its Direct Master Read FIFO is full PCI Bus de-asserts TRDY# when it is not ready
PCI 9056 generates READY# when data is valid on the following clock edge Local Processor generates wait states with WAIT#
PCI 9056
PCI 9056 accessing Local Bus PCI 9056 generates wait states with WAIT# (programmable) Local Bus can respond to PCI 9056 requests with READY#
4.2.4.2
Wait States--PCI Bus
The PCI Bus Master throttles IRDY# and the PCI Bus Slave throttles TRDY# to assert PCI Bus wait state(s).
Figure 4-1. Wait States
Note: Figure 4-1 represents a sequence of Bus cycles.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-3
Section 4--C, J Bus Op
Section 4 C and J Modes Bus Operation
Local Bus Cycles
4.2.5
Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode)
4.2.5.2
Burst-4 Lword Mode
Note: In the following sections, Bterm refers to the PCI 9056 internal register bit and BTERM# refers to the PCI 9056 external signal.
If the Burst Mode bit is enabled and the Bterm Mode bit is disabled, bursting can start on any Lword boundary and continue up to a 16-byte address boundary. After data up to the boundary is transferred, the PCI 9056 asserts a new Address cycle (ADS#).
Table 4-8. Burst-4 Lword Mode
4.2.5.1
Burst and Bterm Modes
Bus Width
32 bit 16 bit 8 bit
Table 4-7. Burst and Bterm on the Local Bus
Mode
Single Cycle 0 1 Burst-4 1 Burst Forever 1 1 0
Burst
Four Lwords or up to a quad-Lword boundary (LA3, LA2 = 11) Four words or up to a Qword boundary (LA2, LA1 = 11) Four bytes or up to a quad-byte boundary (LA1, LA0 = 11)
Burst
0
Bterm
0
Result
One ADS# per data (default). One ADS# per data. One ADS# per four data (recommended for i960 and PPC401 family). One ADS# per BTERM# (refer to Section 4.2.5.2.1).
4.2.5.2.1 Continuous Burst Mode (Bterm "Burst Terminate" Mode)
If both the Burst and Bterm Mode bits are enabled, the PCI 9056 can operate beyond the Burst-4 Lword mode. Bterm mode enables PCI 9056 to perform long bursts to devices that can accept bursts of longer than four Lwords. The PCI 9056 asserts one Address cycle and continues to burst data. If a device requires a new Address cycle (ADS#), it can assert BTERM# input to cause the PCI 9056 to assert a new Address cycle. BTERM# input acknowledges current Data transfer and requests that a new Address cycle be asserted (ADS#). The new address is for the next Data transfer. If the Bterm Mode bit is enabled and the BTERM# signal is asserted, the PCI 9056 asserts BLAST# only if its Read FIFO is full, its Write FIFO is empty, or if a transfer is complete.
On the Local Bus, BLAST# and BTERM# perform the following: * If the Burst Mode bit is enabled, but the Bterm Mode bit is disabled, then the PCI 9056 bursts (up to a Qword boundary) four Lwords. BLAST# is asserted at the beginning of the fourth Lword Data phase (LA[3:2]=11) and a new ADS# is asserted at the first Lword (LA[3:2]=00) of the next burst. * If BTERM# is enabled and asserted, the PCI 9056 terminates the Burst cycle of the end of the current Data phase without generating BLAST#. The PCI 9056 generates a new burst transfer starting with a new ADS#, terminating it normally using BLAST#. * BTERM# input is valid only when the PCI 9056 is Master of the Local Bus (Direct Slave or DMA modes). * As an input, BTERM# is asserted by external logic. It instructs the PCI 9056 to break up a Burst cycle. * BTERM# is used to indicate a memory access is crossing a page boundary or requires a new Address cycle.
Notes: If Address Increment is disabled, the DMA transfer bursts beyond four Lwords. If the Bterm Mode bit is disabled, the PCI 9056 performs the following: * * * 32-bit Local Bus--Bursts up to four Lwords 16-bit Local Bus--Bursts up to two Lwords 8-bit Local Bus--Bursts up to one Lword
4.2.5.3
Partial Lword Accesses
Lword accesses, in which not all byte enables are asserted, are broken into single cycle accesses. Burst start addresses can be any Lword boundary. If the Burst Start Address in a Direct Slave or DMA transfer is not aligned to an Lword boundary, the PCI 9056 first performs a single cycle. It then starts to burst on the Lword boundary if there is remaining data that is not a whole Lword during DMA (for example, it results in a single cycle at the end).
In every case, it performs four transactions.
4-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Big Endian/Little Endian
Section 4 C and J Modes Bus Operation
4.2.6
Recovery States (J Mode Only)
In J mode, the PCI 9056 inserts one recovery state between the last Data transfer and the next Address cycle.
Note: The PCI 9056 does not support the i960J function that uses READY# input to add recovery states. No additional recovery states are added if READY# input remains asserted during the last Data cycle.
error (SERR#), or other means of PCI Bus transfer termination as a result of the parity error on the PCI data address, command code, and byte enables. The Local Bus Parity Check is passive and only provides parity information to the Local processor during Direct Master, Direct Slave, and DMA transfers. There is one data parity pin for each byte lane of the PCI 9056 data bus (DP[3:0]). "Even data parity" is asserted for each lane during Local Bus reads from the PCI 9056 and during PCI 9056 Master writes to the Local Bus. Even data parity is checked during Local Bus writes to the PCI 9056 and during PCI 9056 reads from the Local Bus. Parity is checked for each byte lane with an asserted byte enable. If a parity error is detected, LSERR# is asserted in the Clock cycle following the data being checked. Parity is checked for Direct Slave reads, Direct Master writes, and DMA Local Bus reads. The PCI 9056 sets a status bit and asserts an interrupt (LSERR#) in the clock cycle following data being checked if a parity error is detected. However, the Data Parity Error Status bit and interrupt are never set or asserted unless the READY# signal is active and asserted low. This applies only when the READY# signal is disabled in the PCI 9056 register. A workaround for this is to disable the READY# Enable bit and externally pull READY# low.
4.2.7
Local Bus Read Accesses
For all single cycle Local Bus Read accesses, the PCI 9056 reads only bytes corresponding to byte enables requested by the Direct Master. For all Burst Read cycles, the PCI 9056 passes all the bytes and can be programmed to: * Prefetch * Perform Read Ahead mode * Generate internal wait states * Enable external wait control (READY# input) * Enable type of Burst mode to perform
4.2.8
Local Bus Write Accesses
For Local Bus writes, only bytes specified by a PCI Bus master or the PCI 9056 DMA controller are written.
4.2.9
Direct Slave Accesses to 8- or 16-Bit Local Bus
Direct Slave PCI accesses to an 8- or 16-bit Local Bus results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each transfer, byte enables are encoded as in the i960C to provide Local Address bits LA[1:0].
4.3 4.3.1
BIG ENDIAN/LITTLE ENDIAN PCI Bus Little Endian Mode
4.2.10 Local Bus Data Parity
Generation or use of Local Bus data parity is optional. Signals on the data parity pins do not affect operation of the PCI 9056. The PCI Bus parity checking and generation is independent of the Local Bus parity checking and generation. PCI Bus parity checking may result in assertion of PERR#, a PCI Bus system
PCI Bus is a Little Endian bus (that is, the address is invariant and data is Lword-aligned to the lowermost byte lane).
Table 4-9. PCI Bus Little Endian Byte Lanes
Byte Number
0 1 2 3
Byte Lane
AD[7:0] AD[15:8] AD[23:16] AD[31:24]
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-5
Section 4--C, J Bus Op
Section 4 C and J Modes Bus Operation
Big Endian/Little Endian
4.3.2
Local Bus Big/Little Endian Mode
4.3.2.1
The PCI 9056 Local Bus can be programmed to operate in Big or Little Endian mode.
Table 4-10. Byte Number and Lane Cross-Reference
Byte Number Mode Big Endian
3 C 2 1 0 3 J 2 1 0
32-Bit Local Bus--Big Endian Mode
Data is Lword-aligned to the uppermost byte lane (Data Invariance).
Table 4-13. Upper Lword Lane Transfer-- 32-Bit Local Bus
Burst Order Byte Lane
Byte 0 appears on Local Data [31:24] First transfer Byte 1 appears on Local Data [23:16] Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0]
Little Endian
0 1 2 3 0 1 2 3
Byte Lane
LD[7:0] LD[15:8] LD[23:16] LD[31:24] LAD[7:0] LAD[15:8] LAD[23:16] LAD[31:24]
Little Endian 31 BYTE 3 BYTE 2 BYTE 1 BYTE 0 0
Table 4-11. Big/Little Endian Program Mode
BIGEND# Pin
0 0 1 1
BIGEND Register (1=Big, 0=Little)
0 1 0 1
Endian Mode
Big Big Little Big
31 BYTE 0 BYTE 1 BYTE 2 BYTE 3
0
Big Endian
Table 4-12 lists register bits associated with the following cycles.
Table 4-12. Cycle Reference
Cycle
Local access to the Configuration registers Direct Master, Memory, and I/O Direct Slave
Figure 4-2. Big/Little Endian--32-Bit Local Bus
Register Bits
BIGEND[0] BIGEND[1] BIGEND[2], Space 0, and BIGEND[3], Expansion ROM
In Big Endian mode, the PCI 9056 transposes data byte lanes. Data is transferred as listed in Table 4-13 through Table 4-18.
4-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Big Endian/Little Endian
Section 4 C and J Modes Bus Operation
4.3.2.2
16-Bit Local Bus--Big Endian Mode
4.3.2.3
8-Bit Local Bus--Big Endian Mode
For a 16-bit Local Bus, the PCI 9056 can be programmed to use the upper or lower word lanes.
Table 4-14. Upper Word Lane Transfer-- 16-Bit Local Bus
Burst Order
First transfer
For an 8-bit Local Bus, the PCI 9056 can be programmed to use the upper or lower byte lanes.
Table 4-16. Upper Byte Lane Transfer-- 8-Bit Local Bus
Burst Order
First transfer Second transfer Third transfer Fourth transfer
Byte Lane
Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16] Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [23:16]
Byte Lane
Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [31:24] Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [31:24]
Second transfer
Table 4-15. Lower Word Lane Transfer-- 16-Bit Local Bus
Burst Order
First transfer
Table 4-17. Lower Byte Lane Transfer-- 8-Bit Local Bus
Burst Order
First transfer Second transfer Third transfer Fourth transfer
Byte Lane
Byte 0 appears on Local Data [15:8] Byte 1 appears on Local Data [7:0] Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0]
Byte Lane
Byte 0 appears on Local Data [7:0] Byte 1 appears on Local Data [7:0] Byte 2 appears on Local Data [7:0] Byte 3 appears on Local Data [7:0]
Second transfer
31 BYTE 3
Little Endian BYTE 2 BYTE 1
First Cycle
0 BYTE 0
31 BYTE 3
Little Endian BYTE 2 BYTE 1
Second Cycle
0 BYTE 0
First Cycle
15
Second Cycle
0 BYTE 0 BYTE 1 0 Big Endian
Fourth Cycle
Third Cycle
7 8 BYTE 0 7
0 0
15 16 7 BYTE 0 24 7 0 23 BYTE 0
31 BYTE 0 15 Big Endian BYTE 1
15 16 0
0
31 BYTE 0 7
0
Big Endian
Figure 4-3. Big/Little Endian--16-Bit Local Bus
Figure 4-4. Big/Little Endian--8-Bit Local Bus
Section 4--C, J Bus Op
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-7
Section 4 C and J Modes Bus Operation
Serial EEPROM
4.3.2.4
Local Bus Big/Little Endian Mode Accesses
4.4.1.2
Local Initialization
Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of this section.
For each of the following transfer types, the PCI 9056 Local Bus can be independently programmed to operate in Big or Little Endian mode: * Local Bus accesses to the PCI 9056 Configuration registers * Direct Slave PCI accesses to Local Address Space 0 * Direct Slave PCI accesses to Local Address Space 1 * Direct Slave PCI accesses to the Expansion ROM * DMA Channel 0 accesses to the Local Bus * DMA Channel 1 accesses to the Local Bus * Direct Master accesses to the PCI Bus For Local Bus accesses to the Internal Configuration registers and Direct Master accesses, use BIGEND# to dynamically change the Endian mode.
Notes: The PCI Bus is always Little Endian. Only byte lanes are swapped, not individual bits.
4.4
SERIAL EEPROM
Functional operation described can be modified through the PCI 9056 programmable internal registers.
4.4.1
Vendor and Device ID Registers
Three Vendor and Device ID registers are supported: * PCIIDR--Contains normal Device and Vendor IDs. Can be loaded from the serial EEPROM or Local processor(s). * PCISVID--Contains Subsystem and Subvendor IDs. Can be loaded from the serial EEPROM or Local processor(s). * PCIHIDR--Contains hardwired PLX Vendor and Device IDs.
4.4.1.1
Serial EEPROM Initialization
During serial EEPROM initialization, the PCI 9056 responds to Direct Slave accesses with a Retry. During serial EEPROM initialization, the PCI 9056 responds to a Local processor access by delaying acknowledgment of the cycle (READY#).
4-8
Preliminary Information
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 4 C and J Modes Bus Operation
Refer to the document, PCI 9056 Blue Book high when bit 31 is set. When reading the serial Revision 0.91 Correction, for the corrected version EEPROM, bit 31 must be set to 1. of this section. To perform the read, the basic approach is to set the EECS and EEDO bits (bits 25 and 31, respectively) to the desired level and then toggle EESK high and low until done. For example, reading the serial EEPROM at location 0 involves the following steps:
4.4.2
Serial EEPROM Operation
1. Clear EESK, EEDO and EECS bits. 2. Set EECS high. 3. Toggle EESK high, then low. 4. Set EEDO bit high (start bit). 5. Toggle EESK high, then low. 6. Repeat step 6. 7. Clear EEDO. 8. Toggle EESK high, then low. 9. Toggle EESK bit high, then low 8 times (clock in serial EEPROM Address 0). 10. Set bit 31 to float the EEDO pin for reading. 11. Toggle EESK high, then low 16 times (clock in one word from serial EEPROM). 12. After each clock pulse, read bit 27 and save. 13. Clear EECS bit. 14. Toggle EESK high, then low. 15. Read is now complete. The serial EEPROM can also be read or written, using the VPD function. (Refer to Section 10.) The PCI 9056 has two serial EEPROM load options: * Long Load Mode--Default. The PCI 9056 loads 17 Lwords from the serial EEPROM if the Extra Long Load from the Serial EEPROM bit is clear (LBRD0[25]=0) * Extra Long Load Mode--The PCI 9056 loads 23 Lwords from the serial EEPROM if the Extra Long Load from the Serial EEPROM bit is set (LBRD0[25]=1) during a Long Load
Section 4--C, J Bus Op
Preliminary Information 4-9
After reset, the PCI 9056 attempts to read the serial EEPROM to determine its presence. An active Start bit set to 0 indicates a serial EEPROM is present. The PCI 9056 supports 2K bit (FM93CS56L or compatible) or 4K bit (FM93CS66L or compatible) devices. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The first Lword is then checked to verify that the serial EEPROM is programmed. If the first Lword (33 bits) is all ones (1), a blank serial EEPROM is present. If the first Lword (33 bits) is all zeros, no serial EEPROM is present. For both conditions, the PCI 9056 reverts to the default values. (Refer to Table 4-18.) The Programmed Serial EEPROM Present bit is set (CNTRL[28]=1) if the serial EEPROM is programmed (real or random data if a serial EEPROM is detected). The 3.3V serial EEPROM clock (EESK) is derived from the PCI clock. The PCI 9056 generates the serial EEPROM clock by internally dividing the PCI clock by 268. For a 66.6 MHz PCI Bus, EESK is 248.7 kHz; for a 33.3 MHz PCI Bus, EESK is 124.4 kHz. The serial EEPROM can be read or written from the PCI or Local Buses. The Serial EEPROM Control Register bits (CNTRL[31, 27:24]) control the PCI 9056 pins that enable reading or writing of serial EEPROM data bits. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The PCI 9056 provides the ability to manually access the serial EEPROM interface by using CNTRL[31, 27:24] (EESK, EECS, and EEDI/EEDO controlled by software). Bit 24 is used to generate EESK (clock), bit 25 controls the chip select, and bit 31 enables EEDO Input buffer. Bit 27, when read, returns the value of EEDI. Setting bits [31, 25, 24] to 1 causes the EEDI output to go high. A pull-up resistor is required on EEDO to go
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Section 4 C and J Modes Bus Operation
Serial EEPROM
Table 4-18. Serial EEPROM Guidelines
Local Processor
None
Serial EEPROM
None
System Boot Condition
The PCI 9056 uses default values. The EEDI/EEDO pin must be pulled low--a 1K ohm resistor is required (rather than pulled high, which is typically done for this pin). If the PCI 9056 detects all zeros, it reverts to default values. Boot with serial EEPROM values. The Local Init Status bit (LMISC1[2]) must be set by the serial EEPROM. A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO. The PCI 9056 detects a blank device and reverts to default values. A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO. Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of this table entry.
None
Programmed
None Present
Blank None
Present
Programmed
Load serial EEPROM, but the Local processor can reprogram the PCI 9056. Either the Local processor or the serial EEPROM must set the Local Init Status bit (LMISC1[2]=done). A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO.
The PCI 9056 detects a blank serial EEPROM and reverts to default values. A 3K to 10K ohm pull-up resistor is required on EDDI/EEDO. Notes: In some systems, the Local processor may be too late to reconfigure the PCI 9056 registers before the BIOS configures them. The serial EEPROM can be programmed through the PCI 9056 after the system boots in this condition.
Present
Blank
Note: If the serial EEPROM is missing and a Local Processor is present with blank Flash, the condition None/None (as seen in Table 4-18) applies, until the Processor's Flash is programmed.
4.4.2.1
Long Serial EEPROM Load
The registers listed in Table 4-19 are loaded from the serial EEPROM after a reset is de-asserted if the Extra Long Load from Serial EEPROM bit is not set (LBRD0[25]=0). The serial EEPROM is organized in words (16 bit). The PCI 9056 first loads the Most Significant Word bits (MSW[31:16]), starting from the Most Significant bit, (MSB[31]). The PCI 9056 then loads the Least Significant Word bits (LSW[15:0]), starting again from the Most Significant bit (MSB[15]). Therefore, the PCI 9056 loads the Device ID, Vendor ID, Class Code, and so forth. The serial EEPROM values can be programmed using an EEPROM programmer. The values can also be programmed using the PCI 9056 VPD function (refer to Section 10) or through the Serial EEPROM Control register (CNTRL).
The CNTRL register allows programming of the serial EEPROM, one bit at a time. To read back the value from the serial EEPROM, the CNTRL[27] bit (refer to Section 4.4.2) or the VPD function should be utilized. With full utilization of VPD, the designer can perform reads and writes from/to the serial EEPROM, 32 bits at a time. Values should be programmed in the order listed in Table 4-19. The 34, 16-bit words listed in the table are stored sequentially in the serial EEPROM.
4.4.2.2
Extra Long Serial EEPROM Load
The registers listed in the Local Address Space 0/ Expansion ROM Bus Region Descriptor register (LBRD0) are loaded from the serial EEPROM after a reset is de-asserted if the Extra Long Load from Serial EEPROM bit is set (LBRD0[25]=1). The serial EEPROM is organized in words (16 bit). The PCI 9056 first loads the Most Significant Word bits (MSW[31:16]), starting from the Most Significant bit (MSB[31]). It then loads the Least Significant Word bits (LSW[15:0]), restarting from the Most Significant bit (MSB[15]). Therefore, the PCI 9056 loads Device ID, Vendor ID, Class Code, and so forth.
4-10
Preliminary Information
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 4 C and J Modes Bus Operation
The serial EEPROM values can be programmed using an EEPROM programmer. The values can also be programmed using the PCI 9056 VPD function or through the Serial EEPROM Control register (CNTRL).
Table 4-19. Long Serial EEPROM Load Registers
Serial EEPROM Offset
0h 2h 4h 6h 8h Ah Ch Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h Device ID Vendor ID Class Code Class Code / Revision Maximum Latency / Minimum Grant Interrupt Pin / Interrupt Line Routing MSW of Mailbox 0 (User Defined) LSW of Mailbox 0 (User Defined) MSW of Mailbox 1 (User Defined) LSW of Mailbox 1 (User Defined) MSW of Range for PCI-to-Local Address Space 0 LSW of Range for PCI-to-Local Address Space 0
Values should be programmed in the order listed in Table 4-20. The 46 16-bit words listed in Table 4-19 and Table 4-20 should be stored sequentially in the serial EEPROM.
Description
Register Bits Affected PCIIDR[31:16] PCIIDR[15:0] PCICCR[23:8] PCICCR[7:0] / PCIREV[7:0] PCIMLR[7:0] / PCIMGR[7:0] PCIIPR[7:0] / PCIILR[7:0] MBOX0[31:16] MBOX0[15:0] MBOX1[31:16] MBOX1[15:0] LAS0RR[31:16] LAS0RR[15:0] LAS0BA[31:16] LAS0BA[15:0] MARBR[31:16] MARBR[15:0] LMISC2[7:0] / PROT_AREA[7:0] LMISC1[7:0] / BIGEND[7:0] EROMRR[31:16] EROMRR[15:0] EROMBA[31:16] EROMBA[15:0] LBRD0[31:16] LBRD0[15:0] DMRR[31:16] DMRR[15:0] DMLBAM[31:16] DMLBAM[15:0] DMLBAI[31:16] DMPBAM[31:16] DMPBAM[15:0] DMCFGA[31:16] DMCFGA[15:0]
MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 MSW of Mode/DMA Arbitration Register LSW of Mode/DMA Arbitration Register MSW of Local Miscellaneous Control Register 2 / MSW of Serial EEPROM Write-Protected Address LSW of Local Miscellaneous Control Register 1 / LSW of Local Bus Big/Little Endian Descriptor Register MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM MSW of Bus Region Descriptors for PCI-to-Local Accesses LSW of Bus Region Descriptors for PCI-to-Local Accesses MSW of Range for Direct Master-to-PCI LSW of Range for Direct Master-to-PCI MSW of Local Base Address for Direct Master-to-PCI Memory LSW of Local Base Address for Direct Master-to-PCI Memory MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration MSW of PCI Base Address (Remap) for Direct Master-to-PCI LSW of PCI Base Address (Remap) for Direct Master-to-PCI MSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration LSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-11
Section 4--C, J Bus Op
DMLBAI[15:0]
Section 4 C and J Modes Bus Operation
Serial EEPROM
Table 4-20. Extra Long Serial EEPROM Load Registers
Serial EEPROM Offset
44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah Subsystem ID Subsystem Vendor ID MSW of Range for PCI-to-Local Address Space 1 (1 MB) LSW of Range for PCI-to-Local Address Space 1 (1 MB) MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 MSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses LSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses MSW of Hot Swap Control LSW of Hot Swap Control / Hot Swap Next Capability Pointer PCI Arbiter Control Reserved
Description
Register Bits Affected
PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS1BA[31:16] LAS1BA[15:0] LBRD1[31:16] LBRD1[15:0] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] PCIARB[3:0] Reserved
4.4.2.3
New Capabilities Function Support
4.4.2.4
Recommended Serial EEPROMs
The New Capabilities Function Support includes PCI Power Management, Hot Swap, and VPD features, as listed in Table 4-21.
Table 4-21. New Capabilities Function Support Features
New Capability Function
First (Power Management) Second (Hot Swap)
The PCI 9056 is designed to use either a 2K bit (FM93CS56L or compatible) or 4K bit (FM93CS66L or compatible) device.
Note: The PCI 9056 does not support serial EEPROMs that do not support sequential reads (such as the FM93C56L).
4096
100h
PCI Register Offset Location
40h, if the New Capabilities Function Support bit (PCISR[4]) is enabled (PCISR[4] is enabled, by default). 48h, which is pointed to from PMNEXT[7:0]. 4Ch, which is pointed to from HS_NEXT[7:0]. Because PVPD_NEXT[7:0] defaults to zero (0), this indicates that VPD is the last New Capability Function Support feature of the PCI 9056.
2048 VPD 1536 Empty 704 Extra Long 544 Long Load 0 # of bits
80h
60h (PROT_AREA register default) 2Eh
Third (VPD)
22h
0 # of words
Figure 4-5. Serial EEPROM Memory Map
4-12
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 4 C and J Modes Bus Operation
4.4.3
Internal Register Access
4.4.3.1
The PCI 9056 provides several internal registers, which allow for maximum flexibility in the bus-interface design and performance. These registers are accessible from the PCI and Local Buses (refer to Figure 4-6) and include the following: * PCI and Local Configuration registers * DMA registers * Mailbox registers * PCI-to-Local and Local-to-PCI Doorbell registers * Messaging Queue registers (I2O) * Power Management registers * Hot Swap registers * VPD registers
PCI Bus Master Local Bus Master
PCI Bus Access to Internal Registers
The PCI 9056 PCI Configuration registers can be accessed from the PCI Bus with a Configuration Type 0 cycle. All other PCI 9056 internal registers can be accessed by a Memory cycle, with the PCI Bus address that matches the base address specified in PCI Base Address 0 (PCIBAR0[31:8]) for the PCI 9056 Memory-Mapped Configuration register. These registers can also be accessed by an I/O cycle, with the PCI Bus address matching the base address specified in PCI Base Address 1 for the PCI 9056 I/O-Mapped Configuration register. All PCI Read or Write accesses to the PCI 9056 registers can be Byte, Word, or Lword accesses. All PCI Memory accesses to the PCI 9056 registers can be Burst or Non-Burst accesses. The PCI 9056 responds with a PCI disconnect for all Burst I/O accesses (PCIBAR1[31:8]) to the PCI 9056 Internal registers.
PCI 9056
PCI Configuration Registers Local Configuration Registers DMA Registers Mailbox Registers
Set Clear
PCI-to-Local Doorbell Register Local-to-PCI Doorbell Register Messaging Queue Registers Power Management Registers Hot Swap Registers VPD Registers
Set
Figure 4-6. PCI 9056 Internal Register Access
Section 4--C, J Bus Op
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved. Preliminary Information 4-13
Local Interrupt
PCI Interrupt
Clear
Section 4 C and J Modes Bus Operation
Serial EEPROM
4.4.3.2
Local Bus Access to Internal Registers
Address Mode Pin PCI 9056
CCS# (PCI 9056 Chip Select)
The Local processor can access all PCI 9056 internal registers through an external chip select. The PCI 9056 responds to a Local Bus access when the PCI 9056 Configuration Chip Select input (CCS#) is asserted low. Figure 4-7 illustrates how the Configuration Chip Select logic works.
Notes: CCS# must be decoded while ADS# is low. Accesses must be for a 32-bit non-pipelined bus.
PCI 9056 Internal Register Chip Select
Local Read or Write accesses to the PCI 9056 internal registers can be Byte, Word, or Lword accesses. The Local Bus width must be 32-bit to access internal registers. Eight and 16-bit data buses require external latches to form a 32-bit data path for Local Bus access to internal registers. Local accesses to the PCI 9056 internal registers can be Burst or Non-Burst accesses. The PCI 9056 READY# signal indicates that Data transfer is complete.
Figure 4-7. Address Decode Mode
4-14
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 4 C and J Modes Bus Operation
4.4.4
Serial EEPROM and Configuration Initialization Timing Diagrams
Note: In the timing diagrams that follow, the "_" symbol at the end of the signal names represents the "#" symbol.
0us
10us
20us
30us
EESK LRESET# EECS EEDI EEDO
1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 0 D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 BITS [31:16] CONFIGURATION REGISTER 0 HEX D0
INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----|
EESK EEDO
D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] OF CONFIGURATION REGISTER 8 HEX
BITS [15:0] CONFIGURATION REGISTER 0 HEX
CONTINUES
EESK (continues) EECS EEDO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EESK, EEDO, EECS STATUS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ
CONTINUES
Timing Diagram 4-1. Initialization from Serial EEPROM (2K or 4K Bit)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-15
Section 4--C, J Bus Op
Section 4 C and J Modes Bus Operation
Serial EEPROM
Timing Diagram 4-2. Local Interrupt Asserting PCI Interrupt
4-16
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 4 C and J Modes Bus Operation
Timing Diagram 4-3. PCI Configuration Write to PCI Configuration Register
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-17
Section 4--C, J Bus Op
Section 4 C and J Modes Bus Operation
Serial EEPROM
Timing Diagram 4-4. PCI Configuration Read to PCI Configuration Register
4-18
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 4 C and J Modes Bus Operation
Timing Diagram 4-5. Local Configuration Write to Configuration Register (C Mode)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-19
Section 4--C, J Bus Op
Section 4 C and J Modes Bus Operation
Serial EEPROM
Timing Diagram 4-6. Local Configuration Read from Configuration Register (C Mode)
4-20
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 4 C and J Modes Bus Operation
Timing Diagram 4-7. Local Configuration Write to Configuration Register (J Mode)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
4-21
Section 4--C, J Bus Op
Section 4 C and J Modes Bus Operation
Serial EEPROM
Timing Diagram 4-8. Local Configuration Read from Configuration Register (J Mode)
4-22
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
5
C AND J MODES FUNCTIONAL DESCRIPTION
set (CNTRL[30]=1), or the PCI 9056 initiates an external reset.
The functional operation described can be modified through the PCI 9056 programmable internal registers.
5.1.2.2 5.1 5.1.1 5.1.1.1 RESET OPERATION Adapter Mode PCI Bus Input RST#
Local LRESET#
When the Local LRESET# pin is asserted by an external source, the Local Bus interface circuitry, the configuration registers, and the PCI 9056 are reset. The PCI 9056 drives the Local LRESET# pin after it detects a reset for 62 clocks.
The PCI Bus RST# input pin is a PCI Host reset. It causes all PCI Bus outputs to float, resets the entire PCI 9056 and causes the Local LRESET# signal to be asserted.
5.1.2.3
Software Reset
When the Software Reset bit is set (CNTRL[30]=1), the following occurs: * PCI Master logic is held reset * PCI 9056 PCI Configuration registers held in reset * FIFOs are reset * PCI RST# pin is asserted Only the PCI Configuration registers are in reset. A software reset can only be cleared from another Host on the Local Bus, and the PCI 9056 remains in this reset condition until a Local Host clears the bit.
Note: The PCI Bus cannot clear this reset bit because the PCI Bus is in a reset state.
5.1.1.2
Software Reset
A Host on the PCI Bus can set the PCI Adapter Software Reset bit (CNTRL[30]=1) to reset the PCI 9056 and assert LRESET# output. All Local Configuration registers are reset; however, the PCI Configuration DMA and Shared Runtime registers and the Local Init Status bit (LMISC1[2]) are not reset. When the Software Reset bit (CNTRL[30]) is set, the PCI 9056 responds to PCI accesses, but not to Local Bus accesses. The PCI 9056 remains in this reset condition until the PCI Host clears the bit. The serial EEPROM is reloaded, if the Reload Configuration Registers bit is set (CNTRL[29]=1).
Note: The Local Bus cannot clear this reset bit because the Local Bus is in a reset state, even if the Local processor does not use LRESET# to reset.
5.1.2.4
Power Management Reset
Power Management reset is not applicable for Host mode.
5.1.1.3
Power Management Reset
5.2
PCI 9056 INITIALIZATION
When the power management reset is asserted (transition from D3 to any other state), the PCI 9056 resets as if a PCI reset was asserted. (Refer to Section 8, "PCI Power Management.")
5.1.2 5.1.2.1
Host Mode PCI Reset
The PCI 9056 Configuration registers can be programmed by an optional serial EEPROM and/or by a Local processor, as listed in Table 4-18, "Serial EEPROM Guidelines," on page 4-10. The serial EEPROM can be reloaded by setting the Reload Configuration Registers bit (CNTRL[29]). The PCI 9056 retries all PCI cycles until the Local Init Status bit is set to "done" (LMISC1[2]=1).
Note: The PCI Host processor can also access Internal Configuration registers after the Local Init Status bit is set.
The PCI Bus RST# output is driven when the Local LRESET# signal is asserted, the Software Reset bit is
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-1
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Response to FIFO Full or Empty
If a PCI Host is present, the Master Enable, Memory Space, and I/O Space bits (PCICR[2:0], respectively) are programmed by that Host after initialization completes (LMISC1[2]=1).
5.4.1
Direct Master Operation (Local Master-to-Direct Slave)
5.3
RESPONSE TO FIFO FULL OR EMPTY
The PCI 9056 supports a direct access to the PCI Bus by the Local processor or an intelligent controller. Master mode must be enabled in the PCI Command register. The following registers define Local-to-PCI accesses: * Direct Master Memory and I/O Range (DMRR) * Local Base Address for Direct Master to PCI Memory (DMLBAM) * Local Base Address for Direct Master to PCI I/O and Configuration (DMLBAI) * PCI Base Address (DMPBAM) * Direct Master Configuration (DMCFGA) * Direct Master PCI Dual Address Cycles (DMDAC) * Master Enable (PCICR) * PCI Command Code (CNTRL)
Table 5-1 lists the response of the PCI 9056 to full and empty FIFOs.
5.4
DIRECT DATA TRANSFER MODES
The PCI 9056 supports three direct transfer modes: * Direct Master--Local CPU accesses PCI memory or I/O * Direct Slave--PCI Master accesses Local memory or I/O * DMA--PCI 9056 DMA controller reads/writes PCI memory to/from Local memory
Table 5-1. Response to FIFO Full or Empty
Mode
Direct Master Write Direct Master Read Direct Slave Write
Direction
Local-to-PCI
FIFO
Full Empty Full Empty Full Empty Full Empty Full Empty Full Empty Normal
PCI Bus
De-assert REQ# (off PCI Bus) De-assert REQ# or throttle IRDY#1 Normal Disconnect or throttle TRDY#2 Normal Normal Throttle TRDY#2 Normal De-assert REQ# De-assert REQ# Normal Normal Normal
Local Bus
De-assert READY#
PCI-to-Local
De-assert READY# Normal De-assert LHOLD, assert BLAST#3 De-assert LHOLD, assert BLAST#3 Normal De-assert LHOLD, assert BLAST#3 Normal Normal De-assert LHOLD, assert BLAST#3
PCI-to-Local
Direct Slave Read
Local-to-PCI
Local-to-PCI DMA PCI-to-Local
1. Throttle
IRDY# depends on the Direct Master PCI Read Mode bit (DMPBAM[4]). 2. Throttle TRDY# depends on the Direct Slave PCI Write Mode bit (LBRD0[27]). 3. LHOLD de-assert depends upon the Local Bus Direct Slave Release Bus Mode bit (MARBR[21]).
5-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
PCI Bus Master
Local Processor
1
Initialize Local Direct Master Access Registers
Local Range for Direct Master-to-PCI Local Base Address for Direct Master-to-PCI Memory PCl Base Address (Remap) for Direct Master-to-PCI Local Base Address for Direct Master-to-PCI I/O Configuration
I/O or Configuration 0 = I/O 1 = Configuration
PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration PCI Command Register
3
PCI Bus Access
2 FIFOs
64-Lword Deep Write 32-Lword Deep Read Local Base Address for Direct Masterto-PCI Memory Space Local Bus Access
Local Memory PCI Address Space
PCI Base Address Memory Command
Range
Local Base Address for Direct Master-toPCI I/O Configuration
I/O Command
Range
Figure 5-1. Direct Master Access of the PCI Bus
5.4.1.1
Direct Master Memory and I/O Decode
The Range register and the Local Base Address specifies the Local Address bits to use for decoding a Local-to-PCI access (Direct Master). The range of memory or I/O space must be a power of 2 and the Range register value must be the 2's complement of the Range value. In addition, the Local Base Address must be a multiple of the range value.
Any Local Master Address starting from the Direct Master Local Base Address (Memory or I/O) to the range value is recognized as a Direct Master access by the PCI 9056. All Direct Master cycles are then decoded as PCI Memory, I/O, or Configuration Type 0 or Type 1. Moreover, a Direct Master memory or I/O cycle is remapped according to the Remap register value. The Remap Register value must be a multiple of the Direct Master Range value (not the Range register value). The PCI 9056 can only accept Memory cycles from the Local processor. The Local Base Address and/or the range determine whether PCI Memory or PCI I/O transactions occur.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-3
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
Direct Data Transfer Modes
5.4.1.2
Direct Master FIFOs
5.4.1.3
Direct Master Memory Access
For Direct Master Memory access to the PCI Bus, the PCI 9056 has a 64-Lword (256-byte) Write FIFO and a 32-Lword (128-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus and allows high-performance bursting on the PCI and Local Buses. In a Direct Master write, the Local processor (Master) writes data to the PCI Bus (Slave). In a Direct Master read, the Local processor (Master) reads data from the PCI Bus (Slave). The FIFOs that function during a Direct Master write and read are illustrated in Figure 5-2 and Figure 5-3.
The Local processor transfers data through a single or burst Read/Write Memory transaction to the PCI 9056 and PCI Bus. Transactions are initiated by the Local Master (LCPU) when the Generic Local Bus memory address matches the Memory space decoded for Direct Master operations. Upon a Generic Local Bus Read, the PCI 9056 becomes a PCI Bus Master, arbitrates for the PCI Bus, and reads data from the PCI Slave device directly into the Direct Master Read FIFO. When sufficient data is placed into the FIFO, it asserts READY# signal onto the Generic Local Bus to indicate that the requested data is on the Generic Local Bus. The Generic Local processor can read or write to PCI memory. The PCI 9056 converts the Local Read/Write access. The Local Address space starts from Direct Master Local Base Address up to the range. Remap (PCI Base Address) defines the PCI starting address. The PCI 9056 supports both single and Burst cycles performed by the Generic Local processor. A Generic Local Bus Processor single cycle causes a single cycle PCI transaction. A Generic Local Processor Burst cycle asserts a Burst cycle PCI transaction. The PCI 9056 supports infinite Burst transfers. Writes--Upon a Local Bus Write, the Generic Local Bus Master writes data to the Direct Master Write FIFO. When the first data is in the FIFO, the PCI 9056 becomes the PCI Bus Master, arbitrates for the PCI Bus, and writes data to the PCI Slave device. The PCI 9056 continues to accept writes and returns READY# until the Write FIFO is full. It then holds off READY# until space becomes available in the Write FIFO. A programmable Direct Master "almost full" status output is provided (DMPAF). A Generic Local Processor single cycle Write transaction results in PCI 9056 transfers of one Lword data onto a 32-bit PCI Bus. A Generic Local Processor Burst Cycle Write transaction of two Lwords results in PCI 9056 burst transfers of two Lwords to a 32-bit PCI Bus. Any type of Burst Cycles of three Lwords or more results in the PCI 9056 bursting data onto the PCI Bus.
Slave
Master
Slave
LA, ADS#, LBE#, LD/LAD, LW/R#, BLAST#
Master
REQ#
READY#
PCI Bus
GNT# FRAME#, C/BE# AD (addr) IRDY# DEVSEL#, TRDY# AD (data)
PCI 9056
Figure 5-2. Direct Master Write
Slave
Master
Slave
LA, ADS#, LW/R#
Master
REQ# GNT#
IRDY# DEVSEL#, TRDY#, AD (data)
PCI 9056
LD/LAD, READY# BLAST#
Figure 5-3. Direct Master Read
Note: Figures 5-2 and 5-3 represent a sequence of Bus cycles.
Local Bus
PCI Bus
FRAME#, C/BE#, AD (addr)
Local Bus
5-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
The PCI 9056 always starts Direct Master Burst Write transfers on the Lword-aligned PCI Data Addresses. This results in the PCI 9056 performing a dummy PCI cycle with PCI BE# "F" to a Qword-aligned part of the data, when a Qword-unaligned Direct Master Burst Write transfer is performed to a 32-bit PCI slave. Single cycle PCI writes result in a single 32-bit transfer. Reads--The PCI 9056 holds off READY# while gathering an Lword from the PCI Bus. Programmable prefetch modes are available if prefetch is enabled-- prefetch, 4, 8, 16, or continuous--until the Direct Master cycle ends. The Read cycle is terminated when Local BLAST# input is asserted. Unused Read data is flushed from the FIFO. The PCI 9056 does not prefetch Read PCI data for single cycle Direct Master reads (Local BLAST# input asserted during the first Data phase). In this case, for the 32-bit PCI Bus, the PCI 9056 reads a single PCI Lword unless Direct Master Read Ahead mode is enabled. (Refer to Section 5.4.1.7.) For single cycle Direct Master reads, the PCI 9056 passes corresponding PCI Bus byte enables from the Generic Local Bus byte enables (LBE#). For Burst Cycle reads, the PCI 9056 reads entire Lwords (all PCI Bus byte enables are asserted). If the Direct Master Prefetch Limit bit is enabled (DMPBAM[11]=1), the PCI 9056 terminates a read prefetch at 4-KB boundaries, and restarts it as a new PCI Read Prefetch cycle at the start of a new boundary. If the bit is disabled, the prefetch crosses the 4-KB boundaries.
5.4.1.5
Direct Master I/O
If the Configuration Enable bit is cleared (DMCFGA[31]=0), a single I/O access is made to the PCI Bus. The Local Address, Remapped Decode Address bits, and Local byte enables are encoded to provide the address and are output with an I/O Read or Write command during a PCI Address cycle. When the I/O Remap Select bit is set (DMPBAM[13]=1), the PCI Address bits [31:16] are forced to 0 for the 64-KB I/O address limit. For writes, data is loaded into the Write FIFO and READY# is returned to the Local Bus. For reads, the PCI 9056 holds off READY# while receiving an Lword from the PCI Bus.
5.4.1.6
Direct Master Delayed Write Mode
The PCI 9056 supports Direct Master Delayed Write mode transactions, where posted Write data accumulates in the Direct Master Write FIFO before the PCI 9056 requests the PCI Bus. Direct Master Delayed Write mode is programmable to delay REQ# assertion for the number of PCI clocks specified in DMPBAM[15:14]. This feature is useful for gaining higher throughput during Direct Master Write Burst transactions for conditions in which the Local clock frequency is slower than the PCI clock frequency. The PCI 9056 only utilizes the delay counter and accumulates data in the Direct Master Write FIFO for burst transactions on the Local Bus. Otherwise, an immediate single cycle PCI transfer occurs.
5.4.1.4
Direct Master I/O Configuration Access
5.4.1.7
Direct Master Read Ahead Mode
When a Local Direct Master I/O access to the PCI Bus occurs, the PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration Enable bit (DMCFGA[31]) determines whether an I/O or Configuration access is to be made to the PCI Bus. Local Burst accesses are broken into single PCI I/O (address/data) cycles. The PCI 9056 does not prefetch Read data for I/O and Configuration reads. For Direct Master I/O or Configuration cycles, the PCI 9056 asserts the same PCI Bus byte enables as set on the Local Bus.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
The PCI 9056 also supports Direct Master Read Ahead mode (DMPBAM[2]), where prefetched data can be read from the internal FIFO of the PCI 9056 instead of from the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4) for 32-bit Direct Slave transfers. A Local Bus single cycle Direct Master transaction, with Read Ahead mode (DMPBAM[2]) enabled results in the PCI 9056 processing continuous PCI Bus Read burst data with all bytes enabled (C/BE# = 0h).
Preliminary Information
5-5
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
Direct Data Transfer Modes
Local Bus
Local Read request
PCI 9056
Read Ahead mode is set in Internal Registers
PCI Bus
PCI 9056 prefetches data from PCI Bus device
5.4.1.8.1 Direct Master Configuration Cycle Example
To perform a Configuration Type 0 cycle to PCI device on AD[21]: 1. The PCI 9056 must be configured to allow Direct Master access to the PCI Bus. The PCI 9056 must also be set to respond to I/O space accesses. These bits must be set (PCICR[2:0]=111b).
In addition, Direct Master memory and I/O access must be enabled (DMPBAM[1:0]=11).
Read data
Local Bus Master Read returns with "Sequential Address"
Prefetched data is stored in the internal FIFO PCI 9056 returns prefetched data immediately from internal FIFO without reading again from the PCI Bus
PCI 9056 prefetches more data if FIFO space is available
Read data
PCI 9056 prefetches more data from Local memory
2. The Local memory map selects the Direct Master range. For this example, use a range of 1 MB:
1 MB = 220 = 00100000h The value to program into the Range register is the 2's complement of 00100000h (FFF00000h): DMRR = FFF00000h
Figure 5-4. Direct Master Read Ahead Mode
Note: Figure 5-4 represents a sequence of Bus cycles.
5.4.1.8
Direct Master Configuration (PCI Configuration Type 0 or Type 1 Cycles)
If the Configuration Enable bit is set (DMCFGA[31]=1) is set, and if a Direct Master access is made to the Local Bus address programmed in DMLBAM, a Configuration access is made to the PCI Bus. In addition to enabling configuration of this bit, the user must provide all register information. The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/Write cycle must be performed before accessing other registers or devices. If the PCI Configuration Address register selects a Type 0 command, register bits [10:0] are copied to address bits [10:0]. Bits [15:11] (device number) are translated into a single bit being set in the PCI Address bits [31:11]. The PCI Address bits [31:11] can be used as a device select. For a Type 1 command, bits [23:0] are copied from the register to PCI address bits [23:0]. The PCI Address bits [31:24] are set to 0. A Configuration Read or Write command code is output with the address during the PCI Address cycle. (Refer to the DMCFGA register.) For writes, Local data is loaded into the Write FIFO and READY# is returned. For reads, the PCI 9056 holds off READY# while gathering an Lword from the PCI Bus.
3. The Local memory map determines the Local Base Address for the Direct Master-to-PCI I/O Configuration register. For this example, use 40000000h:
DMLBAI = 40000000h
4. The PCI Address (Remap) for Direct Master-to-PCI Memory register must enable the Direct Master I/O access. The Direct Master I/O Access Enable bit must be set (DMPBAM[1]=1). 5. The user must know which PCI device and PCI Configuration register the PCI Configuration cycle is accessing. This example assumes the IDSEL signal of the Target PCI device is connected to AD[21] (logical device #10=0Ah). It also assumes access is to PCIBAR0 (the fourth register, counting from 0. Use Table 11-2 for reference). Set DMCFGA[31, 23:0] as follows:
Bit
1:0 7:2 10:8 15:11 23:16 31
Description
Configuration Type 0. Register Number. Fourth register. Must program a "4" into this value, beginning with bit 2. Function Number. Device Number n-11, where n is the value in AD[n]=21-11 = 10. Bus Number. Configuration Enable.
Value
00b 000100b 000b 01010b 00000000b 1
5-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
Figure 5-5. Dual Address Timing
After these registers are configured, a simple Local Master Memory cycle to the I/O Base Address is necessary to generate a PCI Configuration Read or Write cycle. An offset to the Base Address is not necessary because the register offset for the read or write is specified in the Configuration register. The PCI 9056 takes the Local Bus Master Memory cycle and checks for the Configuration Enable bit (DMCFGA[31]). If set, the PCI 9056 converts the current cycle to a PCI Configuration cycle, using the DMCFGA register and the Write/Read signal (LW/R#). The Register Number and Device Number bits (DMCFGA[7:2] and DMCFGA[15:11], respectively) must be modified and a new Configuration Read/Write cycle must be performed before accessing other registers or devices.
5.4.1.10 PCI Master/Target Abort
The PCI 9056 PCI Master/Target Abort logic enables a Local Bus Master to perform a Direct Master Bus device poll to determine if devices exist (typically when the Local Bus performs Configuration cycles to the PCI Bus). When a PCI Master device attempts to access but does not receive DEVSEL# within six PCI clocks, it results in a Master Abort. The Local Bus Master must clear the Received Master Abort bit or Target Abort bit (PCISR[13 or 11]=0, respectively) and continue by processing the next task. If a PCI Master/Target Abort, or Retry Timeout is encountered during a transfer, the PCI 9056 asserts LSERR# if enabled [INTCSR[1:0]=1, which can be used as a Non-Maskable Interrupt (NMI)]. If a Local Bus Master is waiting for READY#, it is asserted along with BTERM#. The Local Master's interrupt handler can take the appropriate application-specific action It can then clear the Target Abort bit (PCISR[11]) to de-assert the LSERR# interrupt and re-enable Direct Master transfers. If a Local Bus Master is attempting a Burst read from a nonresponding PCI device (Master/Target Abort), it receives READY# and BTERM# for the first cycle only. In addition, the PCI 9056 asserts LSERR# if the Enable Local Bus LSERR# bits are enabled (INTCSR[1:0], which can be used as an NMI). If the Local processor cannot terminate its Burst cycle, it may cause the Local processor to hang. The Local Bus must then be reset from the PCI Bus. If a Local Bus Master cannot terminate its cycle with BTERM# output, it should not perform Burst cycles when attempting to determine whether a PCI device exists.
5.4.1.9
Direct Master PCI Dual Address Cycle
The PCI 9056 supports PCI Dual Address Cycle (DAC) when it is a PCI Bus Master using the DMDAC register for Direct Master transactions. The DAC command is used to transfer a 32-bit address to devices that support 32-bit addressing when the address is not in the low 4-GB Address space. The PCI 9056 performs the address portion of a DAC in two PCI clock periods, where the first PCI address is a Lo-Addr with the command (C/BE[3:0]#) "D" and the second PCI address will be a Hi-Addr with the command (C/BE[3:0]#) "6" or "7", depending upon it being a PCI Read or a PCI Write cycle. Whenever the DMDAC register contains a value of 0x00000000, the PCI 9056 performs a Single Address Cycle (SAC) on the PCI Bus. (Refer to Figure 5-5.)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
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Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
Direct Data Transfer Modes
If a PCI Master/Target Abort is encountered during during a Direct Master transfer, the PCI 9056 stores the PCI Abort Address into the PCI Abort Address register bits (PABTADR[31:0]).
space. In addition, Local mapping registers allow address translation from the PCI Address Space to the Local Address Space. Three spaces are available: * Space 0 * Space 1 * Expansion ROM Expansion ROM is intended to support a bootable ROM device for the Host. Writes--Upon a PCI Bus Write, the PCI Bus Master writes data to the Direct Slave Write FIFO. When the first data is in the FIFO, the PCI 9056 becomes the Generic Local Bus Master, arbitrates for the Generic Local Bus, and writes data to a Generic Local Slave device. The PCI 9056 continues to accept writes and returns TRDY# until the Write FIFO is full. It then holds off TRDY# until space becomes available in the Write FIFO or asserts STOP#, and Retries the PCI Bus Master, dependent upon the register bit setting (LBRD0[27]). A 32-bit PCI Bus Master single cycle Write transaction results in a PCI 9056 transfer of one Lword of data onto a Generic Local Bus. Reads--The PCI 9056 holds off TRDY# while gathering an Lword from the Local Bus, unless the Delayed Read Mode bit is enabled (MARBR[24]=1). (Refer to Section 5.4.2.2.) Programmable Prefetch modes are available, if prefetch is enabled--prefetch, 0-16, or continuous--until the Direct Slave read ends. The Read cycles are terminated on the following clock after FRAME# is de-asserted or the PCI 9056 issues a Retry or disconnect. For the highest data transfer rate, the PCI 9056 supports posted writes and can be programmed to prefetch data during a PCI Burst read. The Prefetch size, when enabled, can be from one to 16 Lwords or until the PCI Bus stops requesting. When the PCI 9056 prefetches, if enabled, it drops the Generic Local Bus after reaching the prefetch counter limit. In Continuous Prefetch mode, the PCI 9056 prefetches as long as FIFO space is available and stops prefetching when the PCI Bus terminates the request. If Read prefetching is disabled, the PCI 9056 disconnects after one Read transfer.
5.4.1.11 Direct Master Memory Write and Invalidate
The PCI 9056 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for Direct Master transfers, as well as for DMA transfers. (Refer to Section 5.5.4.) The PCI 9056 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers.
Direct Master Memory Write and Invalidate transfers
are enabled when the Invalidate Enable and the Memory Write and Invalidate Enable bits are set (DMPBAM[9] and PCICR[4], respectively). In Memory Write and Invalidate mode, if the start address of the Direct Master transfer is on a cache line boundary, the PCI 9056 waits until the number of Lwords required for the specified cache line size are written from the Local Bus before starting a PCI Memory Write and Invalidate access. This ensures a complete cache line write can complete in one PCI Bus ownership. If the start address is not on a cache line boundary, the PCI 9056 starts a normal PCI Write access (PCI command code = 7h). The PCI 9056 does not terminate a normal PCI Write at an MWI cache boundary. The normal PCI Write transfer continues until the Data transfer is complete. If a Target disconnects before a cache line is completed, the PCI 9056 completes the remainder of that cache line, using normal writes.
5.4.2
Direct Slave Operation (PCI Master-to-Local Bus Access)
The PCI 9056 supports burst Memory-Mapped Transfer accesses and I/O-Mapped, PCI-to-Generic Local Bus single Transfer accesses through a 32-Lword (128-byte) Direct Slave Read FIFO and a 64-Lword (256-byte) Direct Slave Write FIFO. The PCI Base Address registers are provided to set up the location of the adapter in the PCI memory and the I/O
5-8
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
In addition to Prefetch mode, the PCI 9056 supports Read Ahead mode. (Refer to Section 5.4.2.3.) Only 32-bit PCI Bus single cycle Direct Slave Read transactions result in the PCI 9056 passing requested PCI bytes (C/BE#) to a Generic Local Bus Target device by way of LBE[3:0]# assertion back to a PCI Bus Master. This transaction results in the PCI 9056 reading one Lword or partial Lword data. For any other types of Read transactions (Burst transfers or Unaligned), the PCI 9056 reads Generic Local Bus data with all bytes asserted (LBE[3:0]# = 0h). Each Local space can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width. The PCI 9056 has an internal wait state generator and external wait state input, READY#. READY# can be disabled or enabled with the Internal Configuration registers. With or without wait state(s), the Local Bus, independent of the PCI Bus, can perform the following: * Burst as long as data is available (Continuous Burst mode) * Burst four Lwords at a time (recommended) * Perform continuous single cycles
PCI Bus single cycle aligned or unaligned 32-bit Direct Slave Delayed Read transactions always result in a 1-Lword single cycle transfer on the Local Bus, with corresponding Local byte enables LBE[3:0]# asserted to reflect the PCI byte enables (C/BE#), unless the PCI Read No Flush Mode bit is enabled (MARBR[28]=1). (Refer to Section 5.4.2.3.) This causes the PCI 9056 to Retry all PCI Bus Read requests that follow, until the original PCI byte enables (C/BE#) are matched.
PCI Bus
PCI 9056
Local Bus
PCI Read request
PCI 9056 instructs PCI Host to "Retry" Read cycle later PCI Bus is free to perform other cycles during this time PCI Host returns to fetch Read data again Read data is now ready for Host
Delayed Read mode is set in Internal Registers PCI 9056 requests Read data from Local Bus Local memory returns requested data to PCI 9056
Data is stored in 32-Lword Internal FIFO
PCI 9056 returns prefetched data immediately
5.4.2.1
Direct Slave Lock
Figure 5-6. Direct Slave Delayed Read
Note: Figure 5-6 represents a sequence of Bus cycles.
The PCI 9056 supports direct PCI-to-Local-Bus Exclusive accesses (locked atomic operations). A PCI-locked operation to the Local Bus results in the entire address Space 0, Space 1, and Expansion ROM space being locked until they are released by the PCI Bus Master. Locked operations are enabled or disabled with the Direct Slave LOCK# Enable bit (MARBR[22]).
In addition to delayed reads, the PCI 9056 supports the following Delayed Read mode functions: * No writes while a read is pending (PCI Retry for writes) * Write and flush pending read
5.4.2.2
Direct Slave Delayed Read Mode
5.4.2.3
Direct Slave Read Ahead Mode
The PCI 9056 can be programmed through the Delayed Read Mode bit (MARBR[24]=1) to perform delayed reads.
The PCI 9056 also supports Direct Slave Read Ahead mode (MARBR[28]), where prefetched data can be read from the internal FIFO of the PCI 9056 instead of from the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4) for 32-bit Direct Slave transfers.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-9
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
Direct Data Transfer Modes
PCI Bus
PCI Read request
PCI 9056
Read Ahead mode is set in Internal Registers
Local Bus
PCI 9056 prefetches data from Local Bus device
Read data PCI Bus Master Read returns with "Sequential Address" Prefetched data is stored in the internal FIFO PCI 9056 returns prefetched data immediately from internal FIFO without reading again from the Local Bus
Direct Slave Write transactions, the PCI 9056 empties the Write FIFO by dumping the data into the Local Bus and does not pass an error condition to the PCI Bus Initiator. During Direct Slave Read transactions, the PCI 9056 issues a Direct Slave Abort to the PCI Bus Initiator every time the Direct Slave Local Bus READY# Timeout is detected.
PCI 9056 prefetches more data if FIFO space is available
5.4.2.6
Direct Slave Transfer
Read data
PCI 9056 prefetches more data from Local memory
A PCI Bus Master addressing the Memory space decoded for the Local Bus initiates transactions. Upon a PCI Read/Write, the PCI 9056 becomes a Local Bus Master and arbitrates for the Local Bus. The PCI 9056 then reads data into the Direct Slave Read FIFO or writes data to the Local Bus. The Direct Slave or Direct Master preempts DMA; however, the Direct Slave does not preempt the Direct Master. (Refer to Section 5.4.3.1.) The PCI 9056 can be programmed to retain the PCI Bus by generating a wait state(s) and de-asserting TRDY#, if the Write FIFO becomes full. The PCI 9056 can also be programmed to retain the Local Bus and continue asserting LHOLD, if the Direct Slave Write FIFO becomes empty or the Direct Slave Read FIFO becomes full. In either case, the Local Bus is dropped when the Local Bus Latency Timer is enabled and expires (MARBR[7:0]). For Direct Slave writes, the PCI Bus writes data to the Local Bus. The Direct Slave is the "Command from the PCI Host," which has highest priority. For Direct Slave reads, the PCI Bus Master reads data from the Local Bus Slave. The PCI 9056 supports on-the-fly Endian conversion for Space 0, Space 1, and Expansion ROM space. The Local Bus can be Big/Little Endian by using the programmable internal register configuration.
Note: The PCI Bus is always Little Endian.
Figure 5-7. Direct Slave Read Ahead Mode
Note: Figure 5-7 represents a sequence of Bus cycles.
5.4.2.4
Direct Slave Delayed Write Mode
The PCI 9056 supports Direct Slave Delayed Write mode transactions, where posted Write data accumulates in the Direct Slave Write FIFO before the PCI 9056 requests a Write transaction (ADS# and/or ALE assertion) to be performed on the Local Bus. The Direct Slave Delayed Write mode is programmable to delay the ADS# and/or ALE assertion in the amount of Local clocks (LMISC2[4:2]). This feature is useful for gaining higher throughput during Direct Slave Write burst transactions for conditions in which the PCI clock frequency is slower than the Local clock frequency.
5.4.2.5
Direct Slave Local Bus READY# Timeout Mode
The PCI 9056 supports Direct Slave Local Bus READY# Timeout mode transactions, where the PCI 9056 asserts an internal READY# signal to recover from stalling the Local and PCI Buses. The Direct Slave Local Bus READY# Timeout mode transaction is programmable to select the amount of Local clocks before READY# times out (LMISC2[1:0]). If a Local Slave stalls with a READY# assertion during
5-10
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
Master
FRAME#, C/BE#, AD (addr) IRDY#, AD (data)
Slave
Master
Slave
A fourth register, the Bus Region Descriptor register(s) for PCI-to-Local Accesses (LBRD0 and/or LBRD1), defines the Local Bus characteristics for the Direct Slave regions. (Refer to Figure 5-10.) Each PCI-to-Local Address space is defined as part of reset initialization, as described in Section 5.4.2.7.1. These Local Bus characteristics can be modified at any time before actual data transactions.
PCI 9056
LHOLD LHOLDA LA, ADS#, LW/R# LD/LAD, BLAST# READY#
Local Bus
PCI Bus
DEVSEL#, TRDY#
5.4.2.7.1 Direct Slave Local Bus Initialization
Range--Specifies which PCI Address bits to use for decoding a PCI access to Local Bus space. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. Remap PCI-to-Local Addresses into a Local Address Space--Bits in this register remap (replace) the PCI Address bits used in decode as the Local Address bits. Local Bus Region Descriptor--Specifies the Local Bus characteristics.
Figure 5-8. Direct Slave Write
Master
FRAME#, C/BE#, AD (addr) IRDY#
Slave
Master
Slave
PCI 9056
TRDY#, AD (data)
LHOLD LHOLDA LA, ADS#, LW/R#, BLAST# READY#, LD/LAD
Local Bus
PCI Bus
DEVSEL#
5.4.2.7.2 Direct Slave PCI Initialization
After a PCI reset, the software determines how much address space is required by writing all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9056 returns zeroes (0) in the Don't Care Address bits, effectively specifying the address space required. The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 5-10.)
Figure 5-9. Direct Slave Read
Note: Figures 5-8 and 5-9 represent a sequence of Bus cycles.
5.4.2.7
Direct Slave PCI-to-Local Address Mapping
Note: In I2O mode (QSR[0]=1), Memory-Mapped Local Configuration registers and Space 1 share the PCIBAR0 Base Address. Refer to Section 7.1.10.
Three Local Address spaces--Space 0, Space 1, and Expansion ROM--are accessible from the PCI Bus. Each is defined by a set of three registers: * Local Address Range (LAS0RR, LAS1RR, and/or EROMRR) * Local Base Address (LAS0BA, LAS1BA, and/or EROMBA) * PCI Base Address (PCIBAR2, PCIBAR3, and/or PCIERBAR)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-11
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
Direct Data Transfer Modes
PCI Bus Master
Local Processor 1
Initialize Local Direct Access Registers
2
Initialize PCI Base Address Registers
Range for PCI-to-Local Address Space 0/1 Local Base Address (Remap) for PCI-to-Local Address Space 0/1 Bus Region Descriptors for PCI-to-Local Accesses
Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses
Local Bus Hardware Characteristics
PCI Base Address to Local Address Space 0/1 PCI Base Address to Local Expansion ROM
3
PCI Bus Access
4 FIFOs
64-Lword Deep Write 32-Lword Deep Read Local Bus Access
PCI Address Space
PCI Base Address Local Base Address
Local Memory
Range
Figure 5-10. Local Bus Direct Slave Access
5-12
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Modes
5.4.2.7.3 Direct Slave Byte Enables (C Mode)
During a Direct Slave transfer, each of three spaces (Space 0, Space 1, and Expansion ROM) can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#). LBE[3:0]# are encoded, based on the configured bus width, as follows: 32-Bit Bus--The four-byte enables indicate which of the four bytes are active during a Data cycle: * LBE3# Byte Enable 3--LD[31:24] * LBE2# Byte Enable 2--LD[23:16] * LBE1# Byte Enable 1--LD[15:8] * LBE0# Byte Enable 0--LD[7:0] 16-Bit Bus--LBE[3, 1:0]# are encoded to provide BHE#, LA1, and BLE#, respectively: * LBE3# Byte High Enable (BHE#)--LD[15:8] * LBE2# not used * LBE1# Address bit 1 (LA1) * LBE0# Byte Low Enable (BLE#)--LD[7:0] 8-Bit Bus--LBE[1:0]# are encoded to provide LA[1:0], respectively: * LBE3# not used * LBE2# not used * LBE1# Address bit 1 (LA1) * LBE0# Address bit 0 (LA0)
LBE[3:0]# are encoded, based on the configured bus width, as follows: 32-Bit Bus--The four-byte enables indicate which of the four bytes are active during a Data cycle: * LBE3# Byte Enable 3--LAD[31:24] * LBE2# Byte Enable 2--LAD[23:16] * LBE1# Byte Enable 1--LAD[15:8] * LBE0# Byte Enable 0--LAD[7:0] 16-Bit Bus--LBE[3, 1:0]# are encoded to provide BHE#, LAD1, and BLE#, respectively: * LBE3# Byte High Enable (BHE#)--LAD[15:8] * LBE2# not used * LBE1# Address bit 1 (LAD1) * LBE0# Byte Low Enable (BLE#)--LAD[7:0] 8-Bit Bus--LBE[1:0]# LAD[1:0], respectively: * LBE3# not used * LBE2# not used * LBE1# Address bit 1 (LAD1) * LBE0# Address bit 0 (LAD0) are encoded to provide
5.4.2.7.4.1
Direct Slave Byte Enables Example
A 1 MB Local Address Space, 12300000h through 123FFFFFh, is accessible from the PCI Bus at PCI addresses 78900000h through 789FFFFFh. a. Local initialization software sets the Range and Local Base Address registers as follows: * Range--FFF00000h (1 MB, decode the upper 12 PCI Address bits) Local Base Address (Remap)--123XXXXXh (Local Base Address for PCI-to-Local accesses) [Space Enable bit(s) must be set to be recognized by the PCI Host (LAS0BA[0]=1 and/or LAS1BA[0]=1)]
5.4.2.7.4 Direct Slave Byte Enables (J Mode)
During a Direct Slave transfer, each of three spaces (Space 0, Space 1, and Expansion ROM) can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#).
*
b. PCI Initialization software writes all ones (1) to the PCI Base Address, then reads it back again. * The PCI 9056 returns a value of FFF00000h. The PCI software then writes to the PCI Base Address register(s). PCI Base Address--789XXXXXh (PCI Base Address for Access to the Local Address Space registers, PCIBAR2 and PCIBAR3).
*
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-13
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
Direct Data Transfer Modes
For a PCI Direct access to the Local Bus, the PCI 9056 has a 64-Lword (256-byte) Write FIFO and a 32-Lword (128-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus. The PCI 9056 can be programmed to return a Retry response or to throttle TRDY# for any PCI Bus transaction attempting to write to the PCI 9056 Local Bus when the FIFO is full. For PCI Read transactions from the Local Bus, the PCI 9056 holds off TRDY# while gathering data from the Local Bus. For Read accesses mapped to PCI Memory space, the PCI 9056 prefetches up to 16 Lwords (has Continuous Prefetch mode) from the Local Bus. Unused Read data is flushed from the FIFO. For Read accesses mapped to PCI I/O space, the PCI 9056 does not prefetch Read data. Rather, it breaks each read of a Burst cycle into a single Address/Data cycle on the Local Bus. The Direct Slave Retry Delay Clocks bits (LBRD0[31:28]) can be used to program the period of time in which the PCI 9056 holds off TRDY#. The PCI 9056 issues a Retry to the PCI Bus Transaction Master when the programmed time period expires. This occurs when the PCI 9056 cannot gain control of the Local Bus and return TRDY# within the programmed time period.
de-asserted and the Local Bus Pause Timer is set to zero (0), it requests a DMA transfer from the Local Bus by re-asserting LHOLD. When it receives LHOLDA, it drives the bus and continues the DMA transfer.
5.4.3
Deadlock Conditions
Deadlock can occur when a PCI Bus Master must access the PCI 9056 Local Bus at the same time a Master on the PCI 9056 Local Bus must access the PCI Bus. There are two types of deadlock: * Partial Deadlock--A Local Bus Master is performing a Direct Bus Master access to a PCI Bus device other than the PCI Bus device concurrently trying to access the Local Bus * Full Deadlock--A Local Bus Master is performing a Direct Bus Master access to the same PCI Bus device concurrently trying to access the Local Bus This applies only to Direct Master and Direct Slave accesses through the PCI 9056. Deadlock does not occur in transfers through the PCI 9056 DMA channels or the PCI 9056 internal registers (such as mailboxes). For partial deadlock, the PCI access to the Local Bus times out [the Direct Slave Retry Delay Clock (LBRD0[31:28]), which is programmable through the Local Bus Region Descriptor register] and the PCI 9056 responds with a PCI Retry. PCI r2.2 requires that a PCI Master release its request for the PCI Bus (de-assert REQ#) for a minimum of two PCI clocks after receiving a Retry. This allows the PCI Bus arbiter to grant the PCI Bus to the PCI 9056 so that it can complete its Direct Master access and free up the Local Bus. Possible solutions are described in the following sections for cases in which the PCI Bus arbiter does not function as described (PCI Bus architecture dependent), waiting for a time out is undesirable, or a full deadlock condition exists. When a full deadlock occurs, the only solution is to back off the Local Bus Master.
5.4.2.8
Direct Slave Priority
Direct Slave accesses have a higher priority than DMA accesses, thereby preempting DMA transfers. During a DMA transfer, if the PCI 9056 detects a pending Direct Slave access, it releases the Local Bus within two Data transfers. The PCI 9056 resumes operation after the Direct Slave access completes. When the PCI 9056 DMA controller owns the Local Bus, its LHOLD output and LHOLDA input are asserted. When a Direct Slave access occurs, the PCI 9056 releases the Local Bus within two Lword transfers by de-asserting LHOLD and floating the Local Bus outputs. After the PCI 9056 acknowledges that LHOLDA is de-asserted, it requests the Local Bus for a Direct Slave transfer by asserting LHOLD. When the PCI 9056 receives LHOLDA, it drives the bus and performs the Direct Slave transfer. Upon completing a Direct Slave transfer, the PCI 9056 releases the Local Bus by de-asserting LHOLD and floating the Local Bus outputs. After the PCI 9056 samples LHOLDA is
5-14
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
5.4.3.1
Backoff
The PCI 9056 BREQo signal indicates whether a possible deadlock condition exists. The PCI 9056 starts the Backoff Timer (programmable through registers) when it detects the following conditions: * A PCI Bus Master is attempting to access memory or an I/O device on the Local Bus and is not gaining access (for example, LHOLDA is not received). * A Local Bus Master is performing a Direct Bus Master Read access to the PCI Bus. Or, a Local Bus Master is performing a Direct Bus Master Write access to the PCI Bus and the PCI 9056 Direct Master Write FIFO cannot accept another Write cycle. If the Local Bus Backoff Enable bit is enabled (EROMBA[4]=1), the Backoff Timer expires, and the PCI 9056 has not received LHOLDA, the PCI 9056 asserts BREQo. External bus logic can use this signal to perform backoff. The Backoff cycle is device/bus architecture dependent. External logic (an arbiter) can assert the necessary signals necessary to cause a Local Bus Master to release a Local Bus (backoff). After the Local Bus Master backs off, it can grant the bus to the PCI 9056 by asserting LHOLDA. Once BREQo is asserted, READY# for the current Data cycle is never asserted (the Local Bus Master must perform backoff). When the PCI 9056 detects LHOLDA, it proceeds with the PCI Master-to-Local-Bus access. When this access completes and the PCI 9056 releases the Local Bus, external logic can release the backoff and the Local Bus Master can resume the cycle interrupted by the Backoff cycle. The PCI 9056 Write FIFO retains all data it acknowledged (that is, the last data for which READY# was asserted). After the backoff condition ends, the Local Bus Master restarts the last cycle with ADS#. For writes, data following ADS# should be the data the PCI 9056 did not acknowledge prior to the Backoff cycle (for example, the last data for which READY# is not asserted). If a PCI Read cycle completes when the Local Bus is backed off, the Local Bus Master receives that data if the Local Master restarts the same last cycle (data is not read twice). A new read is performed, if the resumed Local Bus cycle is not the same as the Backed Off cycle.
5.4.3.1.1 Software/Hardware Solution for Systems without Backoff Capability
For adapters that do not support backoff, a possible deadlock solution is as follows. The PCI Host software can use PCI Host software, external Local Bus hardware, general purpose output USERo and general purpose input USERi to prevent deadlock. USERo can be asserted to request that the external arbiter not grant the bus to any Local Bus Master except the PCI 9056. Status output from the Local arbiter can be connected to the general purpose input USERi to indicate that no Local Bus Master owns the Local Bus, or the PCI Host to determine that no Local Bus Master that currently owns the Local Bus can read input. The PCI Host can then perform Direct Slave access. When the Host finishes, it de-asserts USERo.
5.4.3.1.2 Preempt Solution
For devices that support preempt, USERo can be used to preempt the current Bus Master device. When USERo is asserted, the current Local Bus Master device completes its current cycle and releases the Local Bus, de-asserting LHOLD.
5.4.3.2
Software Solutions to Deadlock
Both PCI Host and Local Bus software can use a combination of mailbox registers, doorbell registers, interrupts, direct Local-to-PCI accesses and direct PCI-to-Local accesses to avoid deadlock.
5.5
DMA OPERATION
DMA
The PCI 9056 supports two independent channels capable of transferring data from the: * Local-to-PCI Bus * PCI-to-Local Bus
Each channel consists of a DMA controller and a dedicated bidirectional FIFO. Both channels support Block transfers, Scatter/Gather transfers, with or without End of Transfer (EOT#). Master mode must be enabled with the Master Enable bit (PCICR[2]) before the PCI 9056 can become a PCI Bus Master. In addition, both DMA channels can be programmed to: * Operate in 8-, 16-, or 32-bit Local Bus width * Use zero to 15 internal wait states (Local Bus)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
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Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
DMA Operation
* Enable/disable internal wait states (Local Bus) * Enable/disable Local Bus Burst capability * Limit Local Bus bursts to four (BTERM# enable/ disable) * Hold Local address constant (Local Slave is FIFO) or increment * Perform PCI Memory Write and Invalidate (command code = Fh) or normal PCI Memory Write (command code = 7h) * Pause Local transfer with/without BLAST# (DMA Fast/Slow termination) * Assert PCI interrupt (INTA#) or Local interrupt (LINTo#) when DMA transfer is complete or Terminal Count is reached during Scatter/Gather DMA mode transfers * Operate in DMA Clear Count mode (only if the descriptor is in Local memory) The PCI 9056 also supports PCI Dual Address with the upper 32-bit register(s) (DMADAC0 and/or DMADAC1). The Local Bus Latency Timer determines the number of Local clocks the PCI 9056 can burst data before relinquishing the Local Bus. The Local Bus Pause Timer sets how soon the DMA channel can request the Local Bus.
5.5.2
Block DMA Mode
The Host processor or the Local processor sets the Local and PCI starting addresses, transfer byte count, and transfer direction. The Host or Local processor then sets the DMA Start bit (DMACSR0[1] and/or DMACSR1[1]) to initiate a transfer. The PCI 9056 requests the PCI and Local Buses and transfers data. Once the transfer completes, the PCI 9056 sets the Channel Done bit(s) (DMACSR0[4]=1 and/or DMACSR1[4]=1) and, if enabled, asserts an interrupt(s) (DMAMODE0[10] and/or DMAMODE1[10]) to the Local processor or the PCI Host (programmable). The Channel Done bit(s) can be polled, instead of interrupt generation, to indicate the DMA transfer status. DMA registers are accessible from the PCI and Local Buses. (Refer to Figure 5-11.) During DMA transfers, the PCI 9056 is a Master on both the PCI and Local Buses. For simultaneous access, Direct Slave or Direct Master has a higher priority than DMA. The PCI 9056 releases the PCI Bus, if one of the following conditions occur. (Refer to Figure 5-12 and Figure 5-13): * FIFO is full (PCI-to-Local Bus)
5.5.1
DMA PCI Dual Address Cycle
* FIFO is empty (Local-to-PCI Bus) * Terminal count is reached * PCI Bus Latency Timer expires (PCILTR[7:0])--normally programmed by the Host PCI BIOS--and PCI GNT# de-asserts * PCI Host asserts STOP# The PCI 9056 releases the Local Bus, if one of the following conditions occurs: * FIFO is empty (PCI-to-Local Bus) * FIFO is full (Local-to-PCI Bus) * Terminal count is reached * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * Special cycle BREQi# is asserted * Direct Slave request is pending
The PCI 9056 supports PCI Dual Address Cycles (DAC) when it is a PCI Bus Master, using the DMADAC0 and/or DMADAC1 register(s) for Block DMA transactions. Scatter/Gather DMA can utilize the DAC function by way of the DMADAC0 and/or DMADAC1 register(s) or DMAMODE0[18] and/or DMAMODE1[18]. The DAC command is used to transfer a 32-bit address to devices that support 32-bit addressing when the address is above the 4-GB Address space. The PCI 9056 performs a DAC within two PCI clock periods, where the first PCI address is a Lo-Addr, with the command (C/BE[3:0]#) "D", and the second PCI address is a Hi-Addr, with the command (C/BE[3:0]#) "6" or "7", depending upon whether it is a PCI Read or PCI Write cycle.
5-16
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
Set DMA Mode to Block
Mode Register
PCI Host Memory
Memory Block to Transfer
Set up Transfer Parameters
Single Address--PCI Address Register Dual Address--PCI Addresses Register Local Address Register Transfer Size (byte count) Register Descriptor Pointer Register (set direction only)
Local Memory
Memory Block to Transfer
Command/Status Register
Set Enable and Start bits in DMA Command/Status Register(s) (DMACSR0 and/or DMACSR1) to Initiate DMA Transfer
Figure 5-11. Block DMA Mode Initialization (Single Address or Dual Address PCI)
Slave
DMA Start
Master
(DMALADR1 & DMASIZ1)
Master
DMA Start
Slave
Slave
DMA Start
Master
(DMALADR1 & DMASIZ1)
Master
DMA Start
Slave
(DMALADR1 & DMASIZ1)
(DMALADR1 & DMASIZ1)
REQ# GNT# FRAME#, C/BE#, AD (addr)
LHOLD LHOLDA LA, ADS#, LW/R# BLAST#
Local Bus
PCI Bus
IRDY# DEVSEL#, TRDY#, AD (data)
PCI 9056
REQ# GNT# IRDY# DEVSEL#, TRDY# AD (addr & data)
LHOLD LHOLDA LA, LD/LAD, ADS#, LW/R#, BLAST# READY#
PCI 9056
LD/LAD, READY#
Figure 5-12. DMA, PCI-to-Local Bus
Figure 5-13. DMA, Local-to-PCI Bus
Note: Figures 5-12 and 5-13 represent a sequence of Bus cycles.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Local Bus
PCI Bus
5-17
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
DMA Operation
Table 5-2. DMA Local Burst Mode
Burst Enable Bit
0 1
5.5.2.1
Result
Single cycle Burst up to four Data cycles
Block DMA PCI Dual Address Cycle
BTERM# Enable Bit
X 0
1 Note: "X" is "Don't Care."
1
Burst forever (terminate when BTERM# is asserted or transfer is completed)
The PCI 9056 supports the DAC feature in Block DMA mode. Whenever the DMADAC0 and/or DMADAC1 register(s) contain a value of 0x00000000, the PCI 9056 performs a Single Address Cycle (SAC) on the PCI Bus. Any other value causes a Dual Address to appear on the PCI Bus. (Refer to Figure 5-14.)
Figure 5-14. Dual Address Timing
5.5.3
Scatter/Gather DMA Mode
In Scatter/Gather DMA mode, the Host processor or Local processor sets up descriptor blocks in Local or Host memory composed of PCI and Local addresses, transfer count, transfer direction, and address of next descriptor block. (Refer to Figure 5-15 and Figure 5-16.) The Host or Local processor then: * Enables the Scatter/Gather mode bit(s) (DMAMODE0[9]=1 and/or DMAMODE1[9]=1) * Sets up the address of initial descriptor block in the PCI 9056 Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) * Initiates the transfer by setting a control bit(s) (DMACSR0[1:0] and/or DMACSR1[1:0]) The PCI 9056 supports zero wait state Descriptor Block bursts from the Local and PCI Bus when the Local Burst Enable bit(s) is enabled (DMAMODE0[8]=1 and/or DMAMODE1[8]=1). The PCI 9056 loads the first descriptor block and initiates the Data transfer. The PCI 9056 continues to load descriptor blocks and transfer data until it detects the End of Chain bit(s) is set (DMADPR0[1]=1 and/or
DMADPR1[1]=1) (these bits are part of each descriptor). When the End of Chain bit(s) is detected, the PCI 9056 completes the current descriptor block and sets the DMA Done bit(s) (DMACSR0[4] and/or DMACSR1[4]). If the End of Chain bit(s) is detected, the PCI 9056 asserts a PCI interrupt (INTA#) and/or Local interrupt (LINTo#). The PCI 9056 can also be programmed to assert PCI or Local interrupts after each descriptor is loaded, then finish transferring. If Scatter/Gather descriptors are in Local memory, the DMA controller can be programmed to clear the transfer size at completion of each DMA, using the DMA Clear Count Mode bit(s) (DMAMODE0[16] and/ or DMAMODE1[16]).
Notes: In Scatter/Gather DMA mode, the descriptor includes the PCI and Local Address Space, transfer size, and next descriptor pointer. It also includes a DAC value, if the DAC Chain Load bit(s) is enabled (DMAMODE0[18]=1 and/or DMAMODE1[18]=1). Otherwise, the register (DMADAC0 and/or DMADAC1) values are used. The Descriptor Pointer register(s) (DMADPR0 and/or DMADPR1) contains end of chain (bit 1), direction of transfer (bit 3), next descriptor address (bits [31:4]), interrupt after terminal count (bit 2), and next descriptor location (bit 0) bits. The Local Bus width must be the same as Local Memory Bus width.
5-18
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
A DMA descriptor can be on the Local memory or the PCI memory, or both (for example, one descriptor on Local memory, another descriptor on PCI memory and vice-versa).
5.5.3.1
Scatter/Gather DMA PCI Dual Address Cycle
PCI Bus
Local Bus
Set up Scatter/Gather DMA for PCI-to-Local PCI 9056 retrieves Scatter/Gather data from Local memory PCI 9056 writes data to Local Bus PCI 9056 writes data to Local Bus PCI 9056 retrieves Scatter/Gather data from Local memory PCI 9056 writes data to Local Bus PCI 9056 writes data to Local Bus
PCI 9056 initiates read from PCI Bus PCI 9056 initiates read from PCI Bus
PCI 9056
The PCI 9056 supports the PCI DAC feature in Scatter/Gather DMA mode for Data transfers only. The descriptor blocks should reside below the 4-GB Address space. The PCI 9056 offers three different options of how PCI DAC Scatter/Gather DMA is utilized. Assuming the descriptor blocks are located on the PCI Bus: * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 0. The PCI 9056 performs a Single Address Cycle (SAC) four-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. (Refer to Figure 5-17.) * DMADAC0 and/or DMADAC1 contain(s) an 0x00000000 value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9056 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with PCI DAC on the PCI Bus. (Refer to Figure 5-18.) * DMADAC0 and/or DMADAC1 contain(s) a non-zero value. DMAMODE0[18] and/or DMAMODE1[18] is set to 1. The PCI 9056 performs a SAC five-Lword descriptor block load from PCI memory and DMA transfer with DAC on the PCI Bus. The fifth descriptor overwrites the value of the DMADAC0 and/or DMADAC1 register(s). (Refer to Figure 5-18.)
PCI 9056 initiates read from PCI Bus PCI 9056 initiates read from PCI Bus
Read and Write cycles continue...
Figure 5-15. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus)
PCI Bus
Set up Scatter/Gather DMA for Local-to-PCI PCI 9056 retrieves Scatter/Gather data from PCI memory PCI 9056 writes data to PCI Bus PCI 9056 writes data to PCI Bus PCI 9056 retrieves Scatter/Gather data from PCI memory PCI 9056 writes data to PCI Bus PCI 9056 writes data to PCI Bus
Local Bus
PCI 9056 initiates read from Local Bus
PCI 9056
PCI 9056 initiates read from Local Bus
5.5.3.2
PCI 9056 initiates read from Local Bus PCI 9056 initiates read from Local Bus
DMA Clear Count Mode
Read and Write cycles continue...
Figure 5-16. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus)
Note: Figures 5-15 and 5-16 represent a sequence of Bus cycles.
The PCI 9056 supports DMA Clear Count mode (Write-Back feature, DMAMODE0[16] and/or DMAMODE1[16]). This feature allows users to control the Data transfer blocks during Scatter/Gather DMA operations. The PCI 9056 clears the Transfer Size descriptor to zero (0) by writing to a descriptor memory location at the end of each transfer chain. This feature is available for DMA descriptors located on the Local and PCI Buses.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-19
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
DMA Operation
5.5.3.3
DMA Descriptor Ring Management (Valid Mode)
In Scatter/Gather DMA mode, when the Valid Mode Enable bit(s) is set to 0 (DMAMODE0[20]=0 and/or DMAMODE1[20]=0), the Valid bit (bit 31 of transfer count) is ignored. When the Valid Mode Enable bit(s) is set to 1 (DMAMODE0[20]=1 and/or DMAMODE1 [20]=1), the DMA descriptor proceeds only when the Valid bit is set. If the Valid bit is set, the transfer count is 0, and the descriptor is not the last descriptor, then the DMA controller moves on to the next descriptor in the chain.
When the Valid Stop Control bit(s) is set to 0 (DMAMODE0[21]=0 and/or DMAMODE1[21]=0), the DMA Scatter/Gather controller continuously polls the descriptor with the Valid bit set to 0 (invalid descriptor) until the Valid bit is read to be a 1. When the Valid Stop Control bit(s) is set to 1 (DMAMODE0[21]=1 and/ or DMAMODE1[21]=1), the DMA Scatter/Gather controller pauses if a Valid bit with a value of 0 is detected. In this case, the PCI 9056 must restart the DMA controller by setting bit 1 of the DMA Control/Status register(s) (DMACSR0[1] and/or DMACSR1[1]). The DMA Clear Count mode bit(s) (DMAMODE0[16] and/or DMAMODE1[16]) must be enabled for the Ring Management Valid bit to be cleared at the completion of each descriptor.
5-20
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
1
Set DMA Mode to Scatter/Gather
3
Local or Host Memory PCI Memory
Mode Register
First PCI Address First Local Address First Transfer Size (byte count) Next Descriptor Pointer First Memory Block to Transfer
2
Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s)
PCI Address Local Address Transfer Size (byte count) Next Descriptor Pointer Command/Status Register 4 Set Enable and Start Bits in DMA Command/Status Register(s) (DMACSR0 and/or DMACSR1) to Initiate DMA Transfer End of Chain Specification Bit Local Memory Next Memory Block to Transfer
First Memory Block to Transfer
Next Memory Block to Transfer
Figure 5-17. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address (DMADAC0 and/or DMADAC1) Register Dependent]
1
Set DMA Mode to Scatter/Gather
3
Local or Host Memory PCI Memory
Mode Register
PCI Address Low First Local Address First Transfer Size (byte count) Next Descriptor Pointer PCI Address High First Memory Block to Transfer
2
Set up First Descriptor Pointer Register (Required only for the first Descriptor Pointer) Memory Descriptor Block(s)
PCI Address Low Local Address Transfer Size (byte count) Next Descriptor Pointer
Next Memory Block to Transfer
Command/Status Register 4 Set Enable and Start Bits in DMA Command/Status Register(s) (DMACSR0 and/or DMACSR1) to Initiate DMA Transfer
PCI Address High
Local Memory
End of Chain Specification Bit
First Memory Block to Transfer
Next Memory Block to Transfer
Figure 5-18. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18] and/or DMAMODE1[18]) Descriptor Dependent] (PCI Address High Added)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-21
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
DMA Operation
5.5.4
DMA Memory Write and Invalidate
The PCI 9056 can be programmed to perform Memory Write and Invalidate cycles to the PCI Bus for DMA transfers, as well as Direct Master transfers. (Refer to Section 5.4.1.11.) The PCI 9056 supports Memory Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers. DMA Memory Write and Invalidate transfers are enabled when the DMA controller Memory Write and Invalidate Enable bit(s) (DMAMODE0[13] and/or DMAMODE1[13]) and the Memory Write and Invalidate Enable bit (PCICR[4]) are set. In Memory Write and Invalidate mode, the PCI 9056 waits until the number of Lwords required for specified cache line size are read from the Local Bus before starting the PCI access. This ensures a complete cache line write can complete in one PCI Bus ownership. If a Target disconnects before a cache line completes, the PCI 9056 completes the remainder of that cache line, using normal writes before resuming Memory Write and Invalidate transfers. If a Memory Write and Invalidate cycle is in progress, the PCI 9056 continues to burst if another cache line is read from the Local Bus before the cycle completes. Otherwise, the PCI 9056 terminates the burst and waits for the next cache line to be read from the Local Bus. If the final transfer is not a complete cache line, the PCI 9056 completes the DMA transfer, using normal writes. EOT# signal assertion, in any DMA transfer type, or DREQ0# and/or DREQ1# signal de-assertion in Demand Mode before the cache line is read from the Local Bus, results in the PCI 9056 performing a normal PCI Memory Write to data read into a DMA FIFO.
Note: One to two Data transfers occur after the Abort bit is set. Aborting when no DMA cycles are in progress causes the next DMA to abort.
5.5.5
DMA Priority
The DMA Channel Priority bits (MARBR[20:19]) can be used to specify the following priorities: * Rotating (MARBR[20:19]=00) * DMA Channel 0 (MARBR[20:19]=01) * DMA Channel 1 (MARBR[20:19]=10)
5.5.6
DMA Channel 0 and Channel 1 Interrupts
A DMA channel can assert a PCI Bus or Local Bus interrupt when done (transfer complete) or after a transfer is complete for the current descriptor in Scatter/ Gather DMA mode. The DMA Channel Interrupt Select bit(s) determine whether to assert a PCI (DMAMODE0[17]=1 and/or DMAMODE1[17]=1) or Local (DMAMODE0[17]=0 and/or DMAMODE1[17]=0) interrupt. The PCI or Local processor can read the DMA Channel 0 Interrupt Active bits to determine whether a DMA Channel 0 (INTCSR[21]) or DMA Channel 1 (INTCSR[22]) interrupt is pending. The Channel Done bit(s) (DMACSR0[4] and/or DMACSR1[4]) can be used to determine whether an interrupt is: * DMA Done interrupt * Transfer complete for current descriptor interrupt The Done Interrupt Enable bit(s) (DMAMODE0[10] and/or DMAMODE1[10]) enable a Done interrupt. In Scatter/Gather DMA mode, a bit in the Next Descriptor Pointer register of the channel (loaded from Local memory) specifies whether to assert an interrupt at the end of the transfer for the current descriptor. A DMA Channel interrupt is cleared by the Channel Clear Interrupt bit(s) (DMACSR0[3]=1 and/or DMACSR1[3]=1).
5.5.4.1
DMA Abort
DMA transfers can be aborted, in addition to the EOT# signal, as follows: 1. Clear the DMA Channel Enable bit(s) (DMACSR0[0]=0 and/or DMACSR1[0]=0). 2. Abort DMA by setting the Channel Abort bit(s) (DMACSR0[2]=1 and/or DMACSR1[2]=1). 3. Wait until the Channel Done bit(s) is set (DMACSR0[4]=1 and/or DMACSR1[4]=1).
5.5.7
DMA Data Transfers
The PCI 9056 DMA controller can be programmed to transfer data from the Local-to-PCI Bus or from the PCI-to-Local Bus.
5-22
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
5.5.7.1
Local-to-PCI Bus DMA Transfer
PCI Interrupt Generation (Programmable)
Local Interrupt Generation (Programmable) Unload FIFO with PCI Bus Write Cycles
* Done
FIFO
PCI Bus Arbitration Local Bus Arbitration
Load FIFO with Local Bus Read Cycles
* Done
PCI Bus Arbitration:
Local Bus Arbitration:
* Releases control of PCI Bus
whenever FIFO becomes empty, PCI Bus Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending.
*
Releases control of Local Bus whenever FIFO becomes full, terminal count is reached, Local Bus Latency Timer is enabled and expires, BREQi is asserted, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of empty entries in FIFO becomes available. If Local Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires.
*
GNT# REQ# LHOLDA LHOLD
*
Rearbitrates for control of PCI Bus when preprogrammed number of entries in FIFO becomes available, or after two PCI clocks if disconnect is received.
Figure 5-19. Local-to-PCI Bus DMA Data Transfer Operation
5.5.7.2
PCI-to-Local Bus DMA Transfer
PCI Interrupt Generation (Programmable) Local Interrupt Generation (Programmable)
*
Done Load FIFO with PCI Bus Read Cycles
*
FIFO
PCI Bus Arbitration Local Bus Arbitration
Unload FIFO with Local Bus Write Cycles
Done
PCI Bus Arbitration:
Local Bus Arbitration:
*
Releases control of PCI Bus whenever FIFO becomes full, terminal count is reached, PCI Latency Timer expires and PCI GNT# de-asserts, PCI disconnect is received, or Direct Local-to-PCI Bus request is pending. Rearbitrates for control of PCI Bus when preprogrammed number of empty entries in FIFO becomes available, or after two PCI clocks if disconnect is received. GNT# REQ# LHOLDA LHOLD
*
Releases control of Local Bus whenever FIFO becomes empty, Local Bus Latency Timer is enabled and expires, BREQi is asserted, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of entries becomes available in FIFO or PCI terminal count is reached. If Local Bus Latency Timer is enabled and expires, waits until Local Bus Pause Timer expires.
*
*
Figure 5-20. PCI-to-Local Bus DMA Data Transfer Operation
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-23
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
DMA Operation
5.5.7.3
DMA Unaligned Transfers
For unaligned Local-to-PCI transfers, the PCI 9056 reads a partial Lword from the Local Bus. It continues to read Lwords from the Local Bus. Lwords are assembled, aligned to the PCI Bus address, and loaded into the FIFO. For PCI-to-Local transfers, Lwords are read from the PCI Bus and loaded into the FIFO. On the Local Bus, Lwords are assembled from the FIFO, aligned to the Local Bus address and written to the Local Bus. On both the PCI and Local Buses, the byte enables for writes determine LA[1:0] for the start of a transfer. For the last transfer, byte enables specify the bytes to be written. All reads are Lwords.
These same conditions for DMA PCI-to-Local cause the PCI 9056 to pause the DMA transfer on the Local Bus at the Lword boundary with BLAST# asserted at the last Data transfer. EOT# assertion (along with DREQ0# and/or DREQ1# de-assertion) causes the PCI 9056 to terminate the ongoing Data transfer and flush the DMA FIFO with BLAST# asserted at the last Data transfer. If BLAST# output is required for the last Lword of the DMA transfer (bit [15]=0), the DMA controller transfers one or two Lwords. If DREQ0# and/or DREQ1# is de-asserted during the Address phase of the first transfer in the PCI 9056 Local Bus ownership (ADS#, LHOLDA asserted), the DMA controller completes current Lword. If DREQ0# and/or DREQ1# is de-asserted during any phase other than the Address phase of the first transfer in the PCI 9056 Local Bus ownership, the DMA controller completes the current Lword, and one additional Lword (this allows BLAST# output to be asserted during the final Lword). If the DMA FIFO is full or empty after the Data phase in which DREQ0# and/or DREQ1# is de-asserted, the second Lword is not transferred. DREQ0# and/or DREQ1# controls only the number of Lword transfers. For an 8-bit bus, the PCI 9056 releases the bus after transferring the last byte for the Lword. For a 16-bit bus, the PCI 9056 releases the bus after transferring the last word for the Lword. (Refer to the timing diagrams in Section 5.6.) When the PCI 9056 is in Demand Mode DMA Local-to-PCI Fast Terminate mode (DMAMODE0[15] and/or DMAMODE1[15]) unaligned DMA transfers, it monitors PCI address increments to guarantee a Qword PCI data, 32-bit data completion when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer, Demand Mode DMA pause. Due to the nature of unaligned transfers, the PCI 9056 retains partial Lword data, three or fewer bytes remain in the DMA FIFO and are not transferred when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer. When DREQ0# and/or DREQ1# resumes, the data is transferred to the PCI Bus. If DREQ0# and/or DREQ1# assertion is never resumed for ongoing transfers, the EOT# signal assertion (along with DREQ0# and/or DREQ1# de-assertion) should be used to ensure the partial data successfully transfers to the PCI Bus.
5.5.8
Demand Mode DMA, Channel 0 and Channel 1
The Fast/Slow Terminate Mode Select bit(s) (DMAMODE0[15] and/or DMAMODE1[15]) determines the number of Lwords to transfer after the DMA controller DREQ0# and/or DREQ1# input is de-asserted. If BLAST# output is not required for the last Lword of a DMA transfer (bit [15]=1), the DMA controller releases the data bus after it receives an external READY# or the internal wait state counter decrements to 0 for the current Lword. If the DMA controller is currently bursting data, which is not the last Data phase for the Burst, BLAST# is not asserted. When the PCI 9056 is in Demand Mode DMA Local-to-PCI Slow Terminate mode (DMAMODE0[15] and/or DMAMODE1[15]), it monitors unaligned DMA transfers PCI address increments to guarantee a Qword PCI data, 32-bit data completion when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer, Demand Mode DMA pause. Due to the nature of unaligned transfers, the PCI 9056 retains partial Lword data, three or fewer bytes remain in the DMA FIFO and are not transferred when DREQ0# and/or DREQ1# is de-asserted in the middle of the Data-Pocket transfer. When DREQ0# and/or DREQ1# resumes, the data is transferred to the PCI Bus. If DREQ0# and/or DREQ1# assertion is never resumed for ongoing transfers, the EOT# signal assertion (along with DREQ0# and/or DREQ1# de-assertion) should be used to ensure the partial data successfully transfers to the PCI Bus.
5-24
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Operation
These same conditions for DMA PCI-to-Local cause the PCI 9056 to immediately pause the DMA transfer on the Local Bus at Lword boundary without BLAST# being asserted. EOT# assertion (along with DREQ0# and/or DREQ1# de-assertion) causes the PCI 9056 to immediately terminate the ongoing Data transfer and flush the DMA FIFO without BLAST# being asserted.
5.5.10 DMA Arbitration
The PCI 9056 DMA controller releases control of the Local Bus (de-asserts LHOLD) when one of the following conditions occur: * Local Bus Latency Timer is enabled and expires (MARBR[7:0]) * BREQi is asserted (BREQi can be enabled or disabled, or gated with a Local Bus Latency Timer before the PCI 9056 releases the Local Bus) * Direct Slave access is pending * EOT# input is received (if enabled) The DMA controller releases control of the PCI Bus when one of the following conditions occurs: * FIFOs are full or empty * PCI Bus Latency Timer expires (PCILTR[7:0])--and loses the PCI GNT# signal * Target disconnect response is received The DMA controller de-asserts PCI REQ# for a minimum of two PCI clocks.
5.5.9
End of Transfer (EOT#) Input
The DMA EOT# Enable bit(s) (DMAMODE0[14] and/or DMAMODE1[14]) determines the number of Lwords to transfer after a DMA controller asserts EOT# input. EOT# input should be asserted only when the PCI 9056 owns a bus. If BLAST# output is not required for the last Lword of the DMA transfer (DMAMODE0[15]=1 and/or DMAMODE1[15]=1), the DMA controller releases the data bus and terminates DMA after it receives an external READY#. Or, the internal wait state counter decrements to 0 for the current Lword. If the DMA controller is currently bursting data that is not the last Data phase for the burst, BLAST# output is not asserted. If BLAST# output is required for last Lword of the DMA transfer (DMAMODE0[15]=0 and/or DMAMODE1 [15]=0), the DMA controller transfers one or two Lwords, depending on the Local Bus width. If EOT# is asserted, the DMA controller completes the current Lword and one additional Lword (this allows BLAST# output to be asserted during the final Lword). If the DMA FIFO is full or empty after the Data phase in which EOT# is asserted, the second Lword is not transferred. The DMA controller terminates a transfer on an Lword boundary after EOT# is asserted. For an 8-bit bus, the PCI 9056 terminates after transferring the last byte for the Lword. For a 16-bit bus, the PCI 9056 terminates after transferring the last word for the Lword. During the descriptor loading on the Local Bus, assertion of EOT# causes a complete descriptor load and no subsequent Data transfer; however, this is not recommended. This has no effect when the descriptor is loaded from the PCI Bus.
5.5.11 Local Bus Latency and Pause Timers
The Local Bus Latency and Pause Timers are programmable with the Mode/DMA Arbitration register (MARBR[7:0, 15:8], respectively). If the Local Bus Latency Timer is enabled and expires, the PCI 9056 completes the current Lword transfer and releases LHOLD. After its programmable Pause Timer expires, it reasserts LHOLD. It continues to transfer when it receives LHOLDA. The PCI Bus transfer continues until the FIFO is empty for a Local-to-PCI transfer or full for a PCI-to-Local transfer. The DMA transfer can be paused by writing a 0 to the Channel Enable bit. To acknowledge the disable, the PCI 9056 gets at least one data from the bus before it stops. However, this is not recommended during a burst. The DMA Local Bus Timer starts after the Local Bus is granted to the PCI 9056 and the Local Bus Pause Timer starts after LHOLDA is de-asserted.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-25
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
5.6
C AND J MODES TIMING DIAGRAMS
Timing Diagram 5-1. Direct Master Single Read
5-26
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-2. Direct Master Single Write and Single Read to PCI Memory and I/O Space
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-27
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-3. Direct Master Single Write and Single Read to and from PCI I/O Space
5-28
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-4. Direct Master Burst Write to PCI Memory Space Timing Diagram 5-5. TD-092.tif
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-29
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-6. Direct Master Burst Read from PCI Memory Space Timing Diagram 5-7. TD-096.tif
5-30
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-8. Direct Master Burst Write to PCI I/O Space
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-31
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-9. Direct Master Burst Read from PCI I/O Space
5-32
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-10. Direct Master Burst Write with a Retry on PCI Bus
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-33
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-11. Direct Master Burst Write followed by Direct Master Burst Read
5-34
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
5.6.1
C Mode Only Direct Master Timing Diagrams
Timing Diagram 5-12. Direct Master Memory Write of Four Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-35
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-13. Direct Master Memory Read of Four Lwords
5-36
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-14. Direct Master I/O Write of Four Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-37
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-15. Direct Master I/O Read of Four Lwords
5-38
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-16. Direct Master Single I/O Write
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-39
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-17. Direct Master Single I/O Read
5-40
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-18. Direct Master Memory Read of Four Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-41
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-19. Direct Master Memory Write of Six Lwords
5-42
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-20. Direct Master Memory Write of Seven Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-43
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-21. Direct Master Memory Read of Seven Lwords
5-44
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-22. Direct Master Memory Write of Eight Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-45
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-23. Direct Master Memory Read of Eight Lwords
5-46
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-24. Direct Master Memory Write of 12 Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-47
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-25. Direct Master Memory Read of 12 Lwords
5-48
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-26. Direct Master Memory Write of 32 Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-49
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-27. Direct Master Memory Read of 32 Lwords
5-50
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-28. Direct Master Memory Write of 40 Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-51
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-29. Direct Master Single Read by Direct Master Single Read
5-52
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-30. Direct Master Burst Read with a PCI Retry
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-53
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-31. Direct Master Burst Write Four Lwords
5-54
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-32. Direct Master Burst Read Four Lwords from I/O Space
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-55
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-33. Direct Master MWI 7, Transfer Eight Lwords
5-56
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-34. Direct Master MWI 8 Timing Diagram 5-35. TD-023.tif
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-57
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-36. Direct Master MWI 8, Transfer 16 Lwords
5-58
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-37. Direct Master MWI 16, Transfer Eight Lwords
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-59
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-38. Set Direct Master Write Mode to 8 for Write and Invalidate
5-60
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-39. Set Direct Master Write Mode to 8 for Write and Invalidate (Direct Master MWI 8) Timing Diagram 5-40. TD-028.tif
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-61
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-41. Set Direct Master Write Mode to 16 for Write and Invalidate Timing Diagram 5-42. TD-034.tif
5-62
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-43. Direct Master Single Write Read Memory, LBE = 1110b
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-63
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-44. Direct Master Single Write Read Memory, LBE = 1100b
5-64
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-45. Direct Master Single Write Read Memory, LBE = 1000b
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-65
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-46. Direct Master Memory Single Write Read Big Endian, LBE = 0111b
5-66
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-47. Direct Master Memory Single Write Read Big Endian, LBE = 0011b
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-67
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-48. Direct Master Single Write Read Memory Big Endian Input Timing Diagram 5-49. TD-041.tif
5-68
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-50. Direct Master I/O Single Write Read Big Endian, LBE = 1110b Timing Diagram 5-51. TD-045.tif
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-69
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-52. Direct Master Memory Read Programmable Command Code, CBE = 1100, 1110 Timing Diagram 5-53. TD-047.tif
5-70
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-54. Direct Master Memory Write Programmable Command Code, CBE = 1111
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-71
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-55. Direct Master Type 0, Configuration Device 2, Address 4 Timing Diagram 5-56. TD-050tif
5-72
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-57. Direct Master Type 1, Configuration Device 2, Address 5 Timing Diagram 5-58. TD-052.tif
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-73
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
5.6.2
C Mode Only Direct Slave Timing Diagrams
Timing Diagram 5-59. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, BREQ Enabled Timing Diagram 5-60. TD-054.tif
5-74
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-61. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Read No Write Enabled Timing Diagram 5-62. TD-056.tif
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-75
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-63. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read No Write Enabled
5-76
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-64. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Read Write Flush Enabled
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-77
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-65. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read Write Flush Enabled
5-78
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-66. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Delay Read Enabled
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-79
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-67. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Single Read Ahead Enabled
5-80
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-68. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Burst Read Ahead Enabled
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-81
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-69. Direct Slave Burst Read with Prefetch Data
5-82
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-70. Direct Slave from PCI Bus to 32-Bit Device on Local Bus, Local Timer 8 Expired
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-83
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-71. PCI Memory Write with Parity Error
5-84
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-72. Direct Slave Single Write
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-85
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-73. Direct Slave Single Read
5-86
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-74. Direct Slave Burst 20 Write
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-87
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-75. Direct Slave Burst 20 Read
5-88
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-76. Direct Slave Burst Read
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-89
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
5.6.3
C Mode Only DMA Timing Diagrams
Timing Diagram 5-77. DMA Channel 0 Local-to-PCI (Memory Write Command)
5-90
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-78. DMA Channel 0 PCI-to-Local (Memory Read Line Command)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-91
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-79. DMA Channel 0 PCI-to-Local (Memory Read Command)
5-92
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-80. DMA Channel 1 PCI-to-Local (Memory Read Command)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-93
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
5.6.4
J Mode Only DMA Timing Diagrams
Timing Diagram 5-81. DMA Channel 0 Local-to-PCI (Memory Write Command)
5-94
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J Modes Timing Diagrams
Timing Diagram 5-82. DMA Channel 0 PCI-to-Local (Memory Read Command)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
5-95
Section 5--C, J Func Desc
Section 5 C and J Modes Functional Description
Section 5 C and J Modes Functional Description
C and J Modes Timing Diagrams
Timing Diagram 5-83. DMA Channel 0 PCI-to-Local (Memory Read Line Command)
5-96
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
6
6.1
PCI/LOCAL INTERRUPTS AND USER I/O
INTERRUPTS
SERR# In Host Mode Parity Error Master Abort 256 Retrys Target Abort Local Parity Check
[6] [12] OR [0] [21]
DMA Channel 0 Done DMA Channel 0 Terminal Count Doorbells OR TEA#/ LSERR#
X2 OR X3 X4
[1]
[17]
Mailboxes BIST
[3]
Messaging Queue (outbound overflow) DMA Channel 0 Done DMA Channel 0 Terminal Count Doorbells Master Abort 256 Retrys Target Abort LINTi# (input) Messaging Queue (outbound not empty) DMA Channel 1 Done DMA Channel 1 Terminal Count
X6 OR X7 [12] OR X2 OR X3
X1
Power Management Messaging Queue (inbound not empty) DMA Channel 1 Done
[9] X6 OR X7
[4]
OR
[16]
LINTo# (output)
X5
X4
[10]
DMA Channel 1 Terminal Count INTA# In Host Mode OR
[8]
X8
[20]
INTA#
[11]
X9
X8
The numbers represent bit numbers in the INTCSR register X1 = Outbound Free Queue Overflow Interrupt Full and Mask bits (QSR[7:6]) X2 = Channel 0 Done Interrupt Enable bit (DMAMODE0[10]) X3 = Channel 0 Interrupt after Terminal Count bit (DMADPR0[2]) X4 = Local DMA Channel 0 Interrupt Enable bit (INTCSR[18]) and DMA Channel 0 Interrupt Select bit (DMAMODE0[17]) X5 = Inbound Post Queue Interrupt Not Empty and Inbound Post Queue Interrupt Mask bits (QSR[5:4]) X6 = Channel 1 Done Interrupt Enable bit (DMAMODE1[10]) X7 = Channel 1 Interrupt after Terminal Count bit (DMADPR1[2]) X8 = Local DMA Channel 1 Interrupt Enable bit (INTCSR[19]) and DMA Channel 1 Interrupt Select bit (DMAMODE1[17]) X9 = Outbound Post Queue Interrupt bit (OPQIS[3]) and Outbound Post Queue Interrupt Mask bit (OPQIM[3]) For X4 and X8, if bit 17=0, then LINTo# is asserted and if bit 17=1, then INTA# is asserted.
Figure 6-1. Interrupt and Error Sources
6.1.1
PCI Interrupts (INTA#)
In Adapter mode, a PCI 9056 PCI Interrupt (INTA#) can be asserted by one of the following: * Local-to-PCI Doorbell register * Local Interrupt input * Master/Target Abort Status condition * DMA Channel 0 and Channel 1 Done * DMA Channel 0 and Channel 1 Terminal Count is reached * Messaging Outbound Post Queue not empty * 256 consecutive PCI Retries INTA#, or individual sources of an interrupt, can be enabled or disabled with the PCI 9056 Interrupt Control/Status register (INTCSR). This register also provides the interrupt status of each interrupt source.
The PCI 9056 PCI Bus interrupt is a level output. Disabling an interrupt enable bit or clearing the cause of the interrupt can clear an interrupt.
6.1.2
Local Interrupt Input (LINTi#)
The Local Interrupt Input Enable bit must be enabled (INTCSR[11]=1) for interrupts to be acknowledged by the PCI 9056. Asserting the Local Bus input LINTi# can assert a PCI Bus interrupt. The PCI Host processor can read the PCI 9056 Interrupt Control/Status register (INTCSR) to determine whether an interrupt is pending as a result of LINTi# being asserted (INTCSR[15]). The interrupt remains asserted as long as LINTi# is asserted and the Local Interrupt input is enabled. The PCI Host processor can take adapter-specific action to cause the Local Bus to release LINTi#.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
6-1
Section 6--Interrupts, I/O
Section 6 PCI/Local Interrupts and User I/O
Interrupts
If the PCI Interrupt Enable bit is cleared (INTCSR[8]=0), the PCI interrupt (INTA#) is de-asserted; however, the Local interrupts (LINTi#) and the status bit remain active.
6.1.5
Mailbox Registers
6.1.3
Local Interrupt Output (LINTo#)
The PCI 9056 has eight 32-bit Mailbox registers that can be written to and read from both the PCI and Local Buses. These registers can be used to pass command and status information directly between the PCI and Local Bus devices. A Local interrupt can be asserted, if enabled (INTCSR[3] and INTCSR[16]), when the PCI Host writes to one of the first four Mailbox registers (MBOX0, MBOX1, MBOX2, or MBOX3). To clear the Mailbox registry, the destination bus should read the values currently in the Mailbox registers.
The PCI 9056 Local Interrupt output (LINTo#) can be asserted by one of the following: * PCI-to-Local Doorbell/Mailbox register access. * PCI BIST interrupt. * DMA Channel 0 and Channel 1 Done interrupt. * DMA Channel 0 and Channel 1 Terminal Count is reached. * DMA Abort Interrupt or Messaging Outbound Post Queue is not empty. * PCI INTA# when the HOSTEN# signal is asserted. The PCI 9056 is a PCI Host. LINTo#, or individual sources of an interrupt, can be enabled or disabled with the PCI 9056 Interrupt Control/Status register (INTCSR). This register also provides interrupt status for each interrupt source. The PCI 9056 Local interrupt is a level output. Interrupts can be cleared by disabling the Interrupt Enable bit of a source or by clearing the cause of an interrupt.
6.1.6
Doorbell Registers
The PCI 9056 has two 32-bit Doorbell Interrupt/Status registers. One is assigned to the PCI Bus interface. The other is assigned to the Local Bus interface. A Local processor can assert a PCI Bus interrupt by writing any number other than all zeroes (0) to the Local-to-PCI Doorbell register bits (L2PDBELL[31:0]). A PCI Host can assert a Local Bus interrupt by writing any number other than all zeroes (0) to the PCI-to-Local Doorbell register bits (P2LDBELL[31:0]). The PCI Interrupt and Local Interrupt remain asserted until all bits are cleared to zero (0).
PCI Bus Local Bus PCI Bus Local Bus
6.1.4
Master/Target Abort Interrupt
The PCI 9056 sets the Received Master Abort bit or Target Abort bit (PCISR[13 or 11]=1, respectively) when it detects a Master or Target Abort. These status bits cause the PCI INTA# to be asserted if interrupts are enabled. The interrupt remains set as long as the Receive Master Abort or Target Abort bits remain set and the Master/Target Abort interrupt is enabled. Use PCI Type 0 Configuration or Local accesses to clear the Received Master Abort and Target Abort interrupt bits (PCISR[13, 11]=0, respectively). The Interrupt Control/Status Register bits (INTCSR[26:24]) are latched at the time of a Master or Target Abort interrupt. These bits provide information when an abort occurs, such as which device was the Master when the abort occurred. The PCI Abort Address is stored in the PCI Abort Address register bits (PABTADR[31:0]).
Mailbox registers can be read and/or written from both sides Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5 Mailbox 6 Mailbox 7
Set
Doorbell registers set and clear interrupts PCI-to-Local Local-to-PCI
LINTo# (Interrupt) Set
INTA#
Used for Passing * Commands * Pointers * Status
Figure 6-2. Mailbox and Doorbell Message Passing
6-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Interrupts
Section 6 PCI/Local Interrupts and User I/O
6.1.6.1
Local-to-PCI Doorbell Interrupt
Each bit in the Local-to-PCI Doorbell register is individually controlled. The Local Bus can only set bits in the Local-to-PCI Doorbell register. From Local Bus, writing 1 to any bit position sets that bit and writing 0 has no effect. Bits in the Local-to-PCI Doorbell register can only be cleared from the PCI Bus. From the PCI Bus, writing 1 to any bit position clears that bit and writing 0 has no effect. Interrupts remain set as long as any Local-to-PCI Doorbell register bits are set and the PCI Doorbell Interrupt Enable bit (INTCSR[9]) is set.
Note: If the Local Bus cannot clear a Doorbell Interrupt, do not use the PCI-to-Local Doorbell register.
Interrupts remain set as long as any PCI-to-Local Doorbell register bits are set and the Local Doorbell Interrupt Enable bit is set (INTCSR[17]=1). To prevent race conditions when the Local Bus is accessing the PCI-to-Local Doorbell register (or any Configuration register), the PCI 9056 automatically issues a Retry to the PCI Bus.
6.1.7
Built-In Self Test Interrupt (BIST)
6.1.6.1.1 M Mode Local-to-PCI Doorbell Interrupt
To prevent race conditions from occurring when the PCI Bus is accessing the Local-to-PCI Doorbell register (or any Configuration register), the PCI 9056 automatically de-asserts TA# output to prevent Local Bus configuration accesses.
A PCI Bus Master can assert a Local Bus interrupt by performing a PCI Configuration write, which sets the PCI BIST Interrupt Enable bit (PCIBISTR[6]=1). A Local processor can read the BIST Interrupt Active bit (INTCSR[23]) to determine whether a BIST interrupt is pending. Interrupts remain set as long as the bit is set and the PCI BIST Interrupt Enable bit is set (PCIBISTR[6]=1). The Local Bus then resets the bit when BIST completes. The PCI Host software may fail the device if the bit is not reset after two seconds.
Note: The PCI 9056 does not have an internal BIST.
6.1.6.1.2 C and J Modes Local-to-PCI Doorbell Interrupt
To prevent race conditions from occurring when the PCI Bus is accessing the Local-to-PCI Doorbell register (or any Configuration register), the PCI 9056 automatically de-asserts READY# output to prevent Local Bus configuration accesses.
6.1.8
DMA Channel 0 and Channel 1 Interrupts
6.1.6.2
PCI-to-Local Doorbell Interrupt
A PCI Bus Master can assert a Local Bus interrupt by writing to the PCI-to-Local Doorbell Register bits (P2LDBELL[31:0]). The Local processor can read the Local Doorbell Interrupt Active bit to determine whether a Local doorbell interrupt is pending (P2LDBELL[20]), and if so, read the PCI 9056 PCI-to-Local Doorbell register.
A DMA channel can assert a PCI Bus or Local Bus interrupt when done (transfer complete) or after a transfer is complete for the current descriptor in Scatter/Gather DMA mode. The DMA Channel Interrupt Select bit(s) determine whether to assert a PCI (DMAMODE0[17]=1 and/or DMAMODE1[17]=1) or Local (DMAMODE0[17]=0 and/or DMAMODE1[17]=0) interrupt. The Local or PCI processor can read the DMA Channel Interrupt Active bit(s) to determine whether a DMA Channel 0 (INTCSR[21]) or DMA Channel 1 (INTCSR[22]) interrupt is pending.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
6-3
Section 6--Interrupts, I/O
A Local Bus Master can assert a PCI Bus interrupt by writing to the Local-to-PCI Doorbell Register bit(s) (L2PDBELL[31:0]). The PCI Host processor can read the PCI Doorbell Interrupt Active bit to determine whether a PCI Doorbell interrupt is pending (INTCSR[13]), and if so, read the PCI 9056 Local-to-PCI Doorbell register.
Each bit in the PCI-to-Local Doorbell register is individually controlled. The PCI Bus only sets bits in the PCI-to-Local Doorbell register. From the PCI Bus, writing 1 to any bit position sets that bit and writing 0 to a bit position has no effect. Bits in the PCI-to-Local Doorbell register can only be cleared from the Local Bus. From the Local Bus, writing 1 to any bit position clears that bit and writing 0 has no effect.
Section 6 PCI/Local Interrupts and User I/O
Interrupts
The Channel Done bit(s) (DMACSR0[4] and/or DMACSR1[4]) can be used to determine whether an interrupt is one of the following: * DMA Done interrupt * Transfer complete for current descriptor interrupt The Done Interrupt Enable bit(s) (DMAMODE0[10] and/or DMAMODE1[10]) enable a Done interrupt. In Scatter/Gather DMA mode, a bit in the Next Descriptor Pointer register of the channel (loaded from Local memory) specifies whether to assert an interrupt at the end of the transfer for the current descriptor. A DMA Channel interrupt is cleared by the Channel Clear Interrupt bit(s) (DMACSR0[3]=1 and/or DMACSR1[3]=1).
The PCI 9056 sets the Detected Parity Error bit (PCISR[15]=1) if it detects one of the following conditions: * The PCI 9056 detected a parity error during a PCI Address phase * The PCI 9056 detected a data parity error when it is the target of a write * The PCI 9056 detected a data parity error when performing Master Read operation
6.1.12 M Mode Local TEA# (Local NMI)
A TEA# interrupt is asserted if the following occurs: * PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1). * Detected Parity Error bit is set (PCISR[15]=1). * Direct Master Local Data Parity Check Error Status bit is set (INTCSR[7]=1). * Messaging Outbound Free queue overflows. * PCI SERR# when the HOSTEN# signal is asserted. The PCI 9056 is a PCI Host. The Enable Local Bus TEA# bit (INTCSR[0]) can be used to enable or disable TEA# for an abort or parity error. TEA# is a level output that remains asserted as long as the Abort or Parity Error Status bits are set. The PCI 9056 tolerates TEA# input assertion only during Direct Slave or DMA transactions. The PCI 9056 does not sample TEA# assertion during Direct Master transactions.
6.1.9
All Modes PCI SERR# (PCI NMI)
The PCI 9056 asserts an SERR# pulse if parity checking is enabled (PCICR[6]=1) and it detects an address or 1 is written to the Generate PCI Bus SERR# Interrupt bit (INTCSR[2]) with a current value of 0. SERR# output can be enabled or disabled with the SERR# Enable bit (PCICR[8]).
6.1.10 M Mode PCI SERR#
The PCI 9056 also asserts SERR# if the Local Bus responds with TEA# to the PCI 9056. The TEA# Input Interrupt Mask bit (LMISC1[5]) masks out the SERR# interrupt assertion process.
6.1.11 Local NMI
If the Parity Error Response bit is set (PCICR[6]=1), the PCI 9056 sets the Master Data Parity Error Detected bit (PCISR[8]=1) when the following three conditions are met: * The PCI 9056 asserted PERR# or acknowledged PERR# was asserted * The PCI 9056 was the Bus Master for the operation in which the error occurred * The Parity Error Response bit is set (PCICR[6]=1)
6.1.13 C and J Modes Local LSERR# (Local NMI)
An LSERR# interrupt is asserted if the following conditions occur: * PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1). * Detected Parity Error bit is set (PCISR[15]=1). * Direct Master Local Data Parity Check Error Status bit is set (INTCSR[7]=1). * Messaging Outbound Free queue overflows. * PCI SERR# when the HOSTEN# signal is asserted. The PCI 9056 is a PCI Host.
6-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
User Input and Output
Section 6 PCI/Local Interrupts and User I/O
The Enable Local Bus LSERR# bit (INTCSR[0]) can be used to enable or disable LSERR# for an abort or parity error. LSERR# is a level output that remains asserted as long as the Abort or Parity Error Status bits are set.
6.2
USER INPUT AND OUTPUT
Section 6--Interrupts, I/O
Preliminary Information 6-5
The PCI 9056 supports user input and output pins, USERi and USERo (B14 and C14, respectively). Both are multiplexed with other functional pins. The default PCI 9056 condition are the USERi and USERo functions. USERi is selected when CNTRL[18]=1, and USERo is selected when CNTRL[19]=1. User output data can be logged by writing to the General Purpose Output bit (CNTRL[16]). User input data can be read from the General Purpose Input bit (CNTRL[17]).
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
7
7.1
INTELLIGENT I/O (I2O)
I2O-COMPATIBLE MESSAGE UNIT
shared Local Bus (IOP) memory. The inbound message queue is comprised of a pair of rotating FIFOs implemented in Local memory. The Inbound Free List FIFO holds the message frame addresses (MFA) of available message frames in Local memory. The Inbound Post Queue FIFO holds the MFA of all currently posted messages. External PCI agents, through the Inbound Queue Port location in PCI Address space, access inbound circular FIFOs. (Refer to Table 7-2 on page 7-6.) The Inbound Queue Port, when read by an external PCI agent, returns the Inbound Free List FIFO MFA. The external PCI agent places a message frame into the Inbound Post Queue FIFO by writing its MFA to the Inbound Queue Port location.
The I2O-compatible Messaging Unit supplies two paths for messages, two inbound FIFOs to receive messages from the primary PCI Bus, and two outbound FIFOs to pass messages to the primary PCI Bus. Refer to I2O r1.5 for details. Figure 7-1 and Figure 7-2 illustrate I2O architecture.
No Hardware Changes Required on the Host Side
Host System Memory
Message Frames
Host Local Bus
Host PCI Interface
Host CPU
Inbound Queue Port PCI Bus
Outbound Queue Port
Message Frames
IOP Local Bus
I/O Chip
I/O Chip
Figure 7-1. Typical I2O Server/Adapter Card Design
Note: IOP = I/O Processor.
Present Architecture
API for I/O Commands OSM (I2O Shell)
Messaging Layer
Outbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in the shared PCI Bus (Host System) memory. The Outbound message queue is comprised of a pair of rotating FIFOs implemented in Local memory. The Outbound Free List FIFO holds the message frame addresses (MFA) of available message frames in system memory. The Outbound Post Queue FIFO holds the MFA of all currently posted messages. External PCI agents, through the Outbound Queue Port location in PCI Address space access outbound circular FIFOs. (Refer to Table 7-2 on page 7-6.) The Outbound Queue Port, when read by an external PCI agent, returns the Outbound Post Queue FIFO MFA. The External PCI agent places free message frames into the Outbound Free List FIFO by writing the free MFA into the Outbound Queue Port location. Memory for the circular FIFOs must be allocated in Local (IOP) memory. The base address of the queue is contained in the Queue Base Address bits (QBAR[31:20]). Each FIFO entry is a 32-bit data value. Each read and write of the queue must be a single 32-bit access. Circular FIFOs range in size from 4- to 64-KB entries. All four FIFOs must be the same size and contiguous. Therefore, the total amount of Local memory needed for circular FIFOs ranges from 64 KB to 1 MB. A FIFO
I2O Architecture
OS-Specific Module
(I2O Shell) Hardware Device Module Optional (I2O Shell) DDM
Hardware
Hardware
Figure 7-2. Driver Architecture Compared
7.1.1
Inbound Messages
Inbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in the
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
7-1
Section 7--I2O
IOP Must Have CPU * Memory * Messaging *
IOP Local Memory
Message Queues
PCI 9056 I2O Messaging Unit
7.1.2
Outbound Messages
Section 7 Intelligent I/O (I2O)
I2O-Compatible Message Unit
size is specified in the Circular Queue Size bits (MQCR[5:1]). The starting address of each FIFO is based on the Queue Base Address and the FIFO Size, as listed in Table 7-1.
Table 7-1. Queue Starting Address
FIFO
Inbound Free List Inbound Post List Outbound Post List Outbound Free List
Full flags are always cleared when the queues are disabled or the head and tail pointers are not equal. A full flag is set when the queues are enabled, the head pointer is incremented, and the head and tail pointers become equal. Each circular FIFO has a head pointer and a tail pointer, which are offsets from the Queue Base Address. (Refer to Table 7-2 on page 7-6.) Writes to a FIFO occur at the head of the FIFO and reads occur from the tail. Head and tail pointers are incremented by either the Local processor or the MU hardware. The unit that writes to the FIFO also maintains the pointer. Pointers are incremented after a FIFO access. Both pointers wrap around to the first address of the circular FIFO when they reach the FIFO size, so that the head and tail pointers continuously "chase" each other around in the circular FIFO. The MU wraps the pointers automatically for the pointers that it maintains. IOP software must wrap the pointers that it maintains. Whenever they are equal, the FIFO is empty. To prevent overflow conditions, I2O specifies that the number of message frames allocated should be less than or equal to the number of entries in a FIFO. (Refer to Figure 7-3.) Each inbound MFA is specified by I2O as the offset from the start of shared Local (IOP) memory region 0 to the start of the message frame. Each outbound MFA is specified as the offset from Host memory location 0x00000000h to the start of the message frame in shared Host memory. Because the MFA is an actual address, the message frames need not be contiguous. IOP allocates and initializes inbound message frames in shared IOP memory using any suitable memory allocation technique. Host allocates and initializes outbound message frames in shared Host memory using any suitable memory allocation technique. Message frames are a minimum of 64 bytes in length. I2O uses a "push" (write-preferred) memory model. That means the IOP writes messages and data to the shared Host memory, and the Host writes messages and data to shared IOP memory. Software should make use of Burst and DMA transfers whenever possible to ensure efficient use of the PCI Bus for message passing. Additional information on message implementation may be found in I2O r1.5. passing
Starting Address
QBAR QBAR + (1 * FIFO Size) QBAR + (2 * FIFO Size) QBAR + (3 * FIFO Size)
7.1.3
I2O Pointer Management
The FIFOs always reside in shared Local (IOP) memory and are allocated and initialized by the IOP. Before setting the Queue Enable bit (MQCR[0]=1), the Local processor must initialize the following registers, with the initial offset according to the configured FIFO size: * Inbound Post and Free Head Pointer registers (IPHPR and IFHPR) * Inbound Post and Free Tail Pointer registers (IPTPR and IFTPR) * Outbound Post and Free Head Pointer registers (OPHPR and OFHPR) * Outbound Post and Free Tail Pointer registers (OPTPR and OFTPR) The Messaging Unit automatically adds the Queue Base Address to offset in each head and tail pointer register. The software can then enable I2O. After initialization, the Local software should not write to the pointers managed by the MU hardware. Empty flags are set if the queues are disabled (MQCR[0]=0) or head and tail pointers are equal. This occurs independent of how the head and tail pointers are set. An empty flag is cleared, signifying not empty, only if the queues are enabled and pointers become not equal. If an empty flag is cleared and the queues are enabled, the empty flag is set only if the tail pointer is incremented and the head and tail pointers become equal.
7-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
I2O-Compatible Message Unit
Section 7 Intelligent I/O (I2O)
7.1.4
Inbound Free List FIFO
The Local processor allocates inbound message frames in its shared memory and can place the address of a free (available) message frame into the Inbound Free List FIFO by writing its MFA into the FIFO location pointed to by the Queue Base register + Inbound Free Head Pointer register. The Local processor must then increment the Inbound Free Head Pointer register. A PCI Master (Host or other IOP) can obtain the MFA of a free message frame by reading the Inbound Queue Port Address (40h of the first PCI Memory Base Address register). If the FIFO is empty (no free inbound message frames are currently available, head and tail pointers are equal), the MU returns -1 (FFFFFFFFh). If the FIFO is not empty (head and tail pointers are not equal), the MU reads the MFA pointed to by the Queue Base register + Inbound Free Tail Pointer register, returns its value and increments the Inbound Free Tail Pointer register. If the Inbound Free Queue is not empty, and the Inbound Free Queue Prefetch Enable bit is set (QSR[3]=1), the next entry in the FIFO is read from the Local Bus into a prefetch register. The prefetch register then provides the data for the next PCI read from this queue, thus reducing the number of PCI wait states. (Refer to Figure 7-3.)
The PCI 9056 asserts a Local Interrupt when the Inbound Post Queue FIFO is not empty. The Inbound Post Queue FIFO Interrupt bit in the Queue Status/ Control register (QSR[5]) indicates the interrupt status. The interrupt clears when the Inbound Post Queue FIFO is empty. The Inbound Post Queue FIFO Interrupt Mask bit (QSR[4]) can mask the interrupt. To prevent racing between the time the PCI Write transaction is received until the data is written in Local memory and the Inbound Post Head Pointer register is incremented, any Direct Slave access to the PCI 9056 is issued a Retry.
7.1.6
Outbound Post Queue FIFO
7.1.5
Inbound Post Queue FIFO
A PCI Master (Host or other IOP) can write a message into an available message frame in the shared Local (IOP) memory. It can then post that message by writing the Message Frame Address (MFA) to the Inbound Queue Port Address, IQP (40h of the first PCI Memory Base Address register). When the port is written, the MU writes the MFA to the Inbound Post Queue FIFO location pointed to by the Queue Base register + FIFO Size + Inbound Post Head Pointer register. After the MU writes the MFA to the Inbound Post Queue FIFO, it increments the Inbound Post Head Pointer register. The Inbound Post Tail Pointer register points to the Inbound Post Queue FIFO location, which holds the MFA of the oldest posted message. The Local processor maintains the tail pointer. After a Local processor reads the oldest MFA, it can remove the MFA from the Inbound Post Queue FIFO by incrementing the Inbound Post Tail Pointer register.
A PCI Master can obtain the MFA of the oldest posted message by reading the Outbound Queue Port Address (44h of the first PCI Memory Base Address register). If the FIFO is empty (no further outbound messages are posted, head and tail pointers are equal), the MU returns -1 (FFFFFFFFh). If the Outbound Post Queue FIFO is not empty (head and tail pointers are not equal), the MU reads the MFA pointed to by the Queue Base register + (2 * FIFO Size) + outbound Post Tail Pointer register, returns its value and increments the Outbound Post Tail Pointer register. The PCI 9056 asserts a PCI Interrupt when the Outbound Post Head Pointer register is not equal to the Outbound Post Tail Pointer register. The Outbound Post Queue FIFO Interrupt bit of the Outbound Post Queue Interrupt Status register (OPQIS) indicates the interrupt status. When the pointers become equal, both the interrupt and the Outbound Post Queue FIFO interrupt bit are automatically cleared. Pointers become equal when a PCI Master (Host or other IOP) reads sufficient FIFO entries to empty the FIFO. The Outbound Post Queue FIFO Interrupt Mask register (OPLFIM) can mask the Interrupt.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
7-3
Section 7--I2O
A Local Master (IOP) can write a message into an available message frame in shared Host memory. It can then post that message by writing the Message Frame Address (MFA) to the Outbound Post Queue FIFO location pointed to by the Queue Base register + Outbound Post Head Pointer register + (2 * FIFO Size). The Local processor should then increment the Outbound Post Head Pointer register.
Section 7 Intelligent I/O (I2O)
I2O-Compatible Message Unit
High Address Local Memory
External PCI Agent (Recipient)
PCI Recipient Process: (1) Reads the MFA (2) Reads the message frame (3) Returns the MFA
Local Memory
Incremented by the PCI 9056
PCI 9056 Registers
Write (3) Outbound Queue Port (OQP, PCI offset 44h) through the PCI 9056 Read (1) Address = QBAR + (3*FIFO size) Read Outbound Free List FIFO Incremented by the Local Processor
Head Pointer OFHPR Tail Pointer OFTPR
Local Processor (Sender)
Outbound Queue
Write Outbound Post List FIFO Incremented by the Local Processor
Head Pointer OPHPR Tail Pointer OPTPR
Address = QBAR + (2*FIFO size)
External PCI Agent (Sender)
PCI Sender Process: (1) Reads the MFA (2) Writes the message frame (3) Returns the MFA Write (3) Inbound Queue Port (IQP, PCI offset 40h) through the PCI 9056 Read (1) Address = QBAR + (1*FIFO size) Read Inbound Post List FIFO
Incremented by the PCI 9056 Incremented by the PCI 9056 Head Pointer IPHPR Incremented by the Local Processor Tail Pointer IPTPR
Local Processor (Recipient)
Inbound Queue
Write Inbound Free List FIFO Address = QBAR Low Address Local Memory Incremented by the PCI 9056 Incremented by the Local Processor
Head Pointer IFHPR Tail Pointer IFTPR
Figure 7-3. I2O Circular FIFO Operation
7.1.7
Outbound Post Queue
To reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read from), or when the queue is empty and the head pointer is incremented (queue has been written to).
When the Host CPU reads the Outbound Post Queue, the data is immediately available.
7.1.8
Inbound Free Queue
To reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
7-4
Preliminary Information
I2O-Compatible Message Unit
Section 7 Intelligent I/O (I2O)
from), or when the queue is empty and the head pointer is incremented (queue has been written to). When the Host CPU reads the Inbound Free Queue, the data is immediately available.
7.1.10 I2O Enable Sequence
To enable I2O, the Local processor performs the following: * Initialize Space 1 address and range
7.1.9
Outbound Free List FIFO
* Initialize all FIFOs and Message Frame memory * Set the PCI Base Class Code bits (PCICCR[23:16]) to be an I2O device with Programming Interface 01h * Set the I2O Decode Enable bit (QSR[0]) * Set Local Init Status bit to "done" (LMISC1[2]=1)
Note: The serial EEPROM must not set the Local Init Status bit so that the PCI 9056 issues Retrys to all PCI accesses until the Local Init Status bit is set to "done" by the Local processor.
The PCI Bus Master (Host or other IOP) allocates outbound message frames in its shared memory. The PCI Bus Master can place the address of a free (available) message frame into the Outbound Free List FIFO by writing a Message Frame Address (MFA) to the Outbound Queue Port Address (44h of the first PCI Memory Base Address register). When the port is written, the MU writes the MFA to the Outbound Free List FIFO location pointed to by the Queue Base register + (3 * FIFO Size) + Outbound Free Head Pointer register. After the MU writes the MFA to the Outbound Free List FIFO, it increments the Outbound Free Head Pointer register. When the IOP needs a free outbound message frame, it must first check whether any free frames are available. If the Outbound Free List FIFO is empty (outbound free head and tail pointers are equal), the IOP must wait for the Host to place additional outbound free message frames in the Outbound Free List FIFO. If the Outbound Free List FIFO is not empty (head and tail pointers are not equal), the IOP can obtain the MFA of the oldest free outbound message frame by reading the location pointed to by the Queue Base register + (3 * FIFO Size) + Outbound Free Tail Pointer register. After the IOP reads the MFA, it must increment the Outbound Free Tail Pointer register. To prevent overflow conditions, I2O specifies the number of message frames allocated should be less than or equal to the number of entries in a FIFO. The MU also checks for overflows of the Outbound Free List FIFO. When the head pointer is incremented and becomes equal to the tail pointer, the Outbound Free List FIFO is full, and the MU asserts a LINTo# interrupt. The interrupt is recorded in the Queue Status/Control register (QSR). From the time the PCI Write transaction is received until the data is written into Local memory and the Outbound Free Head Pointer register is incremented, any Direct Slave access to the PCI 9056 is issued a Retry.
Accesses above offset FFh of PCIBAR0 result in Local Space accesses, beginning at offset 100h from the Remap PCI Address to Local Address Space 1 into the Local Address Space bits (LAS1BA[31:4]). Therefore, space located at offset 00h-FFh from LAS1BA is not addressable from the PCI Bus using PCIBAR0.
Note: Because PCI accesses to offset 00h-FFh of PCIBAR0 result in internal configuration accesses, the Inbound Free MFAs must be greater than FFh.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
7-5
Section 7--I2O
The I2O Decode Enable bit (QSR[0]) causes remapping of resources for use in I2O mode. When set, all Memory-Mapped Configuration registers (for example, queue ports 40h and 44h) and Space 1 share the PCIBAR0 register. PCI accesses to offset 00h-FFh of PCIBAR0 result in accesses to the PCI 9056 Internal Configuration registers.
Section 7 Intelligent I/O (I2O)
I2O-Compatible Message Unit
Table 7-2. Circular FIFO Summary
FIFO Name
Inbound Free List FIFO Inbound Post List FIFO Outbound Post List FIFO Outbound Free List FIFO
PCI Port
Inbound Queue Port (Host read) Inbound Queue Port (Host write) Outbound Queue Port (Host read) Outbound Queue Port (Host write)
Generate PCI Interrupt
No
Generate Local Interrupt
No Yes, when Port is written No Yes, (LINTo#) when FIFO is full
Head Pointer Maintained By
Local processor
Tail Pointer Maintained By
MU hardware
No Yes, when FIFO is not empty No
MU hardware
Local processor
Local processor
MU hardware
MU hardware
Local processor
7-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
8
8.1
PCI POWER MANAGEMENT
OVERVIEW
* B1--Intermediate power management state. Full power with clock frequency. PME Event driven bus activity. VCC is applied to all devices on the bus, and no transactions are allowed to occur on the bus. * B2--Intermediate power management state. Full power clock frequency stopped (in the low state). PME Event-driven bus activity. VCC is applied to all devices on the bus; however, the clock is stopped and held in the Low state. * B3 (Off)--Power to the bus is switched off. PME Event-driven bus activity. VCC is removed from all devices on the PCI Bus. All system PCI Buses have an originating device, which can support one or more power states. In most cases, this creates a bridge (such as a Host-to-PCI Bus or a PCI-to-PCI bridge). Function States must be at the same or lower energy state than the bus on which they reside.
The PCI Power Mgmt. r1.1, provides a standard mechanism for operating systems to control add-in cards for power management. PCI Power Mgmt. r1.1 defines four PCI functional power states--D0, D1, D2, and D3. States D0 and D3 are required, while states D1 and D2 are optional. State D0 represents the highest power consumption and state D3 the least. * D0 (Uninitialized)--Enters this state from Power-On Reset or from state D3hot. Supports Direct Slave PCI transactions only. * D0 (Active)--All functions active. * D1--Uses less power than State D0, and more than state D2. Light sleep state. * D2--Uses very little power. The functional states are defined by the allowed activities of the add-in card with the PCI 9056. The function supports PCI Configuration cycles to function if clock is running (Memory, I/O, Bus Mastering, and Interrupts are disabled). It also supports the Wakeup Event from function, but not standard PCI interrupts. * D3hot--Uses lower power than any other state. Supports PCI Configuration cycles to function if clock is running. Supports Wakeup Event from function, but not standard PCI interrupts. When programmed for state D0, an internal soft reset occurs. The PCI Bus drivers must be disabled. PME# context must be retained during this soft reset. * D3cold--No power. Supports Bus reset only. All context is lost in this state. From a power management perspective, the PCI Bus can be characterized at any point in time by one of four power management states--B0, B1, B2, and B3: * B0 (Fully On)--Bus is fully usable with full power and clock frequency, PCI r2.2-compliant. Fully operational bus activity. This is the only Power Management state in which data transactions can occur.
8.1.1
PCI Power Management Functional Description
The PCI 9056 passes power management information and has no inherent power-saving feature. The PCI Status register (PCISR) and the New Capability Pointer register (CAP_PTR) indicate whether a new capability (the Power Management function) is available. The New Capability Functions Support bit (PCISR[4]) enables a PCI BIOS to identify a New Capability function support. This bit is executable for writes from the Local Bus, and reads from both the Local and PCI Buses. CAP_PTR provides an offset into PCI Configuration Space, the start location of the first item in a New Capabilities Linked List. The Power Management Capability ID register (PMCAPID) specifies the Power Management Capability ID, 01h, assigned by the PCI SIG. The Power Management Next Capability Pointer register (PMNEXT) points to the first location of the next item in the capabilities linked list. If Power Management is the last item in the list, then this register should be set to 0. The default value for the PCI 9056 is 48h (Hot Swap).
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
8-1
Section 8--Power Mgmt
Section 8 PCI Power Management
Overview
For the PCI 9056 to change the power state and assert PME#, a Local or PCI Host should set the PME_En bit (PMCSR[8]=1). The Local Host then determines to which power state the backplane should change by reading the Power State bits (PMCSR[1:0]). The Local Host sets up the following: * D2_Support and D1_Support bits (PMC[10:9]) are used by the Local Host to identify power state support * PME_Support bits (PMC[14:11]) are used by the PCI 9056 to identify the PME# Support correspondent to a specific power state (PMCSR[1:0]) The Local Host then sets the PME_Status bit (PMCSR[15]=1) and the PCI 9056 asserts PME#. To clear the PME_Status bit, the PCI Host must write a 1 to the PME# Status bit (PMCSR[15]=1). To disable the PME# Interrupt signal, either Host can write a 0 to the PME_En bit (PMCSR[8]=0). LINTo# is asserted every time the power state in the PMCSR register changes. Transmission from state 11 (D3hot) to state 00 (D0) causes a soft reset. A soft reset should only be initiated from the PCI Bus because the Local Bus interface is reset during a soft reset. The PCI 9056 issues LRESET# and resets all its internal registers to their default values. In state D3hot, PCI Memory and I/O accesses are disabled, as well as PCI interrupts, and only configuration is allowed. Before making LINTo# work, set the Power Management Interrupt Enable bit (INTCSR[4]=1), and clear the interrupt by setting the Power Management Interrupt bit (INTCSR[5]=1). The Data_Scale bits (PMCSR[14:13]) indicate the scaling factor to use when interpreting the value of the Power Management Data bits (PMDATA[7:0]). The value and meaning of the bits depend upon the data value specified in the Data_Select bits (PMCSR[12:9]). The Data_Scale bit value is unique for each Data_Select bit. For Data_Select values from 8 to 15, the Data_Scale bits always return a zero (PMCSR[14:13]=0). PMDATA provides operating data, such as power consumed or heat dissipation.
8.1.2
66 MHz PCI Clock Power Management D2 Support
The PCI 9056 provides full support for the D2 Power Management state at a 33 MHz PCI clock frequency. The PCI r2.2-compliant 66 MHz PCI clock frequency prohibits any change to the clock without the system reset (RST#) being asserted. (Refer to PCI r2.2 and PCI Power Mgmt. r1.1.) Therefore, the PCI 9056 cannot support the D2 Power Management state at 66 MHz. To do that, the PCI 9056 requires an external control to avoid enabling the D2 Power Management feature at a 66 MHz clock frequency. Default booting of the PCI 9056 sets D2 support to a disabled state. All 66 MHz add-in cards, capable of running at a 66 MHz PCI clock frequency, must monitor the M66EN# PCI connector pin. When this pin is present on a card, the Local Processor can monitor the pin, and enable D2 Power Management support (PMC[10]) by way of the register access whenever the M66EN# PCI connector pin is sampled false.
8.1.3
Power Management D3cold Support
The PCI 9056 provides full support for the D3cold Power Management state with PME# assertion and register contents storage. The PCI 9056 has all pins required by the PCI Power Mgmt. r1.1. Special attention is necessary for the following pins: * 2.5VAUX--Power input pin routed to the D3cold support core logic. Due to unavailable power from the PCI slot, 2.5V power must be supplied by an external power source, voltage regulator. * Card_VAUX--3.3VAUX power input pin driven by the PCI backplane through add-in card Auxiliary Power Routing. (Refer to PCI Power Mgmt. r1.1, Figure 12.) * PRESENT_DET--Present Detect pin provided by add-in card Auxiliary Power Routing (refer to PCI Power Mgmt. r1.1, Figure 12) to enable the D3cold PME# assertion feature within the PCI 9056 silicon.
8-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Overview
Section 8 PCI Power Management
* PME#--Optional open drain, active low signal intended to be driven low by the PCI 9056 to request a change in its current power management state and/or to indicate that a PME# has occurred. The PCI 9056 requires external logic to avoid unexpected Wake-Up events to occur whenever an add-in card is plugged into the PCI r2.2-compliant PCI backplane. (Refer to PCI Power Mgmt. r1.1, Chapter 7.) * PMEREQ#--Input signal used to request a wake-up event only when the add-in card is in the D3cold Power Management state. * IDDQEN#--Input signal providing main power status to the PCI 9056 D3cold Power Management logic.
Note: All signal I/Os used for D3cold Power Management support are powered by Card_VAUX power.
Notes: In Power-Saving mode, all PCI and Local Configuration cycles are granted. The PCI 9056 automatically performs a soft reset to a Local Bus on D3-to-D0 transitions.
8.1.5
Non-D3cold Wake-Up Request Example
1. The add-in card (with a PCI 9056 chip installed) is in a powered-down state. 2. The Local CPU performs a write to the PCI 9056 PMCSR register to request a wake-up procedure. 3. As soon as the request is detected, the PCI 9056 drives PME# out to the PCI Bus. 4. The PCI Host accesses the PCI 9056 PMCSR register to disable the PME# output signal and restores the PCI 9056 to the D0 power state. 5. The PCI 9056 completes the power management task by issuing the Local interrupt (LINTo#) to the Local CPU, indicating that the power mode has changed.
8.1.4
System Changes Power Mode Example
1. The Host writes to the PCI 9056 PMCSR register to change the power states. 2. The PCI 9056 sends a local interrupt (LINTo#) to a Local CPU (LCPU). 3. The LCPU has 200 s to read the power management information from the PCI 9056 PMCSR register to implement the power-saving function. 4. After the LCPU implements the power saving function, the PCI 9056 disables all Direct Slave accesses and PCI Interrupt output (INTA#). In addition, the BIOS disables the PCI 9056 Master Access Enable bit (PCICR[2]).
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
8-3
Section 8--Power Mgmt
9
COMPACTPCI HOT SWAP
* Incorporates remaining software connection control resources. Provides ENUM#, Hot Swap switch, and the blue LED. * Early Power Support. * Incorporates a 1V BIAS precharge voltage to the PCI I/O pins--All PCI Bus signals are required to be precharged to a 1V BIAS through a 10K ohm resistor during the Hot Swap process. The PCI 9056 provides an internal voltage regulator to supply 1V, with a built-in 10K ohm resistor, to all required PCI I/O buffers. Other PCI signals can be precharged to VIO.
The PCI 9056 is compliant with the PICMG 2.1, R2.0 requirements for Hot Swap Silicon, including support for Programming Interface (PI = 0), and BIAS Voltage, Early Power, and Initially Not Respond Support.
9.1
OVERVIEW
Hot Swap is used for many CompactPCI applications. Hot Swap functionality allows the orderly insertion and removal of boards without adversely affecting system operation. This is done for repair of faulty boards or system reconfiguration. Additionally, Hot Swap provides access to Hot Swap services, allowing system reconfiguration and fault recovery to occur with no system down time and minimum operator interaction. Adapter insertion/removal logic control resides on the individual adapters. The PCI 9056 uses four pins--BD_SEL#, CPCISW, ENUM# and LEDon#--to implement the hardware aspects of Hot Swap functionality. The PCI 9056 uses the Hot Swap Capabilities register to implement the software aspects of Hot Swap. The PCI 9056 supports the following features specified in the PICMG 2.1, R2.0 requirements for Hot Swap Silicon: * PICMG 2.1, R2.0 compliance * Tolerate VCC from early power * Tolerate asynchronous reset * Tolerate precharge voltage * I/O Buffers must meet modified V/I requirements * Limited I/O pin leakage at precharge voltage * Incorporates Hot Swap Control/Status register (HS_CSR)--Contained within the configuration space. * Incorporates an Extended Capability Pointer (ECP) mechanism--It is required that Software retain a standard method of determining whether a specific function is designed in accordance with PICMG 2.1, R2.0. The Capabilities Pointer is located within standard CSR space, using a bit in the PCI Status register (offset 04h).
9.1.1
Silicon Behavior during Initialization on PCI Bus
The PCI 9056 supports an Initialization-time PCI option, which may be utilized by CompactPCI peripheral adapter cards designed for live insertion. Section 3.1.10 of the PICMG 2.1, R2.0 states, "it is far preferable for boards that are not ready for PCI accesses to Initially Not Respond." The PCI 9056 Initialization-time PCI option allows configuration of the PCI 9056 to provide this preferable Initially Not Respond behavior. This option is detailed in Section 2.4.1.2, "Local Initialization," and Section 4.4.1.2, "Local Initialization." The PCI 9056 supports the PICMG 2.1, R2.0 Programming Interface 0 (PI = 0), as detailed in Figures 29 and 30 of that document. All required register bits and supporting control functionality are included in the CompactPCI Hot Swap Control and Status register (HS_CSR).
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
9-1
Section 9--Hot Swap
Section 9 CompactPCI Hot Swap
Controlling Connection Processes
9.2
CONTROLLING CONNECTION PROCESSES
9.2.1.2
Board Healthy
The following sections are excerpted from PICMG 2.1, R2.0, and modified, as appropriate, for the PCI 9056. (Refer to PICMG 2.1, R2.0 for more details.)
A second radial signal is used to acknowledge board health. It signals that a board is suitable to be released from reset and allowed onto the PCI Bus. Minimally, this signal must be connected to the board's power controller "power good" status line. Use of HEALTHY# can be expanded for applications requiring additional conditions to be met for the board to be considered healthy. On platforms that do not use Hardware Connection Control, this line is not monitored. Platforms implementing this signaling, route these signals radially to a Hot Swap controller.
Platform | Board HSC Platform | Board VIO
9.2.1
Connection Control
Hardware Control provides a means for the platform to control the hardware connection process. The signals listed in the following sections must be supported on all Hot Swap boards for interoperability. Implementations on different platforms may vary.
9.2.1.1
Board Slot Control
BD_SEL#, one of the shortest pins from the CompactPCI backplane, is driven low to enable power-on. For systems not implementing hardware control, it is grounded on the backplane. Systems implementing hardware control radially connect BD_SEL# to a Hot Swap Controller (HSC). The controller terminates the signal with a weak pull-down resistor, and can detect board present when the board pull-up resistor overrides the pull-down resistor. HSC can then control the power-on process by driving BD_SEL# low. The PCI 9056 uses the BD_SEL# signal to high-impedance all local output buffers during the insertion and extraction process. In addition, the PCI 9056 uses BD_SEL# as a qualifier to dynamically connect 1V and VIO BIAS precharge resistors to all required PCI I/O buffers. A pull-up resistor must be provided to the BD_SEL# pin or add-in card, where the pull-up resistor is connected to an early power Power Supply, which provides for proper PCI 9056 operation. (Refer to Section 12, "Pin Description," for precharge connections.)
Platform | Board VIO Power Circuitry HSC PRESENT PWR ON BD_SEL# ON Power Circuitry Platform | Board VIO
NC
Power Circuitry
HEALTHY
HLTY
Power Circuitry
No Hardware Control
Hardware Control
Figure 9-2. Board Healthy
9.2.1.3
Platform Reset
PCI Reset (RST#), as defined by PICMG 2.1, R2.0, is a bus signal on the backplane, driven by the Host. Platforms may implement this signal as a radial signal from the Hot Swap Controller to further control the electrical connection process. Platforms that maintain function of the bus signal, must OR the Host reset signal with the slot-specific signal. Locally, boards must not exit reset until the H1 State is reached (healthy), and they must honor the backplane reset. The Local board reset (LRESET#) must be the logical OR of these two conditions. LRESET# is connected to the PCI 9056 RST# input pin. During a BIAS voltage precharge and platform reset, in insertion and extraction procedures, all PCI I/O buffers must be in a high-impedance state. The PCI 9056 supports this condition when the Host RST# is asserted. To protect the Local board components from early power, the PCI 9056 floats the Local Bus I/ Os. The BD_SEL# pin is used to perform the high-impedance condition on the Local Bus. With full contact of the add-in card to the backplane, BD_SEL# is asserted which ensures that the PCI 9056 asserts
BD_SEL# ON
No Hardware Control
Hardware Control
Figure 9-1. Redirection of BD_SEL#
9-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Controlling Connection Processes
Section 9 CompactPCI Hot Swap
the LRESET# signal to complete a Local board reset task.
connection layer provides protection for the system during all insertions and extractions. This LED indicates the system software is in a state that tolerates board extraction. Upon insertion, the LED is automatically illuminated by the hardware until the hardware connection process completes. The LED remains OFF until the software uses it to indicate extraction is once again permitted. The PCI 9056 uses an open-drain output pin to sink the external LED. The LED state is driven from the LED Software On/Off Switch bit (HS_CSR[3]). The CPCISW input signal acknowledges the state ejector handle change to identify when a board is inserted or removed. The appropriate status bits are set (HS_CSR[7:6]).
Platform | Board PCI_RST# LOCAL_PCI_RST# HOST HOST
Platform | Board PCI_RST#
LOCAL_PCI_RST#
HEALTHY #
HSC HEALTHY#
No Hardware Control
Hardware Connection Control
Figure 9-3. PCI Reset
9.2.2
Software Connection Control
Software Connection Control provides a means to control the Software Connection Process. Hot Swap board resources facilitate software Connection Control. Access to these resources occurs by way of the bus, using PCI protocol transfers (in-band). These resources consist of four elements: * ENUM# driven active indicates the need to change the Hot Swap Board state * A switch, tied to the ejector, indicates the intent to remove a board * LED indicates the software connection process status * Control/Status register allows the software to interact with these resources
9.2.2.2
ENUM#
ENUM# is provided to notify the Host CPU that a board was recently inserted or is about to be removed. This signal informs the CPU that system configuration changed, at which time the CPU performs necessary maintenance such as installing a device driver upon board insertion, or quiescing a device driver prior to board extraction. ENUM# is an open collector bused signal with a pull-up resistor on the Host bus. It may drive an interrupt (preferred) or be polled by the system software at regular intervals. The CompactPCI Hot-Plug System Driver on the system Host manages the ENUM# sensing. Full Hot Swap Boards assert ENUM# until serviced by the Hot-Plug system driver. When a board is inserted into the system and comes out of reset, the PCI 9056 acknowledges the ejector switch state. If this switch is open (ejector handle closed), the PCI 9056 asserts the ENUM# interrupt and sets the ENUM# Status Indicator for Board Insertion bit (HS_CSR[7]). Once the Host CPU installs the proper drivers, it can logically include this board by clearing the interrupt. When a board is about to be removed, the PCI 9056 acknowledges the ejector handle is open, asserts the ENUM# interrupt, and sets the ENUM# Status Indicator for the Board Removal bit (HS_CSR[6]). The Host then logically removes the board and turns on the LED, at which time the board can be removed from the system.
9.2.2.1
Ejector Switch and Blue LED
A microswitch (switch), located in the Hot Swap CompactPCI board card-ejector mechanism, is used to signal impending board removal. This signal asserts ENUM#. When the switch is activated, it is necessary to wait for the LED to light, indicating it is now okay to remove the board. The PCI 9056 implements separate control logic for the microswitch and Blue LED in two different pins (CPCISW and LEDon#, respectively). When the ejector is opened or closed, the switch bounces for a time. The PCI 9056 uses internal debounce circuitry to clean the signal before the remainder of Hot Swap logic acknowledges it. The switch state is sampled six times, at 1 ms intervals, before it is determined to be closed or open. The Blue "Status" LED, located on the front of the Hot Swap CompactPCI board, is illuminated when it is permissible to remove a board. The hardware
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
9-3
Section 9--Hot Swap
Section 9 CompactPCI Hot Swap
Controlling Connection Processes
9.2.2.3
Hot Swap Control/Status Register (HS_CSR)
Hot Swap ID. Bits [7:0] (HS_CNTL[7:0]; PCI:48h, LOC:188h). These bits are set to a default value of 0x06. Next_Cap Pointer. Bits [15:8] (HS_NEXT[7:0]; PCI:49h, LOC:189h). These bits either point to the next New Capability structure, or are set to 0 if this is the last capability in the structure. Bits [9:8] are reserved and should be set to 0. Control. Bits [23:16] (HS_CSR[7:0]; PCI:4Ah, LOC:18Ah). This 8-bit control register is defined in the following table.
Table 9-1. Hot Swap Control
The PCI 9056 supports Hot Swap directly, as a control/status register is provided in Configuration space. This register is accessed through the PCI Extended Capabilities Pointer (ECP) mechanism. The Hot Swap Control/Status register (HS_CSR) provides status read-back for the Hot-Plug System Driver to determine which board is driving ENUM#. This register is also used to control the Hot Swap Status LED on the board front panel, and to de-assert ENUM#.
9.2.2.4
Hot Swap Capabilities Register
Bit
23
Description
ENUM# status--Insertion (1 = board is inserted). ENUM# status--Removal (1 = board is being removed). Programming Interface (PI = 0). LED state (1 = LED on, 0 = LED off). Not used. ENUM# interrupt enable (1 = de-assert, 0 = enable interrupt). Not used.
Register 9-1. Hot Swap Capabilities Register
31 24 23 Control 16 15 Next_Cap Pointer 8 7 0
22 21:20 19 18 17 16
Reserved
Hot Swap ID (06h)
9-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
10
10.1
PCI VITAL PRODUCT DATA (VPD)
OVERVIEW
F. Bit 31 (PVPDAD[15]; PCI:4Eh, LOC:18Eh). This bit sets a flag to indicate when a serial EEPROM data operation is complete. For Write cycles, the four bytes of data are first written into the VPD Data bits, after which the VPD Address is written at the same time the F flag is set to 1. The F flag clears when the serial EEPROM Data transfer completes. For Read cycles, the VPD Address is written at the same time the F flag is cleared to 0. The F flag is set when four bytes of data are read from the serial EEPROM. VPD Data. Bits [31:0] (PVPDATA[31:0]; PCI:50h, LOC:190h). The PVPDATA register is not a pure read/ write register. Data read into the register depends upon the last Read operation performed in PVPDAD[15]. VPD data is written or read through this register. The least-significant byte corresponds to the VPD byte at the address specified by the VPD Address register. Four bytes are always transferred between the register and the serial EEPROM.
Register 10-1. VPD Capabilities Register
31 F 30 16 15 Next_Cap Pointer (0h) VPD Data 8 7 VPD ID (03h) 0
The Vital Product Data (VPD) function in the PCI r2.2 defines a new location and access method. It also defines the Read Only and Read/Write bits. Currently Device ID, Vendor ID, Revision ID, Class Code, Subsystem ID, and Subsystem Vendor ID are required in the Configuration Space Header and are required for basic identification of the device and device configuration. Though this information allows a device to be configured, it is not sufficient to allow a device to be uniquely identified. With the addition of VPD, optional information is provided that allows a device to be uniquely identified and tracked. These additional bits enable current and/or future support tools and reduces the total cost of ownership of PCs and systems. This provides an alternate access method other than Expansion ROM for VPD. VPD is stored in an external serial EEPROM, which is accessed using the Configuration Space New Capabilities function. The VPD registers--PVPDCNTL, PVPD_NEXT, PVPDAD, and PVPDATA--are not accessible for reads from the Local Bus. It is recommended that the VPD function be exercised only from the PCI Bus.
VPD Address
10.1.1 VPD Capabilities Register
VPD ID. Bits [7:0] (PVPDCNTL[7:0]; PCI:4Ch, LOC:18Ch). The PCI SIG assigns these bits a value of 03h by. The VPD ID is hardwired. Next_Cap Pointer. Bits [15:8] (PVPD_NEXT[7:0]; PCI:4Dh, LOC:18Dh). These bits either point to the next New Capability structure, or are set to 0 if this is the last capability in the structure. Bits [9:8] are reserved and should be set to 0. The PCI 9056 defaults to 0x00. This value can be overwritten from the Local Bus. VPD Address. Bits [24:16] (PVPDAD[14:0]; PCI:4Eh, LOC:18Eh). These bits specify the byte address of the VPD to be accessed. All accesses are 32-bits wide; bits [17:16] must be set to 0, with the maximum serial EEPROM size being 4K bits. Bits [30:25] are ignored.
10.1.2
VPD Serial EEPROM Partitioning
To support VPD, the serial EEPROM is partitioned into read only and read/write sections.
10.1.3 Sequential Read Only
The first 736 bits, 92 bytes of the serial EEPROM contain read-only information. The read-only portion of the serial EEPROM is loaded into the PCI 9056, using a sequential Read protocol to the serial EEPROM and occurs after PCI reset. Sequential words are read by holding EECS asserted, following issuance of a serial EEPROM Read command.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
10-1
Section 10--rPD
Section 10 PCI Vital Product Data (VPD)
Overview
10.1.4 Random Read and Write
The PCI 9056 can read and write the read/write portion of serial EEPROM. The Serial EEPROM Starting at Lword Boundary for VPD Accesses bits (PROT_AREA[6:0]) designates this portion. This register is loaded upon power-on and can be written with a desired value starting at location 0. This provides the capability of writing the entire serial EEPROM. Writes to serial EEPROM are comprised of the following three commands: * Write Enable * Write Enable, followed by Write data * Write Disable This is done to ensure against accidental writes to the serial EEPROM. Random cycles allow VPD information to be written and read at any time.
To perform a simple VPD write to the serial EEPROM, the following steps are necessary: 1. Change the write-protected serial EEPROM address in PROT_AREA[6:0] to the desired address. 0x0000000 makes the serial EEPROM removable from the beginning. 2. Write desired data into the PVPDATA register. 3. Write destination serial EEPROM address and flag of operation, value of 1. 4. Probe a flag of operation until it changes to a 0 to ensure the write completes. To perform a simple VPD read from serial EEPROM, the following steps are necessary: 1. Write a destination serial EEPROM address and flag of operation, value of 0. 2. Probe a flag of operation until it changes to a 1 to ensure the Read data is available. 3. Read back the PVPDATA register to see the requested data.
10-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
11
11.1
REGISTERS
SUMMARY OF NEW REGISTERS
This section summarizes the new registers, as compared to the PCI 9054. Refer to the following sections for a full explanation of each register.
Table 11-1. Summary of New Registers (as Compared to the PCI 9054)
Register
PCI Status Hot Swap Control Local Miscellaneous Control 1
Bits
5 7 3 7 0 1 66 MHz-Capable.
Description
Board Insertion ENUM# Status Indicator. Direct Master (PCI Initiator) Write FIFO Flush during PCI Master Abort. Disconnect with Flush Read FIFO. READY# Timeout Enable. READY# Timeout Select. Direct Slave Write Delay. Direct Slave Write FIFO Full Condition. Reserved.
06h 4Ah 0Dh
06h 18Ah 8Dh
0Fh
8Fh
Local Miscellaneous Control 2
4:2 5 7:6
28h
A8h
PCI Base Address (Remap) Register for Direct Master-to-PCI Memory
12, 3
Direct Master Read Prefetch Size Control.
0 1 100h 1A0h PCI Arbiter Control 2 3 31:4 104h 68h 1A4h E8h PCI Abort Address Interrupt Control/Status 31:0 0 20 Serial EEPROM Control, PCI Command Codes, User I/O Control, and Init Control 21 23:22 30 31 19 80h 100h DMA Channel 0 Mode 20 21 31:22
PCI Arbiter Enable. PCI 9056 High Priority. Early Grant Release. PCI Arbiter Parking on PCI 9056. Reserved. PCI Abort Address. Enable Local Bus TEA#/LSERR#. LINTo# Interrupt Status. TEA#/LSERR# Interrupt Status. Reserved. PCI Adapter Software Reset when HOSTEN#=1 and PCI Host Software Reset when HOSTEN#=0. EEDO Input Enable. EOT# End Link. Valid Mode Enable. Valid Stop Control. Reserved.
6Ch
ECh
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-1
Section 11--Registers
PCI Offset
Local Offset
Section 11 Registers
Summary of New Registers
Table 11-1. Summary of New Registers (as Compared to the PCI 9054) (Continued)
PCI Offset
84h (when DMAMODE0[20]=0) 88h (when DMAMODE0[20]=1) 88h (when DMAMODE0[20]=0) 8Ch (when DMAMODE0[20]=1) 8Ch (when DMAMODE0[20]=0) 84h (when DMAMODE0[20]=1)
Local Offset
104h (when DMAMODE0[20]=0) 108h (when DMAMODE0[20]=1) 108h (when DMAMODE0[20]=0) 10Ch (when DMAMODE0[20]=1) 10Ch (when DMAMODE0[20]=0) 104h (when DMAMODE0[20]=1)
Register
DMA Channel 0 PCI Address
Bits
Description
31:0
PCI Address Register.
DMA Channel 0 Local Address
31:0
Local Address Register.
30:23 DMA Channel 0 Transfer Size (Bytes) 31 12 19
Reserved. Valid. Demand Mode. EOT# End Link. Valid Mode Enable. Valid Stop Control. Reserved.
94h
114h
DMA Channel 1 Mode
20 21 31:22
98h (when DMAMODE1[20]=0) 9Ch (when DMAMODE1[20]=1) 9Ch (when DMAMODE1[20]=0) A0h (when DMAMODE1[20]=1) A0h (when DMAMODE1[20]=0) 98h (when DMAMODE1[20]=1)
118h (when DMAMODE1[20]=0) 11Ch (when DMAMODE1[20]=1) 11Ch (when DMAMODE1[20]=0) 120h (when DMAMODE1[20]=1) 120h (when DMAMODE1[20]=0) 118h (when DMAMODE1[20]=1)
DMA Channel 1 PCI Address
31:0
PCI Address Register.
DMA Channel 1 Local Address
31:0
Local Address Register.
30:23 DMA Channel 1 Transfer Size (Bytes) 31 19:16
Reserved. Valid. DMA Channel 1 PCI-to-Local Almost Full (C1PLAF). DMA Channel 1 Local-to-PCI Almost Empty (C1LPAE). DMA Channel 1 Local-to-PCI Almost Full (C1LPAF). DMA Channel 1 PCI-to-Local Almost Empty (C1PLAE).
B0h
130h
DMA Threshold
23:20 27:24 31:28
11-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Register Address Mapping
Section 11 Registers
11.2
REGISTER ADDRESS MAPPING
11.2.1 PCI Configuration Registers
Table 11-2. PCI Configuration Registers
Local Access (Offset from Chip Select Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h BIST To ensure software compatibility with other versions of the PCI 9056 family and to ensure compatibility with future enhancements, write 0 to all unused bits.
31
30
24 Status
23
16
15
8
7
0
00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h
Device ID
Vendor ID Command
N Y N Y [7:0] Y Y Y Y
Y N Y [31:8] N N N N N
Class Code Header Type PCI Bus Latency Timer
Revision ID Cache Line Size
PCI Base Address 0; used for Memory-Mapped Configuration Registers (PCIBAR0) PCI Base Address 1; used for I/O-Mapped Configuration Registers (PCIBAR1) PCI Base Address 2; used for Local Address Space 0 (PCIBAR2) PCI Base Address 3; used for Local Address Space 1 (PCIBAR3) Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of these table entries. Cardbus CIS Pointer (Not supported) Subsystem ID Subsystem Vendor ID New Capability Pointer PCI Base Address for Local Expansion ROM Reserved Reserved
N N Y N, Local [7:0] N Y [7:0], Local [31:0] N, Local [31:8] Y [15, 12:8, 1:0] Y [23:16], Local [15:0] Y [31:16], Local [15:8] Y
N Y N N N Y [31:8]
3Ch
3Ch
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
40h
180h
Power Management Capabilities PMCSR Bridge Support Extensions Control/Status Register
Next_Cap Pointer
Capability ID
N
44h
184h
Data
Power Management Control/Status Register
N
48h
188h
Reserved
Next_Cap Pointer Next_Cap Pointer
Capability ID
Y [15:0]
4Ch 50h
18Ch 190h
F
VPD Address VPD Data
Capability ID
N N
Note: Refer to PCI r2.2 for definitions of these registers.
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-3
Section 11--Registers
PCI Configuration Register Address
PCI/ Local Writable
Serial EEPROM Writable
Section 11 Registers
Register Address Mapping
11.2.2 Local Configuration Registers
Table 11-3. Local Configuration Registers
Local Access (Offset from Chip Select Address) 80h 84h 88h Local Miscellaneous Control 2 To ensure software compatibility with other versions of the PCI 9056 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 24 23 16 15 8 7 0 PCI/Local Writable Y Y Y
PCI (Offset from Base Address) 00h 04h 08h
Serial EEPROM Writable Y Y Y
Range for PCI-to-Local Address Space 0 Local Base Address (Remap) for PCI-to-Local Address Space 0 Mode/DMA Arbitration Serial EEPROM Write-Protecte d Address Boundary Local Miscellaneous Control 1
0Ch
8Ch
Big/Little Endian Descriptor
Y
Y
10h 14h 18h 1Ch 20h 24h 28h 2Ch F0h F4h F8h FCh 100h 104h
90h 94h 98h 9Ch A0h A4h A8h ACh 170h 174h 178h 17Ch 1A0h 1A4h
Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM and BREQo Control Local Bus Region Descriptors (Space 0 and Expansion ROM) for PCI-to-Local Accesses Range for Direct Master-to-PCI Local Base Address for Direct Master-to-PCI Memory Local Base Address for Direct Master-to-PCI I/O Configuration PCI Base Address (Remap) for Direct Master-to-PCI PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration Range for PCI-to-Local Address Space 1 Local Base Address (Remap) for PCI-to-Local Address Space 1 Local Bus Region Descriptor (Space 1) for PCI-to-Local Accesses PCI Base Dual Address Cycle (Remap) for Direct Master-to-PCI (Upper 32 bits) Reserved PCI Abort Address PCI Arbiter Control
Y Y Y Y Y Y Y Y Y Y Y Y Y N
Y Y Y Y Y Y Y Y Y Y Y N Y N
11-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Register Address Mapping
Section 11 Registers
11.2.3 Runtime Registers
Table 11-4. Runtime Registers
Local Access (Offset from Chip Select Address) C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h C0h C4h To ensure software compatibility with other versions of the PCI 9056 family and to ensure compatibility with future enhancements, write 0 to all unused bits. Serial EEPROM Writable Y Y N N N N N N N N N N N N N N
PCI (Offset from Base Address) 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch
31
16
15
0
PCI/Local Writable Y Y Y Y Y Y Y Y Y Y Y Y N N Y Y
Mailbox Register 0 (refer to Note) Mailbox Register 1 (refer to Note) Mailbox Register 2 Mailbox Register 3 Mailbox Register 4 Mailbox Register 5 Mailbox Register 6 Mailbox Register 7 PCI-to-Local Doorbell Register Local-to-PCI Doorbell Register Interrupt Control/Status Serial EEPROM Control, PCI Command Codes, User I/O Control, and Init Control Device ID Unused Vendor ID Revision ID Mailbox Register (refer to Note) Mailbox Register (refer to Note)
Note: MBOX0 and MBOX1 are always accessible at addresses 78h/C0h and 7Ch/C4h, respectively. When the I2O function is disabled (QSR[0]=0), MBOX0 and MBOX1 are also accessible at PCI addresses 40h and 44h for PCI 9060 compatibility. When the I2O function is enabled, the Inbound and Outbound Queue pointers are accessed at addresses 40h and 44h, replacing MBOX0 and MBOX1 in PCI Address space.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-5
Section 11--Registers
Section 11 Registers
Register Address Mapping
11.2.4 DMA Registers
Table 11-5. DMA Registers
Local Access (Offset from Chip Select Address) 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h 138h To ensure software compatibility with other versions of the PCI 9056 family and to ensure compatibility with future enhancements, write 0 to all unused bits. Serial EEPROM Writable N N N N N N N N N N N N N N N
PCI (Offset from Base Address) 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h
31
16
15
8
7
0
PCI/Local Writable Y Y Y Y Y Y Y Y Y Y
DMA Channel 0 Mode DMA Channel 0 PCI Address DMA Channel 0 Local Address DMA Channel 0 Transfer Byte Count DMA Channel 0 Descriptor Pointer DMA Channel 1 Mode DMA Channel 1 PCI Address DMA Channel 1 Local Address DMA Channel 1 Transfer Byte Count DMA Channel 1 Descriptor Pointer Reserved DMA Channel 1 Command/ Status Mode/DMA Arbitration DMA Threshold DMA Channel 0 PCI Dual Address Cycle (Upper 32 bits) DMA Channel 1 PCI Dual Address Cycle (Upper 32 bits) DMA Channel 0 Command/ Status
Y Y Y Y Y
11-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Register Address Mapping
Section 11 Registers
11.2.5 Messaging Queue Registers
Table 11-6. Messaging Queue Registers
Local Access (Offset from Chip Select Address) B0h B4h -- -- 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h To ensure software compatibility with other versions of the PCI 9056 family and to ensure compatibility with future enhancements, write 0 to all unused bits. Serial EEPROM Writable N N N N N N N N N N N N N N N
PCI (Offset from Base Address) 30h 34h 40h 44h C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h
31 Outbound Post Queue Interrupt Status Outbound Post Queue Interrupt Mask Inbound Queue Port Outbound Queue Port Messaging Unit Configuration Queue Base Address Inbound Free Head Pointer Inbound Free Tail Pointer Inbound Post Head Pointer Inbound Post Tail Pointer Outbound Free Head Pointer Outbound Free Tail Pointer Outbound Post Head Pointer Outbound Post Tail Pointer Queue Status/Control
0
PCI/Local Writable N Y PCI PCI Y Y Y Y Y Y Y Y Y Y Y
Notes: When I2O messaging is enabled (QSR[0]= 1), the PCI Master (Host or another IOP) uses the Inbound Queue Port to read Message Frame Addresses (MFAs) from the Inbound Free List FIFO and to write MFAs to the Inbound Post Queue FIFO. The Outbound Queue Port reads MFAs from the Outbound Post Queue FIFO and writes MFAs to the Outbound Free List FIFO. Each Inbound MFA is specified by I2O as an offset from the PCI Base Address 0 (programmed in PCIBAR0) to the start of the message frame. This means that all inbound message frames should reside in PCI Base Address 0 Memory space. Each Outbound MFA is specified by I2O as an offset from system address 0x00000000h. Outbound MFA is a physical 32-bit address of the frame in shared PCI system memory. The Inbound and Outbound Queues may reside in Local Address Space 0 or Space 1 by programming QSR. The queues need not be in shared memory.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-7
Section 11--Registers
Section 11 Registers
PCI Configuration Registers
11.3
PCI CONFIGURATION REGISTERS
All registers may be written to or read from in Byte, Word, or Lword accesses.
Register 11-1. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID
Bit
15:0
Description
Vendor ID. Identifies manufacturer of device. Defaults to the PCI SIG-issued Vendor ID of PLX (10B5h) if blank or if no serial EEPROM is present. Device ID. Identifies particular device. Defaults to PLX part number for PCI interface chip (9056h) if blank or no serial EEPROM is present.
Read
Yes
Write
Local/ Serial EEPROM Local/ Serial EEPROM
Value after Reset
10B5h or 0 9056h or 0
31:16
Yes
Register 11-2. (PCICR; PCI:04h, LOC:04h) PCI Command
Bit
0
Description
I/O Space. Writing a 1 allows the device to respond to I/O space accesses. Writing a 0 disables the device from responding to I/O space accesses. Memory Space. Writing a 1 allows the device to respond to Memory Space accesses. Writing a 0 disables the device from responding to Memory Space accesses. Master Enable. Writing a 1 allows device to behave as a Bus Master. Writing a 0 disables device from generating Bus Master accesses. Special Cycle. Not supported. Memory Write and Invalidate Enable. Writing a 1 enables the Memory Write and Invalidate mode for Direct Master and DMA. (Refer to the DMA Mode register(s), DMAMODE0[13] and/or DMAMODE1[13].) VGA Palette Snoop. Not supported. Parity Error Response. Writing a 0 indicates parity error is ignored and the operation continues. Writing a 1 indicates parity checking is enabled. Wait Cycle Control. Controls whether a device does address/data stepping. Writing a 0 indicates the device never does stepping. Writing a 1 indicates the device always does stepping. Note: Hardwired to 0. SERR# Enable. Writing a 1 enables SERR# driver. Writing a 0 disables SERR# driver. Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers a Master can perform on the bus. Writing a 1 indicates fast back-to-back transfers can occur to any agent on the bus. Writing a 0 indicates fast back-to-back transfers can only occur to the same agent as in the previous cycle. Note: Hardwired to 0. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
1
Yes
Yes
0
2 3 4 5 6
Yes Yes Yes Yes Yes
Yes No Yes No Yes
0 0 0 0 0
7
Yes
No
0
8
Yes
Yes
0
9
Yes
No
0
15:10
Yes
No
0h
11-8
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 11 Registers
Register 11-3. (PCISR; PCI:06h, LOC:06h) PCI Status
Bit
3:0 Reserved. New Capability Functions Support. Writing a 1 supports New Capabilities Functions. If enabled, the first New Capability Function ID is located at PCI Configuration offset [40h]. Can be written only from the Local Bus. Read-only from the PCI Bus. 66 MHz-Capable. If set to 1, this device supports a 66 MHz PCI clock environment. User Definable Functions. If set to 1, this device supports user definable functions. Can be written only from the Local Bus. Read-only from the PCI Bus. Fast Back-to-Back Capable. Writing a 1 indicates an adapter can accept fast back-to-back transactions. Note: Hardwired to 1. Master Data Parity Error Detected. Set to 1 when three conditions are met: 1) PCI 9056 asserted PERR# or acknowledged PERR# asserted; 2) PCI 9056 was Bus Master for operation in which error occurred; 3) Parity Error Response bit is set (PCICR[6]=1). Writing a 1 clears this bit to 0. DEVSEL# Timing. Indicates timing for DEVSEL# assertion. Writing a 01 sets this bit to medium. Note: Hardwired to 01. 11 12 13 14 Target Abort. When set to 1, indicates the PCI 9056 has signaled a Target Abort. Writing a 1 clears this bit to 0. Received Target Abort. When set to 1, indicates the PCI 9056 has received a Target Abort signal. Writing a 1 clears this bit to 0. Received Master Abort. When set to 1, indicates the PCI 9056 has received a Master Abort signal. Writing a 1 clears this bit to 0. Signaled System Error. When set to 1, indicates the PCI 9056 has reported a system error on SERR#. Writing a 1 clears this bit to 0. Detected Parity Error. When set to 1, indicates the PCI 9056 has detected a PCI Bus parity error, even if parity error handling is disabled (the Parity Error Response bit in the Command register is clear). One of three conditions can cause this bit to be set: 1) PCI 9056 detected parity error during PCI Address phase; 2) PCI 9056 detected data parity error when it is the target of a write; 3) PCI 9056 detected data parity error when performing Master Read operation. Writing a 1 clears this bit to 0. Yes Yes Yes Yes Yes/Clr Yes/Clr Yes/Clr Yes/Clr 0 0 0 0
Description
Read
Yes
Write
No
Value after Reset
0h
4
Yes
Local
1
5 6
Yes Yes
Local Local
1 0
7
Yes
No
1
8
Yes
Yes/Clr
0
10:9
Yes
No
01
15
Yes
Yes/Clr
0
Register 11-4. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID
Bit
7:0
Description
Revision ID. Silicon revision of the PCI 9056.
Read
Yes
Write
Local/ Serial EEPROM
Value after Reset
Current Rev # (AA)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-9
Section 11--Registers
Section 11 Registers
PCI Configuration Registers
Register 11-5. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code
Bit
7:0
Description
Register Level Programming Interface. None defined.
Read
Yes
Write
Local/ Serial EEPROM Local/ Serial EEPROM Local/ Serial EEPROM
Value after Reset
0h
15:8
Subclass Code (Other Bridge Device).
Yes
80h
23:16
Base Class Code (Bridge Device).
Yes
06h
Register 11-6. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size
Bit
7:0
Description
System Cache Line Size. Specified in units of 32-bit words (8 or 16 Lwords). If a size other than 8 or 16 is specified, the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers.
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-7. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Bus Latency Timer
Bit
7:0
Description
PCI Bus Latency Timer. Specifies amount of time (in units of PCI Bus clocks) the PCI 9056, as a Bus Master, can burst data on the PCI Bus.
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-8. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type
Bit
6:0
Description
Configuration Layout Type. Specifies layout of bits 10h through 3Fh in configuration space. Only one encoding, 0h, is defined. All other encodings are reserved. Header Type. Writing a 1 indicates multiple functions. Writing a 0 indicates single function.
Read
Yes
Write
Local
Value after Reset
0h
7
Yes
Local
0
11-10
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 11 Registers
Register 11-9. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST)
Bit
3:0 5:4
Description
BIST Pass/Fail. Writing 0h indicates a device passed its test. Non-0h values indicate a device failed its test. Device-specific failure codes can be encoded in a non-0h value. Reserved. PCI BIST Interrupt Enable. The PCI Bus writes 1 to enable BIST. Generates an interrupt to the Local Bus. The Local Bus resets this bit when BIST is complete. The software should fail device if BIST is not complete after two seconds. Refer to the Runtime registers for Interrupt Control/Status. BIST Support. Returns 1 if device supports BIST. Returns 0 if device is not BIST-compatible.
Read
Yes Yes
Write
Local No
Value after Reset
0h 00
6
Yes
Yes
0
7
Yes
Local
0
Register 11-10. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime, and DMA
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. Note: Hardwired to 0. Register Location. Values: 00--Locate anywhere in 32-bit Memory Address space 01--PCI r2.1: Locate below 1-MB Memory Address space PCI r2.2: Reserved 10--Locate anywhere in 32-bit Memory Address space 11--Reserved Note: Hardwired to 00. Prefetchable. Writing a 1 indicates there are no side effects on reads. Does not affect operation of the PCI 9056. Note: Hardwired to 0. Memory Base Address. Memory base address for access to Local, Runtime, and DMA registers (requires 256 bytes). Note: Hardwired to 0h. Memory Base Address. Memory base address for access to Local, Runtime, and DMA registers.
Read
Yes
Write
No
Value after Reset
0
2:1
Yes
No
00
3
Yes
No
0
7:4
Yes
No
0h
31:8
Yes
Yes
0h
Note: For I2O, Inbound message frame pool must reside in address space pointed to by PCIBAR0. Message Frame Address (MFA) is defined by I2O as offset from this base address to start of message frame.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-11
Section 11--Registers
Section 11 Registers
PCI Configuration Registers
Register 11-11. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and DMA
Bit
0 1 7:2
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. Note: Hardwired to 1. Reserved. I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA registers (requires 256 bytes). Note: Hardwired to 0h. I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA registers. PCIBAR1 can be enabled or disabled by setting or clearing the Base Address Register 1 Enable bit (LMISC1[0]).
Read
Yes Yes Yes
Write
No No No
Value after Reset
1 0 0h
31:8
Yes
Yes
0h
Register 11-12. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in LAS0RR register.) Register Location (If Memory Space). Values: 00--Locate anywhere in 32-bit Memory Address space 01--PCI r2.1: Locate below 1-MB Memory Address space PCI r2.2: Reserved 10--Locate anywhere in 32-bit Memory Address space 11--Reserved (Specified in LAS0RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS0RR[3] and provides only status to the system. Does not affect operation of the PCI 9056. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in LAS0RR register.) If I/O Space, bit 3 is included in the base address. Memory Base Address. Memory base address for access to Local Address Space 0. PCIBAR2 can be enabled or disabled by setting or clearing the Space 0 Enable bit (LAS0BA[0]).
Read
Yes
Write
No
Value after Reset
0
Mem: No Yes I/O: bit 1 no, bit 2 yes 00
2:1
3
Yes
Mem: No I/O: Yes
0
31:4
Yes
Yes
0h
11-12
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 11 Registers
Register 11-13. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in LAS1RR register.) Register Location. Values: 00--Locate anywhere in 32-bit Memory Address space 01--PCI r2.1: Locate below 1-MB Memory Address space PCI r2.2: Reserved 10--Locate anywhere in 32-bit Memory Address space 11--Reserved (Specified in LAS1RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS1RR[3] and only provides status to the system. Does not affect operation of the PCI 9056. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in LAS1RR register.) If I/O Space, bit 3 is included in base address. Memory Base Address. Memory base address for access to Local Address Space 1. PCIBAR3 can be enabled or disabled by setting or clearing the Space 1 Enable bit (LAS1BA[0]). If QSR[0]=1, PCIBAR3 returns 0h.
Read
Yes
Write
No
Value after Reset
0
Mem: No Yes I/O: Bit 1 No, Bit 2 Yes 00
2:1
3
Yes
Mem: No I/O: Yes
0
31:4
Yes
Yes
0h
Register 11-14. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address
Bit
31:0 Reserved.
Description
Read
Yes
Write
No
Value after Reset
0h
Register 11-15. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address
Bit
31:0 Reserved.
Description
Read
Yes
Write
No
Value after Reset
0h
Register 11-16. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer
Bit
31:0
Description
Cardbus Information Structure Pointer for PCMCIA. Not supported.
Read
Yes
Write
No
Value after Reset
0h
Register 11-17. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID
Bit
15:0
Description
Subsystem Vendor ID (unique add-in board Vendor ID).
Read
Yes
Write
Local/ Serial EEPROM
Value after Reset
10B5h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-13
Section 11--Registers
Section 11 Registers
PCI Configuration Registers
Register 11-18. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID
Bit
15:0
Description
Subsystem ID (unique add-in board Device ID).
Read
Yes
Write
Local/ Serial EEPROM
Value after Reset
9056h
Register 11-19. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base
Bit Description
Address Decode Enable. Writing a 1 indicates a device accepts accesses to the Expansion ROM address. Writing a 0 indicates a device does not accept accesses to Expansion ROM space. Should be set to 0 if there is no Expansion ROM. Works in conjunction with EROMRR[0]. Reserved. Expansion ROM Base Address (upper 21 bits).
Read
Write
Value after Reset
0
Yes
Yes
0
10:1 31:11
Yes Yes
No Yes
0h 0h
Register 11-20. (CAP_PTR; PCI:34h, LOC:34h) New Capability Pointer
Bit
1:0 7:2 31:8 Reserved. Must be set to 0. New Capability Pointer. Offset into PCI Configuration Space for the location of the first item in the New Capabilities Linked List. Reserved.
Description
Read
Yes Yes Yes
Write
No Local No
Value after Reset
00 40h 0h
Register 11-21. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line
Bit
7:0
Description
Interrupt Line Routing Value. Value indicates which input of the system interrupt controller(s) is connected to each interrupt line of the device.
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-22. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin
Bit Description
Interrupt Pin Register. Indicates which interrupt pin the device uses. The following values are decoded (the PCI 9056 supports only INTA#): 0 = No Interrupt pin 1 = INTA# 2 = INTB# 3 = INTC# 4 = INTD#
Read
Write
Value after Reset
7:0
Yes
Local/ Serial EEPROM
1h
11-14
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 11 Registers
Register 11-23. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt
Bit
7:0
Description
Min_Gnt. Specifies how long a burst period device needs, assuming a clock rate of 33 MHz. Value is a multiple of 1/4 s increments.
Read
Yes
Write
Local/ Serial EEPROM
Value after Reset
0h
Bit
7:0
Description
Max_Lat. Specifies how often the device must gain access to the PCI Bus. Value is a multiple of 1/4 s increments.
Read
Yes
Write
Local/ Serial EEPROM
Value after Reset
0h
Register 11-25. (PMCAPID; PCI:40h, LOC:180h) Power Management Capability ID
Bit
7:0
Description
Power Management Capability ID.
Read
Yes
Write
No
Value after Reset
1h
Register 11-26. (PMNEXT; PCI:41h, LOC:181h) Power Management Next Capability Pointer
Bit
1:0 7:2 Reserved. Must be set to 0. Next_Cap Pointer. Points to the first location of the next item in the capabilities linked list. If Power Management is the last item in the list, then this register should be set to 0.
Description
Read
Yes Yes
Write
No Local
Value after Reset
00 48h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-15
Section 11--Registers
Register 11-24. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat
Section 11 Registers
PCI Configuration Registers
Register 11-27. (PMC; PCI:42h, LOC:182h) Power Management Capabilities
Bit
2:0
Description
Version. Writing a 1h indicates this function complies with PCI Power Mgmt. r1.1. PCI Clock Required for PME# Signal. When set to 1, indicates a function relies on the presence of the PCI clock for PME# operation. The PCI 9056 does not require the PCI clock for PME#, so this bit should be set to 0. Reserved. DSI. When set to 1, the PCI 9056 requires special initialization following a transition to a D0 uninitialized state before a generic class device driver is able to use it. AUX_Current. Supported by way of the PMDATA register per PCI Power Mgmt. r1.1. D1_Support. When set to 1, the PCI 9056 supports the D1 power state. D2_Support. When set to 1, the PCI 9056 supports the D2 power state. PME_Support. Indicates power states in which the PCI 9056 may assert PME#. Value Description XXXX1 PME# can be asserted from D0 XXX1X PME# can be asserted from D1 XX1XX PME# can be asserted from D2 X1XXX PME# can be asserted from D3hot 1XXXX PME# can be asserted from D3cold
Read
Yes
Write
Local
Value after Reset
001
3 4 5
Yes Yes Yes
Local No Local
0 0 0
8:6 9 10
Yes Yes Yes
No Local Local
000 0 0
15:11
Yes
Local
0h
11-16
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 11 Registers
Register 11-28. (PMCSR; PCI:44h, LOC:184h) Power Management Control/Status
Bit Description
Power State. Determines or changes the current power state. State Value 00 D0 01 D1 10 D2 11 D3hot Transition from a D3hot state to a D0 state causes a soft reset. Should only be initiated from the PCI Bus because the Local Bus interface is reset during a soft reset. In a D3hot state, PCI Memory and I/O accesses are disabled, as well as PCI interrupts, and only configuration access is allowed. The same is true for the D2 state if the corresponding D2_Support pin is set. 7:2 8 12:9 Reserved. PME_En. Writing a 1 enables PME# to be asserted. Data_Select. Selects which data to report through the Data register and Data_Scale bits. Data_Scale. Indicates the scaling factor to use when interpreting the value of the Data register. Value and meaning of these bits depends on the data value selected by the Data_Select bit. When the Local CPU initializes the Data_Scale values, must use the Data_Select bit to determine which Data_Scale value it is writing. For Power Consumed and Power Dissipated data, the following scale factors are used. Unit values are in watts. Value Scale 0 Unknown 1 0.1x 2 0.01x 3 0.001x PME_Status. Indicates PME# is being driven if the PME_En bit is set (PMCSR[8]=1). Writing a 1 from the Local Bus sets this bit; writing a 1 from the PCI Bus clears this bit to 0. Depending on the current power state, set only if the appropriate PME_Support bit(s) is set (PMC[15:11]=1). Yes Yes Yes No Yes Yes 0h 0 0h
Read
Write
Value after Reset
1:0
Yes
Yes
00
14:13
Yes
Local
00
15
Yes
Local/ Set, PCI/Clr
0
Register 11-29. (PMCSR_BSE; PCI:46h, LOC:186h) PMCSR Bridge Support Extensions
Bit
7:0 Reserved.
Description
Read
Yes
Write
No
Value after Reset
0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-17
Section 11--Registers
Section 11 Registers
PCI Configuration Registers
Register 11-30. (PMDATA; PCI:47h, LOC:187h) Power Management Data
Bit Description
Power Management Data. Provides operating data, such as power consumed or heat dissipation. Data returned is selected by the Data_Select bit(s) (PMCSR[12:9]) and scaled by the Data_Scale bit(s) (PMCSR[14:13]). Description Data_Select 0 D0 Power Consumed 1 D1 Power Consumed 2 D2 Power Consumed 3 D3 Power Consumed 4 D0 Power Dissipated 5 D1 Power Dissipated 6 D2 Power Dissipated 7 D3 Power Dissipated
Read
Write
Value after Reset
7:0
Yes
Local
0h
Register 11-31. (HS_CNTL; PCI:48h, LOC:188h) Hot Swap Control
Bit
7:0 Hot Swap ID.
Description
Read
Yes
Write
Local/ Serial EEPROM
Value after Reset
06h
Register 11-32. (HS_NEXT; PCI:49h, LOC:189h) Hot Swap Next Capability Pointer
Bit
1:0 7:2 Reserved. Must be set to 0. Next_Cap Pointer. Points to the first location of the next item in the capabilities linked list. If Hot Swap is the last item in the list, then this register should be set to 0.
Description
Read
Yes Yes
Write
No Local/ Serial EEPROM
Value after Reset
00 4Ch
Register 11-33. (HS_CSR; PCI:4Ah, LOC:18Ah) Hot Swap Control/Status
Bit
0 1 2 3 5:4 6 7 15:8 Reserved. ENUM# Interrupt Clear. Writing a 0 enables the interrupt. Writing a 1 clears the interrupt. Reserved. LED Software On/Off Switch. Writing a 1 turns on the LED. Writing a 0 turns off the LED. Programming Interface. Board Removal ENUM# Status Indicator. Writing a 1 reports the ENUM# assertion for removal process. Board Insertion ENUM# Status Indicator. Writing a 1 reports the ENUM# assertion for insertion process. Reserved.
Description
Read
Yes Yes Yes Yes Yes Yes Yes Yes
Write
No Yes/Clr No PCI No Yes Yes No
Value after Reset
0 0 0 0 00 0 0 0h
11-18
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 11 Registers
Register 11-34. (PVPDCNTL; PCI:4Ch, LOC:18Ch) PCI Vital Product Data Control
Bit
7:0
Description
VPD ID. Capability ID = 03h for VPD.
Read
PCI
Write
No
Value after Reset
03h
Register 11-35. (PVPD_NEXT; PCI:4Dh, LOC:18Dh) PCI Vital Product Data Next Capability Pointer
Bit
1:0 7:2 Reserved. Must be set to 0. Next_Cap Pointer. Points to first location of next item in the capabilities linked list. VPD is the last item in the capabilities linked list. This register is set to 0h.
Description
Read
Yes PCI
Write
No Local
00 0h
Register 11-36. (PVPDAD; PCI:4Eh, LOC:18Eh) PCI Vital Product Data Address
Bit
14:0
Description
VPD Address. Byte address of the VPD address to be accessed. Supports a 2K or 4K bit serial EEPROM. Bits [1:0] must be set to 0. F. Flag used to indicate when the transfer of data between PVPDATA and the storage component is complete. Writing a 0 along with the VPD address causes a read of VPD information into PVPDATA. The hardware sets this bit to 1 when the VPD Data transfer is complete. Writing a 1 along with the VPD address causes a write of VPD information from PVPDATA into a storage component. The hardware sets this bit to 0 after the Write operation is complete.
Read
PCI
Write
Yes
Value after Reset
0h
15
PCI
Yes
0
Register 11-37. (PVPDATA; PCI:50h, LOC:190h) PCI VPD Data
Bit
31:0 VPD Data.
Description
Read
PCI
Write
Yes
Value after Reset
0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-19
Section 11--Registers
Value after Reset
Section 11 Registers
Local Configuration Registers
11.4
LOCAL CONFIGURATION REGISTERS
Register 11-38. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates Local Address Space 0 maps into PCI Memory space. Writing a 1 indicates Local Address Space 0 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: 2/1 Meaning 00 Locate anywhere in 32-bit PCI Address space 01 PCI r2.1: Locate below 1-MB Memory Address space PCI r2.2: Reserved 10 Locate anywhere in 32-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0.Bit 2 is included with bits [31:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect operation of the PCI 9056, but is used for system status). When mapped into I/O space, it is included with bits [31:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 0. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others (used in conjunction with PCIBAR2). Default is 1 MB. Notes: Range (not Range register) must be power of 2. "Range register value" is 2's complement of range. User should limit all I/O spaces to 256 bytes per PCI r2.2.
Read
Yes
Write
Yes
Value after Reset
0
2:1
Yes
Yes
00
3
Yes
Yes
0
31:4
Yes
Yes
FFF0000h
Register 11-39. (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap)
Bit
0 1 3:2
Description
Space 0 Enable. Writing a 1 enables decoding of PCI addresses for Direct Slave access to Local Bus Space 0. Writing a 0 disables decoding. Reserved. If Local Bus Space 0 is mapped into Memory space, bits are not used. When mapped into I/O space, included with bits [31:4] for remapping. Remap PCI Address to Local Address Space 0 into Local Address Space. Bits in this register remap (replace) PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register).
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
0 0 00
31:4
Yes
Yes
0h
11-20
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 11 Registers
Register 11-40. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/DMA Arbitration
Bit
7:0
Description
Local Bus Latency Timer. Number of Local Bus clock cycles to occur before de-asserting HOLD and releasing the Local Bus. Local Bus Pause Timer. Number of Local Bus Clock cycles to occur before reasserting HOLD after releasing the Local Bus. The pause timer is valid only during DMA. Local Bus Latency Timer Enable. Writing a 1 enables the latency timer. Writing a 0 disables the latency timer. Local Bus Pause Timer Enable. Writing a 1 enables the pause timer. Writing a 0 disables the pause timer. Local Bus BREQ Enable. Writing a 1 enables the Local Bus BR#/BREQi. When BR#/BREQi is active, the PCI 9056 de-asserts HOLD and releases the Local Bus. DMA Channel Priority. Writing a 00 indicates a rotational priority scheme. Writing a 01 indicates Channel 0 has priority. Writing a 10 indicates Channel 1 has priority. Writing an 11 indicates reserved. Local Bus Direct Slave Release Bus Mode. When set to 1, the PCI 9056 de-asserts HOLD and releases the Local Bus when the Direct Slave Write FIFO becomes empty during a Direct Slave Write or when the Direct Slave Read FIFO becomes full during a Direct Slave Read. Direct Slave LOCK# Enable. Writing a 1 enables Direct Slave locked sequences. Writing a 0 disables Direct Slave locked sequences. PCI Request Mode. Writing a 1 causes the PCI 9056 to de-assert REQ# when it asserts FRAME during a Master cycle. Writing a 0 causes the PCI 9056 to leave REQ# asserted for the entire Bus Master cycle. Delayed Read Mode. When set to 1, the PCI 9056 operates in Delayed Transaction mode for Direct Slave reads. The PCI 9056 issues a Retry to the PCI Host and prefetches Read data. PCI Read No Write Mode. Writing a 1 forces a Retry on writes if a read is pending. Writing a 0 allows writes to occur while a read is pending. PCI Read with Write Flush Mode. Writing a 1 submits a request to flush a pending Read cycle if a Write cycle is detected. Writing a 0 submits a request to not effect pending reads when a Write cycle occurs (PCI r2.2-compatible). Gate Local Bus Latency Timer with BREQi (C and J modes only). PCI Read No Flush Mode. Writing a 1 submits a request to not flush the Read FIFO if the PCI Read cycle completes (Read Ahead mode). Writing a 0 submits a request to flush the Read FIFO if a PCI Read cycle completes. When set to 0, reads from the PCI Configuration Register address 00h returns Device ID and Vendor ID. When set to 1, reads from the PCI Configuration register address 00h returns Subsystem ID and Subsystem Vendor ID. FIFO Full Status Flag. When set to 1, the Direct Master Write FIFO is almost full. Reflects the value of the DMPAF pin. BIGEND#/WAIT# Input/Output Select (M mode only). Writing a 1 selects the wait functionality of the signal. Writing a 0 selects Big Endian input functionality.
Read
Yes
Write
Yes
Value after Reset
0h
15:8
Yes
Yes
0h
16 17
Yes Yes
Yes Yes
0 0
18
Yes
Yes
0
20:19
Yes
Yes
00
21
Yes
Yes
1
22
Yes
Yes
0
23
Yes
Yes
0
24
Yes
Yes
0
25
Yes
Yes
0
26
Yes
Yes
0
27 28
Yes Yes
Yes Yes
0 0
29
Yes
Yes
0
30
Yes
No
0
31
Yes
Yes
0
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-21
Section 11--Registers
Section 11 Registers
Local Configuration Registers
Register 11-41. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor
Bit Description
Configuration Register Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for Local accesses to the Configuration registers. Writing a 0 specifies Little Endian ordering. Big Endian mode can be specified for Configuration register accesses by asserting BIGEND# during the Address phase of the access. Direct Master Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for Direct Master accesses. Writing a 0 specifies Little Endian ordering. Big Endian mode can be specified for Direct Master accesses by asserting BIGEND# input pin during the Address phase of the access. Direct Slave Address Space 0 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for Direct Slave accesses to Local Address Space 0. Writing a 0 specifies Little Endian ordering. Direct Slave Address Expansion ROM 0 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for Direct Slave accesses to Expansion ROM. Writing a 0 specifies Little Endian ordering. Big Endian Byte Lane Mode. Writing a 1 specifies that in any Endian mode, use the following byte lanes for the modes listed: M Mode [0:15] for a 16-bit Local Bus [0:7] for an 8-bit Local Bus C and J Modes [31:16] for a 16-bit Local Bus [31:24] for an 8-bit Local Bus Writing a 0 specifies that in any Endian mode, use the following byte lanes for the modes listed: M Mode [16:31] for a 16-bit Local Bus [24:31] for an 8-bit Local Bus C and J Modes [15:0] for a 16-bit Local Bus [7:0] for an 8-bit Local Bus Direct Slave Address Space 1 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for Direct Slave accesses to Local Address Space 1. Writing a 0 specifies Little Endian ordering. DMA Channel 1 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for DMA Channel 1 accesses to the Local Address space. Writing a 0 specifies Little Endian ordering. DMA Channel 0 Big Endian Mode (Address Invariance). Writing a 1 specifies use of Big Endian data ordering for DMA Channel 0 accesses to the Local Address space. Writing a 0 specifies Little Endian ordering.
Read
Write
Value after Reset
0
Yes
Yes
0
1
Yes
Yes
0
2
Yes
Yes
0
3
Yes
Yes
0
4
Yes
Yes
0
5
Yes
Yes
0
6
Yes
Yes
0
7
Yes
Yes
0
11-22
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 11 Registers
Register 11-42. (LMISC1; PCI:0Dh, LOC:8Dh) Local Miscellaneous Control1
Bit Description
Base Address Register 1 Enable. If set to 1, the Base Address 1 Register for I/O accesses to Configuration registers is enabled. If set to 0, the Base Address 1 Register for I/O accesses to Configuration registers is disabled. This option is intended for embedded systems only. This bit should be set to 1 for PC platforms. Base Address Register 1 Shift. If Base Address Register 1 Enable is low, and this bit is set to 0, then PCIBAR2 and PCIBAR3 remain at PCI Configuration addresses 18h and 1Ch. If Base Address Register 1 Enable is low, and this bit is set to 1, then PCIBAR2 (Local Address Space 0) and PCIBAR3 (Local Address Space 1) are shifted to become PCIBAR1 and PCIBAR2 at PCI Configuration addresses 14h and 18h. Set if a blank region in Base Address Register Space cannot be accepted by system BIOS. Local Init Status. Writing a 1 indicates Local Init done. Responses to PCI accesses prior to this bit being set are determined by the USERi state at PCI RST# de-assertion, as described in Sections 2.4.1.2 and 4.4.1.2. Direct Master (PCI Initiator) Write FIFO Flush during PCI Master Abort. When set to 1, the PCI 9056 flushes the Direct Master Write FIFO each time the Direct Slave or Master Abort occurs. When set to 0, the PCI 9056 keeps data in the Direct Master Write FIFO. M Mode Direct Master Delayed Read Enable. Writing a 1 enables the PCI 9056 to operate in Delayed Transaction mode for Direct Master reads. The PCI 9056 issues a RETRY# to the M mode Master and prefetches Read data from the PCI Bus. M Mode TEA# Input Interrupt Mask. When set to 1, TEA# input causes SERR# output on the PCI Bus if enabled (PCICR[8]=1) and the Signaled System Error bit is set (PCISR[14]=1). Writing 0 masks the TEA# input to create SERR#. The SERR# Status bit is set in both cases. Direct Master Write FIFO Almost Full RETRY# Output Enable. When set to 1, the PCI 9056 issues a RETRY# to the MPC850 or MPC860. Disconnect with Flush Read FIFO. Value of 1 causes a disconnect with flushing of the Read FIFO in Delayed Read mode (MARBR[24]). Value of 0 causes a disconnect without flushing the Read FIFO (as a Retry).
Read
Write
Value after Reset
0
Yes
Yes
1
1
Yes
Yes
0
2
Yes
Local/ Serial EEPROM
0
3
Yes
Yes
0
4
Yes
Yes
0
5
Yes
Yes
0
6 7
Yes Yes
Yes Yes
0 0
Register 11-43. (PROT_AREA; PCI:0Eh, LOC:8Eh) Serial EEPROM Write-Protected Address Boundary
Bit Description
Serial EEPROM Starting at Lword Boundary (48 Lwords = 192 bytes) for VPD Accesses. Any serial EEPROM address below this boundary is read-only. Note: Anything below the programmed address may contain the PCI 9056 Configuration data. Reserved.
Read
Write
Value after Reset
6:0
Yes
Yes
0110000
7
Yes
No
0
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-23
Section 11--Registers
Section 11 Registers
Local Configuration Registers
Register 11-44. (LMISC2; PCI:0Fh, LOC:8Fh) Local Miscellaneous Control 2
Bit
0 1
Description
READY# Timeout Enable. Value of 1 enables READY# timeout enable. READY# Timeout Select. Values: 1 = 64 clocks 0 = 32 clocks Direct Slave Write Delay. Delay in LCLK of TS#/ADS# from a valid address. Values: 0 = 0 LCLK 2 = 8 LCLK 4 =20 LCLK 6 = 28 LCLK 1 = 4 LCLK 3 = 16 LCLK 5 = 24 LCLK 7 = 32 LCLK Direct Slave Write FIFO Full Condition. Value of 1 guarantees that when the Direct Slave Write FIFO is full with Direct Slave Write data, there is always one location remaining empty for the Direct Slave Read address to be accepted by the PCI 9056. Value of 0 Retries all Direct Slave Read accesses when the Direct Slave Write FIFO is full with Direct Slave Write data. Reserved.
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
4:2
Yes
Yes
000
5
Yes
Yes
0
7:6
Yes
No
00
Register 11-45. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range
Bit
0 10:1
Description
Address Decode Enable. Bit 0 can only be enabled from the serial EEPROM. To disable, set the PCI Expansion ROM Address Decode Enable bit to 0 (PCIERBAR[0]=0). Reserved. Specifies which PCI Address bits to use for decoding a PCI-to-Local Bus Expansion ROM. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others (used in conjunction with PCIERBAR). Note: Range (not Range register) must be power of 2. "Range register value" is 2's complement of range.
Read
Yes Yes
Write
Serial EEPROM Only No
Value after Reset
0 0h
31:11
Yes
Yes
0h
11-24
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 11 Registers
Register 11-46. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) and BREQo Control
Bit Description
M Mode: RETRY# Signal Assertion Delay Clocks. Number of Local Bus clocks in which a Direct Slave BR# request is pending and a Local Direct Master access is in progress and not being granted the bus BG# before asserting RETRY#. Once asserted, RETRY# remains asserted until PCI 9056 samples de-assertion of BB# by the Local Arbiter (LSB is 8 or 64 clocks). C and J Modes: Backoff Request Delay Clocks. Number of Local Bus clocks in which a Direct Slave HOLD request is pending and a Local Direct Master access is in progress and not being granted the bus (LHOLDA) before asserting BREQo (Backoff Request Out). BREQo remains asserted until the PCI 9056 receives LHOLDA (LSB is 8 or 64 clocks). Local Bus Backoff Enable (M, C, and J modes). Writing a 1 enables the PCI 9056 to assert RETRY#/BREQo. Backoff Timer Resolution. Writing a 1 changes the LSB of the Backoff Timer from 8 to 64 clocks. Reserved. Remap PCI Expansion ROM Space into Local Address Space. Bits in this register remap (replace) the PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register).
Read
Write
Value after Reset
4 5 10:6
Yes Yes Yes
Yes Yes No
0 0 0h
31:11
Yes
Yes
0h
Register 11-47. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor
Bit
1:0 5:2 6
Description
Memory Space 0 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Memory Space 0 Internal Wait States (data-to-data; 0-15 wait states). Memory Space 0 TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. Memory Space 0 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Memory Space 0 Prefetch Disable. When mapped into Memory space, writing a 0 enables Read prefetching. Writing a 1 disables prefetching. If prefetching is disabled, the PCI 9056 disconnects after each Memory read. Expansion ROM Space Prefetch Disable. Writing a 0 enables Read prefetching. Writing a 1 disables prefetching. If prefetching is disabled, the PCI 9056 disconnects after each Memory read. Prefetch Counter Enable. When set to 1 and Memory prefetching is enabled, the PCI 9056 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9056 ignores the count and continues prefetching until it is terminated by the PCI Bus. Prefetch Counter. Number of Lwords to prefetch during Memory Read cycles (0-15). A count of zero selects a prefetch of 16 Lwords. Reserved. Expansion ROM Space Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width.
Read
Yes Yes Yes
Write
Yes Yes Yes
Value after Reset
M = 11 J = 11 C = 11 0h 1
7
Yes
Yes
0
8
Yes
Yes
0
9
Yes
Yes
0
10
Yes
Yes
0
14:11 15 17:16
Yes Yes Yes
Yes No Yes
0h 0 M = 11 J = 11 C = 11
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-25
Section 11--Registers
3:0
Yes
Yes
0h
Section 11 Registers
Local Configuration Registers
Register 11-47. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor (Continued)
Bit
21:18 22
Description
Expansion ROM Space Internal Wait States (data-to-data; 0-15 wait states). Expansion ROM Space TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. Expansion ROM Space BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or to Section 4.2.5 for C and J modes. Memory Space 0 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Extra Long Load from Serial EEPROM. Writing a 1 loads the Subsystem ID and Local Address Space 1 registers. Writing a 0 indicates not to load them. Expansion ROM Space Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Direct Slave PCI Write Mode. Writing a 0 indicates the PCI 9056 should disconnect when the Direct Slave Write FIFO is full. Writing a 1 indicates the PCI 9056 should de-assert TRDY# when the Direct Slave Write FIFO is full. Direct Slave Retry Delay Clocks. Contains the value (multiplied by 8) of the number of PCI Bus clocks after receiving a PCI-to-Local Read or Write access and not successfully completing a transfer. Pertains to Direct Slave writes only when the Direct Slave PCI Write Mode bit is set (bit [27]=1).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0h 1
23
Yes
Yes
0
24
Yes
Yes Serial EEPROM Only Yes
0
25
Yes
0
26
Yes
0
27
Yes
Yes
0
31:28
Yes
Yes
4h (32 clocks)
Register 11-48. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master-to-PCI
Bit
15:0 Reserved (64-KB increments). Specifies which Local Address bits to use for decoding a Local-to-PCI Bus access. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0h to all others. Note: Range (not Range register) must be power of 2. "Range register value" is 2's complement of range.
Description
Read
Yes
Write
No
Value after Reset
0h
31:16
Yes
Yes
0h
Register 11-49. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master-to-PCI Memory
Bit
15:0 31:16 Reserved. Assigns a value to bits to use for decoding Local-to-PCI Memory accesses. Note: Local Base Address value must be a multiple of the Range (not the Range register). Yes Yes 0h
Description
Read
Yes
Write
No
Value after Reset
0h
11-26
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 11 Registers
Register 11-50. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master-to-PCI I/O Configuration
Bit
15:0 Reserved. Assigns a value to bits to use for decoding Local-to-PCI I/O or Configuration accesses. 31:16
Description
Read
Yes
Write
No
Value after Reset
0h
Refer to DMPBAM[13] for the I/O Remap Address option.
Register 11-51. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master-to-PCI Memory
Bit
0
Description
Direct Master Memory Access Enable. Writing a 1 enables decode of Direct Master Memory accesses. Writing a 0 disables decode of Direct Master Memory accesses. Direct Master I/O Access Enable. Writing a 1 enables decode of Direct Master I/O accesses. Writing a 0 disables decode of Direct Master I/O accesses. Direct Master Cache Enable. Writing a 1 causes prefetch to occur infinitely. Direct Master Read Prefetch Size Control. Values: 00 = The PCI 9056 continues to prefetch Read data from the PCI Bus until the Direct Master access is finished. This may result in an additional four unneeded Lwords being prefetched from the 32-bit PCI Bus. 01 = Prefetch up to four Lwords from the 32-bit PCI Bus. 10 = Prefetch up to eight Lwords from the 32-bit PCI Bus. 11 = Prefetch up to 16 Lwords from the 32-bit PCI Bus. Direct Master Burst reads must not exceed programmed limit. Direct Master PCI Read Mode. Writing a 0 indicates the PCI 9056 should release the PCI Bus when the Read FIFO becomes full. Writing a 1 indicates the PCI 9056 should retain the PCI Bus and de-assert IRDY# when the Read FIFO becomes full. Programmable Almost Full Flag. When the number of entries in the 32-word Direct Master Write FIFO exceeds a (programmed value +1), the MDREQ#/DMPAF signal is asserted high. Memory Write and Invalidate Mode. When set to 1, the PCI 9056 waits for 8 or 16 Lwords to be written from the Local Bus before starting a PCI access. In addition, all Memory Write and Invalidate cycles to the PCI Bus must be 8 or 16 Lword bursts. Direct Master Prefetch Limit. Writing a 1 causes the PCI 9056 to terminate a prefetch at 4-KB boundaries and restart when the boundary is crossed. Writing an 0 results in continuous prefetch over the boundary space. I/O Remap Select. Writing a 1 forces PCI Address bits [31:16] to all zeros. Writing a 0 uses bits [31:16] of this register as PCI Address bits [31:16].
Read
Yes
Write
Yes
Value after Reset
0
1 2
Yes Yes
Yes Yes
0 0
12, 3
Yes
Yes
00
4
Yes
Yes
0
10, 8:5
Yes
Yes
00000
9
Yes
Yes
0
11
Yes
Yes
0
13
Yes
Yes
0
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-27
Section 11--Registers
Notes: Local Base Address value must be a multiple of the Range (not the Range register).
Yes
Yes
0h
Section 11 Registers
Local Configuration Registers
Register 11-51. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master-to-PCI Memory (Continued)
Bit Description
Direct Master Write Delay. Delays PCI Bus request after Direct Master Burst Write cycle has started. Values: 00 = No delay; start cycle immediately 01 = Delay 4 PCI clocks 10 = Delay 8 PCI clocks 11 = Delay 16 PCI clocks Remap Local-to-PCI Space into PCI Address Space. Bits in this register remap (replace) Local Address bits used in decode as the PCI Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register).
Read
Write
Value after Reset
15:14
Yes
Yes
00
31:16
Yes
Yes
0h
Register 11-52. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration
Bit
1:0 7:2 10:8 15:11 23:16 30:24 Configuration Type. Values: 00 = Type 0 01 = Type 1 Register Number. Function Number. Device Number. Bus Number. Reserved. Configuration Enable. Writing a 1 allows Local-to-PCI I/O accesses to be converted to a PCI Configuration cycle. Parameters in this table are used to assert the PCI Configuration address. Note: For more information, refer to the Direct Master Configuration cycle example in Section 3.4.1.9 for M mode or Section 5.4.1.8.1 for C and J modes.
Description
Read
Yes Yes Yes Yes Yes Yes
Write
Yes Yes Yes Yes Yes No
Value after Reset
00 0 0 0 0h 0h
31
Yes
Yes
0
11-28
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 11 Registers
Register 11-53. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates Local Address Space 1 maps into PCI Memory space. Writing a 1 indicates Address Space 1 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: 2/1 Meaning 00 Locate anywhere in 32-bit PCI Address space 01 PCI r2.1: Locate below 1-MB Memory Address space PCI r2.2: Reserved 10 Locate anywhere in 32-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [31:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect operation of the PCI 9056, but is used for system status). When mapped into I/O space, included with bits [31:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 1. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. (Used in conjunction with PCIBAR3.) Default is 1 MB. If QSR[0]=1, defines PCI Base Address 0. Notes: Range (not Range register) must be power of 2. "Range register value" is 2's complement of range. User should limit all I/O spaces to 256 bytes.
Read
Yes
Write
Yes
Value after Reset
0
2:1
Yes
Yes
00
3
Yes
Yes
0
31:4
Yes
Yes
FFF0000h
Register 11-54. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap)
Bit
0 1 3:2
Description
Space 1 Enable. Writing a 1 enables decoding of PCI addresses for Direct Slave access to Local Bus Space 1. Writing a 0 disables decoding. Reserved. Not used if Local Bus Space 1 is mapped into Memory space. Included with bits [31:4] for remapping when mapped into I/O space. Remap PCI Address to Local Address Space 1 into Local Address Space. Bits in this register remap (replace) the PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a multiple of the Range (not the Range register).
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
0 0 00
31:4
Yes
Yes
0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-29
Section 11--Registers
Section 11 Registers
Local Configuration Registers
Register 11-55. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor
Bit
1:0 5:2 6
Description
Memory Space 1 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Memory Space 1 Internal Wait States (data-to-data; 0-15 wait states). Memory Space 1 TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. Memory Space 1 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Memory Space 1 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Memory Space 1 Prefetch Disable. When mapped into Memory space, writing a 0 enables Read prefetching. Writing a 1 disables prefetching. If prefetching is disabled, the PCI 9056 disconnects after each Memory read. Prefetch Count Enable. When set to 1 and Memory prefetching is enabled, the PCI 9056 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9056 ignores the count and continues prefetching until it is terminated by the PCI Bus. Prefetch Counter. Number of Lwords to prefetch during Memory Read cycles (0-15). A count of zero selects a prefetch of 16 Lwords. Reserved.
Read
Yes Yes Yes
Write
Yes Yes Yes
Value after Reset
M = 11 J = 11 C = 11 0h 1
7
Yes
Yes
0
8
Yes
Yes
0
9
Yes
Yes
0
10
Yes
Yes
0
14:11 31:15
Yes Yes
Yes No
0h 0h
Register 11-56. (DMDAC; PCI:FCh, LOC:17Ch) Direct Master PCI Dual Address Cycle Upper Address
Bit
31:0
Description
Upper 32 Bits of PCI Dual Address Cycle PCI Address during Direct Master Cycles. If set to 0, the PCI 9056 performs 32-bit Direct Master Address access.
Read
Yes
Write
Yes
Value after Reset
0h
11-30
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 11 Registers
Register 11-57. (PCIARB; PCI:100h, LOC:1A0h) PCI Arbiter Control
Bit
0
Description
Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of this table entry. PCI 9056 High Priority. Value of 0 indicates the PCI 9056 participates in round-robin arbitration with the other PCI Masters. Value of 1 indicates a two-level, round-robin arbitration scheme is enabled. The other PCI Bus Masters participate in their own round-robin arbitration. The winner of this arbitration then arbitrates for the PCI Bus with the PCI 9056 (when using the Internal PCI arbiter). Early Grant Release. Value of 0 indicates the PCI 9056 keeps GNT# asserted until another Master requests use of the PCI Bus. Value of 1 indicates the PCI 9056 always de-asserts the current GNT# when FRAME# is asserted (when using the internal PCI arbiter). PCI Arbiter Parking on PCI 9056. Value of 1 indicates the PCI arbiter parks the grant on the PCI 9056. Value of 0 indicates the PCI arbiter parks the grant on the current PCI Master (when using the internal PCI arbiter). Reserved.
Read
Write
Value after Reset
1
Yes
0
2
PCI/ Local
Yes
0
3 31:4
PCI/ Local Y
PCI/ Local N
0 0
Register 11-58. (PABTADR; PCI:104h, LOC:1A4h) PCI Abort Address
Bit
31:0
Description
PCI Abort Address. When a PCI Master/Target Abort occurs, the starting address of the current access is returned to this register.
Read
Yes
Write
No
Value after Reset
0000h
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-31
Section 11--Registers
PCI/ Local
Section 11 Registers
Runtime Registers
11.5
RUNTIME REGISTERS
Register 11-59. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0
Bit
32-Bit Mailbox Register. 31:0 Note: Inbound Queue Port replaces Mailbox Register 0 when the I2O function is enabled (QSR[0]=1). Mailbox Register 0 is always accessible at PCI address 78h and Local address C0h. Yes Yes 0h
Description
Read
Write
Value after Reset
Register 11-60. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1
Bit
32-Bit Mailbox Register. 31:0 Note: Mailbox Register 1 is replaced by Outbound Queue Port when the I2O function is enabled (QSR[0]=1). Mailbox Register 1 is always accessible at PCI address 7Ch and Local address C4h. Yes Yes 0h
Description
Read
Write
Value after Reset
Register 11-61. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2
Bit
31:0 32-Bit Mailbox Register.
Description
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-62. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3
Bit
31:0 32-Bit Mailbox Register.
Description
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-63. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4
Bit
31:0 32-Bit Mailbox Register.
Description
Read
Yes
Write
Yes
Value after Reset
0h
11-32
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Runtime Registers
Section 11 Registers
Register 11-64. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5
Bit
31:0 32-Bit Mailbox Register.
Description
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-65. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6
Bit
31:0 32-Bit Mailbox Register.
Description
Read
Yes
Write
Yes
0h
Register 11-66. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7
Bit
31:0 32-Bit Mailbox Register.
Description
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-67. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell
Bit Description
Doorbell Register. The PCI Bus Master can write to this register and assert a Local interrupt to the Local processor. The Local processor can then read this register to determine which doorbell bit was set. The PCI Bus Master sets the doorbell by writing a 1 to a particular bit. The Local processor can clear a doorbell bit by writing a 1 to that bit position.
Read
Write
Value after Reset
31:0
Yes
Yes/Clr
0h
Register 11-68. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell
Bit Description
Doorbell Register. The Local processor can write to this register and assert a PCI interrupt. The PCI Bus Master can then read this register to determine which doorbell bit was set. The Local processor sets the doorbell by writing a 1 to a particular bit. The PCI Bus Master can clear a doorbell bit by writing a 1 to that bit position.
Read
Write
Value after Reset
31:0
Yes
Yes/Clr
0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-33
Section 11--Registers
Value after Reset
Section 11 Registers
Runtime Registers
Register 11-69. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status
Bit
0
Description
Enable Local Bus TEA#/LSERR#. Writing a 1 enables PCI 9056 to assert TEA#/LSERR# interrupt when the Received Master Abort bit is set (PCISR[13]=1 or INTCSR[6]=1). Enable Local Bus TEA#/LSERR# when a PCI parity error occurs during a PCI 9056 Master Transfer or a PCI 9056 Slave access. Generate PCI Bus SERR# Interrupt. When set to 0, writing 1 asserts the PCI Bus SERR# interrupt. Mailbox Interrupt Enable. Writing a 1 enables a Local Interrupt to be asserted when the PCI Bus writes to MBOX0 through MBOX3. To clear a Local Interrupt, the Local Bus Master must read the Mailbox. Used in conjunction with the Local Interrupt Output Enable bit (INTCSR[16]). Power Management Interrupt Enable. Writing a 1 enables a Local Interrupt to be asserted when the Power Management Power State changes. Power Management Interrupt. When set to 1, indicates a Power Management interrupt is pending. A Power Management interrupt is caused by a change in the Power State register (PMCSR). Writing a 1 clears the interrupt. Direct Master Write/Direct Slave Read Local Data Parity Check Error Enable. Writing a 1 enables a Local Data Parity error signal to be asserted through the LSERR#/TEA# pin. INTCSR[0] must be enabled for this to have an effect. Direct Master Write/Direct Slave Read Local Data Parity Check Error Status. When set to 1, indicates the PCI 9056 has detected a Local Data Parity check error, even if the Check Parity Error bit is disabled. Writing 1 clears this bit to 0. PCI Interrupt Enable. Writing a 1 enables PCI interrupts. PCI Doorbell Interrupt Enable. Writing a 1 enables Doorbell interrupts. Used in conjunction with the PCI Interrupt Enable bit (INTCSR[8]). Clearing the doorbell interrupt bits that caused the interrupt also clears the interrupt. PCI Abort Interrupt Enable. Values of 1 enables Master Abort or Master detect of a Target Abort to assert a PCI interrupt. Used in conjunction with the PCI Interrupt Enable bit (INTCSR[8]). Clearing the abort status bits also clears the PCI interrupt. Local Interrupt Input Enable. Writing a 1 enables a Local interrupt input to assert a PCI interrupt. Used in conjunction with the PCI Interrupt Enable bit (INTCSR[8]). Clearing the Local Bus cause of the interrupt also clears the interrupt. Retry Abort Enable. Writing a 1 enables the PCI 9056 to treat 256 Master consecutive Retries to a Target as a Target Abort. Writing a 0 enables the PCI 9056 to attempt Master Retries indefinitely. PCI Doorbell Interrupt Active. When set to 1, indicates the PCI Doorbell interrupt is active. PCI Abort Interrupt Active. When set to 1, indicates the PCI Abort interrupt is active. Local Input Interrupt Active. When set to 1, indicates the Local Input interrupt is active. Local Interrupt Output Enable. Writing a 1 enables Local interrupt output. Used in conjunction with the Mailbox Interrupt Enable bit (INTCSR[3]). Local Doorbell Interrupt Enable. Writing a 1 enables Doorbell interrupts. Used in conjunction with the Local Interrupt Enable bit. Clearing the Local Doorbell Interrupt bits that caused the interrupt also clears the interrupt.
Read
Yes
Write
Yes
Value after Reset
0
1 2
Yes Yes
Yes Yes
0 0
3
Yes
Yes
0
4
Yes
Yes
0
5
Yes
Yes/Clr
0
6
Yes
Yes
0
7
Yes
Yes/Clr
0
8 9
Yes Yes
Yes Yes
1 0
10
Yes
Yes
0
11
Yes
Yes
0
12
Yes
Yes
0
13 14 15 16
Yes Yes Yes Yes
No No No Yes
0 0 0 1
17
Yes
Yes
0
11-34
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Runtime Registers
Section 11 Registers
Register 11-69. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status (Continued)
Bit
18
Description
Local DMA Channel 0 Interrupt Enable. Writing a 1 enables DMA Channel 0 interrupts. Used in conjunction with the Local Interrupt Enable bit. Clearing the DMA status bits also clears the interrupt. Local DMA Channel 1 Interrupt Enable. Writing a 1 enables DMA Channel 1 interrupts. Used in conjunction with the Local Interrupt Enable bit. Clearing the DMA status bits also clears the interrupt. Local Doorbell Interrupt Active. Reading a 1 indicates the Local Doorbell interrupt is active. DMA Channel 0 Interrupt Active. Reading a 1 indicates the DMA Channel 0 interrupt is active. DMA Channel 1 Interrupt Active. Reading a 1 indicates the DMA Channel 1 interrupt is active. BIST Interrupt Active. Reading a 1 indicates the BIST interrupt is active. The BIST (built-in self test) interrupt is asserted by writing a 1 to bit 6 of the PCI Configuration BIST register. Clearing bit 6 clears the interrupt. Refer to the PCIBISTR register for a description of the self test. Reading a 0 indicates the Direct Master was the Bus Master during a Master or Target Abort. Reading a 0 indicates DMA Channel 0 was the Bus Master during a Master or Target Abort. Reading a 0 indicates DMA Channel 1 was the Bus Master during a Master or Target Abort. Reading a 0 indicates a Target Abort was asserted by the PCI 9056 after 256 consecutive Master retries to a Target. Reading a 1 indicates the PCI Bus wrote data to MBOX0. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Reading a 1 indicates the PCI Bus wrote data to MBOX1. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Reading a 1 indicates the PCI Bus wrote data to MBOX2. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Reading a 1 indicates the PCI Bus wrote data to MBOX3. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1).
Read
Yes
Write
Yes
Value after Reset
0
19
Yes
Yes
0
20 21 22
Yes Yes Yes
No No No
0 0 0
23
Yes
No
0
24 25 26 27 28 29 30 31
Yes Yes Yes Yes Yes Yes Yes Yes
No No No No No No No No
1 1 1 1 0 0 0 0
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-35
Section 11--Registers
Section 11 Registers
Runtime Registers
Register 11-70. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control, and Init Control
Bit
3:0 7:4 11:8 15:12 16 17
Description
PCI Read Command Code for DMA. PCI Write Command Code for DMA. PCI Memory Read Command Code for Direct Master. PCI Memory Write Command Code for Direct Master. General Purpose Output. Writing a 1 causes USERo output to go high. Writing a 0 causes USERo output to go low. General Purpose Input. Reading a 1 indicates the USERi input pin is high. Reading a 0 indicates the USERi pin is low. Writing a 1 selects USERi to be an input to the chip. Writing a 0 selects LLOCKi# as an input. Enables the user to select between the USERi and LLOCKi# functions when USERi is chosen to be an input. The select bit(s) for the pin is DMAMODE0[12] and/or DMAMODE1[12]. Writing a 1 selects USERo to be an output from the chip. Writing a 0 selects LLOCKo# as an output. Enables the user to select between the USERo and LLOCKo# functions when USERo is chosen to be an output. The select bit(s) for the pin is DMAMODE0[12] and/or DMAMODE1[12]. LINTo# Interrupt Status. When HOSTEN# is enabled, reading a 1 indicates the LINTo# interrupt is active by way of the INTA# PCI interrupt. Writing a 1 clears this bit. TEA#/LSERR# Interrupt Status. When HOSTEN# is enabled, reading a 1 indicates the TEA#/LSERR# interrupt is active by way of the SERR# PCI System Error. Writing a 1 clears this bit. Reserved. Serial EEPROM Clock for Local or PCI Bus Reads or Writes to Serial EEPROM. Toggling this bit asserts the serial EEPROM clock. (Refer to manufacturer's data sheet for particular serial EEPROM being used.) Serial EEPROM Chip Select. For Local or PCI Bus reads or writes to the serial EEPROM, setting this bit to 1 provides the serial EEPROM chip select. Write Bit to Serial EEPROM. For writes, this output bit is input to the serial EEPROM. Clocked into the serial EEPROM by the serial EEPROM clock. Read Bit from Serial EEPROM. (Refer to Sections 2.4.2 and 2.4.2.1 for M mode or Sections 4.4.2 and 4.4.2.1 for C and J modes.) Programmed Serial EEPROM Present. When set to 1, indicates that a blank or programmed serial EEPROM is present. Reload Configuration Registers. When set to 0, writing a 1 causes the PCI 9056 to reload the Local Configuration registers from the serial EEPROM. PCI Adapter Software Reset when HOSTEN#=1. Writing a 1 holds the PCI 9056 Local Bus logic in a reset state, and asserts LRESET# output. Contents of the PCI Configuration registers and the shared Runtime registers are not reset. A software reset can only be cleared from the PCI Bus. PCI Host Software Reset when HOSTEN#=0. Writing a 1 holds the PCI 9056 PCI Bus logic in a reset state, and asserts RST# output. Contents of the Local Configuration, shared Runtime, DMA, and Messaging Queue registers are not reset. A software reset can only be cleared from the Local Bus. EEDO Input Enable. When set to 1, the EEDI/EEDO I/O buffer is placed in Bus high-impedance state, enabling the serial EEPROM data to be read. The serial EEPROM data resides in CNTRL[27].
Read
Yes Yes Yes Yes Yes Yes
Write
Yes Yes Yes Yes Yes No
Value after Reset
1110 0111 0110 0111 1 --
18
Yes
Yes
1
19
Yes
Yes
1
20
Yes
Yes/Clr
0
21 23:22 24
Yes Yes Yes
Yes/Clr No Yes
0 00 0
25 26 27 28 29
Yes Yes Yes Yes Yes
Yes Yes No No Yes
0 0 -- 0 0
30
Yes
Yes
0
31
Yes
No
0
11-36
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Registers
Section 11 Registers
Register 11-71. (PCIHIDR; PCI:70h, LOC:F0h) PCI Hardwired Configuration ID
Bit
15:0 31:16
Description
Vendor ID. Identifies manufacturer of device. Hardwired to the PCI SIG-issued Vendor ID of PLX (10B5h). Device ID. Identifies particular device. Hardwired to the PLX part number for PCI interface chip 9056h.
Read
Yes Yes
Write
No No
Value after Reset
10B5h 9056h
Register 11-72. (PCIHREV; PCI:74h, LOC:F4h) PCI Hardwired Revision ID
Bit
7:0
Description
Revision ID. Hardwired silicon revision of the PCI 9056.
Read
Yes
Write
No
Value after Reset
Current Rev # (AA)
11.6
DMA REGISTERS
Register 11-73. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode
Bit
1:0 5:2 6 7 8
Description
Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Internal Wait States (data-to-data). TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Local Burst Enable. Writing a 1 enables Local bursting. Writing a 0 disables Local bursting. Scatter/Gather Mode. Writing a 1 indicates Scatter/Gather mode is enabled. For Scatter/Gather mode, DMA source address, destination address, and byte count are loaded from memory in PCI or Local Address spaces. Writing a 0 indicates Block mode is enabled. Done Interrupt Enable. Writing a 1 enables an interrupt when done. Writing a 0 disables an interrupt when done. If DMA Clear Count mode is enabled, the interrupt does not occur until the byte count is cleared. Local Addressing Mode. Writing a 1 holds the Local Address bus constant. Writing a 0 indicates the Local Address is incremented. Demand Mode. Writing a 1 causes the DMA controller to operate in Demand mode. In Demand mode, the DMA controller transfers data when its DREQ0# input is asserted. Asserts DACK0# to indicate the current Local Bus transfer is in response to DREQ0# input. DMA controller transfers Lwords (32 bits) of data. This may result in multiple transfers for an 8- or 16-bit bus. Memory Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9056 performs Memory Write and Invalidate cycles to the PCI Bus. The PCI 9056 supports Memory Write and Invalidate sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers. Transfers must start and end at cache line boundaries. DMA EOT# Enable. Writing a 1 enables the EOT# input pin. Writing a 0 disables the EOT# input pin.
Read
Yes Yes Yes Yes Yes
Write
Yes Yes Yes Yes Yes
Value after Reset
M = 11 J = 11 C = 11 0h 1 0 0
9
Yes
Yes
0
10 11
Yes Yes
Yes Yes
0 0
12
Yes
Yes
0
13
Yes
Yes
0
14
Yes
Yes
0
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-37
Section 11--Registers
Section 11 Registers
DMA Registers
Register 11-73. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode (Continued)
Bit Description
Fast/Slow Terminate Mode Select. Writing a 0 sets PCI 9056 into the Slow Terminate mode. As a result in C or J modes, BLAST# is asserted on the last Data transfer to terminate DMA transfer. As a result in M mode, BDIP# is de-asserted at the nearest 16-byte boundary and stops the DMA transfer. Writing a 1 indicates that if EOT# is asserted or DREQ0# is de-asserted in Demand mode during DMA will immediately terminate the DMA transfer. In M mode, writing a 1 indicates BDIP# output is disabled. As a result, the PCI 9056 DMA transfer terminates immediately when EOT# is asserted or when DREQ0# is de-asserted in Demand mode. DMA Clear Count Mode. Writing a 1 clears the byte count in each Scatter/ Gather descriptor when the corresponding DMA transfer is complete. DMA Channel 0 Interrupt Select. Writing a 1 routes the DMA Channel 0 interrupt to the PCI Bus interrupt. Writing a 0 routes the DMA Channel 0 interrupt to the Local Bus interrupt. DAC Chain Load. When set to 1, enables the descriptor to load the PCI Dual Address Cycle value. Otherwise, it uses the register contents. EOT# End Link. Used only for Scatter/Gather DMA transfers. When EOT# is asserted, value of 1 indicates the DMA transfer ends the current Scatter/Gather link and continues with the remaining Scatter/Gather transfers. When EOT# is asserted, value of 0 indicates the DMA transfer ends the current Scatter/Gather transfer and does not continue with the remaining Scatter/Gather transfers. Valid Mode Enable. Value of 0 indicates the Valid bit (DMASIZ0[31]) is ignored. Value of 1 indicates the DMA descriptors are processed only when the Valid bit is set (DMASIZ0[31]). If the Valid bit is set, the transfer count is 0, and the descriptor is not the last descriptor in the chain. The DMA controller then moves to the next descriptor in the chain. Valid Stop Control. Value of 0 indicates the DMA Chaining controller continuously polls a descriptor with the Valid bit set to 0 (invalid descriptor) if the Valid Mode Enable bit is set (bit [20]=1). Value of 1 indicates the Chaining controller stops polling when the Valid bit with a value of 0 is detected (DMASIZ0[31]=0). In this case, the CPU must restart the DMA controller by setting the Start bit (DMACSR0[1]=1). A pause sets the DMA Done bit (DMACSR0[4]). Reserved.
Read
Write
Value after Reset
15
Yes
Yes
0
16 17 18
Yes Yes Yes
Yes Yes Yes
0 0 0
19
Yes
Yes
0
20
Yes
Yes
0
21
Yes
Yes
0
31:22
Yes
No
0h
Register 11-74. (DMAPADR0; (PCI:84h, LOC:104h when DMAMODE0[20]=0 or PCI:88h, LOC:108h when DMAMODE0[20]=1) DMA Channel 0 PCI Address
Bit
31:0
Description
PCI Address Register. Indicates from where in PCI Memory space DMA transfers (reads or writes) start.
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-75. (DMALADR0; PCI:88h, LOC:108h when DMAMODE0[20]=0 or PCI:8Ch, LOC:10Ch when DMAMODE0[20]=1) DMA Channel 0 Local Address
Bit
31:0
Description
Local Address Register. Indicates from where in Local Memory space DMA transfers (reads or writes) start.
Read
Yes
Write
Yes
Value after Reset
0h
11-38
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Registers
Section 11 Registers
Register 11-76. (DMASIZ0; PCI:8Ch, LOC:10Ch when DMAMODE0[20]=0 or PCI:84h, LOC:104h when DMAMODE0[20]=1) DMA Channel 0 Transfer Size (Bytes)
Bit
22:0 30:23 31
Description
DMA Transfer Size (Bytes). Indicates the number of bytes to transfer during a DMA operation. Reserved. Valid. When the Valid Mode Enable bit is set (DMAMODE0[20]=1), indicates the validity of this DMA descriptor.
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
0h 0h
Register 11-77. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer
Bit
0 1
Description
Descriptor Location. Writing a 1 indicates PCI Address space. Writing a 0 indicates Local Address space. End of Chain. Writing a 1 indicates end of chain. Writing a 0 indicates not end of chain descriptor. (Same as Block mode.) Interrupt after Terminal Count. Writing a 1 causes an interrupt to be asserted after the terminal count for this descriptor is reached. Writing a 0 disables interrupts from being asserted. Direction of Transfer. Writing a 1 indicates transfers from the Local Bus to the PCI Bus. Writing a 0 indicates transfers from the PCI Bus to the Local Bus. Next Descriptor Address. Qword-aligned (bits [3:0]=0000).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
3 31:4
Yes Yes
Yes Yes
0 0h
Register 11-78. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode
Bit
1:0 5:2 6
Description
Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 or 11 indicates a 32-bit bus width. Internal Wait States (data-to-data). TA#/READY# Input Enable. Writing a 1 enables TA#/READY# input. Writing a 0 disables TA#/READY# input. BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.5 for M mode or Section 4.2.5 for C and J modes. Local Burst Enable. Writing a 1 enables Local bursting. Writing a 0 disables Local bursting. Scatter/Gather Mode. Writing a 1 indicates Scatter/Gather mode is enabled. For Scatter/Gather mode, the DMA source address, destination address, and byte count are loaded from memory in PCI or Local Address spaces. Writing a 0 indicates Block mode is enabled. Done Interrupt Enable. Writing a 1 enables interrupt when done. Writing a 0 disables the interrupt when done. If DMA Clear Count mode is enabled, the interrupt does not occur until the byte count is cleared. Local Addressing Mode. Writing a 1 holds the Local address bus constant. Writing a 0 indicates the Local address is incremented.
Read
Yes Yes Yes
Write
Yes Yes Yes
Value after Reset
M = 11 J = 11 C = 11 0h 1
7
Yes
Yes
0
8
Yes
Yes
0
9
Yes
Yes
0
10
Yes
Yes
0
11
Yes
Yes
0
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-39
Section 11--Registers
0h
Section 11 Registers
DMA Registers
Register 11-78. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode (Continued)
Bit Description
Demand Mode. Writing a 1 causes the DMA controller to operate in Demand mode. In Demand mode, the DMA controller transfers data when its DREQ1# input is asserted. Asserts DACK1# to indicate the current Local Bus transfer is in response to DREQ1# input. DMA controller transfers Lwords (32 bits) of data. This may result in multiple transfers for an 8- or 16-bit bus. Memory Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9056 performs Memory Write and Invalidate cycles to the PCI Bus. The PCI 9056 supports Memory Write and Invalidate sizes of 8 or 16 Lwords. Size is specified in the System Cache Line Size bits (PCICLSR[7:0]). If a size other than 8 or 16 is specified, the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers. Transfers must start and end at cache line boundaries. DMA EOT# Enable. Writing a 1 enables the EOT# input pin. Writing a 0 disables the EOT# output pin. Fast/Slow Terminate Mode Select. Writing a 0 sets the PCI 9056 into Slow Terminate mode. As a result in C or J modes, BLAST# is asserted to terminate the DMA transfer. As a result in M mode, BDIP# is de-asserted at the nearest 16-byte boundary and stops the DMA transfer. Writing a 1 indicates that asserting EOT# during DMA will terminate the DMA transfer. In M mode, writing a 1 indicates BDIP# output is disabled. As a result, the PCI 9056 DMA transfer terminates immediately when EOT# is asserted. DMA Clear Count Mode. When set to 1, the byte count in each Scatter/ Gather descriptor is cleared when the corresponding DMA transfer is complete. DMA Channel 1 Interrupt Select. Writing a 1 routes the DMA Channel 1 interrupt to the PCI Bus interrupt. Writing a 0 routes the DMA Channel 1 interrupt to the Local Bus interrupt. DAC Chain Load. When set to 1, enables the descriptor to load the PCI Dual Address Cycle value. Otherwise, it uses the register contents. EOT# End Link. Used only for DMA Scatter/Gather transfers. When EOT# is asserted, value of 1 indicates the DMA transfer ends the current Scatter/ Gather link and continues with the remaining Scatter/Gather transfers. When EOT# is asserted, value of 0 indicates the DMA transfer completes the current Scatter/Gather transfer, but does not continue with the remaining Scatter/ Gather transfers. Valid Mode Enable. Value of 0 indicates the Valid bit (DMASIZ1[31]) is ignored. Value of 1 indicates the DMA descriptors are processed only when the Valid bit is set (DMASIZ1[31]). If the Valid bit is set, the transfer count is 0, and the descriptor is not the last descriptor in the chain. The DMA controller then moves to the next descriptor in the chain. Valid Stop Control. Value of 0 indicates the DMA Scatter/Gather controller continuously polls a descriptor with the Valid bit set to 0 (invalid descriptor) if the Valid Mode Enable bit is set (bit [20]=1). Value of 1 indicates the Scatter/ Gather controller stops polling when the Valid bit with a value of 0 is detected (DMASIZ1[31]=0). In this case, the CPU must restart the DMA controller by setting the Start bit (DMACSR1[1]=1). A pause sets the DMA Done bit (DMASCR1[4]). Reserved.
Read
Write
Value after Reset
12
Yes
Yes
0
13
Yes
Yes
0
14
Yes
Yes
0
15
Yes
Yes
0
16
Yes
Yes
0
17
Yes
Yes
0
18
Yes
Yes
0
19
Yes
Yes
0
20
Yes
Yes
0
21
Yes
Yes
0
31:22
Yes
No
0h
11-40
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Registers
Section 11 Registers
Register 11-79. (DMAPADR1;PCI:98h, LOC:118h when DMAMODE1[20]=0 or PCI:9Ch, LOC:11Ch when DMAMODE1[20]=1) DMA Channel 1 PCI Address
Bit
31:0
Description
PCI Address Register. Indicates from where in PCI Memory space DMA transfers (reads or writes) start.
Read
Yes
Write
Yes
Value after Reset
0h
Bit
31:0
Description
Local Address Register. Indicates from where in Local Memory space DMA transfers (reads or writes) start.
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-81. (DMASIZ1; PCI:A0h, LOC:120h when DMAMODE1[20]=0 or PCI:98h, LOC:118h when DMAMODE1[20]=1) DMA Channel 1 Transfer Size (Bytes)
Bit
22:0 30:23 31
Description
DMA Transfer Size (Bytes). Indicates the number of bytes to transfer during a DMA operation. Reserved. Valid. When the Valid Mode Enable bit is set (DMAMODE1[20]=1), indicates the validity of this DMA descriptor.
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
0h 0h 0h
Register 11-82. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer
Bit
0 1
Description
Descriptor Location. Writing a 1 indicates PCI Address space. Writing a 0 indicates Local Address space. End of Chain. Writing a 1 indicates end of chain. Writing a 0 indicates not end of chain descriptor. (Same as Block mode.) Interrupt after Terminal Count. Writing a 1 causes an interrupt to be asserted after the terminal count for this descriptor is reached. Writing a 0 disables interrupts from being asserted. Direction of Transfer. Writing a 1 indicates transfers from the Local Bus to the PCI Bus. Writing a 0 indicates transfers from the PCI Bus to the Local Bus. Next Descriptor Address. Qword-aligned (bits [3:0]=0000).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
3 31:4
Yes Yes
Yes Yes
0 0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-41
Section 11--Registers
Register 11-80. (DMALADR1;PCI:9Ch, LOC:11Ch when DMAMODE1[20]=0 or PCI:A0h, LOC:120h when DMAMODE1[20]=1) DMA Channel 1 Local Address
Section 11 Registers
DMA Registers
Register 11-83. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status
Bit
0
Description
Channel 0 Enable. Writing a 1 enables channel to transfer data. Writing a 0 disables the channel from starting a DMA transfer, and if in the process of transferring data, suspends the transfer (pause). Channel 0 Start. Writing a 1 causes the channel to start transferring data if the channel is enabled. Channel 0 Abort. Writing a 1 causes the channel to abort current transfer. Channel 0 Enable bit must be cleared (bit [0]=0). Sets Channel 0 Done (bit [4]=1) when abort is complete. Channel 0 Clear Interrupt. Writing a 1 clears Channel 0 interrupts. Channel 0 Done. Reading a 1 indicates a channel transfer is complete. Reading a 0 indicates a channel transfer is not complete. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
1
No
Yes/Set
0
2 3 4 7:5
No No Yes Yes
Yes/Set Yes/Clr No No
0 0 1 000
Register 11-84. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status
Bit
0
Description
Channel 1 Enable. Writing a 1 enables channel to transfer data. Writing a 0 disables the channel from starting a DMA transfer, and if in the process of transferring data, suspends the transfer (pause). Channel 1 Start. Writing a 1 causes channel to start transferring data if the channel is enabled. Channel 1 Abort. Writing a 1 causes channel to abort current transfer. Channel 1 Enable bit must be cleared (bit [0]=0). Sets Channel 1 Done (bit [4]=1) when abort is complete. Channel 1 Clear Interrupt. Writing a 1 clears Channel 1 interrupts. Channel 1 Done. Reading a 1 indicates a channel transfer is complete. Reading a 0 indicates a channel transfer is not complete. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
1
No
Yes/Set
0
2 3 4 7:5
No No Yes Yes
Yes/Set Yes/Clr No No
0 0 1 000
Register 11-85. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Same as Register 11-40 "(MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/DMA Arbitration," on page 11-21.
11-42
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
DMA Registers
Section 11 Registers
Register 11-86. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold
Bit
3:0
Description
DMA Channel 0 PCI-to-Local Almost Full (C0PLAF). Number of full entries (divided by two, minus one) in the FIFO before requesting the Local Bus for writes. (C0PLAF+1) + (C0PLAE+1) should be a FIFO Depth of 32. DMA Channel 0 Local-to-PCI Almost Empty (C0LPAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting the Local Bus for reads. (C0LPAF+1) + (C0LPAE+1) should be a FIFO depth of 32. DMA Channel 0 Local-to-PCI Almost Full (C0LPAF). Number of full entries (divided by two, minus one) in the FIFO before requesting the PCI Bus for writes. DMA Channel 0 PCI-to-Local Almost Empty (C0PLAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting the PCI Bus for reads. DMA Channel 1 PCI-to-Local Almost Full (C1PLAF). Number of full entries (divided by two, minus one) in the FIFO before requesting the Local Bus for writes. (C1PLAF+1) + (C1PLAE+1) should be a FIFO Depth of 32. DMA Channel 1 Local-to-PCI Almost Empty (C1LPAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting the Local Bus for reads. (C1LPAF+1) + (C1LPAE+1) should be a FIFO depth of 32. DMA Channel 1 Local-to-PCI Almost Full (C1LPAF). Number of full entries (divided by two, minus one) in the FIFO before requesting the PCI Bus for writes. DMA Channel 1 PCI-to-Local Almost Empty (C1PLAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting the PCI Bus for reads.
Read
Yes
Write
Yes
Value after Reset
0h
7:4
Yes
Yes
0h
11:8
Yes
Yes
0h
15:12
Yes
Yes
0h
19:16
Yes
Yes
0h
23:20
Yes
Yes
0h
27:24
Yes
Yes
0h
31:28
Yes
Yes
0h
Note: For DMA Channel 0 only, if number of entries needed is x, then the value is one less than half the number of entries (that is, x/2 - 1).
Register 11-87. (DMADAC0; PCI:B4h, LOC:134h) DMA Channel 0 PCI Dual Address Cycle Upper Address
Bit
31:0
Description
Upper 32 Bits of the PCI Dual Address Cycle PCI Address during DMA Channel 0 Cycles. If set to 0h, the PCI 9056 performs a 32-bit DMA Channel 0 Address access.
Read
Yes
Write
Yes
Value after Reset
0h
Register 11-88. (DMADAC1; PCI:B8h, LOC:138h) DMA Channel 1 PCI Dual Address Cycle Upper Address
Bit
31:0
Description
Upper 32 Bits of the PCI Dual Address Cycle PCI Address during DMA Channel 1 Cycles. If set to 0h, the PCI 9056 performs a 32-bit DMA Channel 1 Address access.
Read
Yes
Write
Yes
Value after Reset
0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-43
Section 11--Registers
Section 11 Registers
Messaging Queue Registers
11.7
MESSAGING QUEUE REGISTERS
Register 11-89. (OPQIS; PCI:30h, LOC:B0h) Outbound Post Queue Interrupt Status
Bit
2:0 3 31:4 Reserved. Outbound Post Queue Interrupt. Set when the Outbound Post Queue is not empty. Not affected by the Interrupt Mask bit. Reserved.
Description
Read
Yes Yes Yes
Write
No No No
Value after Reset
000 0 0h
Register 11-90. (OPQIM; PCI:34h, LOC:B4h) Outbound Post Queue Interrupt Mask
Bit
2:0 3 31:4 Reserved. Outbound Post Queue Interrupt Mask. Writing a 1 masks the interrupt. Reserved.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
000 1 0h
Register 11-91. (IQP; PCI:40h) Inbound Queue Port
Bit Description
Value written by the PCI Master is stored into the Inbound Post Queue, which is located in Local memory at the address pointed to by the Queue Base Address + Queue Size + Inbound Post Head Pointer. From the time of the PCI write until the Local Memory write and update of the Inbound Post Queue Head Pointer, further accesses to this register result in a Retry. A Local interrupt is asserted when the Inbound Post Queue is not empty. When the port is read by the PCI Master, the value is read from the Inbound Free Queue, which is located in Local memory at the address pointed to by the Queue Base Address + Inbound Free Tail Pointer. If the queue is empty, FFFFFFFFh is returned.
Read
Write
Value after Reset
31:0
PCI
PCI
0h
Register 11-92. (OQP; PCI:44h) Outbound Queue Port
Bit Description
Value written by the PCI Master is stored into the Outbound Free Queue, which is located in Local memory at the address pointed to by the Queue Base Address + 3*Queue Size + Outbound Free Head Pointer. From the time of the PCI write until the Local Memory write and update of the Outbound Free Queue Head Pointer, further accesses to this register result in a Retry. If the queue fills up, a Local NMI interrupt is asserted. When the port is read by the PCI Master, the value is read from the Outbound Post Queue, which is located in Local memory at the address pointed to by the Queue Base Address + 2*Queue Size + Outbound Post Tail Pointer. If the queue is empty, FFFFFFFFh is returned. A PCI interrupt is asserted if the Outbound Post Queue is not empty.
Read
Write
Value after Reset
31:0
PCI
PCI
0h
11-44
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Messaging Queue Registers
Section 11 Registers
Register 11-93. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration
Bit
0
Description
Queue Enable. Writing a 1 allows accesses to the Inbound and Outbound Queue ports. If cleared to 0, writes are accepted but ignored and reads return FFFFFFFFh. Circular Queue Size. Contains the size of one of the circular FIFO queues. Each of the four queues are the same size. Queue Size Encoding values: Bits [5:1] Number of entries Total size 00001 4-KB entries 64 KB 00010 8-KB entries 128 KB 00100 16-KB entries 256 KB 01000 32-KB entries 512 KB 10000 64-KB entries 1 MB Reserved.
Read
Yes
Write
Yes
Value after Reset
0
5:1
Yes
Yes
00001
31:6
Yes
No
0h
Register 11-94. (QBAR; PCI:C4h, LOC:144h) Queue Base Address
Bit
19:0 31:20 Reserved. Queue Base Address. Local Memory base address of circular queues. Queues must be aligned on a 1-MB boundary.
Description
Read
Yes Yes
Write
No Yes
Value after Reset
0h 0h
Register 11-95. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer
Bit
1:0 19:2 31:20 Reserved. Inbound Free Head Pointer. Local Memory Offset for the Inbound Free Queue. Maintained by the Local CPU software. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
Register 11-96. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer
Bit
1:0 19:2 31:20 Reserved. Inbound Free Tail Pointer. Local Memory offset for the Inbound Free Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
Register 11-97. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer
Bit
1:0 19:2 31:20 Reserved. Inbound Post Head Pointer. Local Memory offset for the Inbound Post Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-45
Section 11--Registers
Section 11 Registers
Messaging Queue Registers
Register 11-98. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer
Bit
1:0 19:2 31:20 Reserved. Inbound Post Tail Pointer. Local Memory offset for the Inbound Post Queue. Maintained by the Local CPU software. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
Register 11-99. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer
Bit
1:0 19:2 31:20 Reserved. Outbound Free Head Pointer. Local Memory offset for the Outbound Free Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
Register 11-100. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer
Bit
1:0 19:2 31:20 Reserved. Outbound Free Tail Pointer. Local Memory offset for the Outbound Free Queue. Maintained by the Local CPU software. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
Register 11-101. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer
Bit
1:0 19:2 31:20 Reserved. Outbound Post Head Pointer. Local Memory offset for the Outbound Post Queue. Maintained by the Local CPU software. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
Register 11-102. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer
Bit
1:0 19:2 31:20 Reserved. Outbound Post Tail Pointer. Local Memory offset for the Outbound Post Queue. Maintained by the hardware and incremented modulo the queue size. Queue Base Address.
Description
Read
Yes Yes Yes
Write
No Yes No
Value after Reset
00 0h 0h
11-46
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Messaging Queue Registers
Section 11 Registers
Register 11-103. (QSR; PCI:E8h, LOC:168h) Queue Status/Control
Bit Description
I2O Decode Enable. When set, replaces the MBOX0 and MBOX1 registers with the Inbound and Outbound Queue Port registers and redefines Space 1 as PCI Base Address 0 to be accessed by PCIBAR0. Former Space 1 registers LAS1RR, LAS1BA, and LBRD1 should be programmed to configure their shared I2O Memory space, defined as PCI Base Address 0. Queue Local Space Select. When set to 0, use the Local Address Space 0 Bus Region descriptor for Queue accesses. When set to 1, use the Local Address Space 1 Bus Region descriptor for Queue accesses. Outbound Post Queue Prefetch Enable. Writing a 1 causes prefetching to occur from the Outbound Post Queue if it is not empty. Inbound Free Queue Prefetch Enable. Writing a 1 causes prefetching to occur from the Inbound Free Queue if it is not empty. Inbound Post Queue Interrupt Mask. Writing a 1 masks the interrupt. Inbound Post Queue Interrupt Not Empty. Set when the Inbound Post Queue is not empty. Not affected by the Interrupt Mask bit. Outbound Free Queue Overflow Interrupt Mask. When set to 1, masks the interrupt. Value of 0 clears the mask. Outbound Free Queue Overflow Interrupt Full. Set when the Outbound Free Queue becomes full. A Local TEA#/LSERR# (NMI) interrupt is asserted. Writing a 1 clears the interrupt. Unused.
Read
Write
Value after Reset
0
Yes
Yes
0
1
Yes
Yes
0
2 3 4 5 6
Yes Yes Yes Yes Yes
Yes Yes Yes No Yes
0 0 1 0 1
7 31:8
Yes Yes
Yes/Clr No
0 0h
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
11-47
Section 11--Registers
12
12.1
PIN DESCRIPTION
PIN SUMMARY
The IDDQEN# pin has an internal pull-down resistor. The pins in the following table have internal pull-up resistors.
Tables in this section describe each PCI 9056 pin. Table 12-4 through Table 12-9 provide pin information common to all Local Bus modes of operation: * PCI System Bus Interface * JTAG * CompactPCI Hot Swap * System * Serial EEPROM Interface * Power and Ground Pins in Table 12-10 through Table 12-12 correspond to the PCI 9056 Local Bus modes--M, C, and J: * M Bus Mode Interface Pin Description (32-bit address/32-bit data, non-multiplexed) * C Bus Mode Interface Pin Description (32-bit address/32-bit data, non-multiplexed) * J Bus Mode Interface Pin Description (32-bit address/32-bit data, multiplexed) For a visual view of the chip pinout, refer to Section 14, "Physical Specs." All Local Bus internal pull-up resistors go through a 50K-ohm resistor. All Local Bus internal pull-down resistors go through a 50K-ohm resistor. All Local I/O pins should have external pull-up or pull-down resistors, which depend upon the application and pin polarity. (Use approximately 3K to 10K ohms.) This is recommended due to the weak value of the internal pull-up and pull-down resistors. Unspecified pins are not connected (NC).
Note for PCI Pins: DO NOT pull any pins up or down unless the PCI 9056 is being used in an embedded design. Refer to PCI r2.2, page 138.
Table 12-1. Pins with Internal Pull-Up Resistors
ADS# BLAST# DACK0# DREQ1# LA[31:30] C, J Modes LBE[3:0]# LINTo# MDREQ#/ DMPAF/EOT# TA# WAIT# BDIP# BTERM# DACK1# EEDI/EEDO LA[0:1] M Mode LD[31:0] C Mode LRESET# PMEREQ# TEA# BI# BURST# DP[3:0] HOSTEN# LA[3:31] M Mode LD[0:31] M Mode LSERR# RD/WR# TS# BIGEND#/ WAIT# CCS# DREQ0# LA[28:2] C, J Modes LAD[31:0] J Mode LINTi# LW/R# READY# TSIZ[0:1]
The pins in the following table have no internal resistors. A pull-up or pull-down resistor is recommended, based upon the pin functionality.
Table 12-2. Pins with No Internal Resistors
BB# BREQo LA2 M Mode MODE1 BG# EECS LHOLD RETRY# BR# EESK LHOLDA USERo/ LLOCKo# BREQi LA29 C, J Modes MODE0 USERi/ LLOCKi#
Notes: Due to the complexity of pin multiplexing, LA[29] (C mode) or LA[2] (M mode), requires an external pull-up resistor. In J mode, ALE requires a pull-down resistor. Refer to Table 2-18 or Table 4-18 for pull-up and pull-down resistor requirements for the EEDI/EEDO pin.
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-1
Section 12--Pin Description
Section 12 Pin Description
Pin Summary
The following table lists abbreviations used in this section to represent various pin types.
Table 12-3. Pin Type Abbreviations
Abbreviation
I/O I O TS OC or OD TP STS DTS Input and output Input only Output only Three-state Open collector or open drain Totem pole Sustained three-state, driven high for one CLK before float Driven three-state, driven high for one-half CLK before float
Pin Type
12-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Pinout Common to All Bus Modes
Section 12 Pin Description
12.2
PINOUT COMMON TO ALL BUS MODES
Table 12-4. PCI System Bus Interface Pins
Symbol Signal Name Total Pins Pin Type Pin Number
C4, A2, D4, C3, B2, B1, A1, C2, C1, D2, E3, D1, F3, E1, F2, F1, K3, L1, L2, L3, M1, N1, L4, M3, P1, N3, M4, P2, T1, R1, R2, P3
Function
AD[31:0]
Address and Data
32
I/O TS PCI
PCI multiplexed address/data bus.
C/BE[3:0]#
Bus Command and Byte Enables
4
I/O TS PCI
E4, G3, K2, N2
All multiplexed on the same PCI pins. During the Address phase of a transaction, defines the bus command. During the Data phase, used as byte enables. Refer to the PCI r2.2 for further detail if needed.
DEVSEL#
Device Select
1
H3
FRAME#
Cycle Frame
1
I/O STS PCI
G2
Driven by the current Master to indicate beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, Data transfers continue. When FRAME# is de-asserted, the transaction is in the final Data phase. GNT0#: When the internal PCI arbiter is enabled, the PCI GNT0# signal is an output to an arbitrating master. The PCI 9056 arbiter asserts GNT0# to grant the PCI Bus to the master. REQ#: When the internal PCI arbiter is disabled, GNT0# becomes the REQ# output from the PCI 9056 to an external arbiter. The PCI 9056 asserts REQ# to request the PCI Bus. When the internal PCI arbiter is enabled, the PCI GNT[6:1]# signals are outputs, one each to an arbitrating master. The PCI 9056 arbiter asserts one of the GNT# signals to grant the PCI Bus to the corresponding master. Note: PCI Arbiter pins are type "TP" when the PCI arbiter is enabled. Otherwise, they are left floating.
GNT0#
Internal Arbiter Grant 0
O
REQ#
External Arbiter Request
1
O STS PCI
A3
GNT[6:1]#
Internal Arbiter Grant 6-1
6
O TP
T5, R5, R4, N5, T3, T2
IDSEL
Initialization Device Select
1
I
D3
Used as a chip select during Configuration Read and Write transactions. As an input, it is available only if HOSTEN# is asserted (drives LINTo# onto a Local Bus to a Local processor). The PCI 9056 is a PCI Host. As an output, the PCI 9056 drives INTA# to perform a PCI Interrupt request. Indicates ability of the initiating agent (Bus Master) to complete the current Data phase of the transaction.
INTA#
Interrupt A
1
I/O OC PCI I/O STS PCI
B4
IRDY#
Initiator Ready
1
G1
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-3
Section 12--Pin Description
I/O STS PCI
When actively driven, indicates the driving device has decoded its address as the Target of the current access. As input, indicates whether any device on the bus is selected.
Section 12 Pin Description
Pinout Common to All Bus Modes
Table 12-4. PCI System Bus Interface Pins (Continued)
Symbol
LOCK# Lock
Signal Name
Total Pins
1
Pin Type
I/O STS PCI
Pin Number
H1
Function
Indicates an atomic operation that may require multiple transactions to complete. Even parity across AD[31:0] and C/BE[3:0]#. All PCI agents require parity generation. PAR is stable and valid one clock after the Address phase. For Data phases, PAR is stable and valid one clock after either IRDY# is asserted on a Write transaction or TRDY# is asserted on a Read transaction. Once PAR is valid, it remains valid until one clock after the current Data phase completes. Provides timing for all transactions on PCI and is an input to every PCI device. The PCI 9056 PCI Bus operates up to 66 MHz. Reports data parity errors during all PCI transactions, except during a special cycle. Asserted to alert system to a power management event. Multiplexed input pin. REQ0#: When the internal PCI arbiter is enabled, the PCI REQ0# signal is an input from an arbitrating master. REQ0# is asserted to the PCI 9056 arbiter by the master to request the PCI Bus. GNT#: When the internal PCI arbiter is disabled, REQ0# becomes the GNT# input to the PCI 9056 from an external arbiter. The arbiter asserts GNT# to grant the PCI Bus to the PCI 9056. REQ[6:1]# are not used. When the internal PCI arbiter is enabled, the PCI REQ[6:1]# signals are inputs, one each from an arbitrating master. REQ[6:1]# is asserted to the PCI 9056 arbiter by the corresponding master to request the PCI Bus. As an input, used to bring PCI-specific registers, sequencers, and signals to a consistent state. As an output, available only if HOSTEN# is asserted, causing the entire PCI Bus to reset by way of LRESET# assertion. The PCI 9056 is a PCI Host. As an input, available only if HOSTEN# is asserted, causing TEA#/LSERR# to be asserted any time the PCI error occurs. The PCI 9056 is a PCI Host. As an output, reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result is catastrophic.
PAR
Parity
1
I/O TS PCI
K1
PCLK
Clock
1
I I/O STS PCI O OC PCI
J1
PERR#
Parity Error
1
J2
PME#
Power Management Event
1
A6
REQ0#
Internal Arbiter Request 0
GNT#
External Arbiter Grant
1
I
D5
REQ[6:1]#
Internal Arbiter Request 6-1
6
I
R6, N6, T4, P5, R3, P4
RST#
Reset
1
I/O
C5
SERR#
Systems Error
1
I/O OC PCI
J3
12-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Pinout Common to All Bus Modes
Section 12 Pin Description
Table 12-4. PCI System Bus Interface Pins (Continued)
Symbol
STOP# Stop
Signal Name
Total Pins
1
Pin Type
I/O STS PCI I/O STS PCI
Pin Number
H2
Function
Indicates the current Target is requesting that the Master stop the current transaction. Indicates ability of the Target agent (selected device) to complete the current Data phase of the transaction.
TRDY# Total
Target Ready
1 64
H4
Table 12-5. JTAG Pins
Symbol
TCK
Signal Name
Test Clock Input
Total Pins
1
Pin Type
I
Pin Number
B5
Function
Clock source for the PCI 9056 test access port (TAP). Legal rates for TCK are either equal to the LCLK rate or less than one-half the LCLK rate.
TDI
Test Data Input
1
I
D6
TDO
Test Data Output
1
O TS PCI I I
A4
Used to transmit serial data from the PCI 9056 TAP. Data from the selected shift register is shifted out of TDO. Sampled by the TAP on the rising edge of TCK. The TAP state machine uses the TMS pin to determine the TAP mode. Resets JTAG.
TMS TRST# Total
Test Mode Select Test Reset
1 1 5
A5 C6
Table 12-6. CompactPCI Hot Swap Pins
Symbol
BD_SEL#
Signal Name
CompactPCI Board Select
Total Pins
1
Pin Type
I
Pin Number
B6
Function
CompactPCI board select for Hot Swap system. For non-CompactPCI systems, this pin should be grounded. Input that monitors CompactPCI board latch status. For non-CompactPCI systems, this pin should be pulled high. Interrupt output asserted when an adapter using PCI 9056 has been inserted or is ready to be removed from a PCI slot. Activates the CompactPCI Hot Swap board indicator LED.
CPCISW
CompactPCI Switch Sense
1
I O OC PCI O TP 24 mA
T6
ENUM#
Enumeration
1
P6
LEDon# Total
CompactPCI LED On
1 4
N7
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-5
Section 12--Pin Description
Used to input data into the TAP. When the TAP enables this pin, it is sampled on the rising edge of TCK and the sampled value is input to the selected TAP shift register.
Section 12 Pin Description
Pinout Common to All Bus Modes
Table 12-7. System Pins
Symbol Signal Name Total Pins Pin Type Pin Number Function
Provides main power status to the PCI 9056 D3cold Power Management logic. For all normal operations, this pin should be connected directly to the 3.3V power line. For IDDQ' tests. the pin should be grounded. Selects the PCI 9056 bus operation mode: Mode 0 Mode 1 Bus Mode 1 1 M 0 0 C 1 0 J 0 1 Reserved When asserted, configures the PCI 9056 as a host bridge, setting reset and interrupt signal directions for system board applications. When de-asserted, configures the PCI 9056 as a peripheral bridge, setting reset and interrupt signal directions for peripheral board applications.
IDDQEN#
Buffered PCI Frame
1
I
B7
MODE[1:0]
Bus Mode
2
I
A15, B15
HOSTEN#
Host Enable
1
I
B12
Total
4
Table 12-8. Serial EEPROM Interface Pins
Symbol
EECS
Signal Name
Serial EEPROM Chip Select
Total Pins
1
Pin Type
O TP 12 mA I/O TP (TS if CNTRL[31]=1) 12 mA O TP 12 mA
Pin Number
A8
Function
Serial EEPROM chip select.
EEDI/EEDO
Serial EEPROM Data IN/ Serial EEPROM Data OUT
1
C8
Multiplexed Write and Read data to the serial EEPROM pin.
EESK Total
Serial Data Clock
1 3
B8
Serial EEPROM clock pin.
12-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Pinout Common to All Bus Modes
Section 12 Pin Description
Table 12-9. Power and Ground Pins
Symbol Signal Name Total Pins Pin Type Pin Number Function
2.5V to PME logic during D3cold state. For Power Management systems, connect directly to 2.5V regulated power line from Card_VAUX. Otherwise, connect directly to 2.5V power line. 3.3V to PME logic during D3cold state. Refer to the PCI Power Mgmt. r1.1, Figure 12. For non-Power Management systems, connect directly to 3.3V. When sampled as 1, 3.3VAUX power is present and PME# assertion in D3cold is supported. When sampled as 0, 3.3VAUX power is not present and PME# assertion in D3cold is not supported by the PME_Support D3cold bit (PMC[15]). Refer to the PCI Power Mgmt. r1.1 Figure 12. For non-Power Management systems, connect directly to ground.
2.5VAUX
PME 2.5V D3cold Power
1
I
D7
Card_VAUX
PME 3.3V D3cold Power
1
I
A7
PRESENT_DET
3.3V VAUX Present Detect Power
1
I
D8
VIO
PCI System Voltage
4
I
B3, E2, M2, N4 E7, E8, E10, G5, G12, H5, H12, J12, K5, K12, M7, M8, M10
System voltage select, 3.3 or 5V, from PCI Bus.
VRING
I/O Ring Power
13
I
3.3V to I/O ring.
VSS
Ground
55
I
E5, E6, E9, E11, E12, F5-F12, G4, G6-G11, G13, H6-H11, J4-J11, Ground. J13, K6-K11, L5-L12, M5, M6, M9, M11, M12
Total
81
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-7
Section 12--Pin Description
VCORE
Core Power
6
I
D9, F4, F13, K4, K13, N9
2.5V to core.
Section 12 Pin Description
M Bus Mode Pinout
12.3
M BUS MODE PINOUT
Table 12-10. M Mode Local Bus Pins
Symbol Signal Name Total Pins Pin Type Pin Number Function
As an input, the PCI 9056 monitors this signal to determine whether an external Master has ended a Bus cycle. As an output, the PCI 9056 asserts this signal after an external arbiter has granted ownership of the Local Bus and BB# is inactive from another Master. It is recommended to use an external pull-up resistor value of 4.7K ohms be applied to guarantee a fast transition to the inactive state when the PCI 9056 relinquishes ownership of the Local Bus. As an input, driven by the Bus Master during a Burst transaction. The Master de-asserts before the last Data phase on the bus. As an output, driven by the PCI 9056 during the Data phase of a Burst transaction. The PCI 9056 de-asserts before the last Burst Data phase on the bus. Asserted by the Local Bus arbiter in response to BR#. Indicates the requesting Master is next. When asserted, indicates that the Target device does not support Burst transactions. Multiplexed input/output pin. BIGEND#: Can be asserted during the Local Bus Address phase of a Direct Master transfer or Configuration register access to specify use of Big Endian Byte ordering. Big Endian Byte order for Direct Master transfers or Configuration register accesses is also programmable through the Configuration registers. WAIT#: If wait is selected, then the PCI 9056 issues WAIT# when it is a Master on the Local Bus and has internal wait states setup. As a Slave, the PCI 9056 accepts WAIT# as an input from the Bus Master. Asserted by the Master to request use of the Local Bus. The Local Bus arbiter asserts BG# when the Master is next in line for bus ownership. As an input, driven by the Master along with address and data indicating a Burst transfer is in progress. As an output, driven by the PCI 9056 along with address and data indicating a Burst transfer is in progress. Internal PCI 9056 registers are selected when CCS# is asserted low.
BB#
Bus Busy
1
I/O OC 24 mA
A13
BDIP#
Burst Data in Progress
1
I/O TS 24 mA
C12
BG# BI#
Bus Grant Burst Inhibit
1 1
I I
B14 E13
BIGEND#
Big Endian Select
I
1 WAIT# WAIT Input/Output Select I/O TS 24 mA
A9
BR#
Bus Request
1
O TP 24 mA
A16
BURST#
Burst
1
I/O TS 24 mA
A14
CCS#
Configuration Register Select
1
I
B9
12-8
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Bus Mode Pinout
Section 12 Pin Description
Table 12-10. M Mode Local Bus Pins (Continued)
Symbol Signal Name Total Pins Pin Type
O TP 24 mA
Pin Number
Function
When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed. Corresponds to PCI 9056 DMA Channel 0. When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed. Corresponds to PCI 9056 DMA Channel 1. Parity is even for each of up to four byte lanes on the Local Bus. Parity is checked for writes or reads to the PCI 9056. Parity is asserted for reads from or writes by the PCI 9056. When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. Corresponds to PCI 9056 DMA Channel 0. When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. Corresponds to PCI 9056 DMA Channel 1.
DACK0#
DMA Channel 0 Demand Mode Acknowledge
1
C9
DACK1#
DMA Channel 1 Demand Mode Acknowledge
1
O TP 24 mA
B10
DP[0:3]
Data Parity
4
I/O TS 24 mA
D13, C14, B16, D14
DREQ0#
DMA Channel 0 Demand Mode Request
1
I
A10
DREQ1#
DMA Channel 1 Demand Mode Request
1
I
C10
LA[0:31]
Address Bus
32
I/O TS 24 mA
P7, R7, T7, N8, P8, R8, T8, T9, R9, P9, T10, R10, P10, T11, N10, P11, R11, T12, R12, T13, N11, P12, T14, R13, N12, P13, T15, R14, R15, N13, R16, N14 D16 P16, M13, N15, M14, L13, N16, M15, L14, L15, M16, L16, K14, K15, K16, J14, J15, J16, H16, H15, H14, H13, G16, G15, G14, F16, E16, F15, F14, E15, D15, E14, C16 C11
Carries the 32 bits of the physical Address Bus.
LCLK
Local Processor Clock
1
I
Local clock input.
LD[0:31]
Data Bus
32
I/O TS 24 mA
Carries 8-, 16-, or 32-bit data quantities, depending upon bus-width configuration. All Master accesses to the PCI 9056 are 32 bits only.
LINTi#
Local Interrupt Input
1
I
When asserted, causes a PCI interrupt. Synchronous level output that remains asserted as long as an interrupt condition exists. If an edge-level interrupt is required, disabling and then enabling Local interrupts through INTCSR creates an edge if an interrupt condition continues or a new interrupt condition occurs.
LINTo#
Local Interrupt Output
1
O OC 24 mA
B11
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-9
Section 12--Pin Description
Section 12 Pin Description
M Bus Mode Pinout
Table 12-10. M Mode Local Bus Pins (Continued)
Symbol Signal Name Total Pins Pin Type Pin Number Function
As an input, available only if HOSTEN# is asserted, causing RST# to be asserted on the PCI Bus. The PCI 9056 is a PCI Host. As an output, asserted when the PCI 9056 chip is in reset. Can be used to reset the back-end logic on the board. Multiplexed input/output pin. MDREQ#: IDMA M mode Data transfer request start. Always asserted, indicating Data transfer should start. De-asserted only when the Direct Master FIFO becomes full. Programmable through a Configuration register. DMPAF: Direct Master Write FIFO Almost Full status output. Programmable through a Configuration register. EOT#: Terminates the current DMA transfer. Note: EOT# serves as a general purpose EOT. Before asserting EOT#, user should be aware of DMA channel activity. Request a Power Management Event during a D3cold power state. Other Power Management Events should be done through the PCI 9056 Power Management registers. Asserted high for reads and low for writes. Driven by the PCI 9056 when it is a Slave to indicate a Local Master must back off and restart the cycle. In Delayed Read mode, indicates the Master should return for requested data. As an input, when the PCI 9056 is a Bus Master, indicates a Write Data transfer is complete or that Read data on the bus is valid. As an output, when a Local Bus access is made to the PCI 9056, indicates a Write Data transfer is complete or that Read data on the bus is valid. Driven by the Target device, indicating an error condition occurred during a Bus cycle. Indicates the valid address and start of new Bus access. Asserted for the first clock of a Bus access. Driven by current Master along with the address, indicating the data-transfer size. Refer to Section 3.4.3.7.3 for more information.
LRESET#
Local Bus Reset
1
I/O TP 24 mA
D11
MDREQ#
IDMA Data Transfer Request (Available at this location in M mode only) Direct Master Programmable Almost Full 1 End of Transfer for Current DMA Channel
O TS 24 mA O TS 24 mA I
DMPAF
A12
EOT#
PMEREQ#
PME Request
1
I
C7
RD/WR#
Read/Write
1
I/O TS 24 mA O OC 24 mA
P14
RETRY#
Retry
1
B13
TA#
Transfer Acknowledge
1
I/O DTS 24 mA
C15
TEA#
Transfer Error Acknowledge
1
I/O OC 24 mA I/O TS 24 mA I/O TS 24 mA
C13
TS#
Address Strobe
1
D12
TSIZ[0:1]
Transfer Size
2
T16, P15
12-10
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M Bus Mode Pinout
Section 12 Pin Description
Table 12-10. M Mode Local Bus Pins (Continued)
Symbol
USERi
Signal Name
User Input
Total Pins
Pin Type
I
Pin Number
Function
Multiplexed input pin. USERi: General-purpose input that can be read by way of the PCI 9056 Configuration registers. LLOCKi#: Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9056 for direct Local access to the PCI Bus. Multiplexed output pin.
LLOCKi#
Local Lock Input
1
I
A11
USERo
User Output
O TS 24 mA 1 D10 O
LLOCKo#
Local Lock Output
USERo: General-purpose output controlled from the PCI 9056 Configuration registers. LLOCKo#: Indicates an atomic operation for a Direct Slave PCI-to-Local Bus access may require multiple transactions to complete.
Total
95
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-11
Section 12--Pin Description
Section 12 Pin Description
C Bus Mode Pinout
12.4
C BUS MODE PINOUT
Table 12-11. C Mode Local Bus Pins
Symbol
ADS#
Signal Name
Address Strobe
Total Pins
1
Pin Type
I/O TS 24 mA
Pin Number
D12
Function
Indicates valid address and start of new Bus access. Asserted for first clock of Bus access. Can be asserted during the Local Bus Address phase of a Direct Master transfer or Configuration register access to specify use of Big Endian Byte ordering. Big Endian Byte order for Direct Master transfers or Configuration register accesses is also programmable through the Configuration registers. Signal driven by the current Local Bus Master to indicate the last transfer in a Bus access. As an output, asserted by the PCI 9056 after internal wait states have expired (WAIT# de-asserted). Internal wait states are programmed in LAS0BRD[5:2] and/or LAS1BRD[5:2]. Asserted to indicate a Local Bus Master requires the bus. If enabled through the PCI 9056 Configuration registers, the PCI 9056 releases the bus during a DMA transfer if this signal is asserted. Asserted to indicate the PCI 9056 requires the bus to perform a Direct Slave PCI-to-Local Bus access while a Direct Master access is pending on the Local Bus. Can be used with external logic to assert back off to a Local Bus Master. Operational parameters are set up through the PCI 9056 Configuration registers. As input to the PCI 9056: For processors that burst up to four Lwords. If the BTERM# Mode bit is disabled through the PCI 9056 Configuration registers, the PCI 9056 also bursts up to four Lwords. If enabled, the PCI 9056 continues to burst until a BTERM# input is asserted. BTERM# is a Ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9056 programmable wait state generator. As output from the PCI 9056: Asserted, along with READY#, to request break up of a burst and start of a new Address cycle (PCI aborts only). Internal PCI 9056 registers are selected when CCS# is asserted low. When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed. Corresponds to PCI 9056 DMA Channel 0. When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed.
BIGEND#
Big Endian Select
1
I
A9
BLAST#
Burst Last
1
I/O TS 24 mA
A14
BREQi
Bus Request
1
I
A13
BREQo
Bus Request Out
1
O OC 24 mA
B13
BTERM#
Burst Terminate
1
I/O DTS 24 mA
E13
CCS#
Configuration Register Select
1
I
B9
DACK0#
DMA Channel 0 Demand Mode Acknowledge
1
O TP 24 mA
C9
DACK1#
DMA Channel 1 Demand Mode Acknowledge
1
O TP 24 mA
B10
12-12
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C Bus Mode Pinout
Section 12 Pin Description
Table 12-11. C Mode Local Bus Pins (Continued)
Symbol
DMPAF
Signal Name
Direct Master Programmable Almost Full
Total Pins
Pin Type
O TS 24 mA
Pin Number
Function
Multiplexed input/output pin. DMPAF: Direct Master Write FIFO Almost Full status output. Programmable through a Configuration register. EOT#: Terminates the current DMA transfer. Note: EOT# serves as a general purpose EOT. Before asserting EOT#, user should be aware of DMA channel activity.
EOT#
End of Transfer for Current DMA Channel
1
I
A12
DP[3:0]
Data Parity
4
I/O TS 24 mA
D13, C14, B16, D14
Parity is even for each of up to four byte lanes on the Local Bus. Parity is checked for writes or reads to the PCI 9056. Parity is asserted for reads from or writes by the PCI 9056. When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. Corresponds to PCI 9056 DMA Channel 0. When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. Corresponds to PCI 9056 DMA Channel 1.
DREQ0#
DMA Channel 0 Demand Mode Request
1
I
A10
DREQ1#
DMA Channel 1 Demand Mode Request
1
I
C10
LA[31:2]
Address Bus
30
I/O TS 24 mA
P7, R7, T7, N8, P8, R8, T8, T9, R9, P9, T10, R10, P10, T11, N10, P11, R11, T12, R12, T13, N11, P12, T14, R13, N12, P13, T15, R14, R15, N13
Carries the upper 30 bits of physical Address Bus. During bursts, LA[31:2] increment to indicate successive Data cycles.
LBE[3:0]#
Byte Enables
4
I/O TS 24 mA
T16, P15, R16, N14
Encoded, based on the bus-width configuration, as follows: 32-Bit Bus The four byte enables indicate which of the four bytes are active during a Data cycle: LBE3# Byte Enable 3--LD[31:24] LBE2# Byte Enable 2--LD[23:16] LBE1# Byte Enable 1--LD[15:8] LBE0# Byte Enable 0--LD[7:0] 16-Bit Bus LBE[3, 1:0]# are encoded to provide BHE#, LA1, and BLE#, respectively: LBE3# Byte High Enable (BHE#)--LD[15:8] LBE2# not used LBE1# Address bit 1 (LA1) LBE0# Byte Low Enable (BLE#)--LD[7:0] 8-Bit Bus LBE[1:0]# are encoded to provide LA[1:0], respectively: LBE3# not used LBE2# not used LBE1# Address bit 1 (LA1) LBE0# Address bit 0 (LA0)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-13
Section 12--Pin Description
Section 12 Pin Description
C Bus Mode Pinout
Table 12-11. C Mode Local Bus Pins (Continued)
Symbol
LCLK
Signal Name
Local Processor Clock
Total Pins
1
Pin Type
I
Pin Number
D16 P16, M13, N15, M14, L13, N16, M15, L14, L15, M16, L16, K14, K15, K16, J14, J15, J16, H16, H15, H14, H13, G16, G15, G14, F16, E16, F15, F14, E15, D15, E14, C16 A16 Local clock input.
Function
LD[31:0]
Data Bus
32
I/O TS 24 mA
Carries 8-, 16-, or 32-bit data quantities, depending upon bus-width configuration. All Master accesses to the PCI 9056 are 32 bits only.
LHOLD
Hold Request
1
O TP 24 mA
Asserted to request use of the Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. Asserted by the Local Bus arbiter when control is granted in response to LHOLD. Bus should not be granted to the PCI 9056 unless requested by LHOLD. When asserted, causes a PCI interrupt. Synchronous level output that remains asserted as long as an interrupt condition exists. If an edge-level interrupt is required, disabling and then enabling Local interrupts through INTCSR creates an edge if an interrupt condition continues or a new interrupt condition occurs. As an input, available only if HOSTEN# is asserted, causing RST# to be asserted on the PCI Bus. The PCI 9056 is a PCI Host. As an output, asserted when the PCI 9056 chip is in reset. Can be used to reset the back-end logic on the board. Synchronous level output asserted when the PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1). If an edge level interrupt is required, disabling and then enabling LSERR# interrupts through the interrupt/control status creates an edge if an interrupt condition still exists or a new interrupt condition occurs. Asserted low for reads and high for writes. Request a Power Management Event during a D3cold power state. Other Power Management Events should be done through the PCI 9056 Power Management registers.
LHOLDA
Hold Acknowledge
1
I
B14
LINTi#
Local Interrupt Input
1
I
C11
LINTo#
Local Interrupt Output
1
O OC 24 mA
B11
LRESET#
Local Bus Reset
1
I/O TP 24 mA
D11
LSERR#
System Error Interrupt Output
1
O OC 24 mA
C13
LW/R#
Write/Read
1
I/O TS 24 mA
P14
PMEREQ#
PME Request
1
I
C7
12-14
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C Bus Mode Pinout
Section 12 Pin Description
Table 12-11. C Mode Local Bus Pins (Continued)
Symbol Signal Name Total Pins Pin Type Pin Number Function
When the PCI 9056 is a Bus Master, indicates that Read data on the bus is valid or that a Write Data transfer is complete. READY# input is not sampled until the internal wait state counter expires (WAIT# output de-asserted). When a Local Bus access is made to the PCI 9056, indicates that Read data on the bus is valid or that a Write Data transfer is complete. READY# output is not asserted until the Local Master de-asserts the WAIT# input (requesting wait states). Multiplexed input pin. USERi: General-purpose input that can be read by way of the PCI 9056 Configuration registers. LLOCKi#: Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9056 for direct Local access to the PCI Bus. Multiplexed output pin. USERo: General-purpose output controlled from the PCI 9056 Configuration registers. LLOCKo#: Indicates an atomic operation for a Direct Slave PCI-to-Local Bus access may require multiple transactions to complete. As an input, can be asserted to cause the PCI 9056 to insert wait states for Local Direct Master accesses to the PCI Bus. Can be thought of as a Ready input from an external Master for Direct Master accesses. As an output, asserted by the PCI 9056 when internal wait state generator causes wait states. Can be thought of as an output providing PCI 9056 Ready status.
READY#
Ready Input/Output
1
I/O DTS 24 mA
C15
USERi
User Input 1 Local Lock Input
I A11 I
LLOCKi#
USERo
User Output 1
O TS 24 mA O
D10
LLOCKo#
Local Lock Output
WAIT#
Wait Input/Output Select
1
I/O TS 24 mA
C12
Total
95
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-15
Section 12--Pin Description
Section 12 Pin Description
J Bus Mode Pinout
12.5
J BUS MODE PINOUT
Table 12-12. J Mode Local Bus Pins
Symbol
ADS#
Signal Name
Address Strobe
Total Pins
1
Pin Type
I/O TS 24 mA I/O TS 24 mA
Pin Number
D12
Function
Indicates valid address and start of new Bus access. Asserted for first clock of Bus access. Asserted during Address phase and de-asserted before Data phase and before next LCLK rising edge. Can be asserted during the Local Bus Address phase of a Direct Master transfer or Configuration register access to specify use of Big Endian Byte ordering. Big Endian Byte order for Direct Master transfers or Configuration register accesses is also programmable through the Configuration registers. Signal driven by the current Local Bus Master to indicate the last transfer in a Bus access. As an output, asserted by the PCI 9056 after internal wait states have expired (WAIT# de-asserted). Internal wait states are programmed in LAS0BRD[5:2] and/or LAS1BRD[5:2]. Asserted to indicate a Local Bus Master requires the bus. If enabled through the PCI 9056 Configuration registers, the PCI 9056 releases the bus during a DMA transfer if this signal is asserted. Asserted to indicate the PCI 9056 requires the bus to perform a Direct Slave PCI-to-Local Bus access while a Direct Master access is pending on the Local Bus. Can be used with external logic to assert back off to a Local Bus Master. Operational parameters are set up through the PCI 9056 Configuration registers. As input to the PCI 9056: For processors that burst up to four Lwords. If the BTERM# Mode bit is disabled through the PCI 9056 Configuration registers, the PCI 9056 also bursts up to four Lwords. If enabled, the PCI 9056 continues to burst until a BTERM# input is asserted. BTERM# is a Ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9056 programmable wait state generator. As output from the PCI 9056: Asserted, along with READY#, to request break up of a burst and start of a new Address cycle (PCI aborts only). Internal PCI 9056 registers are selected when CCS# is asserted low. When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed. Corresponds to PCI 9056 DMA Channel 0.
ALE
Address Latch Enable
1
T7
BIGEND#
Big Endian Select
1
I
A9
BLAST#
Burst Last
1
I/O TS 24 mA
A14
BREQi
Bus Request
1
I
A13
BREQo
Bus Request Out
1
O OC 24 mA
B13
BTERM#
Burst Terminate
1
I/O DTS 24 mA
E13
CCS#
Configuration Register Select
1
I
B9
DACK0#
DMA Channel 0 Demand Mode Acknowledge
1
O TP 24 mA
C9
12-16
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
J Bus Mode Pinout
Section 12 Pin Description
Table 12-12. J Mode Local Bus Pins (Continued)
Symbol Signal Name
DMA Channel 1 Demand Mode Acknowledge
Total Pins
Pin Type
O TP 24 mA O TS 24 mA O TS 24 mA
Pin Number
Function
When a channel is programmed through the Configuration registers to operate in Demand mode, this output indicates a DMA transfer is being executed. Used in conjunction with DT/R# to provide control for data transceivers attached to the Local Bus. Multiplexed input/output pin. DMPAF: Direct Master Write FIFO Almost Full status output. Programmable through a Configuration register. EOT#: Terminates the current DMA transfer. Note: EOT# serves as a general purpose EOT. Before asserting EOT#, user should be aware of DMA channel activity.
DACK1#
1
B10
DEN#
Data Enable
1
R7
DMPAF
Direct Master Programmable Almost Full 1
EOT#
End of Transfer for Current DMA Channel
I
A12
DP[3:0]
Data Parity
4
I/O TS 24 mA
D13, C14, B16, D14
DREQ0#
DMA Channel 0 Demand Mode Request
1
I
A10
When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. Corresponds to PCI 9056 DMA Channel 0. When a channel is programmed through the Configuration registers to operate in Demand mode, this input serves as a DMA request. Corresponds to PCI 9056 DMA Channel 1. Used in conjunction with DEN# to provide control for data transceivers attached to the Local Bus. When asserted, indicates the PCI 9056 receives data.
DREQ1#
DMA Channel 1 Demand Mode Request
1
I
C10
DT/R#
Data Transmit/Receive
1
O TS 24 mA
P7
LA[28:2]
Local Address Bus
27
I/O TS 24 mA
N8, P8, R8, T8, T9, R9, P9, T10, R10, P10, T11, N10, P11, R11, T12, R12, T13, N11, P12, T14, R13, N12, P13, T15, R14, R15, N13 P16, M13, N15, M14, L13, N16, M15, L14, L15, M16, L16, K14, K15, K16, J14, J15, J16, H16, H15, H14, H13, G16, G15, G14, F16, E16, F15, F14, E15, D15, E14, C16
Carries the middle 27 bits of the physical address bus. During bursts, it is incremented to indicate successive Data cycles. The lowest two bits, LA[3:2], carry the Word address of the 32-bit Memory address. All bits are incremented during a Burst access.
LAD[31:0]
Address/Data Bus
32
I/O TS 24 mA
During an Address phase, the bus carries the upper 30 bits of the physical Address Bus. During a Data phase, the bus carries 32 bits of data.
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-17
Section 12--Pin Description
Parity is even for each of up to four byte lanes on the Local Bus. Parity is checked for writes or reads to the PCI 9056. Parity is asserted for reads from or writes by the PCI 9056.
Section 12 Pin Description
J Bus Mode Pinout
Table 12-12. J Mode Local Bus Pins (Continued)
Symbol Signal Name Total Pins Pin Type Pin Number Function
Encoded, based on the bus-width configuration, as follows: 32-Bit Bus The four byte enables indicate which of the four bytes are active during a Data cycle: LBE3# Byte Enable 3--LAD[31:24] LBE2# Byte Enable 2--LAD[23:16] LBE1# Byte Enable 1--LAD[15:8] LBE0# Byte Enable 0--LAD[7:0] 16-Bit Bus LBE[3, 1:0]# are encoded to provide BHE#, LAD1, and BLE#, respectively: LBE3# Byte High Enable (BHE#)--LAD[15:8] LBE2# not used LBE1# Address bit 1 (LAD1) LBE0# Byte Low Enable (BLE#)--LAD[7:0] 8-Bit Bus LBE[1:0]# are encoded to provide LAD[1:0], respectively: LBE3# not used LBE2# not used LBE1# Address bit 1 (LAD1) LBE0# Address bit 0 (LAD0) Local clock input. Asserted to request use of the Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. Asserted by the Local Bus arbiter when control is granted in response to LHOLD. Bus should not be granted to the PCI 9056 unless requested by LHOLD. When asserted, causes a PCI interrupt. Synchronous level output that remains asserted as long as an interrupt condition exists. If an edge-level interrupt is required, disabling and then enabling Local interrupts through INTCSR creates an edge if an interrupt condition still exists or a new interrupt condition occurs. As an input, available only if HOSTEN# is asserted, causing RST# to be asserted on the PCI Bus. The PCI 9056 is a PCI Host. As an output, asserted when the PCI 9056 chip is in reset. Can be used to reset the back-end logic on the board. Synchronous level output asserted when the PCI Bus Target Abort bit is set (PCISR[11]=1) or Received Master Abort bit is set (PCISR[13]=1). If an edge level interrupt is required, disabling and then enabling LSERR# interrupts through the interrupt/control status creates an edge if an interrupt condition still exists or a new interrupt condition occurs.
LBE[3:0]#
Byte Enables
4
I/O TS 24 mA
T16, P15, R16, N14
LCLK LHOLD
Local Processor Clock Hold Request
1 1
I O TP 24 mA
D16 A16
LHOLDA
Hold Acknowledge
1
I
B14
LINTi#
Local Interrupt Input
1
I
C11
LINTo#
Local Interrupt Output
1
O OC 24 mA
B11
LRESET#
Local Bus Reset
1
I/O TP 24 mA
D11
LSERR#
System Error Interrupt Output
1
O OC 24 mA
C13
12-18
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
J Bus Mode Pinout
Section 12 Pin Description
Table 12-12. J Mode Local Bus Pins (Continued)
Symbol
LW/R#
Signal Name
Write/Read
Total Pins
1
Pin Type
I/O TS 24 mA
Pin Number
P14
Function
Asserted low for reads and high for writes. Request a Power Management Event during a D3cold power state. Other Power Management Events should be done through the PCI 9056 Power Management registers. When the PCI 9056 is a Bus Master, indicates that Read data on the bus is valid or that a Write Data transfer is complete. READY# input is not sampled until the internal wait state counter expires (WAIT# output de-asserted). When a Local Bus access is made to the PCI 9056, indicates that Read data on the bus is valid or that a Write Data transfer is complete. READY# output is not asserted until the Local Master de-asserts the WAIT# input (requesting wait states). Multiplexed input pin. USERi: General-purpose input that can be read by way of the PCI 9056 Configuration registers. LLOCKi#: Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9056 for direct Local access to the PCI Bus. Multiplexed output pin. USERo: General-purpose output controlled from the PCI 9056 Configuration registers. LLOCKo#: Indicates an atomic operation for a Direct Slave PCI-to-Local Bus access may require multiple transactions to complete. As an input, can be asserted to cause the PCI 9056 to insert wait states for Local Direct Master accesses to the PCI Bus. Can be thought of as a Ready input from an external Master for Direct Master accesses. As an output, asserted by the PCI 9056 when internal wait state generator causes wait states. Can be thought of as an output providing PCI 9056 Ready status.
PMEREQ#
PME Request
1
I
C7
READY#
Ready Input/Output
1
I/O DTS 24 mA
C15
USERi
User Input 1
I A11
LLOCKi#
Local Lock Input
I
USERo
User Output 1
O TS 24 mA O
D10
LLOCKo#
Local Lock Output
WAIT#
Wait Input/Output Select
1
I/O TS 24 mA
C12
Total
95
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
12-19
Section 12--Pin Description
Section 12 Pin Description
Debug Interface
12.6
DEBUG INTERFACE
Table 12-13. JTAG Instructions
Instruction
Extest Sample/Preload Bypass
The PCI 9056 provides a JTAG Boundary Scan interface which can be utilized to debug a pin's connectivity to the board.
Input Code
0000 0100 1111
Comments
IEEE 1149.1 standard IEEE 1149.1 standard IEEE 1149.1 standard
12.6.1 IEEE 1149.1 Test Access Port (JTAG Debug Port)
The IEEE 1149.1 Test Access Port (TAP), commonly called the JTAG (Joint Test Action Group) debug port, is an architectural standard described in IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture. The standard describes a method for accessing internal chip facilities using a four- or five-signal interface. The JTAG debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. The enhancements, which comply with IEEE Standard 1149.1-1990 for vendor-specific extensions, are compatible with standard JTAG hardware for boundary-scan system testing. * JTAG Signals--JTAG debug port implements the four required JTAG signals, TCLK, TMS, TDI, TDO, and the optional TRST# signal. * JTAG Clock Requirements--The TCLK signal frequency can range from DC to one-half of the internal chip clock frequency. * JTAG Reset Requirements--JTAG debug port logic is reset at the same time as a system reset. Upon receiving TRST#, the JTAG TAP controller returns to the Test-Logic Reset state.
Table 12-14. JTAG Infrared Outputs
Instruction
Extest Sample/Preload Bypass
IR Output
0001 0101 1101
Comments
IEEE 1149.1 standard IEEE 1149.1 standard IEEE 1149.1 standard
12.6.3 JTAG Boundary Scan
Boundary Scan Description Language (BSDL), IEEE Standard 1149.1b-1994, is a supplement to IEEE Standard 1149.1-1990 and IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture. BSDL, a subset of the IEEE Standard 1076-1993 VHSIC Hardware Description Language (VHDL), allows a rigorous description of testability features in components which comply with the standard. It is used by automated test pattern generation tools for package interconnect tests and electronic design automation (EDA) tools for synthesized test logic and verification. BSDL supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. The primary components of BSDL include the logical port description, physical pin map, instruction set, and boundary register description. The logical port description assigns symbolic names to the pins of a chip. Each pin has a logical type of in, out, inout, buffer, or linkage that defines the logical direction of signal flow.
12.6.2 JTAG Instructions
The JTAG debug port provides the standard extest, sample/preload, and bypass instructions. Invalid instructions behave as the bypass instruction. There are three private instructions. The following tables list the JTAG instructions and infrared (IR) outputs.
12-20
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Debug Interface
Section 12 Pin Description
The physical pin map correlates the logical ports of the chip to the physical pins of a specific package. A BSDL description can have several physical pin maps; each map is given a unique name. Instruction set statements describe the bit patterns that must be shifted into the Instruction Register to place the chip in the various test modes defined by the standard. Instruction set statements also support descriptions of instructions that are unique to the chip. The boundary register description lists each cell or shift stage of the Boundary Register. Each cell has a unique number; the cell numbered 0 is the closest to the Test Data Out (TDO) pin and the cell with the highest number is closest to the Test Data In (TDI) pin. Each cell contains additional information, including: * Cell type * Logical function of the cell * Safe value * Control cell number * Disable value * Result value
Section 12--Pin Description
Preliminary Information 12-21
* Logical port associated with the cell
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
13
13.1
ELECTRICAL SPECIFICATIONS
GENERAL ELECTRICAL SPECIFICATIONS
Table 13-1. Absolute Maximum Ratings
Specification
Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground (I/O VDD) Supply Voltage to Ground (Core VDD) Supply Voltage to Ground (VIO) Input Voltage (VIN) Output Voltage (VOUT) Maximum Package Power Dissipation -55 to +125 C -40 to +85 C -0.5 to +4.6V -0.5 to +3.6V -0.5 to +6.5V VSS -0.5 to 6.5V VSS -0.5V to VDD +0.5 1.5W
Maximum Rating
Table 13-2. Operating Ranges
Ambient Temperature
-40 to +85 C
Supply Voltage (I/O VDD)
3.0 to 3.6V
Supply Voltage (Core VDD)
2.3 to 2.7V
Input Voltage (VIN) Min
VSS
Max
VIO
Table 13-3. Capacitance (Sample Tested Only)
Value Parameter
CIN COUT
Test Conditions
VIN = 0V VOUT = 0V
Pin Type
Input Output
Typical
4 6
Maximum
6 10
Units
pF pF
The following table lists the package thermal resistance in C/W (j-a).
Table 13-4. Package Thermal Resistance
Linear Air Flow 0m/s
30
1m/s
22
2m/s
19
3m/s
17
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
13-1
Section 13--Electrical Specs
Section 13 Electrical Specifications
General Electrical Specifications
Table 13-5. Electrical Characteristics over Operating Range
Buffer Type
Parameter
Description
Test Conditions
Min
Max
Units
Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of this table.
13-2
Preliminary Information
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
General Electrical Specifications
Section 13 Electrical Specifications
Table 13-5. Electrical Characteristics over Operating Range (Continued)
Buffer Type
Parameter
Description
Test Conditions
Min
Max
Units
Refer to the document, PCI 9056 Blue Book Revision 0.91 Correction, for the corrected version of this table.
PCI 9056 Data Book, Version 0.91b (c) 2002 PLX Technology, Inc. All rights reserved.
Preliminary Information
13-3
13--Electrical Specifications
Section 13 Electrical Specifications
Local Inputs
13.2
LOCAL INPUTS
Local Clock T T Inputs
SETUP HO LD
Valid
Figure 13-1. PCI 9056 Local Input Setup and Hold Waveform Table 13-6. AC Electrical Characteristics (Local Inputs) over Operating Range (M Mode)
Signals (Synchronous Inputs) CL = 50 pF, VCC = 3.0V, Ta = 85 C
BB# BDIP#/WAIT# BG# BI# BIGEND#/WAIT# BURST# CCS# DP[0:3] LA[0:31] LD[0:31] MDREQ#/DMPAF/EOT# RD/WR# TA# TS# TSIZ[0:1] USERi/LLOCKi# DREQ0#
TSETUP (ns) (WORST CASE)
4.5
THOLD (ns) (WORST CASE)
1
4.5
4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.5
4.5 4.5
Input Clocks
Local Clock Input Frequency PCI Clock Input Frequency
Min
0 0
Max
66 MHz 66 MHz
13-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Inputs
Section 13 Electrical Specifications
Table 13-7. AC Electrical Characteristics (Local Inputs) over Operating Range (C and J Modes)
Signals (Synchronous Inputs) CL = 50 pF, VCC = 3.0V, Ta = 85 C
ADS# ALE BIGEND# BLAST# BREQi BTERM# CCS# DMPAF/EOT# DP[3:0] LAD[31:0] LBE[3:0]# LD[31:0] LHOLDA LW/R# READY# USERi/LLOCKi# DREQ0# WAIT# Bus Mode C, J J C, J C, J C, J C, J C, J C, J C, J J C, J C C, J C, J C, J C, J C, J C, J
TSETUP (ns) (WORST CASE)
4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5
THOLD (ns) (WORST CASE)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Input Clocks
Local Clock Input Frequency PCI Clock Input Frequency
Bus Mode
C, J C, J
Min
0 0
Max
66 MHz 66 MHz
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
13-5
Section 13--Electrical Specs
Section 13 Electrical Specifications
Local Outputs
13.3
LOCAL OUTPUTS
Local Clock
T
V A L ID
(MAX)
T
V A L ID
(MIN)
Outputs
Valid
Figure 13-2. PCI 9056 Local Output Delay
Table 13-8. AC Electrical Characteristics (Local Outputs) over Operating Range (M Mode)
Signals (Synchronous Outputs) CL = 50 pF, VCC = 3.0V, Ta = 85 C
BB# BDIP# BI# BIGEND#/WAIT# BR# BURST# DP[0:3] LA[0:31] LD[0:31] MDREQ#/DMPAF/EOT# RD/WR# RETRY# TA# TEA# TS# TSIZ[0:1] DACK0# USERo/LLOCKo# Notes: All TVALID (Min) values are greater than 5 ns.
Clock to Out Worst Case (ns) TVALID (Max)
9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0
Timing derating for loading is 35 PS/PF.
13-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Outputs
Section 13 Electrical Specifications
Table 13-9. AC Electrical Characteristics (Local Outputs) over Operating Range (C and J Modes)
Signals (Synchronous Outputs) CL = 50 pF, VCC = 3.0V, Ta = 85 C
ADS# BLAST# BREQo BTERM# DEN# DMPAF/EOT# DP[3:0] DT/R# LA[31:2] LA[28:2] LAD[31:0] LBE[3:0]# LD[31:0] LHOLD LSERR# LW/R# READY# DACK0# USERo/LLOCKo# WAIT# Notes: All TVALID (Min) values are greater than 5 ns. Timing derating for loading is 35 PS/PF. Bus Mode C, J C, J C, J C, J J C, J C, J J C J J C, J C C, J C, J C, J C, J C, J C, J C, J
Output TVALID (Max)
9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0
Local 1.5V Clock
1.5V Max. 24.2 ns Max. 11.6 ns
Max. 9.1 ns Address Bus
Figure 13-3. PCI 9056 ALE Output Delay to the Local Clock at 33 MHz Clock
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
13-7
Section 13--Electrical Specs
14
14.1
-A-
PHYSICAL SPECS
MECHANICAL DIMENSIONS
D D2 A (Note 3)
14-1
aaa A2 Seating Plane E2 E3
-BA1 CAB C 3 2 %%Cb A
T R P N M L K J H G F E D C B A 1234 56789
c
D3
Solder Ball
Detail "A"
E
(Note 2)
eee aaa fff
Top View
D1 e
"A"
B
C
1
Side View
Detail "B"
"B"
Notes: 1. Controlling Dimension: Millimeter 2. Primary Datum C and Seating Plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C. 4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. 5. Reference document: JEDEC MO-192.
Figure 14-1. Mechanical Dimensions--Top, Side, and Bottom Views
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Section 14--Physical Specs
Bottom View
E1
Section 14 Physical Specs
Ball Grid Assignments
14.2
BALL GRID ASSIGNMENTS
1 2 AD30 3 GNT0# or REQ# VIO 4 TDO 5 TMS 6 PME# 7 CARD_VAUX 8 EECS
A
AD25
B
AD26
AD27
INTA#
TCK
BD_SEL#
IDDQEN#
EESK EEDI/ EEDO PRESENT_DET
C
AD23
AD24
AD28
AD31
RST# REQ0# or GNT# VSS
TRST#
PMEREQ#
D
AD20
AD22
IDSEL
AD29
TDI
2.5VAUX
E
AD18
VIO
AD21
C/BE3#
VSS
VRING
VRING
F
AD16
AD17
AD19
VCORE
VSS
VSS
VSS
VSS
G
IRDY#
FRAME#
C/BE2#
VSS
VRING
VSS
VSS
VSS
H
LOCK#
STOP#
DEVSEL#
TRDY#
VRING
VSS
VSS
VSS
J
PCLK
PERR#
SERR#
VSS
VSS
VSS
VSS
VSS
K
PAR
C/BE1#
AD15
VCORE
VRING
VSS
VSS
VSS
L
AD14
AD13
AD12
AD9
VSS
VSS
VSS
VSS
M
AD11
VIO
AD8
AD5
VSS
VSS
VRING
VRING LA3 (M) LA28 (C,J) LA4 (M) LA27 (C,J) LA5 (M) LA26 (C,J) LA6 (M) LA25 (C,J)
N
AD10
C/BE0#
AD6
VIO
GNT3#
REQ5#
LEDon# LA0 (M) LA31 (C) DT/R# (J) LA1 (M) LA30 (C) DEN# (J) LA2 (M) LA29 (C) ALE (J)
P
AD7
AD4
AD0
REQ1#
REQ3#
ENUM#
R
AD2
AD1
REQ2#
GNT4#
GNT5#
REQ6#
T
AD3
GNT1#
GNT2#
REQ4#
GNT6#
CPCISW
Figure 14-2. Ball Grid Assignments (A1-A8 through T1-T8)
14-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Ball Grid Assignments
Section 14 Physical Specs
9 BIGEND# (all) WAIT# (M) CCS#
10 DREQ0#
11 USERi/ LLOCKi# LINTo#
12 MDREQ# (M) DMPAF (all) EOT# (all) HOSTEN# BDIP# (M) WAIT# (C,J) TS# (M) ADS# (C,J) VSS
13 BB# (M) BREQi (C,J) RETRY# (M) BREQo (C,J) TEA# (M) LSERR# (C,J) DP0 (M) DP3 (C,J) BI# (M) BTERM# (C,J) VCORE
14 BURST# (M) BLAST# (C,J) BG# (M) LHOLDA (C,J) DP1 (M) DP2 (C,J) DP3 (M) DP0 (C,J) LD30 (M) LD1 (C) LAD1 (J) LD27 (M) LD4 (C) LAD4 (J) LD23 (M) LD8 (C) LAD8 (J) LD19 (M) LD12 (C) LAD12 (J) LD14 (M) LD17 (C) LAD17 (J) LD11 (M) LD20 (C) LAD20 (J) LD7 (M) LD24 (C) LAD24 (J) LD3 (M) LD28 (C) LAD28 (J) LA31 (M) LBE0# (C,J) RD/WR#(M) LW/R# (C,J) LA27 (M) LA4 (C,J) LA22 (M) LA9 (C,J)
15 MODE1
16 BR# (M) LHOLD (C,J) DP2 (M) DP1 (C,J) LD31 (M) LD0 (C) LAD0 (J) LCLK LD25 (M) LD6 (C) LAD6 (J) LD24 (M) LD7 (C) LAD7 (J) LD21 (M) LD10 (C) LAD10 (J) LD17 (M) LD14 (C) LAD14 (J) LD16 (M) LD15 (C) LAD15 (J) LD13 (M) LD18 (C) LAD18 (J) LD10 (M) LD21 (C) LAD21 (J) LD9 (M) LD22 (C) LAD22 (J) LD5 (M) LD26 (C) LAD26 (J) LD0 (M) LD31 (C) LAD31 (J) LA30 (M) LBE1# (C,J) TSIZ0 (M) LBE3# (C,J) A
DACK1#
MODE0 TA# (M) READY# (C,J) LD29 (M) LD2 (C) LAD2 (J) LD28 (M) LD3 (C) LAD3 (J) LD26 (M) LD5 (C) LAD5 (J) LD22 (M) LD9 (C) LAD9 (J) LD18 (M) LD13 (C) LAD13 (J) LD15 (M) LD16 (C) LAD16 (J) LD12 (M) LD19 (C) LAD19 (J) LD8 (M) LD23 (C) LAD23 (J) LD6 (M) LD25 (C) LAD25 (J) LD2 (M) LD29 (C) LAD29 (J) TSIZ1 (M) LBE2# (C,J) LA28 (M) LA3 (C,J) LA26 (M) LA5 (C,J)
B
DACK0#
DREQ1# USERo/ LLOCKo# VRING
LINTi#
C
VCORE
LRESET#
D
VSS
VSS
E
VSS
VSS
VSS
VSS
F
VSS
VSS
VSS
VRING
VSS LD20 (M) LD11 (C) LAD11 (J) VSS
G
VSS
VSS
VSS
VRING
H
VSS
VSS
VSS
VRING
J
VSS
VSS
VSS
VRING
VCORE LD4 (M) LD27 (C) LAD27 (J) LD1 (M) LD30 (C) LAD30 (J) LA29 (M) LA2 (C,J) LA25 (M) LA6 (C,J) LA23 (M) LA8 (C,J) LA19 (M) LA12 (C,J)
K
VSS
VSS
VSS
VSS
L
VSS
VRING LA14 (M) LA17 (C,J) LA12 (M) LA19 (C,J) LA11 (M) LA20 (C,J) LA10 (M) LA21 (C,J)
VSS LA20 (M) LA11 (C,J) LA15 (M) LA16 (C,J) LA16 (M) LA15 (C,J) LA13 (M) LA18 (M)
VSS LA24 (M) LA7 (C,J) LA21 (M) LA10 (C,J) LA18 (M) LA13 (C,J) LA17 (M) LA14 (C,J)
M
VCORE LA9 (M) LA22 (M) LA8 (M) LA23 (C,J) LA7 (M) LA24 (C,J)
N
P
R
T
Figure 14-3. Ball Grid Assignments (A9-A16 through T9-T16)
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
14-3
Section 14--Physical Specs
A
A.1
GENERAL INFORMATION ORDERING INSTRUCTIONS
A.2 UNITED STATES AND INTERNATIONAL REPRESENTATIVES, AND DISTRIBUTORS
The PCI 9056 is a 32-bit, 66 MHz PCI I/O Accelerator featuring advanced PLX proprietary Data Pipe Architecture technology, which includes two DMA engines, programmable Direct Slave and Direct Master Data Transfer modes, and PCI messaging functions. The PCI 9056 offers 3.3V, 5V tolerant PCI and Local signaling, and supports Universal PCI Adapter designs, 3.3V core, low-power CMOS offered in a 256-pin (ball) PBGA. The device is designed to operate at Industrial Temperature range.
Table A-1. Available Package
Package
256-pin PBGA
A list of PLX Technology, Inc., representatives and distributors can be found at http://www.plxtech.com.
A.3
TECHNICAL SUPPORT
PLX Technology, Inc., technical support information is listed at http://www.plxtech.com; or call 408 774-9060 or 800 759-3735.
Ordering Part Number
PCI 9056-AA66BI
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
A-1
Appendix A--General Info
Index
A
Abort 6-2 DMA 3-23, 5-22 PCI Master/Target 3-8, 5-7-5-8, 11-9, 11-31 absolute maximum rating 13-1 accesses address, decode enable 11-14 burst memory-mapped 1-8 bus 11-8 byte 2-1, 4-1, 11-8 debug interface 12-20-12-21 direct data transfer modes 3-2, 5-2 Direct Master 3-3, 3-5, 5-3, 5-5 Direct Master memory 3-4, 5-4 Direct Slave 2-1, 2-4, 2-8, 2-13, 3-2, 3-3, 3-14, 4-1, 4-5, 4-8, 4-13, 5-2, 5-4, 5-12, 11-20, 11-29 disabled 8-2, 8-3, 11-17 Hot Swap 9-1, 9-3, 9-4 I/O 2-1, 4-1 configuration 3-5, 5-5 space 11-8 internal registers 2-13, 2-14, 4-14 Local Bus Big/Little Endian 2-7, 4-8 read 2-4, 4-5 write 2-4, 4-5 local initialization 2-8, 4-8 locked atomic operations 3-10, 5-9 Lword partial 2-4, 4-4 read or write 2-1, 4-1, 11-8 Max_Lat 11-15 memory base address 11-11 memory space 11-8 PCI Bus Master 1-8, 2-4 PCIBAR0 2-14, 3-7, 4-13, 5-6, 7-5, 11-3, 11-7, 11-11, 11-47 PCIBAR1 2-14, 4-13, 11-3, 11-12, 11-23 PCIBAR2 3-13, 3-15, 5-11, 5-13, 11-3, 11-12, 11-20, 11-23 PCIBAR3 3-13, 3-15, 5-11, 5-13, 11-3, 11-13, 11-23, 11-29 PCIBAR4 11-3, 11-13 PCIBAR5 11-3, 11-13 PCI-to-Local 11-4 PCI-to-Local Bus space 11-20 RST# timing 1-7 single 1-8 software reset 3-1, 5-1 VPD 10-1, 11-19, 11-23 VPD Expansion ROM 1-7 word 2-1, 4-1, 11-8 AD[31:0] 12-3, 14-3 adapter cards, high-performance 1-4-1-6 Adapter mode 3-1, 5-1 address bits for decoding 3-13, 5-11 boundary 2-3, 4-4 burst start 2-4, 4-4 Bus modes, multiplexed and non-multiplexed 12-1 cycle 2-3, 2-4, 4-4 decode enable 11-14, 11-24 Direct Slave byte enables 5-13 initialization 3-14, 5-11 EROMBA 2-11, 3-13, 3-17, 4-11, 5-11, 5-15, 11-25 invariance 2-5, 2-6, 4-5, 4-6 LAS0BA 2-11, 3-13, 3-15, 4-11, 5-11, 5-13, 11-12, 11-20 LAS0RR 2-11, 3-13, 4-11, 5-11, 11-12, 11-20 LAS1BA 2-12, 3-13, 3-15, 4-12, 5-11, 5-13, 7-5, 11-13, 11-29, 11-47 LAS1RR 2-12, 3-13, 4-12, 5-11, 11-13, 11-29, 11-47 LBRD0 2-3, 2-9, 2-11, 2-12, 3-2, 3-9, 3-12, 3-13, 3-16, 4-3, 4-9, 4-10, 4-11, 5-2, 5-8, 5-11, 5-14, 11-25 LBRD1 2-3, 2-12, 3-9, 3-12, 3-13, 4-3, 4-12, 5-8, 5-11, 11-30, 11-47 local bits 2-4, 4-5 local bus initialization 3-13, 5-11 local spaces 0 2-7, 4-8 1 2-7, 4-8 mapping 3-13, 5-11 multiple independent spaces 1-1, 1-2 multiplexed and non-multiplexed Local Bus modes 12-1 PCI command 11-8 status 11-9 PCIBAR0 2-14, 3-7, 4-13, 5-6, 7-5, 11-3, 11-7, 11-11, 11-47 PCIBAR1 2-14, 4-13, 11-3, 11-12, 11-23 PCIBAR2 3-13, 3-15, 5-11, 5-13, 11-3, 11-12, 11-20, 11-23 PCIBAR3 3-13, 3-15, 5-11, 5-13, 11-3, 11-13, 11-23, 11-29 PCIBAR4 11-3, 11-13 PCIBAR5 11-3, 11-13 PCI-to-Local spaces 1-8
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-1
Index
ADS# to C and J modes
PROT_AREA 2-11, 4-11, 10-2, 11-23 PVPDAD 10-1, 11-19 Read Ahead mode 1-8 read and write, random 10-2 register 1-10 register mapping 11-3-11-7 VPD 10-1 ADS# 5-10, 11-24, 12-1, 12-12, 12-16, 13-5, 14-3 ALE 5-10, 12-1, 12-16, 13-5, 14-3 arbitration DMA 3-29, 5-25 local bus 2-2, 4-2 MARBR 2-2, 2-11, 3-2, 3-9, 3-10, 3-11, 3-12, 3-13, 3-18, 3-23, 3-27, 3-29, 4-2, 4-11, 5-2, 5-8, 5-9, 5-10, 5-16, 5-22, 5-25, 11-21, 11-23 PCI 2-2, 4-2 PCI or Local Bus 4-2 round-robin 11-31 architecture boundary scan 12-20 atomic operations, locked 3-10, 5-9
BR# 2-2, 3-16, 3-29, 11-21, 11-25, 12-1, 12-8, 13-6, 14-3 BREQi 4-2, 5-16, 5-25, 11-21, 12-1, 12-12, 12-16, 13-5, 14-3 BREQo 5-15, 11-4, 11-21, 11-25, 12-1, 12-12, 12-16, 13-7, 14-3 BTERM# 2-3, 3-12, 3-13, 3-18, 3-20, 3-28, 3-29, 4-3, 4-4, 5-7, 5-16, 5-18, 11-25, 11-26, 11-30, 11-37, 11-39, 12-1, 12-12, 12-16, 13-5, 13-7, 14-3 buffered PCI 1-10 burst operation, zero wait state 1-7 BURST# 2-4, 3-5, 12-1, 12-8, 13-4, 13-6, 14-3 Bus operation 2-1-2-20, 4-1-4-22 protocol devices 1-7 See Also Local Bus or PCI Bus byte enables 5-5, 5-13, 5-24 See Also LBE[3:0]#
C
C and J modes AC electrical characteristics 13-5, 13-7 accesses byte 4-1 direct data transfer modes 5-2 Direct Master memory 5-4 Direct Slave 4-1, 4-5, 4-8, 5-2 I/O 4-1 internal registers 4-14 Local Bus Big/Little Endian 4-8 read and write 4-5 local initialization 4-8 Lword partial 4-4 read or write 4-1 software reset 5-1 Adapter mode 5-1 address boundary 4-4 cycle 4-4 Direct Slave byte enables 5-13 local bits 4-5 arbitration, PCI or Local Bus 4-2 backoff 5-15 base address 5-13 Block DMA mode 5-16-5-18 Block DMA, Dual Address cycle 5-18 Bus interface pin description 12-1 operation 4-1-4-22 byte enables 5-13
B
B0 -B3power management states 8-1 backoff deadlock, during 3-17, 5-15 preempt deadlock solution 3-17, 5-15 software solution for deadlock 3-17, 5-15 solution for deadlock 3-17, 5-15 timer 3-17, 5-15, 9-25 BB# 1-8, 2-2, 3-2, 3-12, 3-16, 3-17, 3-29, 11-25, 12-1, 12-8, 13-4, 13-6, 14-3 BD_SEL# 9-1, 9-2, 12-5, 14-3 BDIP# 2-3, 2-4, 3-4, 3-5, 3-13, 3-20, 3-27, 3-28, 3-29, 11-38, 11-40, 12-1, 12-8, 13-4, 13-6, 14-3 BG# 2-2, 3-16, 3-17, 3-27, 3-29, 11-25, 12-1, 12-8, 13-4, 14-3 BI# 2-3, 2-4, 3-8, 3-12, 3-18, 3-20, 3-28, 3-29, 12-1, 12-8, 13-4, 13-6, 14-3 BIAS precharge voltage 9-3 Big Endian See Endian Big/Little Endian Descriptor register (BIGEND) 2-5, 2-11, 4-6, 4-11, 11-22 BIGEND 2-5, 2-11, 4-6, 4-11, 11-22 BIGEND# 1-8, 2-5, 2-7, 4-6, 4-8, 11-21, 11-22, 12-1, 12-8, 12-12, 12-16, 13-4, 13-5, 13-6, 14-3 BIST 6-3 BLAST# 3-18, 4-2, 4-4, 5-2, 5-5, 5-16, 5-24, 5-25, 11-38, 11-40, 12-1, 12-12, 12-16, 13-5, 13-7, 14-3 Block DMA mode 1-2 Block Dual Address cycle 3-20, 5-18
Index-2
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
C and J modes
to C and J modes Command codes 4-1 Direct Master Local-to-PCI 4-1 Direct Slave 4-1 DMA Master 4-1 PCI Master 4-1 configuration cycles 5-6-5-7 initialization timing diagrams 4-15-4-22 local initialization 4-8 local registers 4-8 PCI, registers 4-13 registers 5-1 serial EEPROM 5-1 data transfers 1-8 deadlock conditions 5-14 Delayed Read mode 5-9 Direct Master access 5-3 Delayed Write mode 5-5 Dual Address cycle 5-7 FIFOs 5-4 I/O 5-5 I/O configuration access 5-5 I/O decode 5-3 Local-to-PCI Command codes 4-1 memory 5-3 memory access 5-4 memory write and invalidate 5-8 operation 5-2 Read Ahead mode 5-5-5-6 Direct Slave accesses to 8- or 16-bit Local Bus 4-5 Big Endian/Little Endian cycle reference table 4-6 Command code, memory write and invalidate 4-1 Command codes 4-1 Direct Data Transfer mode 5-2-5-15 example 5-13-5-14 FIFO full or empty, response to 5-2 initialization 5-11 Local Bus Big Endian/Little Endian mode accesses 4-8 lock 5-9 operation 5-8-5-14 priority 5-14 Read Ahead mode 5-9-5-10 serial EEPROM initialization 4-8, 4-13 transfer 5-10 wait states Local Bus 4-3 DMA Abort 5-22 arbitration 5-25 channel interrupts 5-22 Clear Count mode 5-19 configuration 5-1 data transfers 5-22-5-24 Demand mode 5-24 Descriptor Ring Management 5-20 Dual Address cycle 5-16 Master Command codes 4-1 memory write and invalidate 5-22 operation 5-15-5-25 priority 5-22 transfer 4-4 unaligned transfers 5-24 dual address 4-1, 5-17 dual address timing 5-7 end of transfer (EOT#) input 5-25 Endian, Big/Little 4-5-4-8 FIFO, response to full or empty 5-2 FIFOs 5-10 Continuous Burst mode 4-4 Direct Slave 5-2, 5-9 functional description 5-1-5-114 host mode 5-1 I/O decode 5-3 Direct Master 5-5 initialization Direct Slave 5-11 local 4-8 Local Address Big/Little Endian mode 4-8 increment 4-4, 5-16 mapping 5-11 Local Bus 5-1 Big/Little Endian mode 4-6-4-9 characteristics 5-11 cycles 4-2, 4-5 Direct Slave access 5-12 Command codes 4-1 operation 5-2 FIFO, response to full or empty 5-2 Latency Timer 1-8, 4-2, 5-10, 5-16, 5-25 Pause Timer 4-2, 5-14, 5-16, 5-25 Local LRESET# 5-1 Local NMI 6-4 Local SERR# 6-4
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-3
Index
C/BE[3:0]# to Clear Count mode
Local-to-PCI doorbell interrupt 6-3 map PCI software 5-11 serial EEPROM memory 4-12 map/remap 5-11, 5-13 Master Command codes 4-1 memory 5-10 read 4-1 serial EEPROM map 4-12 write 4-1 write and invalidate, Direct Master 5-8 memory commands aliased 4-1 basic 4-1 new capabilities structure 4-12 PCI arbitration 4-2 Dual Address cycle 4-1 reset 5-1 PCI Bus 5-3 cycles 4-1 Direct Slave operation 5-2 FIFO, response to full or empty 5-2 input 5-1 internal registers, access to 4-14 Latency Timer 5-16, 5-25 Little Endian mode 4-5 software reset 5-1 wait states 4-3 PCI Master Command codes 4-1 PCI Master/Target Abort 5-7-5-8 pinout, C mode 12-12-12-15 pinout, J mode 12-16-12-19 Power Management reset 5-1 range for decoding 5-11, 5-13 read 5-2 accesses 4-1, 4-14 Command codes, Direct Slave 4-1 FIFOs 4-4 I/O command 4-1 Local Bus accesses 4-5 memory command 4-1 memory line 4-1 memory multiple 4-1 Read Ahead mode 4-5 serial EEPROM 4-12 Read Ahead mode, in burst read cycles 4-5 READY#, serial EEPROM initialization 4-8, 4-13 Scatter/Gather DMA mode 5-18-5-21 serial EEPROM 4-8-4-22
device ID registers 4-8 extra long load 4-10-4-12 extra long load registers 4-12 long load 4-10-4-11 long load registers 4-11 memory map 4-12 new capabilities function support 4-12 operation 4-9 PCI Bus, access to internal registers 4-14 recommended 4-12 register access, internal 4-13 software reset 5-1 timing diagrams 4-15-4-22 vendor ID registers 4-8 single address block DMA initialization 5-17 software reset 5-1 timing diagrams 4-15-4-22, 5-26-5-96 configuration initialization 4-15-4-22 Vital Product Data (VPD) new capabilities function feature 4-12 register access, internal 4-13 serial EEPROM, read or write 4-9 wait state control 4-3 generation 4-5 Local Bus 4-3 PCI Bus 4-3 write 5-2 accesses 4-1, 4-14 Command codes, Direct Slave 4-1 I/O command 4-1 Local Bus accesses 4-5 memory command 4-1 memory write and invalidate 4-1 serial EEPROM operation 4-9 C/BE[3:0]# 2-1, 2-4, 3-6, 3-7, 3-10, 3-18, 4-1, 5-4, 5-5, 5-7, 5-9, 5-16, 12-3, 12-4, 14-3 CAP_PTR 8-1, 11-14 capacitance 13-1 Card_VAUX 8-2, 8-3, 12-7, 14-3 CCS# 2-14, 4-14, 12-1, 12-8, 12-12, 12-16, 13-4, 13-5, 14-3 channels, DMA 1-10 circular FIFOs summary 7-6 Clear Count mode 3-22, 5-16, 5-18, 5-19, 5-20
Index-4
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
clocks
to D3cold clocks EESK 2-8, 4-9 input 13-4 PCI 2-8, 4-9, 11-16 PCIMGR 11-15 RST# 1-7 running 8-1 serial EEPROM 2-8, 4-9 CNTRL 2-1, 2-8, 2-10, 2-12, 3-1, 3-2, 4-1, 4-9, 4-10, 5-1, 5-2, 6-5, 11-36 Command codes 2-1, 4-1 CompactPCI high-performance adapter cards 1-4-1-5 Hot Swap 9-1-9-4 applications 9-1 blue LED 9-3 board healthy 9-2 board slot control 9-2 capabilities register bit definition 9-4 compliant 1-7, 1-10 control bits 9-4 Control/Status register (HS_CSR) 9-4 controlling connection processes 9-2 ejector switch 9-3 ENUM# 9-3 hardware connection control 9-2 ID 9-4 Next_Cap Pointer 9-4 pins 9-1, 12-5 platform reset 9-2 Silicon 1-4 software connection control 9-3 Hot Swap Silicon 1-4 compatible message unit 7-1 configuration accesses 1-7 Big/Little Endian 3-12, 5-10 command type 2-1, 4-1 control/status register 9-4 cycles 2-14, 3-6-3-7, 4-13, 5-6-5-7 Hot Swap 9-1, 9-4 initialization 5-1 layout type 11-10 load information 1-9 local cycles 8-3 initialization 2-8, 4-8 registers 2-8, 2-13, 3-1, 4-8, 4-13, 11-4, 11-20-11-31 messaging unit 11-7 new capabilities 10-1 PCI cycles 8-3 registers 2-13, 2-14, 4-13, 11-3, 11-8-11-19 PCI 9056 initialization 3-1 Power Management 8-2 register space 1-7 registers 3-1, 5-1, 11-8-11-31 address mapping 11-3-11-7 serial EEPROM 3-1, 5-1 software reset 3-1 space 9-4, 10-1 subsystem ID 1-7 subsystem vendor ID 1-7 system reconfiguration 9-1, 9-3 VPD 10-1 Configuration Address register (DMCFGA) 2-11, 3-2, 3-5, 3-6, 4-11, 5-2, 5-5, 5-6, 11-28 configuration initialization timing diagrams 2-15-2-20, 4-15-4-22 conversion Big/Little Endian 3-12, 5-10 on-the-fly 3-12, 5-10 counter, programmable prefetch 1-8, 1-10, 5-8 CPCISW 9-1, 9-3, 12-5, 14-3 CPU host 9-3 cycles configuration 3-6, 5-6 dual address 3-7, 5-7 Local Bus 2-2-2-5, 4-2-4-5 memory write and invalidate 3-8, 5-8
D
D0 functional power state 8-1 support 1-7, 8-2, 11-16, 11-17 D1 functional power state 8-1 support 1-7, 11-16, 11-17 D2 functional power state 8-1 support 1-7, 8-2, 11-16, 11-17 D3cold functional power state 8-1 PME logic, during 12-6, 12-7
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-5
Index
D3hot to Direct Slave
PME request 12-10, 12-14, 12-19 support 1-5, 1-7, 1-10, 8-2, 1-7, 11-16 D3hot functional power state 8-1 support 1-7, 8-2, 1-7, 11-16, 11-17 DAC (Dual Address cycle) 3-7, 5-7 DACK0# 1-3, 11-37, 12-1, 12-9, 12-12, 12-16, 13-6, 13-7, 14-3 DACK1# 1-3, 11-40, 12-1, 12-9, 12-12, 12-17, 14-3 data bus 2-4, 3-27, 3-28, 4-5, 5-24, 5-25, 12-3, 12-9, 12-14, 12-17 contents for read and write cycles 3-15 Data Pipe Architecture technology 1-1-1-3 See Also DMA data transfer mode 3-2-3-17, 5-2-5-15 Direct Master 3-2, 5-2 Direct Slave 3-2, 5-2 DMA 3-2, 5-2 data transfers, DMA Local-to-PCI 3-26, 5-23 PCI-to-Local 3-26, 5-23 deadlock access, during 3-16, 5-14 conditions 3-16, 5-14 full 3-16, 5-14 partial 3-16, 5-14 debug interface JTAG test access port 12-20 test access method 12-20-12-21 port 12-20 Delayed Read mode 1-10, 3-10, 5-9 Delayed Write mode 3-5, 5-5 Demand mode DMA Local-to-PCI Fast Terminate mode 3-27, 5-24 DMA Local-to-PCI Slow Terminate mode 3-28, 5-24 DMA support 1-10 DEN# 12-17, 13-7, 14-3 Descriptor Ring Management 3-22, 5-20 device ID 11-8 DEVSEL# 3-8, 5-7, 11-9, 12-3, 14-3 direct interface Local Bus 1-7 Local-to-PCI Command codes 4-1 Direct Master 3-11, 5-10 access 3-3, 5-3 configuration 3-6, 5-6 counter, programmable prefetch 1-8 Delayed Write mode 3-5, 5-5
Dual Address cycle 3-7, 5-7 FIFOs 3-3-3-4, 5-4 I/O configuration access 3-5, 5-5 I/O decode 3-3, 5-3 interrupts 6-4 Local Bus cycles 2-2, 4-2 Local Bus data parity 2-4-2-5, 4-5 Local Bus Endian mode 2-5, 2-7, 4-6, 4-8 Local Bus Read accesses 2-4, 4-5 Local-to-PCI Command codes 2-1, 4-1 memory 3-3, 5-3 access 3-4, 5-4 write and invalidate 3-8, 5-8 operation 3-2, 5-2 PCI Arbitration 2-2, 4-2 PCI Dual Address Cycle Upper Address register (DMDAC) 3-2, 3-7, 5-2, 5-7, 11-30 wait states, Local Bus 2-3, 4-3 writes 5-4 Direct Slave accesses to 8- or 16-bit Local Bus 2-4, 4-5 Big Endian/Little Endian cycle reference table 2-5, 4-6 BTERM# input 2-3, 4-4 bursting 1-8 Command code 2-1, 4-1 Command codes 2-1, 4-1 counter, programmable prefetch 1-8, 1-10 description 1-1, 1-2 Direct Data Transfer mode 3-2-3-17, 5-2-5-15 example 5-13-5-14 FIFO depth 1-7 FIFO full or empty, response to 3-2, 5-2 initialization, local bus 3-13, 5-11 Keep Bus mode 1-8 Local Bus Big/Little Endian mode accesses 2-7, 4-8 Local Bus cycles 2-2, 4-2 lock 3-10, 5-9 Lword accesses, partial 2-4, 4-4 operation 3-9-3-16, 5-8-5-14 PCI-to-Local Address spaces 1-8 Power Management 8-1 Power mode example 8-3 priority 3-16, 5-14 Read Ahead mode 1-8 serial EEPROM initialization 2-8, 2-13, 4-8, 4-13 space 0 enable in LAS0BA 11-20 space 1 enable in LAS1BA 11-29 transactions 1-8
Index-6
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
disconnect, Flush Read FIFO to DMLBAI
transfer 3-11 transfer size 3-15 wait states 2-3, 4-3 disconnect, Flush Read FIFO 11-23 DMA Abort 3-23, 5-22 arbitration 3-29, 5-25 Arbitration register (DMAARB) 11-42 Block Dual Address cycle 3-20, 5-18 Block mode 1-2 Channel 0 Command/Status register (DMACSR0) 3-18, 3-20, 3-22, 3-25, 5-16, 5-18, 5-20, 5-22, 6-4, 11-42 Descriptor Pointer register (DMADPR0) 3-20, 5-18, 11-39 Local Address register (DMALADR0) 11-38 Mode register (DMAMODE0) 2-3, 3-12, 3-18, 3-20, 3-22, 3-24, 3-25, 3-27, 3-28, 4-3, 5-16, 5-18, 5-19, 5-21, 5-22, 5-24, 5-25, 6-3, 6-4, 11-2, 11-8, 11-36, 11-37, 11-38, 11-39, 11-41 PCI Address register (DMAPADR0) 11-38 Transfer Size register (DMASIZ0) 11-39 Channel 1 Command/Status register (DMACSR1) 3-18, 3-20, 3-22, 3-25, 5-16, 5-18, 5-20, 5-22, 6-4, 11-42 Descriptor Pointer register (DMADPR1) 3-20, 5-18, 11-41 Local Address register (DMALADR1) 11-41 Mode register (DMAMODE1) 2-3, 3-12, 3-18, 3-20, 3-22, 3-24, 3-25, 3-27, 3-28, 4-3, 5-16, 5-18, 5-19, 5-21, 5-22, 5-24, 5-25, 6-3, 6-4, 11-2, 11-8, 11-36, 11-38, 11-39, 11-41 PCI Address register (DMAPADR1) 11-41 Transfer Size register (DMASIZ1) 11-41 channels interrupts 3-25, 5-22 number of 1-9, 1-10 Clear Count mode 3-22, 5-19, 5-20 configuration 3-1, 5-1 controller 2-4, 4-5 data transfers 1-2 Local-to-PCI 3-26, 5-23 PCI-to-Local 3-26, 5-23 Demand mode 1-10, 3-27, 3-28, 5-24 Descriptor Ring Management 3-22, 5-20 direct hardware control 1-3 dual address 3-7, 3-20 Dual Address cycle 3-18, 5-7, 5-16, 5-18 interrupts 6-1, 6-3-6-4 list management 1-2 local bus error 3-27 Master Command codes 2-1, 4-1 priority 3-23, 5-22 read 1-7 registers 11-11, 11-37-11-43 registers, address mapping 11-6 ring management 1-2 Scatter/Gather 3-22, 3-24, 5-20 list management 1-2 mode 1-2 Threshold register (DMAATH) 11-43 transfer 2-4, 4-4 unaligned transfer support 1-8 transfers 3-27, 5-24 wait states 2-3 write 1-7 DMA 0 PCI Dual Address Cycle Upper Address register (DMADAC0) 3-18, 3-20, 3-22, 3-24, 5-16, 5-18, 5-19, 5-21, 11-43 DMA 1 PCI Dual Address Cycle Upper Address register (DMADAC1) 3-18, 3-20, 3-22, 3-24, 5-16, 5-18, 5-19, 5-21, 11-43 DMA channels 1-10 DMAARB 11-42 DMACSR0 3-18, 3-20, 3-22, 3-25, 5-16, 5-18, 5-20, 5-22, 6-4, 11-38, 11-42 DMACSR1 3-18, 3-20, 3-22, 3-25, 5-16, 5-18, 5-20, 5-22, 6-4, 11-40, 11-42 DMADAC0 3-7, 3-18, 3-20, 3-22, 3-24, 5-7, 5-16, 5-18, 5-19, 5-21, 11-43 DMADAC1 3-7, 3-18, 3-20, 3-22, 3-24, 5-7, 5-16, 5-18, 5-19, 5-21, 11-43 DMADPR0 3-20, 5-18, 11-39 DMADPR1 3-20, 5-18, 11-41 DMALADR0 11-38 DMALADR1 11-41 DMAMODE0 2-3, 3-12, 3-18, 3-20, 3-22, 3-24, 3-25, 3-27, 3-28, 4-3, 5-16, 5-18, 5-19, 5-21, 5-22, 5-24, 5-25, 6-3, 6-4, 11-2, 11-8, 11-36, 11-37, 11-38, 11-39, 11-41 DMAMODE1 2-3, 3-12, 3-18, 3-20, 3-22, 3-24, 3-25, 3-27, 3-28, 4-3, 5-16, 5-18, 5-19, 5-21, 5-22, 5-24, 5-25, 6-3, 6-4, 11-2, 11-8, 11-36, 11-38, 11-39, 11-41 DMAPADR0 11-38 DMAPADR1 11-41 DMASIZ0 11-38, 11-39 DMASIZ1 11-38, 11-40, 11-41 DMATHR 11-43 DMCFGA 2-11, 3-2, 3-5, 3-6, 4-11, 5-2, 5-5, 5-6, 11-28 DMDAC 3-2, 3-7, 5-2, 5-7, 11-30 DMLBAI 2-11, 3-2, 3-7, 4-11, 5-2, 5-6, 11-27
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-7
Index
DMLBAM to FIFOs
DMLBAM 2-11, 3-2, 4-11, 5-2, 11-26 DMPAF 3-4, 5-4, 11-21, 11-27, 12-1, 12-10, 12-13, 12-17, 13-4, 13-5, 13-6, 13-7, 14-3 DMPBAM 2-1, 2-2, 2-11, 3-2, 3-6, 3-8, 3-9, 4-1, 4-2, 4-11, 5-2, 5-5, 5-6, 5-8, 11-27 DMRR 2-11, 3-2, 3-7, 4-11, 5-2, 5-6, 11-26 Doorbell registers 1-10, 6-2 L2PDBELL 6-2, 6-3, 11-33 P2LDBELL 6-2, 6-3, 11-33 DP[0:3] 2-4, 12-9, 12-13, 13-4, 13-6, 14-3 DP[3:0] 4-5, 12-1, 12-17, 13-5, 13-7, 14-3 DREQ0# 1-3, 3-9, 3-23, 3-27, 3-28, 3-29, 5-22, 5-24, 5-25, 11-37, 11-38, 12-1, 12-9, 12-13, 12-17, 14-3 DREQ1# 1-3, 3-9, 3-23, 3-27, 3-28, 3-29, 5-22, 5-24, 5-25, 11-40, 12-1, 12-9, 12-13, 12-17, 13-4, 13-5, 14-3 DT/R# 12-17, 13-7, 14-3 Dual Address block DMA initialization 5-17 cycle 2-1, 3-18, 4-1, 5-16 timing 3-8, 3-21, 5-7 Dual Address Cycle Upper Address register (DMDAC) 3-2, 3-7, 5-2, 5-7, 11-30
E
EECS 2-9, 2-15, 4-9, 4-15, 12-1, 12-6, 14-3 EEDI 2-9, 2-15, 4-9, 4-15, 11-36, 12-1, 12-6, 14-3 EEDO 2-9, 2-15, 4-9, 4-15, 11-1, 11-36, 12-1, 12-6, 14-3 EESK 2-8, 2-9, 2-15, 4-9, 4-15, 12-1, 12-6, 14-3 electrical characteristics over operating range 13-2 electrical specifications 13-1-13-7 AC characteristics (C and J modes) 13-5, 13-7 AC characteristics (M mode) 13-4, 13-6 capacitance 13-1 local inputs 13-4 local output delay 13-6 local outputs 13-6 embedded design 12-1 host designs 1-6 systems 1-1 enable sequence 7-5 end of transfer (EOT#) input 3-28, 5-25 Endian Big 2-5-2-7, 4-5-4-8 16-bit Local Bus, upper and lower word lane transfers 2-6, 4-7 32-bit Local Bus, upper Lword lane transfer 2-6, 4-6 8-bit Local Bus, upper and lower byte lane transfers 2-7, 4-7
byte number and lane cross-reference 2-5, 4-6 cycle reference table 2-5, 4-6 Local Bus 2-5, 4-6 Local Bus accesses 2-7, 4-8 on-the-fly conversion 3-12, 5-10 Program mode 2-5, 4-6 Little 2-5-2-7, 4-5-4-8 byte number and lane cross-reference 2-5, 4-6 cycle reference table 2-5, 4-6 Local Bus 2-5, 4-6 Local Bus accesses 2-7, 4-8 on-the-fly conversion 3-12, 5-10 PCI Bus 2-5, 4-5 Program mode 2-5, 4-6 Endian, Big/Little conversion 1-8 ENUM# 1-4, 9-1, 9-3, 9-4, 11-1, 11-18, 12-5, 14-3 EOT# 1-3, 3-20, 3-23, 3-27, 3-28, 3-29, 5-15, 5-22, 5-24, 5-25, 11-1, 11-2, 11-37, 11-38, 11-40, 12-1, 12-10, 12-13, 12-17, 13-4, 13-5, 13-6, 13-7, 14-3 EROMBA 2-11, 3-13, 3-17, 4-11, 5-11, 5-15, 11-25 EROMRR 2-11, 3-13, 4-11, 5-11, 11-14, 11-24 error sources 6-1 Expansion ROM Range register (EROMRR) 2-11, 3-13, 4-11, 5-11, 11-14, 11-24 register (EROMBA) 2-11, 3-13, 3-17, 4-11, 5-11, 5-15, 11-25
F
F bit (flag) 10-1 Fast Terminate mode 3-27, 5-24 FIFOs circular summary 7-6 CNTRL, in 11-23 Continuous Burst mode 2-4, 4-4 depth 1-7, 1-10 Direct Master 3-3-3-4, 5-4 Direct Slave operation 3-2, 5-2 Read Ahead mode 3-11 transfer 3-11, 5-10 enable high-performance bursting 1-8 full or empty, response to 3-2, 5-2 I2O circular operation 7-4 inbound free list 7-3 inbound post queue 7-3 outbound free list 7-5 outbound post queue 7-3 programmable 1-7 Read Ahead mode 1-8
Index-8
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
flush
to Inbound flush 3-10, 5-9 FRAME# 2-2, 3-10, 4-2, 5-8, 11-21, 11-31, 12-3, 14-3 free list FIFO inbound 7-3, 7-4 outbound 7-4, 7-5 free queue, inbound 7-4 functional description C and J modes 5-1-5-114 M mode 3-1-3-55 functional power states 8-1
I
I/O accelerator 1-3 configuration access 3-5, 5-5 decode 3-3, 5-3 Direct Master 3-5, 5-5 Hot Swap requirement 9-1 insertion and extraction, during 9-3 user 6-1-6-5 See Also user input and output I2O circular FIFOs operation 7-4 messaging unit 1-10 See Also Intelligent I/O IBM, PPC401 1-7 ID Configuration ID register (PCIIDR) 2-11, 4-8, 4-11, 11-8 device 11-8 Hardwired Configuration ID register (PCIHIDR) 2-7, 11-37 Hardwired Revision ID register (PCIHREV) 11-37 Hot Swap 9-4 PCI Subsystem register 2-12, 4-12, 11-14 PCI Subsystem Vendor register 2-7, 2-12, 4-8, 4-12, 11-13 Power Management Capability ID register (PMCAPID) 8-1, 11-15 Revision ID register (PCIREV) 2-11, 4-11, 11-9 serial EEPROM, revision 11-9 serial EEPROM, subsystem 11-14 serial EEPROM, vendor 11-8 vendor 11-8 VPD 11-19 IDDQEN# 8-3, 12-1, 12-6, 14-3 IDMA operation 3-9 IDSEL 3-7, 5-6, 12-3, 14-3 IEEE Standard Test Access Port and Boundary-Scan Architecture 12-20 IFHPR 7-2, 11-45 IFTPR 7-2, 11-45 Inbound Free Head Pointer register (IFHPR) 7-2, 11-45 free list FIFO 7-3 Free Tail Pointer register (IFTPR) 7-2, 11-45 IFHPR 7-2 IFTPR 7-2 IPHPR 7-2 IPTPR 7-2
general electrical specifications 13-1-13-3 absolute maximum ratings 13-1 operating ranges 13-1 over operating range 13-2 thermal resistance of packages 13-1 GNT# 3-18, 3-29, 5-16, 5-25, 11-31, 12-4, 14-3 GNT[6:1]# 12-3, 14-3 GNT0# 11-31, 12-3, 14-3
H
hardware control 1-3 diagram 7-4 high-performance adapter cards 1-4-1-5 hold waveform 13-4 host designs, embedded 1-6 Host mode 3-1, 5-1 Local LRESET# 3-1, 5-1 Power Management reset 3-1, 5-1 software reset 3-1, 5-1 HOSTEN# 6-2, 6-4, 11-1, 11-36, 12-1, 12-6, 12-10, 12-14, 12-18, 14-3 Hot Plug 1-7, 1-10 system driver 9-3, 9-4 Hot Swap Control register (HS_CNTL) ID 2-12, 4-12, 9-4, 11-18 Control/Status register (HS_CSR) 1-4, 2-12, 2-13, 4-12, 9-1, 9-3, 9-4, 11-18 ID 2-12, 4-12, 9-4, 11-18 Next Capability Pointer register (HS_NEXT) 11-18 resources 9-3 Silicon 1-4 Hot Swap Silicon 1-4 HS_CNTL 2-12, 4-12, 9-4, 11-18 HS_CSR 1-4, 2-12, 2-13, 4-12, 9-1, 9-3, 9-4, 11-18 HS_NEXT 11-18
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-9
Index
G
initialization to LAS0BA
Post Head Pointer register (IPHPR) 7-2, 11-45 post queue FIFOs 7-3 Post Tail Pointer register (IPTPR) 7-2, 11-46 queue port 7-4 Queue Port register (IQP) 7-3, 11-44 initialization 3-1, 5-1 C and J modes 5-1 Direct Slave 3-14 example 3-15, 5-13 local bus 3-13, 5-11 PCI 5-11 local 2-8, 4-8 M mode 3-1 PCI 9056 configuration 3-1 PMC 11-16 reset 3-13, 5-11 Initialization Control register (CNTRL) 2-1, 2-8, 2-10, 2-12, 3-1, 3-2, 4-1, 4-9, 4-10, 5-1, 5-2, 6-5, 11-36 Initially Not Respond 1-5, 2-8, 4-8, 9-1 Initially Retry 2-8, 4-8 input PCI Bus 3-1, 5-1 user 6-5 INTA# 3-18, 3-20, 5-16, 5-18, 6-1, 6-2, 8-3, 11-14, 11-36, 12-3, 14-3 INTCSR 3-8, 3-25, 5-7, 5-22, 6-1, 6-2, 6-3, 6-4, 6-5, 8-2, 11-34-11-35, 12-9, 12-14, 12-18 Intel i960 1-7 intelligent I/O 7-1-7-6 circular FIFOs summary 7-6 compatible message unit 7-1 I2O circular FIFO operation 7-4 inbound free list FIFOs 7-3 free queue 7-4 messages 7-1 post queue FIFOs 7-3 outbound free list FIFO 7-5 messages 7-1 post queue 7-4 post queue FIFOs 7-3 pointer management 7-2 Intelligent I/O (I2O) Architecture Specification, Revision 1.5 1-9, 7-1, 7-2 intelligent I2O enable sequence 7-5 interface, Local Bus circuitry 3-1, 5-1
Interrupt Control/Status register (INTCSR) 3-8, 3-25, 5-7, 5-22, 6-1, 6-2, 6-3, 6-4, 6-5, 8-2, 11-34-11-35, 12-9, 12-14, 12-18 interrupts built-in self test (BIST) 6-3 disabled 8-1, 8-2, 11-17 DMA 3-25, 5-22 DMA Channels 0 and 1 6-3-6-4 doorbell register 6-2 ENUM# 9-3, 9-4 clear 11-18 driven 9-3 generator 1-9 INTA# 6-1 line 2-11, 4-11, 11-3, 11-14 local input (LINTi#) 6-1 output (LINTo#) 6-2, 8-3 Local-to-PCI 1-9 Local-to-PCI doorbell 6-3 mailbox register 6-2 Master/Target Abort 6-2 PCI and Local 6-1-6-5 PCI-to-Local 1-9 pin 2-11, 4-11, 11-3, 11-14 Power Management Event (PME#) 1-7 sources 6-1 User I/O 6-1-6-5 IPHPR 7-2, 11-45 IPTPR 7-2, 11-46 IQP 7-3, 11-44 IRDY# 2-3, 3-2, 4-3, 5-2, 11-27, 12-3, 14-3
J
J mode See C and J modes JTAG boundary scan interface 12-20-12-21 instructions 12-20 pins 12-5
L
L2PDBELL 6-2, 6-3, 11-33 LA[0:31] 12-1, 12-9, 13-4, 13-6, 14-3 LA[1:0] 4-5 LA[28:2] 12-1, 12-17, 13-7, 14-3 LA[31:0] 12-1 LA[31:2] 3-15, 12-13, 14-3 LAD[31:0] 4-6, 12-17, 12-18, 13-5, 13-7, 14-3 LAS0BA 2-11, 3-13, 3-15, 4-11, 5-11, 5-13, 11-12, 11-20
Index-10
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
LAS0RR
to Local Bus LAS0RR 2-11, 3-13, 4-11, 5-11, 11-12, 11-20 LAS1BA 2-12, 3-13, 3-15, 4-12, 5-11, 5-13, 7-5, 11-13, 11-29, 11-47 LAS1RR 2-12, 3-13, 4-12, 5-11, 11-13, 11-29, 11-47 Latency Timer Local Bus 1-8, 2-2, 2-3, 3-12, 3-13, 3-18, 3-27, 3-29, 4-2, 5-10, 5-16, 5-25, 11-21 PCI Bus 3-18, 3-29, 5-16, 5-25, 11-10 latency, reduced data 1-8 LBE[3:0]# 5-9, 5-13, 12-1, 12-13, 12-18, 13-5, 13-7, 14-3 LBRD0 2-3, 2-9, 2-11, 2-12, 3-2, 3-9, 3-12, 3-13, 3-16, 4-3, 4-9, 4-10, 4-11, 5-2, 5-8, 5-11, 5-14, 11-25 LBRD1 2-3, 2-12, 3-9, 3-12, 3-13, 4-3, 4-12, 5-8, 5-11, 11-30, 11-47 LCLK 11-24, 12-5, 12-9, 12-14, 12-16, 12-18, 13-3, 14-3 LD[0:31] 2-5, 3-15, 4-6, 5-13, 12-1, 12-9, 12-13, 13-4, 13-6, 14-3 LD[0:7] 2-5, 3-15, 4-6, 5-13, 12-13 LD[16:23] 2-5, 3-15, 4-6, 5-13, 12-13 LD[24:31] 2-5, 3-15, 4-6, 5-13, 12-13 LD[31:0] 2-5, 3-15, 4-6, 5-13, 12-1, 12-13, 12-14, 13-5, 13-7, 14-3 LD[8:15] 2-5, 3-15, 4-6, 5-13, 12-13 LEDon# 9-1, 9-3, 12-5, 14-3 LHOLD 1-8, 4-2, 5-2, 5-10, 5-14, 5-25, 11-25, 12-1, 12-14, 12-18, 13-7, 14-3 LHOLDA 4-2, 5-14, 5-15, 5-24, 5-25, 11-25, 12-1, 12-14, 12-18, 13-5, 14-3 LINTi# 6-1-6-2, 12-1, 12-9, 12-14, 12-18, 14-3 LINTo# 3-18, 3-20, 5-16, 5-18, 6-2, 7-5, 7-6, 8-2, 8-3, 11-1, 11-36, 12-1, 12-3, 12-9, 12-14, 12-18, 14-3 list management 1-2 Little Endian See Endian LLOCKi# 11-36, 12-1, 12-11, 12-15, 12-19, 13-4, 13-5, 14-3 LLOCKo# 11-36, 12-1, 12-11, 12-15, 12-19, 13-6, 13-7, 14-3 LMISC1 2-8, 2-9, 2-11, 3-1, 3-2, 3-4, 3-6, 3-9, 3-13, 3-27, 4-8, 4-10, 4-11, 5-1, 5-2, 6-4, 7-5, 11-12, 11-23 LMISC2 2-11, 3-11, 4-11, 5-10, 11-24 Local Address Big/Little Endian mode 2-7, 4-8 EROMBA 2-11, 3-13, 3-17, 4-11, 5-11, 5-15, 11-25 increment 2-3, 3-18, 4-4, 5-16 LAS0BA 2-11, 3-13, 3-15, 4-11, 5-11, 5-13, 11-12, 11-20 LAS0RR 2-11, 3-13, 4-11, 5-11, 11-12, 11-20 LAS1RR 2-12, 3-13, 4-12, 5-11, 11-13, 11-29, 11-47 mapping 3-13, 5-11 PCIBAR2 3-13, 3-15, 5-11, 5-13, 11-3, 11-12, 11-20, 11-23 PCIBAR3 3-13, 3-15, 5-11, 5-13, 11-3, 11-13, 11-23, 11-29 PCIBAR4 11-3, 11-13 PCIBAR5 11-3, 11-13 PCI-to-Local spaces 1-8 Space 0 Local Base Address register (LAS0BA) 2-11, 3-13, 3-15, 4-11, 5-11, 5-13, 11-12, 11-20 Space 0 Range register (LAS0RR) 2-11, 3-13, 4-11, 5-11, 11-12, 11-20 Space 0/Expansion ROM register (LBRD0) 2-3, 2-9, 2-11, 2-12, 3-2, 3-9, 3-12, 3-13, 3-16, 4-3, 4-9, 4-10, 4-11, 5-2, 5-8, 5-11, 5-14, 11-25 Space 1 Bus Region Descriptor register (LBRD1) 2-3, 2-12, 3-9, 3-12, 3-13, 4-3, 4-12, 5-8, 5-11, 11-30, 11-47 Space 1 Local Base Address register (LAS1BA) 2-12, 3-13, 3-15, 4-12, 5-11, 5-13, 7-5, 11-13, 11-29, 11-47 Space 1 Range register (LAS1RR) 2-12, 3-13, 4-12, 5-11, 11-13, 11-29, 11-47 spaces 3-9, 5-8, 11-3, 11-4 Local Base Address register for PCI Configuration (DMLBAI) 2-11, 3-2, 3-7, 4-11, 5-2, 5-6, 11-27 Local Base Address register for PCI Memory (DMPBAM) 2-1, 2-2, 2-11, 3-2, 3-6, 3-8, 3-9, 4-1, 4-2, 4-11, 5-2, 5-5, 5-6, 5-8, 11-27 Local Bus 3-1, 3-13 access internal registers 2-14, 4-14 accesses 5-1 arbitration 2-2, 4-2 Base Address register (DMLBAM) 2-11, 3-2, 4-11, 5-2, 11-26 Big/Little Endian mode 2-5-2-7, 4-6-4-8 common pin information, all modes of operation 12-1-12-7 configuration registers 11-4, 11-20-11-31 cycles 2-2-2-4, 4-2-4-5 direct interface 1-7 Direct Slave access 3-14, 5-12 Command codes 2-1, 4-1 initialization 3-13, 5-11 operation 3-2, 5-2 error condition 3-27 FIFO, response to full or empty 3-2, 5-2 I/Os 9-3 interface 2-13 LAS0BA 2-11, 3-13, 3-15, 4-11, 5-11, 5-13, 11-12, 11-20 LAS0RR 2-11, 3-13, 4-11, 5-11, 11-12, 11-20 LAS1BA 2-12, 3-13, 3-15, 4-12, 5-11, 5-13, 7-5, 11-13, 11-29, 11-47 LAS1RR 2-12, 3-13, 4-12, 5-11, 11-13, 11-29, 11-47
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-11
Index
local input setup to M mode
Latency Timer 1-8, 2-2, 2-3, 3-12, 3-13, 3-18, 3-27, 3-29, 4-2, 5-10, 5-16, 5-25, 11-21 LBRD0 11-25-11-26 LBRD1 2-3, 2-12, 3-9, 3-12, 3-13, 4-3, 4-12, 5-8, 5-11, 11-30, 11-47 Pause Timer 3-16, 3-27, 4-2, 5-14, 5-16, 5-25, 11-21 PCISR 11-9 pins 12-8-12-19 PMCSR 11-17 Power Management 8-1 Read Ahead mode 1-8, 3-11, 5-9 registers 4-13 serial EEPROM 2-8, 4-9 signaling 1-9 target regions, characteristics defined 5-11 types 2-2, 4-2 VPD 10-1 wait states 2-3 width 5-13 width control 1-2 local input setup 13-4 Local LRESET# 3-1, 5-1 Local Miscellaneous Control register (LMISC1) 2-8, 2-9, 2-11, 3-1, 3-2, 3-4, 3-6, 3-9, 3-13, 3-27, 4-8, 4-10, 4-11, 5-1, 5-2, 6-4, 7-5, 11-12, 11-23 Local Miscellaneous Control register (LMISC2) 2-11, 3-11, 4-11, 5-10, 11-24 Local NMI 6-4 Local Range register (DMRR) 2-11, 3-2, 3-7, 4-11, 5-2, 5-6, 11-26 Local SERR# 6-4 local signal output delay 13-6 Local-to-PCI doorbell interrupt 6-3 lock atomic operations 3-10, 5-9 Direct Slave 3-10, 5-9 LOCK# 3-10, 5-9 LOCK# 1-8, 3-10, 5-9, 11-21, 12-4, 14-3 LRESET# 3-1, 5-1, 8-2, 9-3, 11-36, 12-1, 12-4, 12-10, 12-14, 12-18, 14-3 LSERR# 4-5, 5-7, 6-4-6-5, 11-1, 11-34, 11-36, 11-47, 12-1, 12-14, 12-18, 13-7, 14-3 LW/R# 5-7, 12-1, 12-14, 12-19, 13-5, 13-7, 14-3 Lword accesses, partial 2-4, 3-27, 4-4, 5-8, 5-24
M
M mode AC electrical characteristics 13-4, 13-6 accesses byte 2-1
Direct Master memory 3-4 Direct Slave 2-1, 2-4, 2-8, 3-2 I/O 2-1 internal registers 2-13, 2-14 Local Bus Big/Little Endian 2-7 Local Bus read 2-4 Local Bus write 2-4 local initialization 2-8 Lword 2-1 Lword, partial 2-4 PCI Master 3-2 software reset 3-1 word 2-1 adapter mode 3-1 address boundary 2-3 burst start 2-4 cycle 2-3, 2-4 local bits 2-4 arbitration local bus 2-2 PCI 2-2 backoff 3-17 base address 3-15 Block DMA Dual Address cycle 3-20 Block DMA mode 3-18-3-20 Bus mode interface pin description 12-1 Bus operation 2-1-2-20 Command codes Direct Slave 2-1 DMA Master 2-1 Local-to-PCI 2-1 PCI Master 2-1 configuration cycles 3-6-3-7 initialization timing diagrams 2-15-2-20 local initialization 2-8 local registers 2-8, 3-1 PCI registers 2-13, 2-14 registers 3-1 serial EEPROM 3-1 data transfers 1-8 deadlock conditions 3-16 Delayed Read mode 3-10 Direct Master access 3-3 Delayed Write mode 3-5 Dual Address cycle 3-7 FIFOs 3-3-3-4
Index-12
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
M mode
to M mode I/O 3-5 configuration access 3-5 decode 3-3 Local-to-PCI Command codes 2-1 memory 3-3 access 3-4 write and invalidate 3-8 operation 3-2 Read Ahead mode 3-5-3-6 Direct Slave accesses to 8- or 16-bit Local Bus 2-4 Big Endian/Little Endian cycle reference table 2-5 Command codes 2-1 example 3-15-3-16 FIFO full or empty, response to 3-2 initialization 3-13 Local Bus Big Endian/Little Endian mode accesses 2-7 lock 3-10 Lword accesses, partial 2-4 operation 3-9-3-16 priority 3-16 Read Ahead mode 3-11 serial EEPROM initialization 2-8, 2-13 transfer 3-11-3-13 transfer size 3-15-3-16 wait states 2-3 DMA Abort 3-23 arbitration 3-29 channel interrupts 3-25 Clear Count mode 3-22 configuration 3-1 data transfers 3-25-3-27 Demand mode 3-27 Dual Address cycle 3-18 local bus error 3-27 Master Command codes 2-1 memory write and invalidate 3-22-3-23 operation 3-17-3-29 priority 3-23 transfer 2-4 unaligned transfers 3-27 DMA Descriptor Ring Management 3-22 dual address timing 3-8, 3-21 end of transfer (EOT#) input 3-28 Endian, Big 2-5-2-7 Endian, Little 2-5-2-7 FIFO full or empty, response to 3-2 FIFOs 3-11 Continuous Burst mode 2-4 Direct Slave 3-11 Direct Slave operation 3-2 functional description 3-1-3-55 host mode 3-1 I/O decode 3-3 I/O Direct Master 3-5 IDMA operation 3-9 initialization 3-1 Direct Slave 3-14 local 2-8 Local Address Big/Little Endian mode 2-7 Mapping 3-13 Local Address increment 2-3, 3-18 Local Bus 3-15 access internal registers 2-14 Big/Little Endian mode 2-5-2-7 characteristics 3-13 cycles 2-2, 2-4, 2-5 Direct Slave access 3-14 Command codes 2-1 operation 3-2 FIFO, response to full or empty 3-2 Latency Timer 2-2, 2-3, 3-12, 3-13, 3-18, 3-27, 3-29 Pause Timer 3-16, 3-27 response to 3-1 Local LRESET# 3-1 Local NMI 6-4 Local TEA# 6-4 Local-to-PCI doorbell interrupt 6-3 map PCI software 3-14 serial EEPROM memory 2-13 map/remap 3-13, 3-15 memory 3-11 commands 2-1 read and write 2-1 serial EEPROM map 2-13 write and invalidate, Direct Master 3-8 new capabilities structure 2-13 Pause Timer 3-29 PCI arbitration 2-2 reset 3-1 SERR# 6-4
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-13
Index
Mailbox to mapping
PCI Bus 3-3 access to internal registers 2-14 cycles 2-1 Direct Slave operation 3-2 FIFO, response to full or empty 3-2 input 3-1 Latency Timer 3-18, 3-29 Little Endian mode 2-5 software reset 3-1 wait states 2-3 PCI Master Command codes 2-1 PCI Master/Target Abort 3-8 pinout 12-8-12-11 Power Management reset 3-1 range for decoding 3-13, 3-15 read accesses 2-14 Direct Slave 3-2 Direct Slave Command codes 2-1 FIFOs 2-4 I/O command 2-1 Local Bus accesses 2-4 memory line 2-1 memory multiple 2-1 Read Ahead mode 2-4 serial EEPROM 2-13 serial EEPROM operation 2-8 Read Ahead mode, in burst read cycles 2-4 read and write accesses 2-1 memory command 2-1 read cycles 3-15 Scatter/Gather DMA mode 3-20-3-22 Scatter/Gather DMA PCI Dual Address cycle 3-22, 3-24 SDMA operation 3-9 serial EEPROM 2-7-2-20 device ID registers 2-7 extra long load 2-11, 2-12 long load 2-10-2-11 memory map 2-13 new capabilities function 2-13 operation 2-8 PCI Bus access to internal registers 2-14 recommended 2-13 register access, internal 2-13 software reset 3-1 timing diagrams 2-15-2-20 vendor ID registers 2-7 software reset 3-1 TA# serial EEPROM initialization 2-8, 2-13
timing diagrams 2-15-2-20, 3-30-3-55 configuration initialization 2-15-2-20 serial EEPROM 2-15-2-20 transfer size bits (TSIZ[0:1]) 2-4 Vital Product Data (VPD) new capabilities function 2-13 register access, internal 2-13 serial EEPROM, read or write 2-9 wait state control 2-2 generation 2-4 Local Bus 2-3 PCI Bus 2-3 write accesses 2-14 cycles 3-15 Direct Slave 3-2 Direct Slave Command codes 2-1 I/O command 2-1 Local Bus accesses 2-4 memory write and invalidate 2-1 serial EEPROM operation 2-8 Mailbox register 0 (MBOX0) 2-11, 4-11, 6-2, 11-5, 11-32, 11-34, 11-35, 11-47 register 1 (MBOX1) 2-11, 4-11, 6-2, 11-5, 11-32, 11-34, 11-35, 11-47 register 2 (MBOX2) 6-2, 11-32, 11-34, 11-35 register 3 (MBOX3) 6-2, 11-32, 11-34, 11-35 register 4 (MBOX4) 11-32 register 5 (MBOX5) 11-33 register 6 (MBOX6) 11-33 register 7 (MBOX7) 11-33 mailbox registers 1-10, 6-2, 11-32-11-33 management, pointer 7-2 map Direct Slave 1-8 PCI software 3-14, 5-11 remap PCI-to-Local addresses 3-13, 5-11 serial EEPROM memory 2-13, 4-12 See Also mapping and remap mapping EROMBA 2-11, 3-13, 3-17, 4-11, 5-11, 5-15, 11-25 LAS0BA 2-11, 3-13, 3-15, 4-11, 5-11, 5-13, 11-12, 11-20 LAS1BA 2-12, 3-13, 3-15, 4-12, 5-11, 5-13, 7-5, 11-13, 11-29, 11-47 PCI-to-Local 3-13, 5-11 register address 11-3-11-7
Index-14
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
MARBR
to non-multiplexed MARBR 2-2, 2-11, 3-2, 3-9, 3-10, 3-11, 3-12, 3-13, 3-18, 3-23, 3-27, 3-29, 4-2, 4-11, 5-2, 5-8, 5-9, 5-10, 5-16, 5-22, 5-25, 11-21, 11-23 Master See Direct Master Master Abort 3-8, 5-7-5-8, 11-9, 11-31 interrupt 6-2 Master Command codes 4-1 Master/Target Abort interrupt 6-2 maximum rating 13-1 MBOX 0 2-11, 4-11, 6-2, 11-5, 11-32, 11-34, 11-35, 11-47 1 2-11, 4-11, 6-2, 11-5, 11-32, 11-34, 11-35, 11-47 2 6-2, 11-32, 11-34, 11-35 3 6-2, 11-32, 11-34, 11-35 4 11-32 5 11-33 6 11-33 7 11-33 MDREQ# 3-4, 11-27, 12-1, 12-10, 13-4, 13-6, 14-3 memory accesses 2-14, 3-7, 3-13, 3-15, 4-13, 5-6, 5-11, 5-13, 7-5, 11-3, 11-7, 11-11, 11-12, 11-13, 11-20, 11-23, 11-29, 11-47 address spaces 11-12, 11-13, 11-20, 11-29 base address 11-11, 11-12, 11-13 commands aliased 2-1, 4-1 basic 2-1, 4-1 Direct Slave transfer 3-11, 5-10 disabled 8-1 local spaces 1-8 mapped configuration registers 11-3 mapping 11-20, 11-29 PCI 8-2, 11-17 PCIBAR0 2-14, 3-7, 4-13, 5-6, 7-5, 11-3, 11-7, 11-11, 11-47 PCIBAR2 3-13, 3-15, 5-11, 5-13, 11-3, 11-12, 11-20, 11-23 PCIBAR3 3-13, 3-15, 5-11, 5-13, 11-3, 11-13, 11-23, 11-29 PCIBAR4 11-3, 11-13 PCIBAR5 11-3, 11-13 posted writes (PMW) 1-8 prefetchable 11-12, 11-13 read 2-1, 4-1 register location 11-11, 11-12, 11-13 remap 11-20 serial EEPROM map 2-13, 4-12 space indicator 11-11, 11-12, 11-13, 11-20, 11-29 spaces 11-8, 11-20, 11-29 write 2-1, 4-1 write and invalidate 11-8, 11-10 write and invalidate, Direct Master 3-8, 5-8 write transfers 11-10 messages inbound 7-1 outbound 7-1 Messaging Queue Configuration register (MQCR) 7-2, 11-45 Messaging Queue registers 11-44-11-47 address mapping 11-7 Mode/DMA Arbitration register (MARBR) 2-2, 2-11, 3-2, 3-9, 3-10, 3-11, 3-12, 3-13, 3-18, 3-23, 3-27, 3-29, 4-2, 4-11, 5-2, 5-8, 5-9, 5-10, 5-16, 5-22, 5-25, 11-21, 11-23 MODE[1:0] 4-2, 12-6, 14-3 Motorola MPC850 1-7, 2-4, 3-9, 3-20 PowerQUICC adapter design 1-3, 1-4 MPC860 1-7, 2-3, 2-4, 3-9, 3-20 PowerQUICC adapter design 1-3, 1-4 MQCR 7-2, 11-45 multiplexed interface 12-1 Local Bus types 1-7, 2-2, 4-2, 12-1 PCI address/data bus 12-3 pins, input/output 6-5, 12-10, 12-11, 12-13, 12-15, 12-17, 12-19 pins, PCI 12-3 single pin, CompactPCI 1-10 write and read data 12-6
N
new capabilities functions support 11-9 linked list 8-1 Next_Cap Pointer 9-4 register 8-1 structure 1-7, 2-13, 4-12, 9-4, 10-1 support bit 8-1 VPD 10-1 New Capabilities Pointer register (CAP_PTR) 8-1, 11-14 non-multiplexed interface 12-1 Local Bus types 1-7, 2-2, 4-2, 12-1
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-15
Index
OFHPR to PCI Base Address register
O
OFHPR 7-2, 11-46 OFTPR 7-2, 11-46 on-the-fly Big/Little Endian conversion 3-12, 5-10 operating ranges 13-1 OPHPR 7-2, 11-46 OPQIM 11-44 OPQIS 7-3, 11-44 OPTPR 7-2, 11-46 OQP 11-44 ordering instructions A-1 Outbound Free Head Pointer register (OFHPR) 7-2, 11-46 free list FIFO 7-5 free queue 7-4 Free Tail Pointer register (OFTPR) 7-2, 11-46 OFHPR 7-2 OFTPR 7-2 OPHPR 7-2, 11-46 OPTPR 7-2 Post Head Pointer register (OPHPR) 7-2, 11-46 post queue 7-4 post queue FIFOs 7-3 Post Queue Interrupt Mask register (OPQIM) 11-44 Post Queue Interrupt Status register (OPQIS) 7-3, 11-44 Post Tail Pointer register (OPTPR) 7-2, 11-46 queue port 7-4 Queue Port register (OQP) 11-44 output, user 6-5
P
P2LDBELL 6-2, 6-3, 11-33 PABTADR 3-8, 5-8, 6-2, 11-31 package specs 14-1-14-3 PAR 12-4, 14-3 Pause Timer 3-16, 3-27, 3-29, 4-2, 5-14, 5-16, 5-25, 11-21 PBGA ordering instructions A-1 package mechanical dimensions 14-1 packaging 1-9 PCB layout suggested land pattern 14-1 PCI 9056 features 1-10 pinout 12-3-12-19, 14-2-14-3 PCI arbitration 2-2, 4-2 buffered 1-10
Built-In Self Test register (PCIBISTR) 6-3, 11-11, 11-35 Cache Line Size register (PCICLSR) 3-8, 3-22, 5-8, 5-22, 11-10, 11-37, 11-40 Cardbus CIS Pointer register (PCICIS) 11-13 Class Code register (PCICCR) 2-11, 4-11, 7-5, 11-10 Command Codes register (CNTRL) 2-1, 2-8, 2-10, 2-12, 3-1, 3-2, 4-1, 4-9, 4-10, 5-1, 5-2, 6-5, 11-36 Command register (PCICR) 3-2, 3-6, 3-8, 3-18, 3-22, 5-2, 5-6, 5-8, 5-15, 5-22, 6-4, 11-8, 11-9, 11-23 Configuration ID register (PCIIDR) 2-11, 4-8, 4-11, 11-8 Dual Address cycle 2-1, 4-1 Expansion ROM Base register (PCIERBAR) 3-13, 5-11, 11-14, 11-24 Hardwired Configuration ID register (PCIHIDR) 2-7, 11-37 Hardwired Revision ID register (PCIHREV) 11-37 Header Type register (PCIHTR) 11-10 industrial implementations 1-1 Interrupt Line register (PCIILR) 2-11, 4-11, 11-14 Interrupt Pin register (PCIIPR) 2-11, 4-11, 11-14 Master Command codes 4-1 Master/Target Abort 3-8, 5-7-5-8, 11-31 Max_Lat register (PCIMLR) 2-11, 4-11, 11-15 Min_Gnt register (PCIMGR) 2-11, 4-11, 11-15 pins 12-3-12-5 reset, Host mode 3-1 Revision ID register (PCIREV) 2-11, 4-11, 11-9 Status register (PCISR) 2-13, 3-8, 3-13, 3-27, 4-12, 5-7, 6-2, 6-4, 11-9, 11-23, 11-34, 12-14, 12-18 Subsystem ID register (PCISID) 2-12, 4-12, 11-14 Subsystem Vendor ID register (PCISVID) 2-7, 2-12, 4-8, 4-12, 11-13 Vital Product Data Address register (PVPDAD) 10-1, 11-19 Vital Product Data Control register (PVPDCNTL) 10-1, 11-19 Vital Product Data Next Capability Pointer register (PVPD_NEXT) 2-13, 4-12, 10-1, 11-19 PCI 9054 1-10 PCI 9056 compared with PCI 9054 and PCI 9656 1-10 compatibility with other PLX chips 1-9 major features 1-7-1-8 PCI 9656 1-10 PCI Abort Address register (PABTADR) 3-8, 5-8, 6-2, 11-31 PCI Arbiter Control register (PCIARB) 2-12, 4-12, 11-31 PCI Base Address register PCIBAR0 2-14, 3-7, 4-13, 5-6, 7-5, 11-3, 11-7, 11-11, 11-47 PCIBAR1 2-14, 4-13, 11-3, 11-12, 11-23
Index-16
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Bus to pins
PCIBAR2 3-13, 3-15, 5-11, 5-13, 11-3, 11-12, 11-20, 11-23 PCIBAR3 3-13, 3-15, 5-11, 5-13, 11-3, 11-13, 11-23, 11-29 PCIBAR4 11-3, 11-13 PCIBAR5 11-3, 11-13 PCI Bus accessibility of spaces 1-8, 3-13, 5-11 board healthy 9-2 cycles 2-1, 4-1 Direct Slave accesses 4-5 example 3-15, 5-13 lock 3-10, 5-9 operation 3-2, 5-2 transfer 3-11, 5-10 drivers 8-1 FIFO, response to full or empty 3-2, 5-2 input RST# 3-1, 5-1 internal registers, access to 2-14, 4-14 Latency Time register (PCILTR) 3-18, 3-29, 5-16, 5-25, 11-10 Latency Timer 3-18, 11-3, 11-10 Little Endian mode 2-5, 2-7, 4-5 Master accesses 2-4 PCIMLR 2-11, 4-11, 11-15 PMCSR 8-2, 8-3, 11-3, 11-17, 11-18, 11-34 software reset 3-1, 5-1 VPD 10-1 wait states 2-3, 4-3 PCI Bus Power Management Interface Specification, Revision 1.1 8-1, 8-2, 8-3, 11-16, 12-7 PCI Hot-Plug Specification, Revision 1.0 1-7 PCI Initiator See Direct Master PCI Local Bus Specification, Revision 2.1 1-7, 1-10, PCIBAR3 3-13, 3-15, 5-11, 5-13, 11-3, 11-13, 11-23, 11-29 PCIBAR4 11-3, 11-13 PCIBAR5 11-3, 11-13 PCIBISTR 6-3, 11-11, 11-35 PCICCR 2-11, 4-11, 7-5, 11-10 PCICIS 11-13 PCICLSR 3-8, 3-22, 5-8, 5-22, 11-10, 11-37, 11-40 PCICR 3-2, 3-6, 3-8, 3-18, 3-22, 5-2, 5-6, 5-8, 5-15, 5-22, 6-4, 11-8, 11-9, 11-23 PCIERBAR 3-13, 5-11, 11-14, 11-24 PCIHIDR 2-7, 4-8, 11-37 PCIHREV 11-37 PCIHTR 11-10 PCIIDR 2-7, 2-11, 4-8, 4-11, 11-8 PCIILR 2-11, 4-11, 11-14 PCIIPR 2-11, 4-11, 11-14 PCILTR 3-18, 3-29, 5-16, 5-25, 11-10 PCIMGR 2-11, 4-11, 11-15 PCIMLR 2-11, 4-11, 11-15 PCIREV 2-11, 4-11, 11-9 PCISID 2-12, 4-12, 11-14 PCISR 2-13, 3-8, 3-13, 3-27, 4-12, 5-7, 6-2, 6-4, 11-9, 11-23, 11-34, 12-14, 12-18 PCISVID 2-7, 2-12, 4-8, 4-12, 11-13 PCI-to-Local 3-26 PCI-to-Local doorbell interrupt 6-3 PCLK 12-4, 13-3, 14-3 PERR# 2-4, 4-5, 6-4, 11-9, 12-4, 14-3 physical specs 14-1-14-3 PICMG 2.1, R2.0, CompactPCI Hot Swap Specification 1-4, 1-7, 1-10, 2-8, 4-9, 9-1, 9-2 pinout PBGA 12-3-12-19, 14-2-14-3 specs 14-1-14-3 pins 12-1-12-19 2.5VAUX 8-2, 12-7, 14-3 AD[31:0] 12-3, 14-3 ADS# 5-10, 11-24, 12-1, 12-12, 12-16, 13-5, 14-3 ALE 5-10, 12-1, 12-16, 13-5, 14-3 BB# 1-8, 2-2, 3-2, 3-12, 3-16, 3-17, 3-29, 11-25, 12-1, 12-8, 13-4, 13-6, 14-3 BD_SEL# 9-1, 9-2, 12-5, 14-3 BDIP# 2-3, 2-4, 3-4, 3-5, 3-13, 3-20, 3-27, 3-28, 3-29, 11-38, 11-40, 12-1, 12-8, 13-4, 13-6, 14-3 BG# 2-2, 3-16, 3-17, 3-27, 3-29, 11-25, 12-1, 12-8, 13-4, 14-3 BI# 2-3, 2-4, 3-8, 3-12, 3-18, 3-20, 3-28, 3-29, 12-1, 12-8, 13-4, 13-6, 14-3 BIGEND# 1-8, 2-5, 2-7, 4-6, 4-8, 11-21, 11-22, 12-1, 12-8, 12-12, 12-16, 13-4, 13-5, 13-6, 14-3
11-11, 11-12, 11-13, 11-20, 11-29
PCI Local Bus Specification, Revision 2.2 1-3, 1-4,
1-7, 1-10, 1-11, 2-1, 2-8, 3-16, 4-1, 4-8, 5-14, 8-1, 8-2, 8-3, 10-1, 11-3, 11-11, 11-12, 11-13, 11-20, 11-29, 12-1, 12-3
PCI Master Command codes 2-1, 4-1 PCI NMI, all modes 6-4 PCI SERR#, all modes 6-4 PCI Target See Direct Slave PCIARB 2-12, 4-12, 11-31 PCIBAR0 2-14, 3-7, 4-13, 5-6, 7-5, 11-3, 11-7, 11-11, 11-47 PCIBAR1 2-14, 4-13, 11-3, 11-12, 11-23 PCIBAR2 3-13, 3-15, 5-11, 5-13, 11-3, 11-12, 11-20, 11-23
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-17
Index
pins to pins
BLAST# 3-18, 4-2, 4-4, 5-2, 5-5, 5-16, 5-24, 5-25, 11-38, 11-40, 12-1, 12-12, 12-16, 13-5, 13-7, 14-3 BR# 2-2, 3-16, 3-29, 11-21, 11-25, 12-1, 12-8, 13-6, 14-3 BREQi 4-2, 5-16, 5-25, 11-21, 12-1, 12-12, 12-16, 13-5, 14-3 BREQo 5-15, 11-4, 11-21, 11-25, 12-1, 12-12, 12-16, 13-7, 14-3 BTERM# 2-3, 3-12, 3-13, 3-18, 3-20, 3-28, 3-29, 4-3, 4-4, 5-7, 5-16, 5-18, 11-25, 11-26, 11-30, 11-37, 11-39, 12-1, 12-12, 12-16, 13-5, 13-7, 14-3 BURST# 2-4, 3-5, 12-1, 12-8, 13-4, 13-6, 14-3 C Bus mode 12-12-12-15 C/BE[3:0]# 2-1, 2-4, 3-6, 3-7, 3-10, 3-18, 4-1, 5-4, 5-5, 5-7, 5-9, 5-16, 12-3, 12-4, 14-3 Card_VAUX 8-2, 8-3, 12-7, 14-3 CCS# 2-14, 4-14, 12-1, 12-8, 12-12, 12-16, 13-4, 13-5, 14-3 common to all bus modes 12-3-12-7 CompactPCI Hot Swap 12-5 CPCISW 9-1, 9-3, 12-5, 14-3 DACK0# 1-3, 11-37, 12-1, 12-9, 12-12, 12-16, 13-6, 13-7, 14-3 DACK1# 1-3, 11-40, 12-1, 12-9, 12-12, 12-17, 14-3 DEN# 12-17, 13-7, 14-3 DEVSEL# 3-8, 5-7, 11-9, 12-3, 14-3 DMPAF 3-4, 5-4, 11-21, 11-27, 12-1, 12-10, 12-13, 12-17, 13-4, 13-5, 13-6, 13-7, 14-3 DP[0:3] 2-4, 12-9, 12-13, 13-4, 13-6, 14-3 DP[3:0] 4-5, 12-1, 12-17, 13-5, 13-7, 14-3 DREQ0# 1-3, 3-9, 3-23, 3-27, 3-28, 3-29, 5-22, 5-24, 5-25, 11-37, 11-38, 12-1, 12-9, 12-13, 12-17, 14-3 DREQ1# 1-3, 3-9, 3-23, 3-27, 3-28, 3-29, 5-22, 5-24, 5-25, 11-40, 12-1, 12-9, 12-13, 12-17, 13-4, 13-5, 14-3 DT/R# 12-17, 13-7, 14-3 EECS 2-9, 2-15, 4-9, 4-15, 12-1, 12-6, 14-3 EEDI 2-9, 2-15, 4-9, 4-15, 11-36, 12-1, 12-6, 14-3 EEDO 2-9, 2-15, 4-9, 4-15, 11-1, 11-36, 12-1, 12-6, 14-3 EESK 2-8, 2-9, 2-15, 4-9, 4-15, 12-1, 12-6, 14-3 ENUM# 1-4, 9-1, 9-3, 9-4, 11-1, 11-18, 12-5, 14-3 EOT# 1-3, 3-20, 3-23, 3-27, 3-28, 3-29, 5-15, 5-22, 5-24, 5-25, 11-1, 11-2, 11-37, 11-38, 11-40, 12-1, 12-10, 12-13, 12-17, 13-4, 13-5, 13-6, 13-7, 14-3 FRAME# 2-2, 3-10, 4-2, 5-8, 11-21, 11-31, 12-3, 14-3 GNT# 3-18, 3-29, 5-16, 5-25, 11-31, 12-4, 14-3 GNT[6:1]# 12-3, 14-3 GNT0# 11-31, 12-3, 14-3 ground 12-7 HOSTEN# 6-2, 6-4, 11-1, 11-36, 12-1, 12-6, 12-10, 12-14, 12-18, 14-3 IDDQEN# 8-3, 12-1, 12-6, 14-3 IDSEL 3-7, 5-6, 12-3, 14-3 INTA# 3-18, 3-20, 5-16, 5-18, 6-2, 8-3, 11-14, 11-36, 12-3, 14-3
IRDY# 2-3, 3-2, 4-3, 5-2, 11-27, 12-3, 14-3 J Bus mode 12-16-12-19 JTAG 12-5 LA[0:31] 12-1, 12-9, 13-4, 13-6, 14-3 LA[28:2] 12-1, 12-17, 13-7, 14-3 LA[31:0] 12-1 LA[31:2] 3-15, 12-13, 14-3 LAD[31:0] 4-6, 12-17, 12-18, 13-5, 13-7, 14-3 LBE[3:0]# 5-9, 5-13, 12-1, 12-13, 12-18, 13-5, 13-7, 14-3 LCLK 11-24, 12-5, 12-9, 12-14, 12-16, 12-18, 13-3, 14-3 LD[0:31] 2-5, 3-15, 4-6, 5-13, 12-1, 12-9, 12-13, 13-4, 13-6, 14-3 LD[0:7] 2-5, 3-15, 4-6, 5-13, 12-13 LD[16:23] 2-5, 3-15, 4-6, 5-13, 12-13 LD[24:31] 2-5, 3-15, 4-6, 5-13, 12-13 LD[31:0] 2-5, 3-15, 4-6, 5-13, 12-1, 12-13, 12-14, 13-5, 13-7, 14-3 LD[8:15] 2-5, 3-15, 4-6, 5-13, 12-13 LEDon# 9-1, 9-3, 12-5, 14-3 LHOLD 1-8, 4-2, 5-2, 5-10, 5-14, 5-25, 11-25, 12-1, 12-14, 12-18, 13-7, 14-3 LHOLDA 4-2, 5-14, 5-15, 5-24, 5-25, 11-25, 12-1, 12-14, 12-18, 13-5, 14-3 LINTi# 6-1-6-2, 12-1, 12-9, 12-14, 12-18, 14-3 LINTo# 3-18, 3-20, 5-16, 5-18, 6-2, 7-5, 7-6, 8-2, 8-3, 11-1, 11-36, 12-1, 12-3, 12-9, 12-14, 12-18, 14-3 LLOCKi# 11-36, 12-1, 12-11, 12-15, 12-19, 13-4, 13-5, 14-3 LLOCKo# 11-36, 12-1, 12-11, 12-15, 12-19, 13-6, 13-7, 14-3 LOCK# 1-8, 3-10, 5-9, 11-21, 12-4, 14-3 LRESET# 3-1, 5-1, 8-2, 9-3, 11-36, 12-1, 12-4, 12-10, 12-14, 12-18, 14-3 LSERR# 4-5, 5-7, 6-4-6-5, 11-1, 11-34, 11-36, 11-47, 12-1, 12-14, 12-18, 13-7, 14-3 LW/R# 5-7, 12-1, 12-14, 12-19, 13-5, 13-7, 14-3 M Bus mode 12-8-12-11 MDREQ# 3-4, 11-27, 12-1, 12-10, 13-4, 13-6, 14-3 MODE[1:0] 4-2, 12-6, 14-3 PAR 12-4, 14-3 PCI 12-3-12-5 PCLK 12-4, 13-3, 14-3 PERR# 2-4, 4-5, 6-4, 11-9, 12-4, 14-3 PME# 1-7, 8-2, 8-3, 11-16, 11-17, 12-4, 12-7, 14-3 PMEREQ# 8-3, 12-1, 12-10, 12-14, 12-19, 14-3 power 12-7 PRESENT_DET 8-2, 12-7, 14-3 RD/WR# 3-7, 12-1, 12-10, 13-4, 13-6, 14-3 READY# 4-3, 4-5, 4-8, 4-13, 5-2, 5-4, 5-5, 5-7, 5-9, 5-15, 5-24, 12-15, 12-19, 13-5, 13-7, 14-3
Index-18
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
platform, reset
to priority DMA REQ# 2-2, 3-2, 3-5, 3-16, 3-29, 4-2, 5-2, 5-5, 5-14, 5-25, 11-21, 12-3, 14-3 REQ[6:1]# 12-4, 14-3 REQ0# 11-31, 12-4, 14-3 RETRY# 3-2, 3-4, 3-6, 3-9, 3-17, 11-23, 11-25, 12-1, 12-10, 13-6, 14-3 RST# 1-7, 3-1, 5-1, 8-2, 9-2, 11-36, 12-4, 12-10, 12-14, 12-18, 14-3 serial EEPROM 12-6 SERR# 2-4, 3-13, 3-27, 4-5, 6-4, 11-8, 11-9, 11-23, 11-34, 11-36, 12-4, 14-3 STOP# 3-9, 3-18, 5-8, 5-16, 12-5, 14-3 system 12-6 TA# 2-2, 3-2, 3-4, 3-5, 3-6, 3-8, 3-9, 3-10, 3-13, 3-27, 12-10, 14-3 TCK 12-5, 14-3 TDI 12-5, 12-20, 12-21, 14-3 TDO 12-5, 12-20, 12-21, 14-3 TEA# 2-5, 3-8, 3-13, 3-27, 6-4, 11-1, 11-23, 11-34, 11-36, 11-47, 12-1, 12-4, 12-10, 13-6, 14-3 TMS 12-5, 12-20, 14-3 TRDY# 2-3, 3-2, 3-9, 3-12, 3-15, 3-16, 4-3, 5-2, 5-8, 5-10, 5-14, 11-26, 12-4, 12-5, 14-3 TRST 12-5, 12-20, 14-3 TS# 2-3, 2-4, 2-14, 3-11, 3-12, 3-17, 3-27, 11-24, 12-1, 12-10, 13-4, 13-6, 14-3 TSIZ[0:1] 2-4, 3-5, 3-10, 3-15, 12-1, 12-10, 13-4, 13-6, 14-3 USERi 3-17, 5-15, 6-5, 11-36, 12-1, 12-11, 12-15, 12-19, 13-4, 13-5, 14-3 USERo 3-17, 5-15, 6-5, 11-36, 12-1, 12-11, 12-15, 12-19, 13-6, 13-7, 14-3 VCORE 12-7, 14-3 VIO 9-1, 9-2, 12-7, 13-1, 14-3 VRING 12-7, 14-3 VSS 12-7, 13-1, 13-2, 14-3 WAIT# 4-3, 11-21, 12-1, 12-8, 12-15, 12-19, 13-4, 13-5, 13-6, 13-7, 14-3 platform, reset 9-2 PLX Technology, Inc. company background 1-1 product ordering instructions A-1 representatives and distributors A-1 technical support A-1 PMC 8-2, 11-16, 11-17, 12-7 PMCAPID 8-1, 11-15 PMCSR 8-2, 8-3, 11-3, 11-17, 11-18, 11-34 PMCSR_BSE 11-17 PMDATA 8-2, 11-16, 11-18 PME# 1-7, 8-2, 8-3, 11-16, 11-17, 12-4, 12-7, 14-3 PME#_Status 8-2, 11-17 PMEREQ# 8-3, 12-1, 12-10, 12-14, 12-19, 14-3 PMNEXT 2-13, 4-12, 8-1, 11-15 pointer diagram 7-4 pointer management 7-2 post queue 7-4 FIFO, inbound 7-3 FIFO, outbound 7-3 outbound 7-4 power and ground pins 12-7 Power Management 8-1-8-3 66 MHz PCI Clock, D2 support 8-2 Capabilities register (PMC) 8-2, 11-16, 11-17, 12-7 Capability ID register (PMCAPID) 8-1, 11-15 Control/Status register (PMCSR) 8-2, 8-3, 11-3, 11-17, 11-18, 11-34 D3cold PME logic, during 12-6, 12-7 PME request 12-10, 12-14, 12-19 support 1-5, 1-10 Data register (PMDATA) 8-2, 11-16, 11-18 functional description 8-1-8-2 Next Capability Pointer register (PMNEXT) 2-13, 4-12, 8-1, 11-15 pins 8-2, 8-3, 12-4, 12-7, 12-10, 12-14 PMCSR Bridge Support Extension register (PMCSR_BSE) 11-17 Power mode example 8-3 power state support 1-7 reset 3-1, 5-1 states 8-1 system changes 8-3 wake-up request example 8-3 See D0, D1, D2, D3hot or D3cold power states, functional 8-1 PowerQUICC 1-7 adapter design 1-3, 1-4 precharge voltage, BIAS 9-3 preempt deadlock solution 3-17, 5-15 prefetch LAS0RR 11-20 LAS1RR 11-29 PCIBAR0 11-11 PCIBAR2 11-12 PCIBAR3 11-13 programmable counter 1-8, 1-10, 5-8 Read Ahead mode 1-8 Direct Master 3-5-3-6, 5-5-5-6 Direct Slave 3-11, 5-9-5-10 PRESENT_DET 8-2, 12-7, 14-3 priority DMA 3-23, 5-22
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-19
Index
programmable to read
programmable almost full flag 11-27 almost full status output 12-10, 12-13, 12-17 Direct Master Delayed Write mode 3-5, 5-5 Transfer mode 1-3 Direct Slave Delayed Write mode 3-11, 5-10 Local Bus READY# Timeout mode 5-10 Local Bus TA# Timeout mode 3-11 Transfer mode 1-3 FIFOs 1-7 internal register configuration 1-8, 3-12, 5-10 internal registers 2-1, 2-7, 3-1, 4-1, 4-8, 5-1 Local Bus Latency timer 3-29, 5-25 Pause timer 3-29, 5-25 Region Descriptor register 5-14 wait states 1-1 prefetch counter 1-8, 1-10 modes 3-5, 5-5 wait state counter 2-2 generator 12-12, 12-15, 12-16, 12-19 wait states 1-8 Programming Interface 1-5, 7-5, 9-2, 9-4, 11-10, 11-18 PROT_AREA 2-11, 4-11, 10-2, 11-23 PVPD_NEXT 2-13, 4-12, 10-1, 11-19 PVPDAD 10-1, 11-19 PVPDATA, PCI VPD Data register 10-1, 11-19 PVPDCNTL 10-1, 11-19
port, inbound 7-4 port, outbound 7-4 starting address 7-2 Status/Control register (QSR) 7-3, 7-5, 11-5, 11-7, 11-13, 11-29, 11-32, 11-47
R
Range registers Expansion ROM register (EROMRR) 11-24 Local Address Space 0 for PCI-to-Local Bus (LAS0RR) 11-20 Local Address Space 1 for PCI-to-Local Bus (LAS1RR) 11-29 Local Range Register for Direct Master-to-PCI (DMRR) 2-11, 3-2, 3-7, 4-11, 5-2, 5-6, 11-26 ranges, operating 13-1, 13-2 RD/WR# 3-7, 12-1, 12-10, 13-4, 13-6, 14-3 read accesses 2-1, 2-14, 4-1, 4-14 configuration command 2-1, 4-1 delayed 1-10 Direct Master 1-7 Direct Slave 1-7, 3-2, 3-10, 5-2, 5-9 Direct Slave Command codes 2-1, 4-1 Direct Slave transfer 3-11, 5-10 DMA 1-7 FIFOs 1-8, 2-4, 3-4, 3-9, 4-4, 5-4, 5-8 I/O command 2-1, 4-1 Local Bus accesses 2-4, 4-5 memory command 2-1, 4-1 line 2-1, 4-1 multiple 2-1, 4-1 PCI initialization 3-14, 5-11 Power mode example 8-3 Read Ahead mode 2-4, 3-5-3-6, 3-11, 4-5, 5-5-5-6, 5-9-5-10 read and write, random 10-2 sequential read only 10-1 serial EEPROM 2-13 accidental write 10-2 control 1-10, 2-10, 4-11 operation 2-8, 4-9 VPD 10-1 data 10-1 read and write, random 10-2 registers 10-1, 11-19 sequential read only 10-1 serial EEPROM partitioning 10-1
Q
QBAR 7-1, 7-2, 11-45 QSR 7-3, 7-5, 11-5, 11-7, 11-13, 11-29, 11-32, 11-47 Queue Base Address register (QBAR) 7-1, 7-2, 11-45 circular FIFO operation diagram 7-4 circular FIFO summary 7-6 FIFOs 7-2-7-6 I2O 7-5 I2O pointer management 7-2 inbound free 7-4 inbound free list FIFO 7-3 inbound messages 7-1 outbound free list FIFO 7-5 outbound messages 7-1 outbound post 7-4 outbound post FIFO 7-3
Index-20
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Read Ahead mode to registers
Read Ahead mode burst read cycles 2-4, 4-5 Direct Master 3-5-3-6, 5-5-5-6 Direct Slave 3-11, 5-9-5-10 supported 1-8 Read mode, Delayed 3-10, 5-9 READY# 4-3, 5-2, 5-4, 5-5, 5-7, 5-9, 5-15, 5-24, 12-15, 12-19, 14-3 Bus mode 13-5, 13-7 input 4-5 output 13-7 serial EEPROM initialization 4-8, 4-13 reconfiguration, system See configuration recovery states (J mode only) 4-5 registers addresses 1-10 BIGEND 2-5, 2-11, 4-6, 4-11, 11-22 CAP_PTR 8-1, 11-14 CNTRL 2-1, 2-8, 2-10, 2-12, 3-1, 3-2, 4-1, 4-9, 4-10, 5-1, 5-2, 6-5, 11-36 DMAARB 11-42 DMACSR0 3-18, 3-20, 3-22, 3-25, 5-16, 5-18, 5-20, 5-22, 6-4, 11-38, 11-42 DMACSR1 3-18, 3-20, 3-22, 3-25, 5-16, 5-18, 5-20, 5-22, 6-4, 11-40, 11-42 DMADAC0 3-18, 3-20, 3-22, 3-24, 5-16, 5-18, 5-19, 5-21, 11-43 DMADAC1 3-18, 3-20, 3-22, 3-24, 5-16, 5-18, 5-19, 5-21, 11-43 DMADPR0 3-20, 5-18, 11-39 DMADPR1 3-20, 5-18, 11-41 DMALADR0 11-38 DMALADR1 11-41 DMAMODE0 2-3, 3-12, 3-18, 3-20, 3-22, 3-24, 3-25, 3-27, 3-28, 4-3, 5-16, 5-18, 5-19, 5-21, 5-22, 5-24, 5-25, 6-3, 6-4, 11-2, 11-8, 11-36, 11-37, 11-38, 11-39, 11-41 DMAMODE1 2-3, 3-12, 3-18, 3-20, 3-22, 3-24, 3-25, 3-27, 3-28, 4-3, 5-16, 5-18, 5-19, 5-21, 5-22, 5-24, 5-25, 6-3, 6-4, 11-2, 11-8, 11-36, 11-38, 11-39, 11-41 DMAPADR0 11-38 DMAPADR1 11-41 DMASIZ0 11-38, 11-39 DMASIZ1 11-38, 11-40, 11-41 DMATHR 11-43 DMCFGA 2-11, 3-2, 3-5, 3-6, 4-11, 5-2, 5-5, 5-6, 11-28 DMDAC 3-2, 3-7, 5-2, 5-7, 11-30 DMLBAI 2-11, 3-2, 3-7, 4-11, 5-2, 5-6, 11-27 DMLBAM 2-11, 3-2, 4-11, 5-2, 11-26 DMPBAM 2-1, 2-2, 2-11, 3-2, 3-6, 3-8, 3-9, 4-1, 4-2, 4-11, 5-2, 5-5, 5-6, 5-8, 11-27 DMRR 2-11, 3-2, 3-7, 4-11, 5-2, 5-6, 11-26 doorbell 6-2, 6-3, 11-33 EROMBA 2-11, 3-13, 3-17, 4-11, 5-11, 5-15, 11-25 EROMRR 2-11, 3-13, 4-11, 5-11, 11-14, 11-24 HS_CNTL 2-12, 4-12, 9-4, 11-18 HS_CSR 1-4, 2-12, 2-13, 4-12, 9-1, 9-3, 9-4, 11-18 HS_NEXT 11-18 IFHPR 7-2, 11-45 IFTPR 7-2, 11-45 INTCSR 3-8, 3-25, 5-7, 5-22, 6-1, 6-2, 6-3, 6-4, 6-5, 8-2, 11-34, 12-9, 12-14, 12-18 IPHPR 7-2, 11-45 IPTPR 7-2, 11-46 IQP 7-3, 11-44 L2PDBELL 6-2, 6-3, 11-33 LAS0BA 2-11, 3-13, 3-15, 4-11, 5-11, 5-13, 11-12, 11-20 LAS0RR 2-11, 3-13, 4-11, 5-11, 11-12, 11-20 LAS1BA 2-12, 3-13, 3-15, 4-12, 5-11, 5-13, 7-5, 11-13, 11-29, 11-47 LAS1RR 2-12, 3-13, 4-12, 5-11, 11-13, 11-29, 11-47 LBRD0 2-3, 2-9, 2-11, 2-12, 3-2, 3-9, 3-12, 3-13, 3-16, 4-3, 4-9, 4-10, 4-11, 5-2, 5-8, 5-11, 5-14, 11-25 LBRD1 2-3, 2-12, 3-9, 3-12, 3-13, 4-3, 4-12, 5-8, 5-11, 11-30, 11-47 LMISC1 2-8, 2-9, 2-11, 3-1, 3-2, 3-4, 3-6, 3-9, 3-13, 3-27, 4-8, 4-10, 4-11, 5-1, 5-2, 6-4, 7-5, 11-12, 11-23 LMISC2 2-11, 3-11, 4-11, 5-10, 11-24 mailbox 6-2, 11-32-11-33 MARBR 2-2, 2-11, 3-2, 3-9, 3-10, 3-11, 3-12, 3-13, 3-18, 3-23, 3-27, 3-29, 4-2, 4-11, 5-2, 5-8, 5-9, 5-10, 5-16, 5-22, 5-25, 11-21, 11-23 MBOX0 2-11, 4-11, 6-2, 11-5, 11-32, 11-34, 11-35, 11-47 MBOX1 2-11, 4-11, 6-2, 11-5, 11-32, 11-34, 11-35, 11-47 MBOX2 6-2, 11-32, 11-34, 11-35 MBOX3 6-2, 11-32, 11-35 MBOX4 11-32 MBOX5 11-33 MBOX6 11-33 MBOX7 11-33 MQCR 7-2, 11-45 new, summary of 11-1 OFHPR 7-2, 11-46 OFTPR 7-2, 11-46 OPHPR 7-2, 11-46 OPQIM 11-44 OPQIS 7-3, 11-44 OPTPR 7-2, 11-46 OQP 11-44 P2LDBELL 6-2, 6-3, 11-33 PABTADR 3-8, 5-8, 6-2, 11-31 PCIARB 2-12, 4-12, 11-31 PCIBAR0 2-14, 3-7, 4-13, 5-6, 7-5, 11-3, 11-7, 11-11, 11-47
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-21
Index
remap to serial EEPROM
PCIBAR1 2-14, 4-13, 11-3, 11-12, 11-23 PCIBAR2 3-13, 3-15, 5-11, 5-13, 11-3, 11-12, 11-20, 11-23 PCIBAR3 3-13, 3-15, 5-11, 5-13, 11-3, 11-13, 11-23, 11-29 PCIBAR4 11-3, 11-13 PCIBAR5 11-3, 11-13 PCIBISTR 6-3, 11-11, 11-35 PCICCR 2-11, 4-11, 7-5, 11-10 PCICIS 11-13 PCICLSR 3-8, 3-22, 5-8, 5-22, 11-10, 11-37, 11-40 PCICR 3-2, 3-6, 3-8, 3-18, 3-22, 5-2, 5-6, 5-8, 5-15, 5-22, 6-4, 11-8, 11-9, 11-23 PCIERBAR 3-13, 5-11, 11-14, 11-24 PCIHIDR 2-7, 4-8, 11-37 PCIHREV 11-37 PCIHTR 11-10 PCIIDR 2-7, 2-11, 4-8, 4-11, 11-8 PCIILR 2-11, 4-11, 11-14 PCIIPR 2-11, 4-11, 11-14 PCILTR 3-18, 3-29, 5-16, 5-25, 11-10 PCIMGR 2-11, 4-11, 11-15 PCIMLR 2-11, 4-11, 11-15 PCIREV 2-11, 4-11, 11-9 PCISID 2-12, 4-12, 11-14 PCISR 2-13, 3-8, 3-13, 3-27, 4-12, 5-7, 6-2, 6-4, 11-9, 11-23, 11-34, 12-14, 12-18 PCISVID 2-7, 2-12, 4-8, 4-12, 11-13 PMC 8-2, 11-16, 11-17, 12-7 PMCAPID 8-1, 11-15 PMCSR 8-2, 8-3, 11-3, 11-17, 11-18, 11-34 PMCSR_BSE 11-17 PMDATA 8-2, 11-16, 11-18 PMNEXT 2-13, 4-12, 8-1, 11-15 PROT_AREA 2-11, 4-11, 10-2, 11-23 PVPD_NEXT 2-13, 4-12, 10-1, 11-19 PVPDAD 10-1, 11-19 PVPDATA 10-1, 11-19 PVPDCNTL 10-1, 11-19 QBAR 7-1, 7-2, 11-45 QSR 7-3, 7-5, 11-5, 11-7, 11-13, 11-29, 11-32, 11-47 summary of new 11-1 remap PCI-to-Local addresses 3-13, 5-11 See Also map and mapping REQ# 2-2, 3-2, 3-5, 3-16, 3-29, 4-2, 5-2, 5-5, 5-14, 5-25, 11-21, 12-3, 14-3 REQ[6:1]# 12-4, 14-3 REQ0# 11-31, 12-4, 14-3
reset platform 9-2 software 3-1, 5-1 RETRY# 3-2, 3-4, 3-6, 3-9, 3-17, 11-23, 11-25, 12-1, 12-10, 13-6, 14-3 ring management 1-2 round-robin arbitration 11-31 RST# 1-7, 3-1, 5-1, 8-2, 9-2, 11-36, 12-4, 12-10, 12-14, 12-18, 14-3 runtime registers 11-32-11-37 address mapping 11-5
S
Scatter/Gather 3-22, 3-24, 5-18 DMA 3-22, 5-20 list management 1-2 mode, DMA 1-2 ring management 1-2 SDMA accesses 3-4 channels 3-4 operation 3-9 sequence, enable 7-5 serial EEPROM 2-7-2-20, 3-1, 4-8-4-22, 5-1 accidental write to 10-2 address decode enable 11-24 base class code 11-10 Control register (CNTRL) 2-1, 2-8, 2-10, 2-12, 3-1, 3-2, 4-1, 4-9, 4-10, 5-1, 5-2, 6-5, 11-36 device ID 11-8 device ID registers 2-7, 4-8 extra long load 2-11, 2-12, 4-10-4-12 extra long load registers 2-12, 4-12 Hot Swap ID 11-18 initialization 2-8, 4-8 interface 1-9 interface pins 12-1 interrupt pin register 11-14 long load 2-10-2-11, 4-10-4-11 long load registers 2-11, 4-11 memory map 2-13, 4-12 new capabilities function 2-13, 4-12 Next_Cap pointer 11-18 operation 2-8, 4-9 PCI Bus, access to internal registers 2-14, 4-14 pins 12-6 read and write, random 10-2 read control 1-10 read-only portion 10-1 recommended 2-13, 4-12
Index-22
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
SERR#
to USERo register access, internal 2-13, 4-13 register level programming interface 11-10 revision ID 11-9 software reset 3-1, 5-1 subclass code 11-10 subsystem ID 11-14 support 1-10 timing diagrams 2-15-2-20, 4-15-4-22 vendor ID 11-8 vendor ID registers 2-7, 4-8 VPD address 11-19 VPD stored in 10-1 VPD, simple read or write to 10-2 Write-Protected Address Boundary register (PROT_AREA) 2-11, 4-11, 10-2, 11-23 writes to 10-2 SERR# 2-4, 3-13, 3-27, 4-5, 6-4, 11-8, 11-9, 11-23, 11-34, 11-36, 12-4, 14-3 signal names 12-3-12-19 C Bus mode 12-12-12-15 J Bus mode 12-16-12-19 M Bus mode 12-8-12-11 signal specs 14-1-14-3 signaling 1-9 signals synchronous inputs 13-4, 13-5 synchronous outputs 13-6, 13-7 single address, block DMA initialization 5-17 66 MHz, PCI Clock Power Management D2 support 8-2 Slave See Direct Slave Slow Terminate mode 3-28, 5-24 software connection control 9-3 reset 3-1, 5-1 sources, interrupt and error 6-1 specifications See Preface, electrical specifications, or general electrical specifications states, recovery (J mode only) 4-5 STOP# 3-9, 3-18, 5-8, 5-16, 12-5, 14-3 supplemental documentation See Preface synchronous inputs 13-4, 13-5 outputs 13-6, 13-7 system pins 12-6 system reconfiguration See configuration
T
TA# 2-2, 3-2, 3-4, 3-5, 3-6, 3-8, 3-9, 3-10, 3-13, 3-17, 3-27, 12-10, 14-3 Bus mode 13-4, 13-6 input 2-4 output 13-6 serial EEPROM initialization 2-8, 2-13 Target Abort 3-8, 5-7-5-8, 11-9, 11-31 interrupt 6-2 TCK 12-5, 14-3 TDI 12-5, 12-20, 12-21, 14-3 TDO 12-5, 12-20, 12-21, 14-3 TEA# 2-5, 3-8, 3-13, 3-27, 6-4, 11-1, 11-23, 11-34, 11-36, 11-47, 12-1, 12-4, 12-10, 13-6, 14-3 terms and definitions See Preface thermal resistance, package 13-1 timers See Backoff, Latency, or Pause Timer timing diagrams C and J modes 5-26-5-96 configuration initialization 2-15-2-20 dual address 3-8, 3-21, 5-7 M mode 3-30-3-55 serial EEPROM 2-15-2-20, 4-15-4-22 TMS 12-5, 12-20, 14-3 transfer size 3-15 TRDY# 2-3, 3-2, 3-9, 3-12, 3-15, 3-16, 4-3, 5-2, 5-8, 5-10, 5-14, 11-26, 12-4, 12-5, 14-3 TRST 12-5, 12-20, 14-3 TS# 2-3, 2-4, 2-14, 3-11, 3-12, 3-17, 3-27, 11-24, 12-1, 12-10, 13-4, 13-6, 14-3 TSIZ[0:1] 2-4, 3-15, 12-10, 14-3 3-5, 3-10, 12-1, 13-4, 13-6 data bus 3-15 2.5VAUX 8-2, 12-7, 14-3 Type 0, configuration cycle 2-14, 3-6, 4-13, 5-6 Type 1, configuration cycle 3-6, 5-6
U
unaligned DMA transfer support 1-8 User I/O 6-1-6-5 USERi 3-17, 5-15, 6-5, 11-36, 12-1, 12-11, 12-15, 12-19, 13-4, 13-5, 14-3 USERo 3-17, 5-15, 6-5, 11-36, 12-1, 12-11, 12-15, 12-19, 13-6, 13-7, 14-3
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.
Preliminary Information
Index-23
Index
VCORE to zero wait state burst operation
V
VCORE 12-7, 14-3 vendor ID 11-8 VIO 9-1, 9-2, 12-7, 13-1, 14-3 Vital Product Data (VPD) 10-1-10-2 address 11-3, 11-19 capabilities linked list, last item 11-19 capabilities register 10-1 data 11-3 data register 11-19 ID register 11-19 new capabilities function 2-13 Next_Cap pointer register 11-19 read and write, random 10-2 register access, internal 2-13, 4-9, 4-12, 4-13 registers 11-19 sequential read only 10-1 serial EEPROM accesses 11-23 read or write 2-9 values programmed with 2-10, 4-11 VPD partitioning 10-1 support in PCI 9056 1-7, 1-10 voltage, precharge in BIAS 9-3 VRING 12-7, 14-3 VSS 12-7, 13-1, 13-2, 14-3
W
wait state control 2-2, 4-3 cycle control 11-8 generation 2-4, 3-11, 4-5 Local Bus 2-3, 4-3 PCI Bus 2-3, 4-3 zero 1-7 WAIT# 4-3, 11-21, 12-1, 12-8, 12-15, 12-19, 13-4, 13-5, 13-6, 13-7, 14-3 width control 1-2
write accesses 2-1, 2-14, 4-1, 4-14 configuration command 2-1, 4-1 cycles 10-1 Direct Master 1-7 Direct Slave 1-7, 3-2, 5-2 Direct Slave Command codes 2-1, 4-1 Direct Slave transfer 3-11, 5-10 DMA 1-7 FIFOs 1-8, 2-4, 3-4, 3-9, 4-4, 5-4, 5-8 flush pending 3-10, 5-9 I/O command 2-1, 4-1 Local Bus accesses 2-4, 4-5 memory command 2-1, 4-1 write and invalidate 2-1, 4-1 PCI Power Management 8-1 PCI Power mode example 8-3 posted memory (PMW) 1-8 read and write, random 10-2 serial EEPROM 2-13, 4-12, 10-2 accidental 10-2 control 2-10, 4-11 operation 2-8, 4-9 VPD 10-1 data 10-1 read and write, random 10-2 serial EEPROM partitioning 10-1 simple 10-2 wake-up request example 8-3
Z
zero wait state burst operation 1-7
Index-24
Preliminary Information
PCI 9056 Data Book, Version 0.91 (c) 2001 PLX Technology, Inc. All rights reserved.

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