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MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
This system is an NTSC system PinP system that accommodates subscreen composite input and main screen Y/C input. It is a semiconductor IC circuit having a built-in 96K bit field memory and an analog circuit, which permits a low-cost and compact system configuration.
PIN CONFIGURATION (TOP VIEW)
AVss3 (vcxo) VCXO out VCXO in FILTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 AVssf (ana)
51 Cin 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 TESTEN Yin TEST9 Y-PIP TEST8 C-PIP AVdd4 (da) C-PIPin AVss4 (da) Y-PIPin ADJ-Ysub Yout-sub ADJ-Csub Cout-sub DVss3 (ram) DVdd3 (ram) SWMG/TEST7 VD/CSYNC/TEST6 HD/TEST5 SWM/TEST4 MCK fsc/TEST3 BGP(m)/TEST2 DVdd2
FEATURES
BIAS AVdd3 (vcxo) AVdd2 (m) Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) RESET DVss1 DVdd1 BGP(s)/TEST0
* * * *
* * * * *
Built-in field memory 96K bit for PIP Built-in luminance signal vertical filter No. of subscreen displays: 1 (two sizes, 1/9 and 1/16, can be selected from.) No. of subscreen samples (1/9 - 1/16 sizes) No. of quantization bits: 6 for all Y, B-Y and R-Y No. of horizontal picture elements: 171(Y), 28.5 (B-Y, R-Y) No. of vertical lines: 69/52 Subscreen frame display ON/OFF Built-in analog circuits such as sync chip clamp, VCXO, and analog switch Built-in 2 channels of 8 bit A/D converter (for main signal burst lock and PIP sub signal) Built-in two channels of 8 bit D/A converter (luminance and chroma signals) I2C bus control Controls: display ON/OFF, display size selection, setting of display position, frame ON/OFF, setting of frame level, selection of frame animation/field still image, setting of Y delay amount, color level, tint, black level, etc.
M65617SP
APPLICATION
TV
SCK CSYNC(s)/TEST1 ACK
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V Operating frequency.........................................................14.32 MHz Operating temperature....................................................-10 to 75C Input voltage (CMOS interface) "H"........................V DDx0.7 to VDD V "L".............................0 to VDDx0.3V Output current (output buffer)........................................ 4mA (MAX) Output load capacitance............................................20pF (MAX)
1
DATA CLK DVss2
Outline 52P4B
Circuit current.........................................................................140mA NOTICE: Connect a 0.1F or larger capacitor between VDD and VSS pins. 1 : Include pin capacitance (7pF)
1
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
BLOCK DIAGRAM
SCK CSYNC(s) /TEST1 BGP(s) /TEST0
Yin Sync tip Clamp Cin Vdd / Vss for test DATA CLK ACK Vin(s) Sync tip Clamp Vrt(m) Vrb(m) 2 HD (I C) ADJ-Ysub Yout-sub D/A 8bit D/A 8bit HPLL 4fsc Delay Encode 6 Y Demux RAM 96Kbits
2
Y- PIP Bias RAM(1H) C- PIP
15 3 3 I2C I/F Y A/D 8bit Y/C SEP (LPF,BPF) Sync Sep Phase Select C AFC Timing Gen (Decode) B-Y Demod Tint R-Y 6 6 Y B-Y R-Y Delay MIX fsc Level Detect Bias A/D 8bit Burst Data Sampling Phase Detect Lock/Free-run via I2C VCXO Driver 4fsc VCXO LPF &MPY Delay Luma Clamp Delay
Bias Y 6 Back Porch Clamp
C- PIPin
Y- PIPin
Vert-filter & MUX
SWMG /TEST7 Timing Gen (Memory Cont) VD /CSYNC /TEST6 HD /TEST5 FILTER BIAS VCXO in VCXO out
6 B-Y 6 R-Y
Cout-sub
ADJ-Csub Vin(m)
Vrt(m) Vrb(m)
2
RESET
MCK
BGP(m) /TEST2
fsc /TEST3
SWM /TEST4
2
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION OF PIN
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Name AVss3 (VCXO) VCXO out VCXO in FILTER BIAS AVdd3 (VCXO) AVdd2 (m) Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) RESET DVss1 DVdd1
BGP(s)/TEST0
I/O GND O I O O Vdd Vdd I O O GND Vdd I O O GND I GND Vdd (I/)O I I(/O) O I I GND Vdd (I/)O I(/O) I (I/)O I(/O) I(/O) I(/O) Vdd GND O O O O I GND I Vdd O I O I I I I Vss
Function Grounding (analog burst lock PLL section) Oscillation output signal Oscillation input signal Filter Bias Power supply (analog burst lock PLL section) Power supply (analog main signal A/D section) Main color input signal Main signal A/D reference voltage output + Main signal A/D reference voltage output Grounding (analog main signal A/D section) Power supply (analog sub-signal A/D section) Sub-composite video input signal Sub-signal A/D reference voltage output + Sub-signal A/D reference voltage output Grounding (analog sub-signal A/D section) Power-ON reset input signal. Grounding (digital section) Power supply (digital section) Sub-screen burst gate pulse output Sub-screen 4fsc clock input Sub-screen CSYNC input I2C bus data/acknowledge output signal I2C bus data input signal I2C bus clock input signal Grounding (digital section) Power supply (digital section) For testing For testing For testing For testing Horizontal sync input signal Vertical sync input signal Sub-screen display authorization input signal Power supply (digital RAM section) Grounding (digital RAM section) Sub-screen color signal D/A output signal For adjustment of sub-screen color signal D/A Sub-screen luminance signal D/A output signal For adjustment of sub-screen luminance signal D/A Sub-screen luminance signal re-input signal Grounding (analog D/A and SW sections) Sub-screen color signal re-input signal Power supply (analog D/A & SW sections) PIP color signal output signal For testing PIP luminance signal output signal For testing Main luminance input signal For testing Main color input signal Grounding (analog section)
Remarks
Connected to the power supply with 100k, and grounded with 10F
SCK
CSYNC(s)/TEST1
Open Grounding Pulldown 15k
ACK DATA CLK DVss2 DVdd2
BGP(m)/TEST2
fsc/TEST3 MCK SWM/TEST4 HD/TEST5 VD/CSYNC/ TEST6
SWMG/TEST7
Open Pulldown 15k Grounding Open
Pullup 15k
DVdd3 (ram) DVss3 (ram) Cout-sub ADJ-Csub Yout-sub ADJ-Ysub Y-PIPin AVss4 (da) C-PIPin AVdd4 (da) C-PIP TEST8 Y-PIP TEST9 Yin TESTEN Cin AVssf (ana)
Pullup 15k Grounding Grounding
3
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Symbol VDD3 VI VO IO Pd Topr Tstg Parameter Supply voltage (3.3V) Input voltage Output voltage Output current (1) Power dissipation Operating temperature Storage temperature Limits Min. Max. -0.3 -0.3 -0.3 - - - -10 -50 4.6
VDD3+0.3 VDD3+0.3
Unit V V V mA mW C C
IOL=20 IOH=-26 1400 75 125
1: Output current per output terminal. But Pd limits all current.
DC ELECTRICAL CHARACTERISTICS (VSS=0V)
Symbol VIL VIH VTV T+ VH VOL VOH IOL IOH IIH IIL IOZL IOZH CI CO CIO IDD Parameter Input voltage (CMOS interface) Input voltage schmitt trigger (CMOS interface) Output voltage Output current Input current Output leakage current Input pin capacitance Output pin capacitance Bidirectional pin capacitance Operating current L level H level - +
Hysteresis
Test conditions VDD=2.7V VDD=3.6V VDD=3.3V
L level H level L level H level L level H level L level H level
VDD=3.3V, | IO | <1A VDD=3.0V, VOL=0.4V VDD=3.0V, VOH=2.6V VDD=3.6V, VI=0V VDD=3.6V, VI=3.6V VDD=3.6V, VO=0V VDD=3.6V, VO=3.6V f=1MHz, VDD=0V
3.3V supply
Min. 0 2.52 0.5 1.4 0.3 - 3.25 4 - -1 -1 -1 -1 - - - -
Limits Typ. - - - - - - - - - - - - - 7 7 7 -
Max. 0.81 3.6 1.65 2.4 1.2 0.05 - - -4 1 1 1 1 15 15 15 140
Unit V V V V V V V mA mA A A A A pF pF pF mA
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
2000
POWER DISSIPATION Pd (mW)
1600 1490 1200
800
400
0 0 25 50 75 100 125
AMBIENT TEMPERATURE Ta (C)
4
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (device address=24h, sub-address=00h to 0Fh) Registers requiring user selection/adjustment setting are enclosed in rectangles.
Indication method of reference setting column: Thick letters: Fixed setting value Standard letters: An example as setting for evaluation /: 1/9 - 1/16 sizes Subaddress Bit No. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 03h 4 5 6 7 0 1 2 3 4 5 6 7 Reference setting 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 NB 0 0 0 1 0 0 Register name color (0) color (1) color (2) color (3) color (4) color (5) color (6) killer tint (0) tint (1) tint (2) tint (3) tint (4) tint (5) afcoff decode evenupra bgcs extport (0) extport (1) adclocksel (0) adclocksel (1) Function
Color saturation adjustment; min. value [0], max. value[63], 1/step [3Fh setting]
00h
[1 setting] Color killer; ON [0], OFF [1], [0 setting]
01h
Tint adjustment; setting by complements of 2 0fl to -50fl [00h to 1Fh] +50fl to 0fl [20h to 3Fh] [Normally 00h setting]
[0 setting] Initialization of sub-screen color demodulation; normally [0], initialized [1] Each time reset is cleared and sub-screen input source changed, operate in a sequence of 0 - 1 - 0. Setting of interlace leading line; leading field first/second [1/0], [0 setting] Forced writing of background level [1 significant, normally 0] [0 setting] I2C bus expansion port data (optional function); [Set to either of them] Selection of adc clock delay; [00b setting] Selection of IC operation mode; [01b setting] 16 bits [0] Setting of sub-screen tint offset; [11b setting] Horizontal size Emphasis of high luminance signal area ON/OFF [0/1] [0 setting] Selection of PIP-Y output clamping pulse; [0 setting when PIP is displayed] Vertical size Addition of sync, burst; OFF/ON [0/1] [Normally 0 setting when PIP is displayed] Sync operation; Main input is followed [0], self-propelled [1] [0 setting when PIP is displayed] Setting of sub-screen Y delay amount (D/A output phase against color signal); [4 setting] Min. 280ns [0h], center 0ns [4h], max. +770ns [Fh] acc reference level setting authorization; [1 significant] [0 setting] Display of field still screen/display of animation [0/1] Display of sub-screen frame; NO/YES [0/1] [0] setting (memory access not operated by [1])
02h
1 mode (0) 0 mode (1) 1 crtint (0) 1 crtint (1) 1/0 size-h 0 hpfoff NB bgpmsel 1 in case of 03h<7>(rvs)=1 or 03h<6>(rvhs)=1, 0 in other cases 0/1 size 0 rvhs 0 0 0 1 0 0 1 1 NB rvs ydl (0) ydl (1) ydl (2) ydl (3) test acc lvl wen grc stnby=testreset
04h
5
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress Bit No. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Reference setting 1/0 1/0 1/0 0/0 0/0 1/0 1/0 0/0 0 0 0 0 0 0 1 NB 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0/0 0/0 0/0 0/1 0/0 1/1 0/0 0/0 Register name hp (0) hp (1) hx (0) hx (1) hx (2) hx (3) hx (4) hx (5) contrast (0) contrast (1) contrast (2) contrast (3) contrast (4) contrast (5) contrast (6) free-run bgy (2) bgy (3) bgy (4) bgy (5) ext-sync-sel (0) ext-sync-sel (1) lpf-sel (0) lpf-sel (1) bgby (0) bgby (1) bgby (2) bgry (0) bgry (1) bgry (2) mvc (0) mvc (1) bstby (0) bstby (1) bstby (2) bstby (3) bstby (4) bstby (5) bstby (6) bstby (7) vxa (0) vxa (1) vxa (2) vxa (3) vxa (4) vxa (5) vxa (6) vxa (7) Sample start position Fine adjustment; 70ns/step Function
05h
Sample start position Rough adjustment; Formula: {4-hp<1:0>+(3Fh-hx<5:0>)x4}x70ns-2.5us
06h
Luminance signal sub-DAC control; 1V output at 40h, max. 1.8V output 1V output from sync chip to white peak at 40h Luminance signal level during image period is 100/130 (IRE ratio) x 1V [40h setting with evaluation board]
vcxo oscillation control; lock loop/self-propelled oscillation [0/1] Setting of frame and background luminance level; [8h setting in the case of black frame]
07h
Selection of sub-screen sync input; [Normally 0 setting] Digital [0 or 1], external pin input [2], internal analog [3] Selection of sub-screen luminance signal band [2 setting] 2.3 [00b], 2.1 [01b], 1.6 [10b], 1.3 [11b]MHz Setting of background b-y level; 8 gradations 0(min.)4(center)7(max.) (4 setting if colorless) Setting of background r-y level; 8 gradations 0(min.)4(center)7(max.) (4 setting if colorless) Setting of noise mask gate range for sub-signal sync; 48us [0], 44us [1], 53us [2], OFF [3] [0 setting]
08h
09h
Setting of color signal output burst b-y level; 256 gradations 00h(min.)80h(center)FFh(max.)
0Ah
Setting of display start position (vertical); {vxa<7.0>+17 or 16 (1st field)}line [20h/28h(1/9 - 1/16 sizes) when displayed at the upper left]
6
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress Bit No. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 0Fh 3 4 5 6 7 Reference setting 0/1 0/1 1/0 0/0 0/1 0/1 1/0 0/0 0/0 0/0 0/0 1/0 0/1 0/0 0/0 0/0 0/1 0/0 0/0 1/1 1/0 1/1 1 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 1 0 Register name vya (0) vya (1) vya (2) vya (3) vya (4) vya (5) vya (6) vya (7) hxa (0) hxa (1) hxa (2) hxa (3) hxa (4) hxa (5) hxa (6) hxa (7) hya (0) hya (1) hya (2) hya (3) hya (4) hya (5) ext-bhsel (0) ext-bhsel (1) adj (0) adj (1) adj (2) adj (3) hadj (0) hadj (1) hadj (2) hadj (3) disp bgc dofc y-offset (0) y-offset (1) y-offset (2) y-offset (3) y-offset (4) Setting of luminance signal output DC offset; Set pedestal level within a range of 32 digits/256 digits (complements of 2, "-16fl to +15fl" or "0", provides image data bottom values. It serves fine adjustment of brightness.) Function
0Bh
Setting of display period (vertical); {vya<7:0>} line [44h/33h (1/9-1/16 sizes)]
0Ch
Setting of display start position (horizontal); {hxa0<7:0>x4x70ns+12.8}us [08h-10h (1/9-1/6 sizes) when displayed at the upper left]
0Dh
Setting of display period (horizontal); {(hya0<5:0>-1)x4x70}us [38h/29h (1/9 - 1/16 sizes)]
Selection of sync input for burst clock; HD pin [0 or 1], VD pin [2], internal analog [3] [3 setting] Adjustment of sub-screen display-starting horizontal position; [4h setting] 70ns/step Min. 280ns [0h], center 0ns [4h], +770ns [Fh] Adjustment of supplementary BGP position; [Normally Fh setting] Parameter to adjust PIP Y output signal clamping position to main Y input signal pedestal (when 03h<4>(bgpmsel) = 1) 5.6us[0h], 6.6us [Fh] (pulse width: 2.6us) from the front end of horizontal sync Display control; PIP display OFF/ON [0/1] (ineffective at background) Background display control; OFF/ON [0/1] Authorization of addition of sync when missing main source is detected; OFF/ ON [0/1]
0Eh
7
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION
(device address=24h, subaddress=10h to 1Bh) (Device adress=25h [output], subaddress=1Ch to 1Fh
Indication method of reading column: 0 or 1.... Register with readings .... Register unused Subaddress Bit No. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Reference Register name setting 0 bg-start (0) 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 NB 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 bg-start (1) bg-start (2) bg-start (3) bg-start (4) bg-start (5) swap set-pd-out no-bst-level (0) no-bst-level (1) bw-level (0) bw-level (1) ext-mh-sel (0) ext-mh-sel (1) ext-mv-sel pin28osel color-set (0) color-set (1) color-set (2) color-set (3) color-set (4) color-set (5) color-set (6) test-pip-c-dac-ctrl bgpx (0) bgpx (1) bgpx (2) bgpx (3) bgpx (4) bgpx (5) test-sel180d ti-sel180d color2 (0) color2 (1) color2 (2) color2 (3) color2 (4) color2 (5) dft-wtg teg-vbrin Function
10h
Setting of burst gate pulse phase for internal burst lock; Min.value [0], max.value [63],70ns/step [0Eh setting] (4.8us, pulse width 3us from the front end of horizontal sync)
chg, dis output transfer control; default/reversal [0/1], [1 setting] For testing [0 setting] For testing [0 setting] For testing [0 setting] Selection of main horizontal sync signal input; [normally 0 setting] HD pin[0 or 1], VD-CSYNC pin[2], internal analog [3] election of main vertical sync signal input; VD-CSYNC pin/internal analog [0/1] [Normally 0 setting] Selection of 28 pin output; BGPM [0], RDOF [1] [Normally 1 setting]
11h
12h
Adjustment of color saturation (main burst tracking in); Min. value x 0[0], max. value x 2 [127], [1]/step Output analog voltage value depends upon input burst signal level [Normally 40h setting]
Main burst level tracking function control; ON [0], OFF [1] [0 setting at PIP] When there is no main input burst signal at background display, set 1 to clear the main burst tracking function.
Adjustment of burst gate pulse output phase for sub-screen; [Normal setting value 1Dh]
13h
For testing [Normally 0 setting] For testing [Normally 0 setting]
Adjustment of color saturation; min.value [0], max.value [63], 1/step [Normally 3Fh setting]
14h
15h<5:0>, 16h<7:0> register default gate [Normally 1 setting] For testing [0 setting]
8
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress Bit No. 0 1 2 15h 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Reference Register name setting 1/1 vxs (0) 0/1 vxs (1) 0/0 vxs (2) 1/1 0/0 1/1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 0 vxs (3) vxs (4) vxs (5) whms test-whv clr-mod (0) clr-mod (1) clr-mod (2) clr-mod (3) clr-mod (4) clr-mod (5) clr-mod (6) clr-mod (7) acc-level (0) acc-level (1) acc-level (2) acc-level (3) acc-level (4) acc-level (5) test-clamp autosel doutsel (0) doutsel (1) clocksis (0) clocksis (1) cdaoutsel testyt os test-disp dstry (0) dstry (1) dstry (2) dstry (3) dstry (4) dstry (5) dstry (6) dstry (7) sync (0) sync (1) bpfsel (0) bpfsel (1) ht (0) ht (1) ht (2) ht (3) Function
Setting of sub-screen sample start position (vertical): No setting is necessary when 14h<6> is set to "0". Adjustment setting value is effective when 14h<6> is set to "1". [29h/2Bh (1/9 - 1/16 sizes)]
For testing [0 setting] For testing [0 setting]
16h
For testing [00h setting]
acc reference level: no setting is necessary when 04h<4>=0 [15h setting]
17h
For testing; [0 setting] For testing; [0 setting] For testing; [00b setting] Test clock selection; [00b setting] For testing; [0 setting] For testing; [0 setting] For testing; [0 setting] For testing; [0 setting]
18h
19h
Setting of color signal output burst r-y level; 256 gradations 00h (min.)80h (center)FFh (max.)
Selection of main internal sync separation threshold level; [11b setting] Selection of BPF function before encoding; [00b setting] Display information output timing cycle-adjusting parameter; Adjustment of horizontal display effective data-starting cycle inside ICs [7h setting]
1Ah
9
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress Bit No. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Reference setting 1 1 1 1 1 0 0 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Register name dft-bl dft-misc dft-sg dft-syncbst dft-clevel pin29osel pin29oe dft-clr imag (0) imag (1) imag (2) imag (3) iphase (0) iphase (1) iphase (2) iphase (3) iphase (4) iphase (5) iphase (6) iphase (7) iphase (8) for test for test rdof clamp-offset (0) clamp-offset (1) clamp-offset (2) clamp-offset (3) clamp-offset (4) clamp-offset (5) for test wdof c-dac-ctrl (0) c-dac-ctrl (1) c-dac-ctrl (2) c-dac-ctrl (3) c-dac-ctrl (4) c-dac-ctrl (5) c-dac-ctrl (6) bw Function Register 10h<7:0>, 11h<3.0>default gate; [1 setting] Register 11h<7:4>default gate; [1 setting] Register 13h<7:0>, 14h<6>, 17h<7:6>default gate; [1 setting] Register 19h<7:0>default gate; [1 setting] Register 12h<7:0>default gate; [1 setting] Signal selection at 29 pin output mode; fsc/4fsc [0/1] [0 setting] Operated when adjusting oscillation frequency 29 pin output mode authorization input/output [0/1] [Normally 0 setting] Operated when adjusting oscillation frequency Register 16h<7:0>default gate; [1 setting]
1Bh
For testing
1Ch read
For testing
1Dh read
For testing Simplified verification of main input loss; input unavailable/available [1/0]
1Eh read
Clamping level information; for verification of internal operation information Values are shown that are in proportion and corresponding to the depth of subinput information sync.
For testing Simplified verification of sub-input loss; input unavailable/available [1/0]
1Fh read
Level tracking information; for verification of internal operation information Values are shown that are in proportion and corresponding to main input burst amplitude
Unlock information; for verification of internal operation information
10
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
APPLICATION EXAMPLE
Horizontal sync input signal (main-picture) Vertical sync input signal (main-picture)
Chroma input signal (main-picture)
Luma signal input (main-picture)
Ana. 68p Ana. Ana. 150p 360 Dig 470
104
104
10
Ana. 103 15k
104 104 103 103
Sub-picture displaying on/off
PIP Chroma signal output
PIP Luma signal output
Dig 15k 103 10
10 103
52
50
45
40
35
30
27
M65617SP
1
5
820k
10
15
20
26
12p X1 10p Dig5V Dig Digital +5V power supply Digital +3.3V power supply Digital GND Ana. Analog +3.3V power supply Analog GND Ana.5VAnalog +5V power supply Composite video input signal (sub-picture) 2.2 300 154 1.5 103
100k CX 103
2k
104 103 103
103 103
224
10 103 Ana. Ana.
10 103 104
100k Dig5V Dig5V
47k
12k
47k
103 Ana.
10 Dig SYNC SEP CIRCUIT (OPTIONAL) Y 10k 100 SDA SCL
330 560 100
12k
10
100
10k
I2C BUS Clock input signal I2C BUS DATA input/output signal
C
Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust. And then mix both signals for sub-picture input video signal. (The above external circuit processing aims at controlling white compression of sub-screen input luminance signal and strengthening the color playback function of sub-screen input signal in the case of weak electric field.)
Units Resistance : Capacitance : F
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MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
PIP TV SYSTEM BLOCK DIAGRAM
(BASIC) Composite Video Signal Y C C C BLPLL B-LD Y C CV Y PIP Signal Processing C
Y/C Separation
Y
M65617SP
Y
Video Signal Processing
Deflection Unit Yoke
Y/C Separated Video Signal
HD
VD
(Driving Method and Operating Specification for Serial Interface Data)
(1) Completion and start of serial transfer If DATA (serial signal data) is changed from 'L' to 'H' when CLK (serial clock signal) is 'H', serial transfer is completed to generate a bus-free status. If DATA is changed from 'H' to 'L' when CLK is 'H', serial transfer is started to stand by for subsequent input of CLK and DATA. (2) Serial data transfer Data, which is transferred in the unit of 1 byte, is sent sequentially from the MSB-side bit through DATA. Clock waveform necessary for the transfer of 1 byte represents 9 times, of which address/data are transferred with the initial 8 times, and acknowledge detection performed with the remaining one time. (When reading, 'H' is output to ACK at the agreement of address in the case of address transfer, and at the completion of the 8 bit portion in the case of setting data transfer. When writing, 'H' is output to ACK at the agreement of address in the case of address transfer, and 'L' is output to ACK to detect acknowledge input from master after 8 bit data is output.) DATA needs to be changed when CLK is 'L' if address/data is to be transferred. (Allowing DATA to be changed when CLK is 'H' or simultaneously with the change of CLK, will cause maloperation since no identification is possible of the completion and start of serial transfer. There are no restrictions on the number of bytes of data transferred after the start of serial transfer. (3) Data transfer byte format (data transfer sequence) 1. Data transfer byte format in setting data to M65617SP will be described: Generate a serial transfer start status before sending slave address 24h (00100100b), and then send internal register address (1 byte) followed by setting data (in the unit of 1 byte). For setting data, a single transfer allows more than 1 byte to be transferred. In this case, setting data is read into the register that has been address-incremented one by one from the internal register address sent first. (However, address 00h will be returned to, following address 7Fh.) 2. Data transfer byte format in writing data from M65617SP will be described: Prior to writing data, it is necessary to set the internal address of M65617SP by reading and transferring data. Read and transfer data before performing the completion start of serial transfer. Send slave address 25h (00100101b) in succession, and the reversed information of writing data is output to ACK thereafter. More than 1 byte of writing data can also be transferred. In this case as well, setting data is read into the register that has been address-incremented one by one from the internal register address sent first. (However, address 00h will be returned to, following address 7FNn.)
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MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(The examples of serial byte transmission format)
(1) Reading setting data AAh into internal address 00h of M65617SP:
Transmission Activation
Confirmation of bus free? (DATA='H')
yes S 24h A 00h A AAh ADE
no S : Operation of serial transmission start is applied on CLK for the release of output state A : Acknowledge detection D : Dummy clock feed for the release of acknowledge output state E : Operation of serial transmission completion
(2) Reading setting data FFh, 80h and EEh, individually, into internal address 04h to 06h of M65617SP:
Transmission Activation
Confirmation of bus free? (DATA='H')
yes S 24h A 04h A FFh A 80h A EEh ADE
no is applied on CLK for the release of output state
(3) Writing data on internal address 00h of M65617SP [Standard reading sequence version: 46 pin " L " ]:
Transmission Activation
Confirmation of bus free? (DATA='H')
yes S 24h A 00h ADE S 25h A $$h A'
no A' : Bus free operation by the is applied on CLK for the release of output state master (micro processor)
13
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(4) Writing data on internal address 04h to 06h of M65617SP [Standard reading sequence version: 46 pin " H "]:
Transmission Activation
Confirmation of bus free? (DATA='H')
yes S 24h A 04h ADE S 25h A SSh A'' SSh A'' SSh A'
no A'' : Output `L' operation by the is applied on CLK for the release of output state master (micro processor)
(5) Writing data on internal address 00h of M65617SP [Expanded reading sequence version: 46 pin " H"]:
Transmission Activation
Confirmation of bus free? (DATA='H')
yes S 25h A 00h A $$h A'
no A' : Bus free operation by the is applied on CLK for the release of output state master (micro processor)
(6) Writing data on the internal address 04h to 06h of M65617SP [Expanded reading sequence version: 46 pin " H"]:
Transmission Activation
Confirmation of bus free? (DATA='H')
yes S 25h A 04h A SSh A'' SSh A'' SSh A'
no A'' : Output `L' operation by the is applied on CLK for the release of output state master (micro processor)
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MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
TIMING DIAGRAM
1 2 3 4 5 6 7 8 9 1
CLK
DATA
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
ACK Detec.
Bit7 (MSB)
ACK _ Acknowledge
ACK _ Readout data
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
Bit7 (MSB)
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