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Final Electrical Specifications
LTC1596-1 Serial 16-Bit Multiplying DAC with Clear to Mid-Scale Input
July 1998
FEATURES
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DESCRIPTION
The LTC(R)1596-1 is a serial input, 16-bit multiplying current output DAC. The device is pin and hardware compatible with the 12-bit LTC8143/LTC7543 and comes in 16-pin PDIP and SO wide packages. It offers clear to mid scale for both the clear input and power-on reset. A related device, the LTC1596, is identical except it clears to zero scale. The LTC1596-1 is specified over the industrial temperature range. Sensitivity of INL to op amp VOS is reduced by five times compared to the industry standard 12-bit DACs, so most systems can be easily upgraded to true 16-bit resolution and linearity without requiring more precise op amps. This DAC includes an internal deglitching circuit that reduces the glitch impulse by more than ten times to 1nV-s typ.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Asynchronous Clear Input Clears DAC to Mid Scale DNL and INL: 1LSB Max Low Glitch Impulse: 1nV-s Typ Pin Compatible with Industry Standard 12-Bit DACs: LTC8143/LTC7543 4-Quadrant Multiplication Low Power Consumption Power-On Reset Clears DAC to Mid Scale Daisy-Chain Serial Output
APPLICATIONS
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Process Control and Industrial Automation Software Controlled Gain Adjustment Digitally Controlled Filter and Power Supplies Automatic Test Equipment
TYPICAL APPLICATION Outputs Daisy-Chained Control
Multiplying DAC Has Easy 3-Wire Serial Interface
VREF -10V TO 10V
5V
INTEGRAL NONLINEARITY (LSB)
0.1F 13 10 4 7 5 6 9 8 11 14 15 16 33pF OUT1 STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596-1 SRO LD2 STB2 STB4 DGND AGND 12 TO NEXT DAC FOR DAISY-CHAINING 3
1596-1 F01
OUT2
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1001
VOUT 0V TO -VREF
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Integral Nonlinearity
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 - 1.0 0 49152 16384 32768 DIGITAL INPUT CODE 65535
1596-1 TA02
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LTC1596-1 ABSOLUTE MAXIMUM RATINGS
VDD to AGND .............................................. - 0.5V to 7V VDD to DGND .............................................. - 0.5V to 7V AGND to DGND ............................................ VDD + 0.5V DGND to AGND ............................................. VDD + 0.5V VREF to AGND, DGND............................................. 25V RFB to AGND, DGND .............................................. 25V Digital Inputs to DGND .................. - 0.5V to VDD + 0.5V VOUT1, VOUT2 to AGND ................... - 0.5V to VDD + 0.5V Maximum Junction Temperature .......................... 150C Operating Temperature Range LTC1596-1C ........................................... 0C to 70C LTC1596-1I ....................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW OUT1 OUT2 AGND STB1 LD1 SRO SRI STB2 1 2 3 4 5 6 7 8 16 RFB 15 VREF 14 VDD 13 CLR 12 DGND 11 STB4 10 STB3 9 LD2
ORDER PART NUMBER LTC1596-1ACN LTC1596-1ACSW LTC1596-1BCN LTC1596-1BCSW LTC1596-1CCN LTC1596-1CCSW LTC1596-1AIN LTC1596-1AISW LTC1596-1BIN LTC1596-1BISW LTC1596-1CIN LTC1596-1CISW
N PACKAGE 16-LEAD PDIP
SW PACKAGE 16-LEAD PLASTIC SO WIDE
TJMAX = 150C, JA = 100C/W (N) TJMAX = 150C, JA = 130C/W (SW)
Consult factory for Military grade parts.
VDD = 5V 10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. LTC1596-1A
SYMBOL PARAMETER Accuracy Resolution Monotonicity INL DNL GE Integral Nonlinearity Differential Nonlinearity Gain Error (Note 1) TA = 25C TMIN to TMAX TA = 25C TMIN to TMAX (Note 2) TA = 25C TMIN to TMAX
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
LTC1596-1B
TYP MAX
LTC1596-1C
MIN 16 15 TYP MAX UNITS Bits Bits 4 4 2 2 32 32 LSB LSB LSB LSB LSB LSB
MIN 16 16
TYP MAX MIN 16 16 0.25 1 0.35 1 0.2 0.2 2 3 1 1 16 16
2 2 1 1 16 32
VDD = 5V 10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL ILEAKAGE PARAMETER Gain Temperature Coefficient OUT1 Leakage Current Zero-Scale Error PSRR RREF Power Supply Rejection VREF Input Resistance CONDITIONS (Note 3) Gain/Temperature (Note 4) TA = 25C TMIN to TMAX TA = 25C TMIN to TMAX VDD = 5V 10% (Note 5)
q q q q
MIN
TYP 1
MAX 2 3 15 0.2 1
UNITS ppm/C nA nA LSB LSB LSB/V k
1 5 7
2 10
Reference Input
q
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LTC1596-1
ELECTRICAL CHARACTERISTICS
VDD = 5V 10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER Output Current Settling Time Midscale Glitch Impulse Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error THD Total Harmonic Distortion Output Noise Voltage Density Analog Outputs COUT1 OUT1 Output Capacitance (Note 3) DAC Register Loaded to All 1s DAC Register Loaded to All 0s
q q
CONDITIONS (Notes 6, 7) CFEEDBACK = 33pF (Notes 6, 8) VREF = 10V, 10kHz Sine Wave (Note 9) (Note 10) f = 1kHz
MIN
TYP 1 1 1 1 108 11 115 70
MAX
UNITS s nV-s nV-s mVP-P dB nV/Hz
AC Performance
130 80
pF pF V
Digital Inputs VIH VIL IIN CIN VOH VOL tDS1 tDS2 tDS3 tDS4 tDH1 tDH2 tDH3 tDH4 tSRI tSTB1 to tSTB4 tSTB1 to tSTB4 tLD1, tLD2 tASB tCLR tPD1 tPD Serial Input Data Pulse Width Strobe Pulse Width Strobe Pulse Width LD1, LD2 Pulse Width LSB Strobed into Input Register to Load DAC Register Time Clear Pulse Width STB1 to SRO Propagation Delay STB2, STB3, STB4 to SRO Propagation Delay CL = 50pF CL = 50pF (Note 11) (Note 12) Serial Input to Strobe Hold Time Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance Digital Output High Voltage Digital Output Low Voltage Serial Input to Strobe Setup Time (Note 3) VIN = 0V IOH = 200A IOL = - 1.6mA STB1 Used as the Strobe STB2 Used as the Strobe STB3 Used as the Strobe STB4 Used as the Strobe STB1 Used as the Strobe STB2 Used as the Strobe STB3 Used as the Strobe STB4 Used as the Strobe
q q q q q q
2.4 0.8 0.001 4 0.4 30 20 25 20 30 40 35 40 60 60 60 60 0 100 30 30 150 200 5 -5 0 -5 5 15 10 15 1 8
V A pF V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing Characteristics
q q q q q q q q q q q q q q q q
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LTC1596-1
ELECTRICAL CHARACTERISTICS
SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current Digital Inputs = 0V or VDD Power Supply
q q
VDD = 5V 10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
CONDITIONS MIN 4.5 TYP 5 1.5 MAX 5.5 10 UNITS V A
The q denotes specifications which apply over the full operating temperature range. Note 1: 1LSB = 0.0015% of full scale = 15.3ppm of full scale. Note 2: Using internal feedback resistor. Note 3: Guaranteed by design, not subject to test. Note 4: IOUT1 with DAC register loaded with all 0s. Note 5: Typical temperature coefficient is 100ppm/C. Note 6: OUT1 load = 100 in parallel with 13pF. Note 7: To 0.0015% for a full-scale change, measured from the falling edge of LD1or LD2.
Note 8: VREF = 0V. DAC register contents changed from all 0s to all 1s or all 1s to all 0s. Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s; op amp = LT1007. Note 10: Calculation from en = 4kTRB where: k = Boltzmann constant (J/K); R = resistance (); T = temperature (K); B = bandwidth (Hz). Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time for STB3. Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time for STB3.
PIN FUNCTIONS
OUT1 (Pin 1): True Current Output Pin. Tie to inverting input of current to voltage converter op amp. OUT2 (Pin 2): Complement Current Output Pin. Tie to analog ground. AGND (Pin 3): Analog Ground Pin. STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial Interface Clock Inputs. STB1, STB2 and STB4 are rising edge triggered inputs. STB3 is a falling edge triggered input (see Truth Tables). LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs. When LD1 and LD2 are pulled low, data is loaded from the shift register into the DAC register, updating the DAC output (see Truth Tables). SRO (Pin 6): The Output of the Shift Register. Becomes valid on the active edge of the serial clock. SRI (Pin 7): The Serial Data Input. Data on the SRI pin is latched into the shift register on the active edge of the serial clock. Data is loaded MSB first. DGND (Pin 12): Digital Ground Pin. CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to mid scale when pulled low. This pin should be tied to VDD for normal operation. VDD (Pin 14): The Positive Supply Input. 4.5V VDD 5.5V. Requires a bypass capacitor to ground. VREF (Pin 15): Reference Input. RFB (Pin 16): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp.
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LTC1596-1
TRUTH TABLES
Table 1. LTC1596-1 Input Register
CONTROL INPUTS STB1 STB2 STB3 STB4 0 0 0 0 1 X X X 0 0 X 1 X X 1 1 1 X X 0 X X X X 1 0 0 0 Input Register and SRO Operation Serial Data Bit on SRI Loaded into Input Register, MSB First Data Bit or SRI Appears on SRO Pin After 16 Clocked Bits No Input Register Operation No SRO Operation
Table 2. LTC1596-1 DAC Register
CONTROL INPUTS CLR 0 1 1 1 LD1 X 1 X 0 LD2 X X 1 0 DAC Register Operation Reset DAC Register and Input Register to 1000....000 (Mid Scale) (Asynchronous Operation) No DAC Register Operation Load DAC Register with the Contents of Input Register
BLOCK DIAGRA
VREF 15 56k
VDD 14 DECODER CLR 13 LD1 5 LD2 9
STB1 4 STB2 8 STB3 10 STB4 11 DGND 12
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56k 56k 16 RFB 56k 56k 56k 56k 56k 56k 112k 112k 112k 112k 7k 1 OUT1 2 OUT2 3 AGND CLR LOAD D15 (MSB) D14 D13 D12 D11 *** DAC REGISTER D0 (LSB) CLR CLK OUT INPUT 16-BIT SHIFT REGISTER IN 7 SRI
1596-1 BD
6 SRO
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LTC1596-1 TI I G DIAGRA W
tDS1 tDS2 tDS3 tDS4 STROBE INPUT STB1, STB2, STB4 (INVERT FOR STB3) tDH1 tDH2 tDH3 tDH4 tSTB1 tSTB2 tSTB3 tSTB4 tSTB1 tSTB2 tSTB3 tSTB4 tSRI SRI PREVIOUS WORD D15 MSB D14 D1 D0 LSB tASB tLD1 tLD2 tPD tPD1 D15 (MSB) PREVIOUS WORD D15 (MSB) CURRENT WORD D14 D13 D0 LSB
1596-1 TD
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UW
LD1, LD2
SRO
LTC1596-1
APPLICATIONS INFORMATION
Description The LTC1596-1 is a 16-bit multiplying DAC which has serial inputs and current outputs. It uses precision R/2R technology to provide exceptional linearity and stability. The device operates from a single 5V supply and provides 10V reference input and voltage output ranges when used with an external op amp. This device has a proprietary deglitcher that reduces glitch energy to 1nV-s over a 0V to 10V output range. Serial I/O The LTC1596-1 has an SPI/MICROWIRETM compatible serial port that accepts 16-bit serial words. Data is accepted MSB first and loaded with a load pin. Data is shifted into the SRI data input on the rising edge of the strobe pin. Four strobe pins are available STB1, STB2, STB3 and STB4. STB1, STB2 and STB4 capture data on their rising
MICROWIRE is a trademark of National Semiconductor Corporation.
VREF -10V TO 10V
5V
0.1F 13 10 4 7 5 6 9 8 11 14 15 16 33pF OUT1 STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596-1 SRO LD2 STB2 STB4 DGND AGND 12 TO NEXT DAC FOR DAISY-CHAINING 3
1596-1 F01
OUT2
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Unipolar Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT VOUT -VREF (65,535/65,536) -VREF (32,768/65,536) = -VREF/ 2 -VREF (1/65,536) 0V
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to - VREF
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edges. STB3 captures data on its falling edge (see Truth Table 1). The LTC1596-1 has two load pins, LD1 and LD2. To load data, both pins must be taken low. Normally one of the pins is grounded. An asynchronous clear input (CLR) resets the LTC1596-1 to mid scale when pulled low (see Truth Table 2). The LTC1596-1 also has a data output pin SRO that can be connected to the SRI input of another DAC to daisychain multiple DACs on one 3-wire interface (see the Timing Diagram). 2-Quadrant Multiplying Mode (VOUT = 0V to -VREF) The LTC1596-1 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in Figure 1. With a fixed -10V reference, the circuit shown gives a precision unipolar 0V to 10V output swing.
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LT1001
VOUT 0V TO -VREF
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LTC1596-1
APPLICATIONS INFORMATION
4-Quadrant Multiplying Mode (VOUT = - VREF to VREF) The LTC1596-1 can be used with a dual op amp and three external resistors to provide 4-quadrant multiplying operation as shown in Figure 2. With a fixed 10V reference, the circuit shown gives a precision bipolar -10V to 10V output swing. Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC1596-1, thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Op amp offset will contribute mostly to output offset and gain and will have minimal effect on INL and DNL. For example, a 500V op amp offset will cause about 0.55LSB INL degradation and 0.15LSB DNL degradation with a 10V full-scale range. The main effects of op amp offset will be a degradation of zero-scale error equal to the op amp offset, and a degradation of full-scale error equal to twice the op amp offset. For example, the same 500V op amp offset will cause a 3.3LSB zero-scale error and a 6.5LSB full-scale error with a 10V full-scale range. Op amp input bias current (IBIAS) contributes only a zeroscale error equal to IBIAS(RFB) = IBIAS(RREF) = IBIAS(7k). Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. IOUT2 must be tied to the star ground with as low a resistance as possible.
VREF -10V TO 10V
5V
0.1F 10 4 7 5 6 9 8 11
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16 33pF OUT1
1/2 LT1112 OUT2 2
12 TO NEXT DAC FOR DAISY-CHAINING
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1596-1 F02
Bipolar Offset Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 ANALOG OUTPUT VOUT VREF (32,767/32,768) VREF (1/32,768) 0V -VREF (1/32,768) -VREF
Figure 2. Bipolar Operation (4-Quadrant Multiplication) VOUT = - VREF to VREF
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STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596-1 SRO LD2 STB2 STB4 DGND AGND
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20k
20k
1
10k
1/2 LT1112
VOUT -VREF TO VREF
LTC1596-1
TYPICAL APPLICATION
Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to - VREF
VREF -10V TO 10V
0.1F 13 10 4 7 5 6 9 8 11 14 15 16 33pF OUT1 STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596-1 SRO LD2 STB2 STB4 DGND AGND 12 TO NEXT DAC FOR DAISY-CHAINING 3
1596-1 F01
OUT2
2
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5V
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LT1001
VOUT 0V TO -VREF
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LTC1596-1
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
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Dimensions in inches (millimeters) unless otherwise noted.
N Package 16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770* (19.558) MAX 16 15 14 13 12 11 10 9
0.255 0.015* (6.477 0.381)
1 0.130 0.005 (3.302 0.127) 0.020 (0.508) MIN
2
3
4
5
6
7
8
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
N16 1197
LTC1596-1
PACKAGE DESCRIPTION
0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0 - 8 TYP
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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Dimensions in inches (millimeters) unless otherwise noted.
SW Package 16-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.398 - 0.413* (10.109 - 10.490) 16 15 14 13 12 11 10 9
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
1 0.093 - 0.104 (2.362 - 2.642)
2
3
4
5
6
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8 0.037 - 0.045 (0.940 - 1.143)
0.050 (1.270) TYP
0.004 - 0.012 (0.102 - 0.305)
0.014 - 0.019 (0.356 - 0.482) TYP
S16 (WIDE) 0396
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LTC1596-1
TYPICAL APPLICATION
Bipolar Operation (4-Quadrant Multiplication) VOUT = - VREF to VREF
VREF -10V TO 10V
5V
0.1F 10 4 7 5 6 9 8 11
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OUT1
1/2 LT1112 OUT2 2
12 TO NEXT DAC FOR DAISY-CHAINING
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1596-1 F02
RELATED PARTS
PART NUMBER LTC1590 LTC1595 LTC1596 LTC7541A LTC7543/LTC8143 LTC7545A LTC8043 DESCRIPTION Dual Serial I/O Multiplying IOUT 12-Bit DAC 16-Bit Mulitplying IOUT DAC in SO-8 16-Bit Mulitplying IOUT DAC Parallel I/O Multiplying IOUT 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DACs Parallel I/O Multiplying IOUT 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DAC COMMENTS 16-Pin SO and PDIP, SPI Interface True 16-Bit Upgrade for DAC8043 True 16-Bit Upgrade for DAC8143 and AD7543, Clears to Zero Scale 12-Bit Wide Parallel Input Clear Pin and Serial Data Output (LTC8143) 12-Bit Wide Latched Parallel Input 8-Pin SO and PDIP
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596-1 SRO LD2 STB2 STB4 DGND AGND
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20k
20k
14
15
16 33pF 1
10k
1/2 LT1112
VOUT -VREF TO VREF
15961i LT/TP 0798 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

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