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2.5-A High Performance Smart Power Stepper-Motor Driver with Diagnostic Interface
TLE 5250
SPT-IC Overview Features * * * * * * * * * * * * Single phase driver for stepper motor 2.5 A Low ON-resistance (typical 0.3 ) Wide supply range 6 V to 45 V Wide current range 10 mA to 3 A Fast nominal/actual comparator for micro stepper mode Wide temperature range Short circuit protection Under voltage shutdown Overtemperature shutdown Serial diagnostic interface Fast freewheeling diodes TTL-compatible inputs
P-SIP-15-1
Type TLE 5250 Description
Ordering Code Q67000-A9103
Package P-SIP-15-1
TLE 5250 is a monolithic IC in Smart Power technology for controlling and regulating the motor current in one phase of a bipolar stepping motor. There are other applications in driving DC motors and inductive loads that are operated on constant current. The device has TTL-compatible logic inputs, includes a H-bridge with integrated, fast free-wheeling diodes plus dynamic limiting of the motor current by a chopper mode. The nominal current can be set continuously by a control voltage. Microstep mode can be produced by applying a sinusoidal control voltage. Two TLE 5250s, with a minimum of external circuitry and a single supply voltage, form a complete system - that can be driven direct by an MC- for two-phase, bipolar stepping motors with output current of up to 2.5 A per phase. The outputs of the IC are internally protected against shorted to ground, supply voltage and shorted load. The output stages are also disabled by undervoltage and overtemperature. All fault functions can be detected by the internal diagnostics, which can be read out serially.
Semiconductor Group 1 1998-02-01
TLE 5250
1
15
DIAG PH EN VS Q1 Q1 Sense GND Sense Q2 Q2 VS RS NOM ACT
AEP01471
Figure 1
Pin Configuration (top view)
Semiconductor Group
2
1998-02-01
TLE 5250
Pin Definitions and Functions Pin No. 1 2 Symbol DIAG PH Function Open-drain diagnostics output Input for determining source/sink on outputs Q1 and Q2; when Enable = Low, this pin serves as clock input for reading out diagnostics Input for activating or turning off device (all output transistors turned off); Enable High = output active, Enable Low = diagnostics Supply voltage of IC Power output with integrated free-wheeling diodes Actual-current output: shared, open-source output of sink transistors Ground Power output with integrated free-wheeling diodes Determines turning back on of sink transistor by internally driven, external RC element or external TTL trigger signal Input for reference potential (nominal current) for nominal/ actual comparator Input for actual current for nominal/actual comparator
3
EN
4, 12 5, 6 7, 9 8 10, 11 13 14 15
VS
Q1 Sense GND Q2 RS NOM ACT
Semiconductor Group
3
1998-02-01
Cooling Pin 16 4 Bandgap/Bias Charge Pump
VS VS VCC1 VCC2 Bias VS -6 V
12
Figure 2
VS
Semiconductor Group
Driver 1 T1 T2 Driver 2 T1 T2 T3 T4 Functional Logic Q1 High + -
Undervoltage
Block Diagram
VS -1.5 V
+ 5 Q1 6 Q2 High
Overtemperature
Enable
3
Phase
2
VS -1.5 V
Overload + Q2 Low + 3V 3V
Q1 Low
H-Bridge Output Stage 10 Q2 11
4
G on T4 + 5V + G on T5 5V
Diagn
1
Diagnostics Logic
PWM Logic
Off/ Charge
V ref
Chop Logic
Nom/Act Comp 1 mA + 13 RC/Sync
Nominal
14
Driver 3
T3
T4
Driver 4
+ -
15
8 GND
7 Sense
9 Sense
AEB01468
TLE 5250
1998-02-01
Actual
TLE 5250
Application Two TLE 5250 drivers are required to operate a bipolar stepping motor. To implement full-step operation, a squarewave voltage with the required stepping frequency is applied to the phase input of the upper driver, and the same squarewave voltage, but offset in phase by 90el, to the phase input of the lower driver. Motor-current limiting is produced by a DC signal that is applied to both nominal-current inputs. In microstep operation the nominal current tracks sinusoidally and synchronously with the required stepping frequency. This produces a sinusoidal current in the motor windings to ensure very smooth running and a high stepping frequency. If an instantaneous nominal value (sine or cosine) is held on the second driver, it is possible to set a certain angle of rotation while the motor is stationary. The motor current produced by this depends on nominal voltage and sense resistance (normally 0.5 ), i.e.
V nom [ V ] I M [ V ] = ---------------------RS [ ]
The actual voltage should be thoroughly filtered for precise current regulation, especially in microstep operation. So the actual input is accessible, and an RC element is necessary between the Sense output and Actual input. The resistance RR should correspond to the internal resistance of the nominal-current input-voltage source to prevent additional voltage offset on the nominal/actual comparator.
Circuit Description Outputs Outputs Q1 and Q2 are fed by push-pull output stages. Four integrated free-wheeling diodes referred to ground or the supply voltage protect the integrated circuit against reverse voltages from an inductive load. Enable and Phase Outputs Q1 and Q2 can be disabled by a voltage VInh of 0.8 V on the Enable pin. The sink transistors are enabled by VInh 2 V. The voltage on the Phase input determines the phase of the output current. Output Q1 acts as a sink for VPh 0.8 V and as a source for VPh 2 V. For output Q2 this is reversed: sink for VPh 2 V and source for VPh 0.8 V. The sink transistors are chopped. Low signal on the Enable pin plus a clock signal on the Phase pin enable readout of the multiplexer.
Semiconductor Group
5
1998-02-01
TLE 5250
Nominal-Current Input The peak current in the motor winding is defined by the voltage on the Nominal input. This is compared by a fast comparator to the voltage drop on the actual-current sensor. If the nominal current is exceeded, the sink transistors of the outputs are turned off by the logic. RC/Sync Input The outputs are turned on by the signal applied to the RC input. Synchronization is possible by TTL signal or chopper mode with an external RC combination. Chopper Mode After the supply voltage is applied, capacitor CT is charged with constant current of 1 mA. A regulator limits the maximum voltage on the capacitor to 2.3 V. As a result of the rising current in the motor winding, the voltage on the actual sensor increases. Once the value defined by the nominal-current input is exceeded, the fast comparator resets an RS flipflop. Thus sink transistors T3 and T4 are turned off by the logic. The charge current is turned off and the parallel RT discharges CT. The internal logic is designed so that capacitor CT is always charged before the discharge operation is triggered. This guarantees a constant charge time, even for very small coil currents (see Figure 7). Sync Operation If a sync signal with TTL level is applied to the RC input, the negative edge will set the RS flipflop - by way of the combined Schmitt trigger and monoflop - if the voltage on the current sensor is smaller than the nominal value on the nominal-current input. As in chopper mode, the appropriate output transistors conduct. They are again turned off by resetting the RS flipflop when the voltage on the current sensor becomes greater than the nominal value (see Figure 8). Output-Stage Control This part of the circuit handles turn-off of the output stages when the output is shorted to ground. There is separate current monitoring for this purpose in the source transistors. The temperature of the output stages is also monitored. If this exceeds 175 C, all output stages are turned off, and then turned on again when the temperature drops. Undervoltage also causes turn-off of the transistors in the output stages. These possible fault states are stored in the diagnostics register.
Semiconductor Group
6
1998-02-01
TLE 5250
Diagnostics The information from the different parts of the circuit is collected in the diagnostics and stored in the fault logic. The information is read out on the Diagnostics output (open collector). The fault logic consists of a 16-bit multiplexer that switches information in three categories through to the Diagnostics output. Bit 0 always appears inverted on DIAG when EN is High. This means that, if there is overcurrent on the upper transistor, undervoltage or overtemperature, it will be signaled immediately on the Diagnostics output. DIAG changes from High to Low. Bit 1: check bit. Bits 2, 3, 4 and 5 indicate the momentary status of the comparators on the two outputs (see Figure 2). Changes in the status of the comparators for output monitoring can be observed on DIAG when EN is Low and the counter of the multiplexer is on 2, 3, 4 or 5. This is necessary for detecting underload. Bits 6, 7, 8, 9 The monoflop generates a short strobe signal when the EN edge changes from High to Low. The status of the comparators for output monitoring is stored with this signal and can be read out in bits 6, 7, 8 and 9. When Enable is Low, the Phase input is used as a clock input. As the edge rises, an internal counter is incremented and the corresponding channel of the multiplexer is switched through. As the edge falls, the signal is output inverted. When Enable is High, the counter is reset to zero.
EN
Strobe
Reset
AED01467
Figure 3
Semiconductor Group
7
1998-02-01
TLE 5250
Bits 10, 11 With these bits it is possible to detect the status of the gate voltages of the lower outputstage transistors T3 and T4. Bit 10: status for EN edge transition. Bit 11: whether the lower transistor has at all been turned on. Bit 12 indicates whether the nominal/actual comparator has switched. The comparator switches when the output current is regulated. Bits 13, 14, 15 These bits indicate the presence of overcurrent, undervoltage or overtemperature. A fault is ORed and output direct by bit 0 on DI. When the multiplexer is read out, bits 0 through 15 are output once non-inverted (Phase = Low) and once inverted (Phase = High). Bit Assignment in Error Register Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bits 2-5 Bit 6 Bit 7 Bit 8 Bit 9 = = = = = = = = = = = High for overtemperature/undervoltage/overcurrent always High High when sink transistor Q1 turned on High when sink transistor Q2 turned on High when source transistor Q1 turned on High when source transistor Q2 turned on momentary states for readout bit 2 state for falling edge of Enable signal bit 3 state for falling edge of Enable signal bit 4 state for falling edge of Enable signal bit 5 state for falling edge of Enable signal represent status of outputs for negative change in edge of Enable signal High if gate-source voltage of sink transistors is > 5 V at moment of readout are set if event occurs during switching (Enable = High) High if sink transistor VGS > 5 V High if actual current lower than nominal current High if overcurrent detected on source transistors High if undervoltage detected High if thermal link tripped
Bits 6-10 Bit 11 =
Bits 11-15 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 = = = = =
The memories are erased by a rising edge on the Enable input.
Semiconductor Group
8
1998-02-01
TLE 5250
Logic Assignment: Control Inputs, Output Transistors Enable Phase Output Q1 Output Q2 Transistor T1 Transistor T2 Transistor T3 Transistor T4 L H X - - / = = = = = = L L / / X X X X L H / / X X X X H L L H X - - X H H H L - X X -
Low voltage level, input open High voltage level transistor turned off transistor conducting transistor conducting, switched in current limiting output high-impedance
Semiconductor Group
9
1998-02-01
TLE 5250
RC/Sync 5V 5V Input T3 DFF D TR DT Output 2.3 V Charge-Current and SwitchingThreshold Control, Reset-Pulse Generation N/A Output Q RS FF S R Q & Input T4 Nom/Act QRS FF Comparator + Nominal Actual Gate T4 &
1 mA
Deadtime Comparator + -
Gate T3
+
1.8 V 0.8 V
AES01469
Figure 4
PWM Logic
Semiconductor Group
10
1998-02-01
TLE 5250
Error Status Continuous 0 Check Bit Low 1 Q1 Low Status Continuous 2 Q2 Low Status Continuous 3 Q1 High Status Continuous
1
Overcurrent Flag Q1 Low Status Q2 Low Status Q1 High Status Q2 High Status
M U X C h a n n e l
Diagn. Pin
_ <1
Q2 High Status Continuous 5 & & & & & Q1 Low Status Strobed SQ RQ SQ RQ SQ RQ SQ RQ Gon Status Strobed 10 Gon Status Latched 11 Actual Current up to Nominal Latched 12 Overcurrent T1/T2 Latched 13 Undervoltage Latched 14 Overtemperature Latched 15 Reset Clock SQ RQ & & SQ RQ SQ RQ & SQ RQ SQ RQ & SQ RQ Monoflop Monoflop Strobe Reset Latch Q2 High Status Strobed 9 Q1 High Status Strobed 8 Sequential Multiplexer Q2 Low Status Strobed 7 6 Q
&
MUX 16-to-1
GOn T3
_ <1 GOn Status
GOn T4 Nom/Act Stat. Act>Nom->High Overcurrent T1/T2 Status Undervoltage Status
_ <1
&
Overtemperature Status
Enable Phase
_ <1
Figure 5
Diagnostics Logic
Semiconductor Group
11
1998-02-01
1
AES01470
4
1
TLE 5250
Absolute Maximum Ratings TJ = - 40 to 150 C Parameter Supply voltage Supply current Peak currents on outputs Diode Forward Currents Diode to + VS Diode to sense Output current on actual-current pin Voltage on actual-current pin Ground current, pin 6 Chip temperature Storage temperature Thermal Resistances Junction to ambient Junction case Operating Range Supply voltage Input voltage Enable, Phase, RC/Sync Voltage on nominal pin Voltage on actual pin Output current Q1, Q2 Junction temperature Enable and Phase Inputs H input voltage L input voltage
Semiconductor Group
Symbol min.
VS IS IQ
Limit Values max. 45 3 3 - 0.3 0 -3
Unit V A A
IFH IFL IAct VAct IGND TC Tstg
- - - - 0.3 - - 40 -
3 3 3 5 3 150 125
A A A V A C C
RthjA RthjC
- -
70 3
K/W K/W
VS VI VNOM VACT IQ TJ
6 - 0.3 - 0.3 - - 2.5 - 40
40 5.5 2 2 2.5 150
V V V V A C
VIH VIL
12
2 -
- 0.8
V V
1998-02-01
TLE 5250
Characteristics
VS = 6 to 25 V; TJ 150 C
Parameter Supply current Output Q1, Q2 Turn-on resistance of output RDS ON transistors Phase deadtime Diode forward voltage output to + VS Diode forward voltage actual-current pin to output Nominal Current Input current 0.3 - - - 10 - 0.5 - 1.5 s V Symbol Limit Values min. typ. - max. 11 mA Enable = High - Unit Test Condition
IS
I = 2.5 A, 150 C
-
tD
VFQ
IFH = 2.5 V
-
-
-
1.5
V
IFH = 2.5 V
II8 Offset voltage measured for VI(8 - 4)
0 V actual/nominal pin
0 -4
1 -
2 8
A mV
- -
Actual Current Turn-off delay of nom/act comparator Common-mode error RC/Sync Sync frequency Trigger threshold lower upper Maximum charge voltage
td VComm
- -5
- -
0.5 10
s mV
- -
f VtL VtH VChm
- 0.8 1.7 2.2
20 - - 2.3
100 1 2 2.4
kHz V V V
- - -
R = 39 k C = 820 pF
Semiconductor Group
13
1998-02-01
TLE 5250
Characteristics (cont'd) Parameter Symbol Limit Values min. Undervoltage Cutout Disable Enable Hysteresis Diagnostics Output Activating delay (Enable High Low) Delay phase low to high Delay phase high to low Output voltage low Leakage current high typ. max. Unit Test Condition
VUDIAG VUEN VUH
4 - -
- - -
- 5.3 400
V V mV
- - -
tdef tddr tddf VDiag IDiag
- - - - -
- - - - -
400 500 450 0.4 10
ns ns ns V A
- Enable = Low VS > 5.5 V Enable = Low VS > 5.5 V
IQL = 5 mA VQH = 5 V
Semiconductor Group
14
1998-02-01
TLE 5250
5V
R
2 k
100 nF
22 F (Tantalum)
V Batt
Cooling Pin Diagnostics
GND
VS
1 nF Q1
Phase C Enable
TLE 5250
RN
1 k Nominal Actual RC/Sync. Sense Q2 1 nF
M
CN
68 pF
RT
39.2 k
CT
820 pF
RR
1k
RK
0.5
AES01472
CF
680 pF
RS
Figure 6
Application Circuit 1
Semiconductor Group
15
1998-02-01
TLE 5250
Phase = High or Low Enable 2.3 V 1.8 V
VRC/Sync 0.8 V
QRSFF SI OUT
Coil Current
Actual Voltage
Discharge operation is started when nominal current is reached. C T is discharged by R T . Voltage on RC/Sync was limited internally to 2.3 V in charge operation.
When coil current reaches nominal value, sink transistor is turned off. Independently of this, RC element is charged up to 1.8 V and then discharged. Charge operation is controlled by deadtime comparator. RC element is charged with 1mA.
AED01475
Figure 7
Chopper Mode with External Capacitor CT and Resistor RT
Semiconductor Group
16
1998-02-01
TLE 5250
RC/Sync QRSFF
Coil Current Nominal Voltage Actual Voltage N/A Output
Falling edge turns on sink transistor.
Sink transistor is turned off again when nominal voltage is reached.
AED01476
Figure 8
Synchron Mode
Semiconductor Group
17
1998-02-01
TLE 5250
EN PH
Q1
Q2
L
Strobe Reset Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 0
AED01477
Q1 Low Q2 Low Q1 High
Q2 High Q1 Low Strobed Q2 Low Strobed Q1 High Strobed Q2 High Strobed
For inductive load and faultfree operation, diagnostics when read out must show bit 2 inverted to bit 6 bit 3 inverted to bit 7 bit 4 inverted to bit 8 bit 5 inverted to bit 9
Figure 9
Response to Inductive Loads a) Normal Operation (no current regulation)
Semiconductor Group
18
1998-02-01
TLE 5250
EN PH
Q1
Q2
L
Strobe Reset Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 0
AED01478
Q1 Low Q2 Low Q1 High
Q2 High Q1 Low Strobed Q2 Low Strobed Q1 High Strobed Q2 High Strobed
Bit 2 identical to bit 6 Bit 4 identical to bit 8
= fault
Figure 10 Response to Inductive Loads b) Q1 Shorted to + VS (Phase = High)
Semiconductor Group
19
1998-02-01
TLE 5250
EN PH
Q1
Q2
L
RC/Sync Strobe Reset Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12
AED01479
Figure 11 Response to Inductive Loads c) Q2 Shorted to + VS (Phase = High)
Semiconductor Group
20
1998-02-01
TLE 5250
EN PH
Q1
Q2
L
RC/Sync Strobe Reset Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9
L = 0
AED01480
Indication of low load: bit 2 = bit 3 bit 4 = bit 5 while Enable = Low And conditions bit 2 = /bit 6 bit 3 = /bit 7 bit 4 = /bit 8 bit 5 = /bit 9 are not all satisfied
Figure 12 Response to Inductive Loads d) Low Load
Semiconductor Group
21
1998-02-01
TLE 5250
Package Outlines P-SIP-15-1 (Plastic Single In-Line)
20 0.3 3.8 0.06
4.62 max 1.52 0.08
21 max
17.78 0.25
1 1.27 17.78 0.69 0.1
15 0.25 M 15x
4.14 0.33
10.7 +0.15
0.5 0.13 4.29 9.37
17.5 0.15
0.61 M 15x
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information".
Dimensions in mm
Semiconductor Group
22
1998-02-01
GPI09015

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