View LTC1604_290660.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Final Electrical Specifications
LTC1604 High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown
January 1998
FEATURES
s s s s s s s
DESCRIPTION
The LTC(R)1604 is a 333ksps, 16-bit sampling A/D converter that draws only 220mW from 5V supplies. This high performance device includes a high dynamic range sample-and-hold, a precision reference and a high speed parallel output. Two digitally selectable power shutdown modes provide power savings for low power systems. The LTC1604's full-scale input range is 2.5V. Outstanding AC performance includes 90dB S/(N+D) and - 100dB THD at a sample rate of 333ksps. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 5MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has P compatible,16-bit parallel output port. There is no pipeline delay in conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FlFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
s s s s
A Complete, 333ksps 16-Bit ADC 90dB S/(N+D) and -100dB THD (Typ) Power Dissipation: 220mW (Typ) No Pipeline Delay No Missing Codes over Temperature Nap (7mW) and Sleep (10W) Shutdown Modes Operates with Internal 15ppm/C Reference or External Reference True Differential Inputs Reject Common Mode Noise 5MHz Full Power Bandwidth 2.5V Bipolar Input Range 36-Pin SSOP Package
APPLICATIONS
s s s s s s
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
TYPICAL APPLICATION
2.2F 10F 5V 10 36 10F 5V 10F 3 VREF
+
35 AVDD
+
9
+
10 DGND SHDN 33 CS 32 RD 30 BUSY 27 OVDD 29 5V OR 3V 10F
AVDD
DVDD
4 REFCOMP
7.5k 1.75X
+
47F
4.375V
2.5V REF
AMPLITUDE (dB)
CONTROL LOGIC AND TIMING
CONVST 31
P CONTROL LINES
1 AIN+ DIFFERENTIAL ANALOG INPUT 2.5V 2 AIN-
OGND 28
+ -
16-BIT SAMPLING ADC AGND 5 AGND 6
B15 TO B0
OUTPUT BUFFERS
D15 TO D0
16-BIT PARALLEL BUS 11 TO 26
1604 TA01
AGND 7
AGND VSS 8 34
+
-5V
10F
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
+
LTC1604
U
U
U
LTC1604 4096 Point FFT
0 -20 -40 -60 -80 -100 -120 -140 0 fSAMPLE = 333kHz fIN = 100kHz SINAD = 89dB THD = -96dB
20
40
60 80 100 120 140 160 FREQUENCY (kHz)
1604 TA02
1
LTC1604
ABSOLUTE MAXIMUM RATINGS
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW AIN+ AIN- VREF REFCOMP AGND AGND AGND AGND DVDD 1 2 3 4 5 6 7 8 9 36 AVDD 35 AVDD 34 VSS 33 SHDN 32 CS 31 CONV 30 RD 29 OVDD 28 OGND 27 BUSY 26 D0 25 D1 24 D2 23 D3 22 D4 21 D5 20 D6 19 D7 G PACKAGE 36-LEAD PLASTIC SSOP
Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS)................................ - 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS - 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ....................- 0.3V to 10V Digital Output Voltage .................. - 0.3V to (VDD + 0.3V) Power Dissipation............................................. 500mW Operating Temperature Range .................... 0C to 70C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1604CG
DGND 10 D15 11 D14 12 D13 13 D12 14 D11 15 D10 16 D9 17 D8 18
TJMAX = 125C, JA = 95C/W
Consult factory for A grade, Industrial and Military grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 7) (Note 8) Internal Reference External Reference IOUT(Reference) = 0 CONDITIONS
With Internal Reference (Notes 5, 6)
MIN
q q q
TYP 16 1 0.05 0.125 10
MAX 4 0.125 0.25 0.25 45
UNITS Bits LSB % % % ppm/C
15
A ALOG I PUT
SYMBOL PARAMETER VIN IIN CIN tACQ tAP tjitter CMRR Analog Input Range (Note 2) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio - 2.5V < (AIN- = AIN+) < 2.5V CONDITIONS 4.75 VDD 5.25V, - 5.25 VSS - 4.75V CS = High Between Conversions During Conversions
q q
MIN
TYP 2.5
MAX 1
UNITS V A pF pF ns ns psRMS dB
43 5 380 - 1.5 5 60
2
U
W
U
U
WW
W
U
U
U
LTC1604
DY A IC ACCURACY
SYMBOL S/(N + D) THD PARAMETER
IMD
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75 VDD 5.25V - 5.25V VSS - 4.75V 0 IOUT 1mA IOUT = 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D15 to D0 Hi-Z Output Capacitance D15 to D0 Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
U
U
U
WU U
(Note 5)
CONDITIONS 5kHz Input Signal 100kHz Input Signal 5kHz Input Signal 100kHz Input Signal 100kHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz MIN TYP 90 89 -100 - 94 96 82 5 350 MAX UNITS dB dB dB dB dB dB MHz kHz
Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Up to 5th Harmonic Peak Harmonic or Spurious Noise Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth (S/(N + D) 84dB
U
(Note 5)
MIN 2.475 TYP 2.500 15 0.01 0.01 7.5 4.375 MAX 2.515 45 UNITS V ppm/C LSB/V LSB/V k V
(Note 5)
MIN
q q q
TYP
MAX 0.8 1 0
UNITS V V A pF V V
2.4
5 VDD = 4.75V, IOUT = - 10A VDD = 4.75V, IOUT = - 400A VDD = 4.75V, IOUT = 160A VDD = 4.75V, IOUT = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V VOUT = VDD 4.5
q q q q
4.0 0.05 0.10 0.4 10 15 -10 10
V V A pF mA mA
3
LTC1604
POWER REQUIRE E TS
SYMBOL VDD VSS IDD PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Nap Mode Sleep Mode Negative Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode
ISS
PD
TI I G CHARACTERISTICS
SYMBOL fSMPL(MAX) tCONV tACQ tACQ+CONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time
Throughput Time (Acquisition + Conversion) CS to RD Setup Time CS to CONVST Setup Time SHDN to CS Setup Time SHDN to CONVST Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) CS = Low (Note 10) (Note 10) CL = 25pF
Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD
t11
Bus Relinquish Time LTC1604C LTC1604I
q q q q
t12 t13 t14
RD Low Time CONVST High Time Aperture Delay of Sample-and-Hold
4
UW
(Note 5)
CONDITIONS (Notes 10, 11) (Note 10) CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V
q
MIN 4.75 - 4.75
TYP
MAX 5.25 - 5.25
UNITS V V mA mA A mA A A mW mW mW
18 1.5 1 26 1 1 220 7.5 0.01
27 2.4 100 37 100 100 320 12 1
q
q
UW
(Note 5)
CONDITIONS
q q
MIN 333 1.5
TYP 2.45
MAX 2.8 480 3
UNITS kHz s ns s ns ns ns
(Note 9)
q q q q q
0 10 10 400 40 36 80 60 32 200 -5 40 50 60 60 75 60 70 75
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
q q q
(Note 10) (Note 10) CL = 25pF
q q q
CL = 100pF
q
45 50
(Note 10) (Note 10)
t10 40 2
ns
LTC1604 TI I G CHARACTERISTICS
The q denotes specifications that apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = - 5V, fSMPL = 333kHz, and t r = t f = 5ns unless otherwise specified.
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. The ADC converts the difference voltage between AIN+ and AIN- with a differential range of 2.5V. AIN+ has a 2.5V input range when AIN- is grounded. AIN- (Pin 2): Negative Analog Input. Can be grounded, tied to a DC voltage or driven differentially with AIN+ . VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 2.2F tantalum in parallel with 0.1F ceramic. REFCOMP (Pin 4): 4.375 Reference Compensation Pin. Bypass to AGND with 47F tantalum in parallel with 0.1F ceramic. AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground plane. DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND with 10F tantalum in parallel with 0.1F ceramic. DGND (Pin 10): Digital Ground for Internal Logic. Tie to analog ground plane. D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15 is the Most Significant Bit. BUSY (Pin 27): The BUSY output shows the converter status. It is low when a conversion is in progress. Data is valid on the rising edge of BUSY. OGND (Pin 28): Digital Ground for Output Drivers. OVDD (Pin 29): Digital Power Supply for Output Drivers. Bypass to OGND with 10F tantalum in parallel with 0.1F ceramic. RD (Pin 30): Read Input. A logic low enables the output drivers when CS is low. CONVST (Pin 31): Conversion Start Signal. This active low signal starts a conversion on its falling edge when CS is low. CS (Pin 32): The Chip Select Input. Must be low for the ADC to recognize CONVST and RD inputs. SHDN (Pin 33): Power Shutdown. Drive this pin low with CS low for nap mode. Drive this pin low with CS high for sleep mode. VSS (Pin 34): - 5V Negative Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic. AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic. AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic and connect this pin to Pin 35 with a 10 resistor.
U
U
UW
(Note 5)
Note 6: Linearity, offset and full-scale specification apply for a singleended AIN+ input with AIN- grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 250ns after conversion start or after BUSY rises.
U
5
LTC1604
FU CTIO AL BLOCK DIAGRA
2.2F 10F
3 VREF
+
+
47F
4 REFCOMP 4.375V
7.5k 1.75X
1 AIN DIFFERENTIAL ANALOG INPUT 2.5V
+
+ -
16-BIT SAMPLING ADC B15 TO B0 OUTPUT BUFFERS
OGND 28
10F 16-BIT PARALLEL BUS
- 2 AIN
D15 TO D0
11 TO 26 AGND 5 AGND 6 AGND 7 AGND VSS 8 34
+
-5V
10F
1604 TA01
TEST CIRCUITS
Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 1k DN 1k CL DN CL DN 1k CL DN
5V 1k
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1604 TC01
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1604 TC02
6
+
W
5V 10 36 AVDD 35 AVDD 10F 5V 10F
U
U
+
9
+
10 DGND SHDN 33
DVDD
2.5V REF
CONTROL LOGIC AND TIMING
CS 32 CONVST 31 RD 30 BUSY 27 P CONTROL LINES
LTC1604 OVDD 29 5V OR 3V
CL
LTC1604
APPLICATIONS INFORMATION
CONVERSION DETAILS The LTC1604 uses a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 16-bit parallel output. The ADC is complete with a sample-and-hold, a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) resets. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the Most Significant Bit (MSB) to the Least Significant Bit (LSB). Referring to Figure 1, the AIN+ and AIN- inputs are acquired during the acquire phase and the comparator
CSMPL AIN+ SAMPLE HOLD CSMPL AIN- SAMPLE HOLD HOLD +CDAC ZEROING SWITCHES HOLD
+
-CDAC +VDAC COMP
-
-VDAC SAR
16
OUTPUT LATCHES
Figure 1. Simplified Block Diagram
U
W
U
U
offset is nulled by the zeroing switches. In this acquire phase, a duration of 480ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSMPL capacitors to ground, transferring the differential analog input charge onto the summing junctions. This input charge is successively compared with the binarily weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN- input charges. The SAR contents (a 16-bit data word) which represent the difference of AIN+ and AIN- are loaded into the 16-bit output latches. DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that runs the A/D conversion. The internal clock is factory trimmed to achieve a typical conversion time of 2.45s and a maximum conversion time of 2.8s over the full temperature range. No external adjustments are required. The guaranteed maximum acquisition time is 480ns. In addition, a throughput time (acquisition + conversion) of 3s and a minimum sampling rate of 333ksps are guaranteed.
* * *
D15 D0
1604 F01
7
LTC1604
APPLICATIONS INFORMATION
Power Shutdown The LTC1604 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode all bias currents are shut down and only leakage current remains m (about 1A). Wake-up time from Sleep mode is much slower since the reference circuit must power up and settle. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 160ms with the recommended 47F capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in shutdown when SHDN is low. The shutdown mode is selected with Pin 32 (CS). When SHDN is low, CS low selects nap and CS high selects sleep. Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upsetting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, if CONVST returns high early in the conversion (e.g., CONVST low time <500ns), accuracy is unaffected. Similarly, if CONVST returns high after the conversion is over (e.g., CONVST low time >tCONV), accuracy is unaffected. For best results, keep t 5 less than 500ns or greater than tCONV. Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the
1.4 1.2 1.0
CONVST t1 RD
1604 F03
CHANGE IN DNL
8
U
W
U
U
SHDN t3 CS
1604 F02a
Figure 2a. Nap Mode to Sleep Mode Timing
SHDN t4 CONVST
1604 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing
CS t2
Figure 3. CS top CONVST Setup Timing
0.8 0.6 tCONV 0.4 0.2 0 -0.2 0 400 800 1200 1600 2000 2400 2800
1604 F04
tACQ
CONVST LOW TIME, t5 (ns)
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the CONVST Pulse Returns High Early in the Conversion or After the End of Conversion
LTC1604
APPLICATIONS INFORMATION
conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared data bus. In slow memory and ROM modes (Figures 8 and 9) CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the combined CONVST-RD signal. Conversions are started by the MPU or DSP (no external sample clock is needed). In slow memory mode the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion.
CS = RD = 0 t5 CONVST t6 BUSY
t CONV
DATA
DATA (N - 1) D15 TO D0
Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = )
CS = RD = 0 t13 CONVST t6 BUSY
tCONV t5
DATA
DATA (N - 1) D15 TO D0
Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = )
U
W
U
U
t8
t7 DATA N D15 TO D0 DATA (N + 1) D15 TO D0
1604 F05
t8
t6
t7 DATA N D15 TO D0 DATA (N + 1) D15 TO D0
1604 F06
9
LTC1604
APPLICATIONS INFORMATION
t13 CS = 0 tCONV t5 t8
CONVST t6 BUSY t9 RD t 10 DATA DATA N D15 TO D0
1604 F07
Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD
CS = 0 RD = CONVST t6 BUSY t 10 DATA
t CONV
DATA (N - 1) D5 TO D0
Figure 8. Mode 2. Slow Memory Mode Timing
CS = 0 RD = CONVST t6 BUSY t 10 DATA
t CONV
t 11
DATA (N - 1) D15 TO D0
Figure 9. ROM Mode Timing
10
U
t7
W
U
U
t 12
t 11
t8
t 11
DATA N D15 TO D0
DATA N D15 TO D0
DATA (N + 1) D15 TO D0
1604 F08
t8
DATA N D15 TO D0
1604 F09
LTC1604
PACKAGE DESCRIPTION U
Dimensions in inches (millimeters) unless otherwise noted.
G Package 36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.499 - 0.509* (12.67 - 12.93) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
0.301 - 0.311 (7.65 - 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0.205 - 0.212** (5.20 - 5.38) 0.068 - 0.078 (1.73 - 1.99)
0 - 8
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
0.0256 (0.65) BSC
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.010 - 0.015 (0.25 - 0.38)
0.002 - 0.008 (0.05 - 0.21)
G36 SSOP 1196
11
LTC1604 RELATED PARTS
SAMPLING ADCs
PART NUMBER LTC1410 LTC1415 LTC1419 LTC1605 DESCRIPTION 12-Bit, 1.25Msps, 5V ADC 12-Bit, 1.25Msps, Single 5V ADC Low Power 14-Bit, 800ksps ADC 16-Bit, 100ksps, Single 5V ADC COMMENTS 71.5dB SINAD at Nyquist, 150mW Dissipation 55mW Power Dissipation, 72dB SINAD True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation 10V Inputs, 55mW, Byte or Parallel I/O
DACs
PART NUMBER LTC1595 LTC1596 DESCRIPTION 16-Bit Multiplying IOUT DAC in SO-8 16-Bit Multiplying IOUT DAC COMMENTS 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade 1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417q (408)432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
1604i LT/TP 0198 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

▲Up To Search▲

Price & Availability of LTC1604

	To Download LTC1604 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .