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S1D2502A01
Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
VIDEO AMP MERGED OSD PROCESSOR
The S1D2502A01 is a very high frequency video amplifier & wide range OSD processor 1 chip system with I2C Bus control used in monitors. It contains 3 matched R/G/B video amplifiers with OSD processor and provides flexible interfacing to I2C Bus controlled adjustment systems.
32-DIP-600A
FUNCTIONS
* * * * * * R/G/B video amplifier OSD processor I2C bus control Cut-off brightness control R/G/B sub contrast/cut-off control Half tone
ORDERING INFORMATION
Device S1D2502A01-D0B0 Package 32-DIP-600A Operating Temperature -20 C -- +75 C
FEATURES
VIDEO AMP PART * * 3-channel R/G/B video amplifier, 175MHz @f-3dB I2C bus control items -- Contrast control: -38dB -- Sub contrast control for each channel: -12dB -- Brightness control -- OSD contrast control: -38dB -- Cut-off brightness control (AC coupling) -- Cut-off control for each channel (AC coupling) -- Switch registers for SBLK and video half tone and CLP/BLK polarity selection and INT/EXT CLP selection and generated CLP width control Built in ABL (automatic beam limitation) Built in video input clamp, BRT clamp Built in video half tone (3mode) function on OSD pictures Capable of 8.0Vp-p output swing Improvement of rise & fall time (2.2ns) Cut-off brightness control Built in blank gate with spot killer Clamp pulse generator OSD intensity BLK, CLP polarity selection Clamp gate with anti OSD sagging * * * * * * * * OSD PART * * * * * * * Built in 1K-byte SRAM 448 ROM fonts (each font consists of 12 x 18 dots.) Full screen memory architecture Wide range PLL available (15kHz -- 96kHz, Reference 800 X 600) Programmable vertical height of character Programmable vertical and horizontal positioning Character color selection up to 16 different colors Programmable background color (up to 16 colors) Character blinking, bordering and shadowing Color blinking Character scrolling Fade-in and fade-out Box drawing Character sizing up to four times 76.8MHz pixel frequency from on-chip PLL (Reference 800 X 600)
* * * * * * * * * * *
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
BLOCK DIAGRAM
6
VDDA VSSA
VDD 31
9
ROM (448 x 18 x 12)
ROM Address
RAM (480 x 16)
16
Data Receiver
RAM Data Ctrl Data 16 CLK Frame Ctrl H_Pulse V_Pulse ROM Ctrl Control Register
2
VSS 28
Font Data 12
Ctrl Font
32
HFLB VFLB VCO_IN_P
VCC3 11 Output Stage GND3
9
Display Display Ctrl Controller
OSD PLL
1 3
VREF1 4 Band Gap.Ref VREF 5
R/G/B OSD H/V/CLK Ctrl H/V/CLK Ctrl FBLK Intensity Timing Controller Frame Ctrl ROM Ctrl RGB OSD FBL BLK INTE HT DET. CLP
Latches
30 I C bus decoder D/
2
SDA SCL
29
A BLK Int
R cut off G cut off HFLB B cut off
Multi (3 mode) Half Tone
V/I V/I V/I
27 26 25
RCT GCT BCT
Clamp Pulse Gen.
ABL 8 CONT_CAP 7 RIN 12 GND1 15
ABL
10
CLP_IN
Video Input Clamp
CLP
Video Half Tone SW
FBLK I2C
Sub Cont. Control
I2C
Video Contras t
+
Sub Cont. Control
Amp Out BLK
24
R OUT VCC2
22
R OSD
OSD Input Cilp.
HT DET.
OSD Half Tone SW
FBLK I2C
OSD Cont. Control
I2C
Birght Control
I2C Cont. Cntl I2C CLP
23
R CLP GND2 G CLP G OUT B CLP B OUT
VCC1 13 GIN 14
19 20
G-CHANNEL
G OSD
CLP HT DET. FBLK I2C CLP BLK
21 17
BIN 16
B OSD
CLP HT DET. FBLK
B-CHANNEL
18
IC
2
CLP
BLK
Figure 1. Functional Block Diagram
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S1D2502A01
Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VFLB VSSA VCO_IN_P VREF1 VREF VDDA CONT_CAP ABL_IN GND3 CLP_IN VCC3 RIN VCC1 GIN GND1 BIN
HFLB VDD SDA SCL VSS RCT GCT BCT ROUT RCLP VCC2 GOUT GCLP GND2 BOUT BCLP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Figure 2. Pin Configuration
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
Table 1. Pin Configuration Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VFLB VSSA VCO_IN_P VREF1 VREF VDDA CONT_CAP ABL GND3 CLP_IN VCC3 RIN VCC1 GIN GND1 BIN BCLP BOUT GND2 GCLP GOUT VCC2 RCLP ROUT BCT GCT RCT VSS SCL SDA VDD HFLB I/O I I O O I I I O O O I I/O I Vertical flyback signal Ground (PLL part) This voltage is generated at the external loop filter and goes into the input stage of the VCO. Charge pump output PLL regulator filter +5V supply voltage for PLL part Contrast control for AMP part Auto beam limit. Ground for video AMP part(for AMP control) Video clamp pulse input +12V supply voltage for video AMP part(for AMP control) Video signal input (red) +12V supply voltage for video AMP(for main video signal process) Video signal input (green) Ground for video AMP part(for main video signal process) Video signal input (blue) B output clamp cap Video signal output (blue) Ground for video AMP part(for video output drive) G output clamp cap Video signal output (green) +12V supply voltage for video AMP part(for video output drive) R output clamp cap Video signal output (red) B cut-off output G cut-off output R cut-off output Ground for digital part Serial clock (I2C) Serial data (I2C) +5V supply voltage for digital part Horizontal flyback signal Configuration
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
PIN DESCRIPTION
Table 2. Pin Description Pin No 1 Pin Name VFLB
VFLB HFLB
Schematic
Description FLB signal is in TTL level
32
HFLB
Multi polarity input
3
VCO_IN_P
PLL loop filter output
4
VPEF/
BandGap ref. output
5
VREF
7
Contrast cap (CONT_CAP)
4.0K I2C Data 100A Vref
Contrast cap range (0.1uF -- 5uF)
8
ABL_IN
100K 2K Vref
VCC
ABL input DC range (1 -- 4.5V)
Vref 250A
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
Table 2. Pin Description (Continued) Pin No 10 Pin Name CLP_IN Schematic Description Multi polarity input
VCC 50K
Clamp gate pulse TTL level input
10K
12
Red video input (RIN)
VCC VCC
Max input video signal is 0.7 Vpp
14
Green video input (GIN)
Video_In 0.2K
16
Blue video input (BIN)
12K
17
Blue (B clamp cap)
20
Green (G clamp cap)
0.2K CLP
Brightness controlling actives by charging and discharging of the external cap. (0.1F) (During clamp gate)
23
Red (R clamp)
0.2K
Iclamp
5
S1D2502A01
Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Table 2. Pin Description (Continued) Pin No 18 Pin Name Blue video output (BOUT) Schematic Description Video signal output
VCC
0.05K
21
Green video output (GOUT)
0.5K 0.04K Video_Out
24
Red video output (ROUT)
Isink
27
Red cut-off control (RCT) Green cut-off control (GCT)
0-600uA 0-200uA 50uA 100uA
0.2K CTX
Cut-off control output
26
25
Blue cut-off control (BCT)
29
SCL
SCL
Serial clock input port of I2C bus
30
SDA
SCL
Serial data input port of I2C bus
ACK
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
ABSOLUTE MAXIMUM RATINGS (see 1)
(Ta = 25 C) Table 3. Absolute Maximum Ratings No Item Symbol VCC VDD Topr Tstg VCCop VDDop PD Value Min -20 -65 11.4 4.75 12.0 5.00 Typ Max 13.2 6.5 75 150 12.6 5.25 Unit
1 2 3 4 5
Maximum supply voltage Operating temperature (see 2) Storage temperature Operating supply voltage Power dissipation
V C C V (see 3) W
THERMAL & ESD PARAMETER
Table 4. Thermal & ESD Parameter No 1 2 3 4 5 Item Thermal resistance (junction-ambient) Junction temperature Human body model (C = 100p, R = 1.5k) Machine model (C = 200p, R = 0) Charge device model Symbol ja Tj HBM MM CDM Value Min 2 300 800 Typ 48 150 Max Unit C/W C KV V V
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Tamb = 25 C, VCC = 12V, VDD = VDDA = 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors = 470, except OSD part current 35mA, unless otherwise stated) Table 5. DC Electrical Characteristics
Value Parameter Supply current Minimum supply current Maximum supply current ABS supply current Video input bias voltage Video black level voltage (POR) Black level voltage channel difference (POR) Video black level voltage (FFH) Black level voltage channel difference (FFH) Video black level voltage (00H) Black level voltage channel difference (00H) Spot killer voltage Cut-off current (FFH) Symbol ICC (see 4) ICC min ICC max ICC abs V bias V blackpor V blackpor
(see 5)
Conditions Min 100 VCC = 11.4V VCC = 12.6V VCC = 13.2V 95 105 1.8 1.20 10 04 = FFH (see 13) 2.2 10 04 = 00H 10 VCC = Var. Pin25, 26, 27 = 12V 09 -- 0B: FFH 0C: 00H Pin25, 26, 27 = 12V 09 -- 0C: 00H Pin25, 26, 27 = 12V 09 -- 0B: 00H 0C: FFH Pin25, 26, 27 = 12V 09 -- 0B: 00H 0C: 80H Pin25, 26, 27 = 12V 09 -- 0C: 00H 0E: 11H 9.20 500 Typ 125 110 130 2.1 1.50 2.7 0.2 10.4 625 Max 130 120 140 175 2.4 1.80 3.2 0.5 11.2 750
Unit mA mA mA mA V V % V % V % V A
V blackff V blackff V black00 V black00 Vspot ICTff
Cut-off current (00H) Cut-off brightness current (FFH)
ICT00 ICTBRTff
100
2.0 180
5.0 260
A A
Cut-off brightness current (80H)
ICTBRT80
50
90
130
A
Cut-off offset current 1
ICS1
25
50
75
A
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S1D2502A01
Table 5. DC Electrical Characteristics (Continued)
Value Parameter Cut-off offset current 2 Symbol ICS2 Conditions Min Pin25, 26, 27 = 12V 09 -- 0C: 00H 0E: 12H 0D: 80H 0E: 14H 50 Typ 100 Max 130 A Unit
Soft BLK output voltage Clamp cap voltage (POR)
Vsblk Vcap
6.0
0.2 7.0
0.5 8.0
V V
Total external cut-off current range
Red cut-off
Creen cut-off
Blue cut-off
600uA
Cut-Off Brightness
200uA
CS2 Cut-Off Offset Switch 100uA CS1 50uA 150uA
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
AC ELECTRICAL CHARACTERISTICS (Tamb = 25 C, VCC = 12V, VDD = VDDA = 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors = 470, Vin = 0.7Vpp manually adjust video output pins 18, 21 and 24 to 4V DC for the AC test (see 11) unless otherwise stated (see 12)) Table 6. AC Electrical Characteristics
Value Parameter Contrast max. output voltage Contrast max. output channel difference Contrast center output voltage Contrast center output channel difference Contrast max. - Center attenuation Sub contrast center output voltage Sub contrast center output channel difference Sub contrast min. output voltage Sub contrast min. output channel difference Sub contrast max. - min. attenuation ABL control range R/G/B video rising time (see 7) R/G/B video falling time (see 7) R/G/B blank output rising time (see 7) R/G/B blank output falling time (see 7) R/G/B video band width (see 7, 8) Video AMP 50MHz cross talk Video AMP 130MHz cross talk Absolute gain match Gain change between amplifier Symbol Vcff Vcff Vc80 Vc80 C Vd80 Vd80 Vd00 Vd00 D ABL tr (video) tf (video) tr (blank) tf (blank) f (-3dB) CT_50M
(see7, 9)
Conditions Min 03, 05, 06, 07 = FFH 04, 08 -- 0C = 80H RGB input = S1 03, 04, 08 ~ 0C = 80H 05, 06, 07 = FFH RGB input = S1 C = 20log (Vc80/Vcff) 03 = FFH 04 -- 0C = 80H RGB input = S1 03 = FFH, 05--07: 00H 04, 08 -- 0C = 80H RGB input = S1 D = 20log (Vd00/Vcff)
(see 15)
Unit Typ 5.7 2.85 -6 2.6 1.6 -12 -10 2.2 2.2 6.0 8.0 -25 -15 Max 6.4 3.2 -4 2.9 1.9 -10 -8 2.8 2.8 12.0 15.0 -20 -10 1 1 Vpp % Vpp % dB Vpp % Vpp % dB dB ns ns ns ns MHz dB dB dB dB 5.0 10 2.5 10 -8 2.3 10 1.3 10 -14 -12 175 -1 -1
03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H RGB input = S2 POR HFLB: S4
(see 16) (see 17)
CT_130M
(see7, 9)
(see 18)
Avmatch (see 6) Avtrack
(see 7)
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
OSD ELECTRICAL CHARCTERISTICS (Tamb = 25 C, VCC = 12V, VDD = VDDA = 5V, HFLB input voltage = S3, load rosistors = 470, V-AMP test registor's FBLK, OSD input conditions unless otherwise stated) Table 7. OSD Electrical Chaacteristics
Value Parameter OSD contrast max. output voltage OSD contrast max. output channel difference OSD contrast center output voltage OSD contrast center output channel difference R/G/B OSD rising time R/G/B OSD falling time HT video level HT video output channel difference Symbol Vocff Vocff Voc80 Voc80 tr (OSD) tf (OSD) HTvideo HTvideo ABL = 6V RGB input = S1 03, 05 -- 08: FFH 0D: 01H OSD black conditions input HTvideo = 20log(Vhtvideo/Vcff) ABL = 6V 05 -- 08: FFH 0D: 0FH OSD white condition input HTosd = 20log (Vhtosd/Vocff) Conditions Min 08 = FFH OSD RGB output conditions 5.4 10 2.7 10 -6.0 15 Typ 6.4 3.2 4.0 4.0 -4.5 Max 7.4 3.7 5.0 5.0 -3.0 Vpp % Vpp % ns ns dB % Unit
08 = 80H OSD RGB output conditions
08: FFH
HT OSD level HT OSD output channel difference
HTosd HTosd
-7.0 15
-5.5 -
-4.0 -
dB %
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
OPERATION TIMINGS
Table 8. Operation Timings Parameter Input Signal HFLB, VFLB Horizontal flyback signal frequency Vertical flyback signal frequency I
2C
Symbol fHFLB fVFLB fSCL ths tsus tlow thigh thd tsud tss tfSDA trSDA
Min 500 500 400 400 0 500 500 -
Typ -
Max 120 200 300 20 -
Unit kHz Hz kHz ns ns ns ns ns ns ns ns ns
Interface SDA, SCL (Refer to Figure 3)
SCL clock frequency Hold time for start condition Set up time for stop condition Low duration of clock High duration of clock Hold time for data Set up time for data Time between 2 access Fall time of SDA Rise time of both SCL and SDA
tss SDA ths SCL tsud
thd
tsus thigh tlow
Figure 3. I2C Bus Timing Diagram
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
OSD PART ELECTRICAL CHARACTERISTICS
OSD PART DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VDDA = VDD = 5V) Table 9. OSD Part DC Electrical Characteristics Parameter Supply voltage Supply current (no load on any output) Input voltage Output voltage (lout = 1mA) Input leakage current VCO input voltage Symbol VDD IDD VIH VIL VOH VOL IIL VVCO Min 4.75 0.8VDD 0.8VDD -10 Typ 5.00 2.5 Max 5.25 25 VSS + 0.4 VSS + 0.4 10 Unit V mA V V V V A V
13
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
NOTES: 1. 2. Absolute maximum rating indicates the limit beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the electrical characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. VCC supply pins 11, 13, and 22 must be externally wired together to prevent internal damage during VCC power on/off cycles. The supply current specified is the quiescent current for VCC1/VCC2 and VCC3 with RL = , The supply current for VCC2 (pin 22) also depends on the output load. Output voltage is dependent on load resistor. Test circuit uses RL = 470 Measure gain difference between any two amplifiers Vin = 700mVpp. When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board without socket is recommended. Video amplifier 50MHz cross talk test also requires this printed circuit board. The reason for a double sided full ground plane PCB is that large measurement variations occur in single sided PCBs. Adjust input frequency from 10MHz (AV max reference level) to the -3dB frequency (f -3dB). Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at fin = 50MHz for cross talk 50MHz. A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15kHz. This limit is guaranteed by design. if a lower line rate is used a longer clamp pulse may be required. During the AC test the 4V DC level is the center voltage of the AC output signal. For example. If the output is 4Vpp the signal will swing between 2V DC and 6V DC. These parameters are not tested on each product which is controlled by an internal qualification procedure. The conditions block's 03, 04, 05... etc. signify sub address' 0F03, 0F04, 0F05... etc. Sub address 0F03, 0F05 ~ 0F07: FFH 0F04, 0F08 ~ 0F0C: 80H RGB input = S1, When the ABL input voltage is 0V, the R/G/B's output voltage is VR/VG/VB and uses the formula ABLR = 20log (VR/VcffR) OSD TST mode = High, CLP operation off, RGB input = S5 (frequency sweep), RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), S5's frequency 1MHz 130MHz sweep, -3dB point = 20log (V130MHz/V1MHz) 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H OSD TST mode = High, CLP operation off, RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H R input = S5 (50MHz) CT_50M = 20log (VoutG/VoutR) or 20log (VoutB/VoutR) OSD TST mode = High, CLP operation off, RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H R input = S5 (130MHz) CT_150M = 20log (VoutG/VoutR) or 20log (VoutB/VoutR)
3. 4. 5. 6. 7.
8. 9. 10. 11. 12. 13. 14.
15.
16.
17.
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
TEST SIGNAL FORMAT
Table 10. Test Signal Format
Signal Name S1 [V] Video Input Signal Formal Signal Description Video gain measurement Video = 1MHz/0.7Vpp Sync = 50kHz Sync 4uS S2 [V] 0.7 Vpp f = 200kHz S3 [V] t = 2uS Duty = 50% [t] HFLB (posi & nega.) input f = 50kHz t = 2uS V = 0V/5V [t] OSD level measurement [V] 5V 0V f = 200kHz S5 [V] Vi Vref [t] Vref = input clamp voltage Vi = 0.7Vpp Duty = 50% [t] Crosstalk test Bandwidth measurement 1MHz/10MHz/50MHz/ 130MHz Blank Tr/Tf measurement f = 50kHz V = 0V/5V [t] Video Tr/Tf measurement f = 200kHz V = 0.7Vpp Duty = 50%
f = 50kHz S4
* *
S1, S2 signal's low level must be synchronized with the S3 signal's sync. term. The input signal level uses the IC pin as reference.
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
TEST CIRCUIT
VDD = 5.0V
33 BNC1
33 BNC3
1
33 BNC2 5.6K 562 1 2 SW1 27K 4.7u 1M
VFLB VSSA VCO_IN_P VREF1 VREF VDDA CONT_CAP ABL_IN GND3 CLP_IN VCC3 RIN VCC1 GIN GND1 BIN
HFLB VDD SDA SCL VSS RCT GCT BCT ROUT RCLP VCC2 GOUT GCLP GND2 BOUT BCLP
32 31
33
100u
2 3 4 5
103
30
33
4.7K BNC4 4.7K BNC5
30M
29 28
2K
6
1u 100u 100 ABL 1u 33 BNC6 100u
27
2K
7 8 9 10 11
26
2K
S1D2502A01
25
470
KB2502
24
0.1u
23 22
470
75
0.1u
12
100u BNC7 75 0.1u
21
0.1u
13 14
20 19
470
BNC8 75 0.1u
15 16
18
0.1u
17
BNC9
VCC = 12.0V Magnetic Core
Figure 4. Test Circuit
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
FUNCTIONAL DESCRIPTIONS
DATA TRANSMISSION The interface between S1D2502A01 and MCU follows the I2C protocol. After the starting pulse, the transmission takes place in the following order: Slave address with R/W bit, 2-byte register address, 2-byte data, and stop condition. an acknowledge signal is received for each byte, excluding only the start/stop condition. The 2-byte register address is composed of an 8-bit row address, and an 8-bit column address. The order of transmission for a 2-byte register address is 'Row address Column address'. The 2 bytes of data is because S1D2502A01 has a 16-bit base register configuration. S1D2502A01's slave address is BAh. It is BBh in read mode, and BAh in write mode. * Address Bit Pattern for Display Registers Data (a) row address bit pattern R3 - R0: Valid data for row address A15 X A14 X A13 X A12 X A11 R3 A10 R2 A9 R1 A8 R0
(b) Column address bit pattern C4 - C0: Valid data for column address A7 X X:Don't care bit A6 X A5 X A4 C4 A3 C3 A2 C2 A1 C1 A0 C0
*
Data Transmission Format Start Slave address ACK Row address ACK Column address ACK Data byte N ACK Data byte N+1 ACK Stop Figure 5. Data Transmission Format at Writing Operation
Start Slave address ACK Row address ACK Column address ACK Stop Start Slave address ACK Data byte N ACK Data byte N+1 ACK Stop Figure 6. Data Transmission Format at Reading Operation
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
*
SDA / SCL Signal At Communication
SCL SDA START SCL
...
R/W IIC SLAVE ADDRESS ACK
A15 A14 A13 A12 A11 A10 A9 MSB ADDRESS
A8 ACK
A7
A6
A5
A4 A3 A2 LSB ADDRESS
A1
A0 ACK
SDA
D7
D6
D5 D4 D3 D2 D1 D0 ACK DATA BYTE N(MSB DATA)
D7
D6
D5 D4 D3 D2 D1 D0 DATA BYTE N(LSB DATA) ACK
D7
D6
D5 D4 D3 D2 D1 D0 DATA BYTE N(MSB DATA)
ACK
...
STOP
Figure 7. SDA line and SCL line (Write Operation)
SCL SDA START SCL SDA START IIC SLAVE ADDRESS R/W D15 D14 D13 D12 D11 D10 D9 ACK DATA BYTE N(MSB) D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP IIC SLAVE ADDRESS R/W ACK A15 A14 A13 A12 A11 A10 A9 MSB ADDRESS A8 ACK A7 A6 A5 A4 A3 A2 LSB ADDRESS A1 A0 ACK STOP
DATA BYTE N(LSB)
Figure 8. SDA line and SCL line (Read Operation)
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
MEMORY MAP
00 01 02 Row 00 Row 01
27 28 29 30
Character & Attribute Registers (30 x15 Character Display)
Row 12 Row 13 Row 14 Row 15 00 01 02 03 04 05 06 07 08 0910 11 12 13 14 15 16 Frame Control V-AMP Control Registers Registers Row Attribute Registers V-AMP Test Registers Test Registers 31
Figure 9. Memory Map of Display Registers
The display RAM's address of the row and column number are assigned in order. The display RAM is composed of 4 register groups (character & attribute register, row attribute register, frame control register, and V-AMP control register). The display area in the monitor screen is 30 column x 15 row, so the related character & attribute registers are also 30 column x 15 row. Each register has a character address and characteristics corresponding to the display location on the screen, and one register is composed of 16 bits. The lower 9 bits select the font from the 448 ROM fonts, and the upper 7 bits give font characteristics to the selected font. The row attribute register takes up the display RAM's 31st column. It provides raster color, raster color intensity, character color intensity, horizontal & vertical character size, box, border, and shadow features in units of row. The frame control registers are in the 16th row. It controls OSD's display location, character height, scroll, and fade-in/out in units of frame. The V-AMP control registers are also located in the 16th row.
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REGISTER DESCRIPTION
Character & Attribute Register: Row00 ~ 14, Column00 ~ 29 F E D C B A 9 8 7 6 5
BINV BOX1 BOX0 B G R Blink/Fint C8 C7 C6 C5
4
C4
3
C3
2
C2
1
C1
0
C0
Character Attribute
Character Code (448 fonts)
Row Attribute Register: Row00 ~ 14, Column30 F E D C B A 9 8 7 - BREN INTE CBil BOXE BORD SHA RB RG
6
RR
5
4
3
2
HZ0
1
VZ1
0
VZ0
RINT CINT HZ2
Raster Color Frame Control Register 0: Row15, Column00 F E D C B A 9 8 Fde FdeT VPOL HPOL Frame Control Register 1: Row15, Column01 F E D C B A 9 8
CP1 CP0 Fpll HF2 HF1 HF0 dot1 dot0
Intensity
Character Size
7 -
6
Erase
5
EN
4
Scrl
3
ScrT
2
Bli1
1
Bli0
0
BliT
7 -
6
5
4
CH4
3
CH3
2
CH2
1
CH1
0
CH0
FBLK CH5
PLL Control Frame Control Register 2: Row15, Column02 F E D C B A 9 8
HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0
Character Height Control
7
VP7
6
VP6
5
VP5
4
VP4
3
VP3
2
VP2
1
VP1
0
VP0
Horizontal Start Position
Vertical Start Position
V-AMP Control Register: Row15, Column03 ~ 15 Column03 F E D C B A 9 8 7 6 5 4 3 2 1 0 -VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Column04 F E Column05 F E Column06 F E Contrast Control D C B -A 9 8 7 6 5 4 3 2 1 0
BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRT0
Brightness Control D C B -A 9 8 7 6 5 4 3 2 1 0
RSB7 RSB6 RSB5 RSB4 RSB3 RSB2 RSB1 RSB0
R SUB Contrast Control D C B -A 9 8 7 6 5 4 3 2 1 0
GSB7 GSB6 GSB5 GSB4 GSB3 GSB2 GSB1 GSB0
G SUB Contrast Control
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V-AMP Control Register: Row15, Column03 ~ 15 Column07 F E Column08 F E Column09 F E Column10 F E Column11 F E Column12 F E Column13 F E Column14 F E Column15 F E D C B A 9 8 7 6 5 4 3 2 1 0
BSB7 BSB6 BSB5 BSB4 BSB3 BSB2 BSB1 BSB0
B SUB Control D C B A 9 8 7 6 5 4 3 2 1 0
OSD7 OSD6 OSD5 OSD4 OSD3 OSD2 OSD1 OSD0
OSD Contrast Control D C B A 9 8 7 6 5 4 3 2 1 0
RWB7 RWB6 RWB5 RWB4 RWB3 RWB2 RWB1 RWB0
R Cut-off Control D C B A 9 8 7 6 5 4 3 2 1 0
GWB7GWB6GWB5GWB4GWB3GWB2GWB1GWB0
G Cut-off Control D C B A 9 8 7 6 5 4 3 2 1 0
BWB7 BWB6 BWB5 BWB4 BWB3 BWB2 BWB1 BWB0
B Cut-off Control D C B A 9 8 7 6 5 4 3 2 1 0
CUT7 CUT6 CUT5 CUT4 CUT3 CUT2 CUT1 CUT
Cut-off Brightness Control D C B A 9 8 7
SB
6
HS6
5
HS5
4
HS4
3
HS3
2
HS2
1
HS1
0
HT
Half Tone & Soft Blank Control D C B A 9 8 7 6 5 4 3 2
-
1
CS2
0
CS1
CLPS CLPP BLKP BPW2 BPW1
Clamp, Polarity & Offset Control D C B A 9 8 7 6 5 4 3
TST
2
HS9
1
HS8
0
HS7
Half Tone Control
' - ' ; Don't care bit Figure 10. Register Description
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Table 11. Register Description Registers Character & Attribute Registers (Row 00 -- 14, Column 00 -- 29) Bits C8 -- C0 (Bit 8 -- 0) Blink/FINT (Bit 9) Description Character code address This is the address of 448 ROM fonts. Character blinking/font intensity If row attribute register's INTE bit is set to '1', this bit carries out the font intensity feature, and if not, the character blinking feature instead. In other words, to carry out character blinking, set the INTE bit to '0'. Select frame control register-0's BliT bit as blinking time, and select Bli1, Bli0 Bit as blinking duty. When giving intensity in units of font, refer to the table below.
Blink/FINT 0 0 1 1 1 1 INTE 0 1 0 1 1 1 RINT 0 1 1 CINT 1 0 1 Normal Normal Blink Character intensity Raster intensity Character & raster intensity Function
B, G, R (Bit C -- A) BOX1, BOX0 (Bit E, D)
Character color The character color is chosen from 16 colors using these 3 bits and the row attribute register's CINT bit. Character box drawing You can make 4 box drawing modes using these 2 bits in combination. The box drawings possible with font 'A' are shown below.
BOX0 BOX1
o
1
0
BOX OFF
A A
1
A
Refer to row attribute register's 'BOXE' bit. BINV (Bit F) Box inversion The white box turns black and black box turns white in the box drawing using BOX1, BOX0.
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Table 11. Register Description (Continued) Registers Row Attribute Registers (Row00--14, Column30) Bits VZ1, VZ0 (Bit 1, 0) Vertical character size control
VZ1 VZ0 Vertical Character Size
Description
0 0 1 1
0 1 0 1
1X (1 time) 2X (2 times) 3X (3 times) 4X (4 times)
As shown above, the vertical character size is decided by using these two bits in combination. HZ1, HZ0 (Bit 3, 2) Horizontal character size control
HZ1 HZ0 Horizontal Character Size
0 0 1 1
0 1 0 1
1X (1 time) 2X (2 times) 3X (3 times) 4X (4 times)
As shown above, the horizontal character size is decided by using these two bits in combination. However, unlike VZ, the surrounding area (row) is taken over in the amount of the HZ increase, so you must keep that in mind when changing font size. Refer to Character Size. CINT (Bit 4) Character color intensity When this bit is set to '1', the color intensity of the character on the same row becomes high. Refer to BLINK/FINT, INTE, RINT, and CINT's combination chart in the previous page. (Even if you change this bit, you can't check the intensity feature on the demo board. This is because the OSD IC's output INT is applied as the video Pre Amp's input, and the demo board doesn't apply the OSD IC's INT output to the Pre Amp.) Raster color intensity When this bit is set to '1', the color intensity of the raster on the same row becomes high. Refer to BLINK/FINT, INTE, RINT, and CINT's combination chart in the previous page. (Like CINT given above, you can't check RINT's feature on the demo board.)
RINT (Bit 5)
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Table 11. Register Description (Continued) Registers Row Attribute Registers (Row00 -- 14, Column30) Bits RB, RG, RR (Bit 8 -- 6) Description Raster color is determined by these bits The raster color is chosen from out of 16 colors using these 3 bits and the row attribute register's 'RINT' bit. If 'BOXE' Bit is not '1', the setting of these three bits have no meaning. Refer to 'BOXE' bit shown below. Character shadowing Character shadowing feature is carried out if you set this bit to '1'. Character bordering Character bordering feature is carried out if you set this bit to '1'. BOX enable If you set this bit to '1', it uses the character & attribute register's 'BINV', 'BOX1', and 'BOX0' bits to carry out box drawing, and if you set it to '0', the character & attribute register's bits F~D (BINV, BOX1, BOX0) act as each raster color's B, G, and R. This has higher priority than selection by setting RB, RG, and RR bits. In other words, if the BOXE bit is set to '0', the character & attribute register's BINV, BOX1, and BOX0 each do the function of RB, RG, and RR to decide the raster color, and the original row attribute register's RB, RG, and RR don't do anything. Color blink enable If this bit is '1', the color blinking effect is applied. Color blinking is instead of normal blinking, 8 colors appear in order in the font's character part. Its time and duty is controlled by 'BliT', 'Bli1', and 'Bli0', like in character blinking. Intensity enable Refer to the table on the combination of BLINK/FINT, INTE, RINT, and CINT bits in the explanation of the character & attribute register's BLINK/ FINT bit. Back raster enable If the BREN bit is '1' and the raster color is black, the raster is transparent. That is, the video back raster is shown. If not, the OSD raster covers the video's back raster. Refer to other color effect. Reserved
SHA BORD BOXE (Bit B)
CBli (Bit C)
INTE (Bit D)
BREN (Bit E)
Bit F
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Table 11. Register Description (Continued) Registers Frame Control Registers -- 0 (Row 15, Column 00) Bits BliT (Bit 0) Bli1, Bli0 (Bit 2 -- 1) Description Blink time control If this bit is '1', blink time is 0.5sec, and if not, 1sec. Blinking duty control As the font blinks, there is a time when it is visible and invisible on screen. Blinking duty is the ratio of the invisible time to the visible time, and is decided by the combination of these two bits. In other words, blinking duty is the length of time the font is shown on screen.
Bli1 Bli0 Blinking Duty
0 0 1 1 ScrT (Bit 3) Scrl (Bit 4)
0 1 0 1
Blink Off Duty 25% Duty 50% Duty 75%
Scroll time control If this bit is '1', scroll time is 0.5sec, and if not, 1sec. Scroll enable Scrolling effect is controlled by this bit. If this bit is `1', scrolling effect is enabled. You must remember that scrolling can be turned on/off only when OSD is enabled/disabled. OSD enable OSD is enabled when this bit is '1'. In other words, if this bit isn't '1'OSD is not output inspite of writing control data. We recommend that you enable the OSD after setting the control registers (such as the character & attribute register) because of video and OSD output timing. RAM erasing If this bit is '1', the RAM data (character & attribute registers and row attribute registers) is erased. The time spent in carrying out this operation is called erasing time, which can be calculated as follows. Erasing time = RAM clock x 480 (RAM cell no.) RAM clock = 12 dot clock Dot clock = 1/(dot frequency) Dot frequency = Horizontal frequency x resolution (mode) Therefore, the maximum erasing time value is: (Erasing Time)MAX = (12 x 480) / (15k x 320) = 1.2ms
EN (Bit 5)
Erase (Bit 6)
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Table 11. Register Description (Continued) Registers Frame Control Registers -- 0 (Row 15, Column 00) Bits HPOL (Bit B) VPOL (Bit C) FdeT (Bit D) Fde (Bit E) Description Polarity of horizontal fly back signal If this bit is '1', HFLB's polarity is positive, and if '0', it is negative. In other words, this bit is set to '1' if active high, and '0' if active low. Polarity of vertical fly back signal If this bit is '1', VFLB's polarity is positive, and if '0', it is negative. In other words, this bit is set to '1' if active high, and '0' if active low. Fade-in and fade-out time control If this bit is '1', fade-in/fade-out time is 0.5sec. If not, it is 1sec. Fade-in and fade-out enable This feature is enabled when this bit is '1'. The effect where the display goes from the center to the outside, or from the outside to the center in units of font, is called fade-in/fade-out. Refer to fade-in/fade-out. You must remember that fade-in/fade-out, like scrolling on/off, only occurs when OSD enabled/disabled. Reserved.
Bit F
The purpose of bits 'HPOL', and 'VPOL' is to provide flexibility when using the S1D2502A01 IC. No matter which polarity you choose for the input signal, the IC will handle them identically, so you can select active high or active low according to your convenience.
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Tabel 4. Register Description (Continued) Registers Frame Control Registers -- 1 (Row 15, Column 01) Bits CH5 -- CH0 (bit 5 -- 0) Description Character height control While the purpose of VZ[1:0] (vertical character height) is to control the absolute size of the character, the purpose of CH[5:0] (Character Height) is to output OSD of a uniform size even if the resolution changes. If you adjust the value in the range of CH = 18 -- CH = 63, each line's repeating number is decided (standard height CH = 18 is the reference value), by which the line is repeated. For more information on repeating number selection, refer to character height. Selection of the FBLK output pin's configuration Unlike pin description's FBLK, if this bit is '0', the FBLK pin output is high while the character and raster are being displayed and the character and raster are output as they are. If this bit is '1', the FBLK pin output becomes high only when character is being displayed, so only the character is output. Refer to 'Figure 11. Character/raster signal part. Resolution control (dots/line)
Dot1 Dot0 No. of Dots
FBLK (bit 6)
dot1, dot0 (bit 9, 8)
0 0 1 1
0 1 0 1
320 dots/line 480 dots/line 640 dots/line 800 dots/line
As shown above, the number of dots per horizontal line is decided by a combination of these two bits. HF2--HF0 (bit C -- A) Horizontal frequency PLL's horizontal frequency is decided by the combination of these 3 bits. This is related to the selection of DOT[1:0], so you can't numerically express the frequency range with only the HF[2:0] selection. For more information, please refer to HF Bits Selection. Full range PLL If this bit is '1', the OSD_PLL block's VCO operates at full range (4.8MHz 96MHz). If it is '0', it operates within the region decided by the HF bit [C:A] explained above. if you can't optimize OSD screen decided by the HF bit in the high region, you may set the FPLL bit to `1'.
FPLL (bit D)
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Tabel 4. Register Description (Continued) Registers Frame Control Registers -- 1 (Row 15, Column 01) Bits CP1, CP0 Description Charge pump output current control This is the PLL block's internal phase detector output status, converted into current. Refer to PLL control.
CP1 CP0 Charge Pump Current
0 0 1 1
0 1 0 1
0.50 mA 0.75 mA 1.00 mA 1.25 mA
The output is decided by the combination of these two bits.
FBLK bit setting is explained at the figure below.
Character
Blue
Red
Raster
Raster Blue Bordering Red Character Green
Figure 11. Character/Raster Signal Part
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Tabel 4. Register Description (Continued) Registers Frame Control Registers -- 2 (Row 15, Column 02) V-AMP Control Registers -- 0 (Row 15, Column 03) V-AMP Control Registers -- 1 (Row 15, Column 04) V-AMP Control Registers -- 2 (Row 15, Column 05) V-AMP Control Registers - 3 (Row 15, Column 06) V-AMP Control Registers - 4 (Row 15, Column 07) V-AMP Control Registers - 5 (Row 15, Column 08) V-AMP Control Registers - 6 (Row 15, Column 09) V-AMP Control Registers - 7 (Row 15, Column 10) Bits VP7 -- VP0 HP7 -- HP0 Description Vertical start position control ( = VP[7:0] x 4) Signifies top margin height from the V-Sync reference edge. Horizontal start position control ( = HP[7:0] x 6) Signifies delay of the horizontal display from the H-Sync reference edge to the character's 1st pixel location. The contrast adjustment is made by contrdling simultaneously the gain of three internal variable gain amplifiers. The contrast adjustment allows to cover a typical range of 38dB. The brightness adjustment controls to add the same black level (pedestal) to the 3-channel R/G/B signals after contrast amplifier.
VC7 -- VC0 (bit7 -- 0)
BRT7 -- BRT0 (bit7 -- 0)
RSB7 -- RSB0 (bit7 -- 0)
R channel SUB contrast control. The SUB contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. The SUB contrast adjustment allows you to cover a typical tange of 12dB. G channel SUB contrast control. The SUB contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. The SUB contrast adjustment allows you to cover a typical tange of 12dB. B channel SUB contrast control. The SUB contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. The SUB contrast adjustment allows you to cover a typical tange of 12dB. The OSD contrast adjustment is made by contrdling simultaneously the gain of three internal variable gain amplifiers. The OSD contrast adjustment allows to cover a typical range of 38dB. R channel cut-off control. The cut-off adjustment is used to adjust the raster white balance.
GSB7 -- GSB0 (bit7 -- 0)
BSB7 -- BSB0 (bit7 -- 0)
OSD7 -- OSD0 (bit7 -- 0)
RWB7 -- RWB0 (bit7 -- 0)
GWB7 -- GWB0 (bit7 -- 0)
G channel cut-off control. The cut-off adjustment is used to adjust the raster white balance.
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Tabel 4. Register Description (Continued) Registers V-AMP Control Registers - 8 (Row 15, Column 11) V-AMP Control Registers - 9 (Row 15, Column 12) V-AMP Control Registers - 10 (Row 15, Column 13) Bits BWB7 -- BWB0 (bit7 -- 0) Description B channel cut-off control. The cut-off adjustment B used to adjust the raster white balance.
CUT7 -- CUT0 (bit7 -- 0)
The cut-off brightness adjustment is made by simultaneously controlling the external cut-off current.
HT (bit 0) HS3 -- HS1 (bit3 -- 1)
Video & OSD half tone enable. If you set this bit to '1', the half tone function is on. Then you can see the video signal & OSD raster. HS3 -- HS1 bits select OSD raster color 1 to be half tone. To carry out half tone function, set the HT bit to '1'. HS3 0 0 0 0 1 1 1 1 HS2 0 0 1 1 0 0 1 1 HS1 0 1 0 1 0 1 0 1 OSD G 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Raster Color 1 Black Blue Red Magenta Green Cyan Yellow White POR O
HS6 -- HS4 (bit6 -- 4)
HS6 -- HS4 bits select OSD raster color 2 to be half tone. To carry out half tone function, set the HT bit to '1'. HS6 0 0 0 0 1 1 1 1 HS5 0 0 1 1 0 0 1 1 HS4 0 1 0 1 0 1 0 1 OSD G 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Raster Color 2 Black Blue Red Magenta Green Cyan Yellow White POR O
SB (bit 7)
Soft blanking enable If you set this bit '1', the R/G/B outputs go to GND.
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Tabel 4. Register Description (Continued) Registers V-AMP Control Registers - 11 (Row 15, Column 14) Bits CS2 -- CS1 (bit1 -- bit0) Cut-off offset current control CS2 0 0 1 1 BPW2 -- BPW1 (bit4 -- bit3) CS1 0 1 0 1 Cut-off Offset Current 0 50A 100A 150A POR O Description
Generated clamp pulse width control BPW2 0 0 1 1 BPW1 0 1 0 1 Width 0.33s 0.66s 1.00s 1.33s O POR
To carry out this function, set the CLPS bit to " 0 " BLKP (bit 5) CLPP (bit 6) CLPS (bit 7) Polarity of horizontral fly back signal If this bit is '0', HFLB's polarity is negative, and if '1', it is positive. Polarity of clamp pulse signal If this bit is '0', CLP's polarity is positive, and if '1', it is negative. This bit has meaning only if the CLPS bit is set to '1'. Clamp pulse generation enable If this bit is '0', clamp signal is made using the HFLB signal, so there is no need to supply the clamp signal. and if '1' you must supply external clamp signal. HS9 -- HS7 bits select OSD raster color 3 to be half tone. To carry out half tone function, set the HT bit to " 1 ". HS9 0 0 0 0 1 1 1 1 HS8 0 0 1 1 0 0 1 1 HS7 0 1 0 1 0 1 0 1 OSD G 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Raster Color 3 Black Blue Red Magenta Green Cyan Yellow White POR O
V-AMP Control Registers - 12 (Row 15, Column 15)
HS9 -- HS7 (bit2 -- bit 0)
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VIDEO AMP PART ADDRESS MAP Register sub address (use limited to 1byte out of 2bytes) Table 12. Video AMP Part Address Map SUB Address [Hex] 0F03 0F04 0F05 0F06 0F07 0F08 0F09 0F0A 0F0B 0F0C 0F0D 0F0E 0F0F SB CLPS HS6 CLPP HS5 BLKP Function D7 D6 D5 D4 D3 D2 D1 D0 Contrast control Brightness control SUB contrast control (R) SUB contrast control (G) SUB contrast control (B) OSD contrast control Cut-off control (R) Cut-off control (G) Cut-off control (B) Cut-off brightness control HS4 BPW2 HS3 BPW1 TST HS2 HS9 HS1 CS2 HS8 HT CS1 HS7 POR Value [Hex] 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 00H 10H 00H
In normal status, you must set TST bit to '0'.
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Contrast Register (SUB ADRS: 03H) (Vin = 0.7Vpp, bright: 80H, subcont: FFH) Hex 00 80 FF
B7
0 1 1
B6
0 0 1
B5
0 0 1
B4
0 0 1
B3
0 0 1
B2
0 0 1
B1
0 0 1
B0
0 0 1
Contrast (Vpp) 0 2.85 5.2 0.0223
Gain (dB) -
int. Value (Hex) O
Increment/bit
Brightness Register (3-ch) (SUB ADRS: 04H) (cont: 80H, subcont: 80H) Hex 00 80 FF B7 0 1 1 B6 0 0 1 B5 0 0 1 B4 0 0 1 B3 0 0 1 B2 0 0 1 B1 0 0 1 B0 0 0 1 Brightness (Vpp) 0.2 1.5 2.7 0.01055 O Int. Value (Hex)
Increment/bit
SUB Contrast Register (R/G/B-ch) (SUB ADRS: 05/06/07H) (Vin = 0.7Vpp, bright: 40H, cont: FFH) Hex 00 80 FF B7 0 1 1 B6 0 0 1 B5 0 0 1 B4 0 0 1 B3 0 0 1 B2 0 0 1 B1 0 0 1 B0 0 0 1 SUB Contrast (Vpp) Gain (dB) O Int. Value (Hex)
Increment/bit
OSD Contrast Register (SUB ADRS: 08H) (VOSD = TTL, bright: 80H, subcont: 80H) Hex 00 80 FF B7 0 1 1 B6 0 0 1 B5 0 0 1 B4 0 0 1 B3 0 0 1 B2 0 0 1 B1 0 0 1 B0 0 0 1 OSD Contrast (Vpp) 0 3.2 6.4 0.025 Gain (dB) O Int. Value (Hex)
Increment/bit
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Cut-Off Brightness Register (3-ch) (SUB ADRS: 0CH) Hex 00 80 FF B7 0 1 1 B6 0 0 1 B5 0 0 1 B4 0 0 1 B3 0 0 1 B2 0 0 1 B1 0 0 1 B0 0 0 1 Cut-Off Brightness (A) 0 100 200 0.781 O Int. Value (Hex)
Increment/bit
Cut-Off Register (R/G/B-ch) (SUB ADRS: 09/0A/0BH) (cont = 80H, subcont: 80H) Hex 00 80 FF B7 0 1 1 B6 0 0 1 B5 0 0 1 B4 0 0 1 B3 0 0 1 B2 0 0 1 B1 0 0 1 B0 0 0 1 Cut-Off EXT (A) 0 300 600 2.344 O Int. Value (Hex)
Increment/bit
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ADDRESSING * Display RAM Structure
Row Attribute Register Display RAM Address Area Row 0 1 2 3 . . . . 14 15 0 32 64 96 . . . . 448 . . . . . . . . . . . . . . 29 61 93 30 62 94 31 63 95 Virtual Register
125 126 127 . . . . . . . . . . . .
477 478 479 511
480 481 482 483 484 ... 495 496 Frame/V-AMP Control Registers
Figure 12. Display RAM Structure & Monitor Display Position
Whereas `Figure 9. Memory Map of Display Registers' showed a logical configuration, the Figure above shows a 1KByte SRAM (512 x 16 bit)'s practical and physical configuration. For facilitating internal calculations, addressing is done using exponents of 2, and the rows to the right of the 'Row Attribute Registers', excepting only IFF(255), are 'Virtual Registers' that are not used. If you set 'Frame Control Register 0's 'Erase' bit to '1', 480 areas are erased (excepting only the 16th line) in the Figure above, and the 'Erasing Time' is measured with 480 areas as the standard.
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*
ROM Fonts S1D2502A01 provides 448 Rom fonts for displaying OSD Icons, which allows the use of multi-language OSD Icons. Font $000 is reserved for blank data.
0
1
E
F
00
$000
$001
$00E
$00F
01
$010
$011
$01E
$01F
Standard Fonts
1A
$1A0
$1A1
$1AE
$1AF
1B
$1B0
$1B1
$1BE
$1BF
1C
$1C0
$1C1
$1CE
$1CF
Multi Color
Figure 13. Composition of the ROM Fonts
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COLORING If you have an Intensity feature, the number of possible colors you can express becomes doubled. In other words, the number of colors you can represent with three colors blue, green, and red is 8 ( = 23), but with the intensity feature, it is 16 ( = 24). * Character Color Character color is assinged for each font, and the 4 components for expressing a color are listed below. Blue Green Red Intensity Character & attribute register's B bit[C] Character & attribute register's G bit[B] Character & attribute register's R bit[A] Character & attribute register's BLINK/FINT bit[9] Row attribute register's INTE bit[D] Row attribute register's CINT bit[4] If all 3 bits are set to '1', the character intensity feature is enabled.
*
Raster Color Blue Green Red Row attribute register's RB bit[8] if the row attribute register's 'BOXE' bit is '1', and character & attribute register's 'BINV' bit[F] if BOXE' bit is '0'. Row attribute register's RG bit[7] if row attribute register's 'BOXE' Bit is '1', and character & attribute register's 'BOX1' bit[E] if 'BOXE' bit is '0'. Row attribute register's RR bit[6] if row attribute register's 'BOXE' bit is '1', and character & attribute register's 'BOX0' bit[D] if 'BOXE' bit is '0'. Character & attribute register's BLINK/FINT bit[9] Row attribute register's INTE bit[D] Row attribute register's RINT bit[5] If all 3 bits are set to '1', the raster intensity feature is enabled.
Intensity
According to the 'BOXE' bit setting, raster color can be assigned in units of font or row. There is a trade-off in either case. If 'BOXE' Bit is set to '1', the box drawing feature can be carried out in units of font, but the raster color can only be assigned in units of row. On the other hand, if 'BOXE' bit is set to '0', the box drawing feature can't be carried out, but you can assign raster color in units of font. Notes for When Making S1D2502A01 Fonts Address 000h is appointed as blank data. RAM's initial values are all 0, and all bits are written as 0 when you erase the RAM, so blank data means the initial value. In other words, blank data means 'do nothing'. You don't need to write any data for the space font, except for 000h. It just needs to be an undotted area.
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*
Other Color Effet The row attribute register's 'BREN' bit's function is shown in the Figure below. If you set the 'BREN' bit of the row with the letter A as '0' after selecting A and B's raster color as black, the raster color black will be displayed. But if you set the 'BREN' bit of the row with the letter B as '1', the raster color black becomes invisible, so the back raster color (gray) is displayed as if it is the raster color.
BREN bit = 0 & Rastor Color = Black Gray
BREN bit = 1 & Rastor Color = Black
BREN bit = 1 & Rastor Color = Light Blue
Figure 14. Color Effect by BREN Bit Color blinking is using a selective control bit in blink mode to replace normal blinking with 8 different colors appearing in order on the font's character. Color blinking only replaces normal blinking, and blink time and blink duty are still applied at the same time. Therefore, if the blink duty is not set to off, only 3 ~ 4 colors may appear according to the blink duty, instead of all 8.
SIZING/POSITIONING * Character Size Row attribute register's HZ bit[3:2] and VZ bit[1:0] control the character's vertical and horizontal size by factors of 1/2/3/4 in units of row. VZ is correctly expressed without regard to size since the next line is just pushed down in order, but HZ decides the column that the font occupies according to the size. For example, if HZ [1:0] = 0, 1, the font doubles in the horizontal direction, and one font takes up 2 columns. Therefore, the column address must move in the same amount as the HZ for the next font to be expressed correctly. in other words, if the horizontal size is doubled and takes up 2 columns, the next font must be put 2 columns back.
Original
HZ x 2 VZ x 2
Figure 15. Character Size by VZ, HZ Bits
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
*
Character Height Whereas the purpose of VZ[1:0] (Vertical Character Height) is to adjust the character's absolute size, the purpose of CH[5:0] (Character Height) is to output a uniformly sized OSD even if the resolution changes. To express a Character Height of CH = 18 ~ CH = 63 after receiving CH[5:0]'s input from the frame control register-1, decide on each line's repeating number (Standard Height CH = 18) and repeat the lines. The following Figure shows two examples of a height-controlled character. height control is carried out by repeating some of the lines.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
: added line
Standard Font(12*18)
Standard font in high vertical resolution
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Height-controlled font
: added line
Standard Font(12*18)
Standard font in more higher vertical resolution
Height-controlled font
Figure 16. Character Height
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S1D2502A01
Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Repeating line-number can be found by the following formula. [# of the repeating lines = 2 + N x M], where N = 1, 2, 3, ... and M = round{14 / (CH[5:0]-18)}. 1. If CH[5:0] is greater than 32 and less than or equal to 46 (32 < CH[5:0] 46), all lines are repeated once or twice. The lines that are repeated twice are chosen by the following formula. [# of the repeating lines = 2 + N x M], where N = 1, 2, 3, ... and M = round {14 (CH[5:0]-32)}. 2. If CH[5:0] is greater than 46 and less than or equal to 60 (46 < CH[5:0] 60), all lines are repeated two or three times. The lines that are repeated three times are chosen by the following formula. [# of the repeating lines = 2 + N x M], where N = 1, 2, 3, ... and M = round {14 (CH[5:0]-46)}. 3. If CH[5:0] is greater than 60 and less than or equal to 64 (60 < CH[5:0] 64), all Lines are repeated three or four times. The lines that are repeated four times are chosen by the following formula. [# of the repeating lines = 2 + N x M], where N = 1, 2, 3, ... and M = round {14 (CH[5:0]-60)}. CH's reference value is 18, and even if you input 0, it operates in the same way as when CH = 18. The repeating line-number is limited to 16. If the M value is less than or equal to 1, all lines of the standard font are repeated more than once. Table 13. Repeating Line as Controlling by CH bits Character Height CH = 18 CH = 19 CH = 20, 21 CH = 22 CH = 23 CH = 24 CH = 25, 26, 27 CH = 28 CH = 29 CH = 30 CH = 31 CH = 32, 33, 34, 35 CH = 36 CH = 37 9 6, 13 5, 11, 17 4, 9, 14, 19 3, 7, 11, 15, 19, 21 3, 7, 11, 13, 15, 19, 22 3, 6, 9, 12, 14, 18, 20, 23, 25 3, 6, 9, 11, 13, 15, 18, 21, 23, 25, 26 3, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 27 2, 5, 7, 9, 11, 13, 15, 17, 21, 23, 25, 27, 28 2, 5, 7, 9, 11, 13, 15, 18, 21, 23, 25, 27, 28, 29 18 Repeating Line
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
Table 13. Repeating Line as Controlling by CH bits Character Height CH = 38, 39 CH = 40 CH = 41 CH = 42 CH = 43, 44, 45 CH = 46 CH = 47 CH = 48 CH = 49 CH = 50, 51, 52, 53 CH = 54 CH = 55 CH = 56, 57 CH = 58 CH = 59 CH = 60 CH = 61, 62, 63 12, 25 10, 20, 30 8, 16, 24, 32 6, 12, 18, 24, 30, 36 6, 12, 18, 24, 30, 36, 41 4, 8, 12, 17, 21, 25, 29, 33, 37, 41 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44 4, 8, 12, 16, 20, 23, 26, 29, 33, 37, 41, 45 4, 8, 12, 16, 19, 22, 25, 28, 31, 35, 39, 43, 47 4, 8, 12, 15, 18, 21, 24, 27, 30, 33, 36, 40, 44, 48 27 18, 36 14, 28, 42 12, 23, 34, 45 9, 18, 26, 34, 43, 52 8, 16, 23, 30, 37, 44, 51 Repeating Line (Continued)
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S1D2502A01
Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
*
Positioning The frame control register-2's HP Bit [F:8] signifies delay of the horizontal display from the H-Sync reference edge to the character's 1st pixel location, and is controlled by multiplying HP [F:8]'s range value by 6. Also, VP bit[7:0] signifies the top margin height from the V-Sync reference edge, and is controlled by multiplying 4 to the VP [7:0]'s range value. Refer to the Figure shown below.
(HFLB) HP[7:0] VP[7:0]
OSD characters 30 columns (= 30 x 12 dots)
15 rows (=15 x 18 lines)
Background Screen (VFLB)
Figure 17. Frame Composition with the OSD Characters
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
VISUAL EFFECTS * Box Drawing Set the row attribute register's boxe bit to '1' and enable the box feature. Then set the character & attribute register's BOX bit to select one of 4 modes. Or, use the character & attribute register's BINV bit to inverse the white and black areas of the box mode selected by the BOX bit.
BOX0 BOX1
o
1
0
BOX OFF
A A
1
A
Figure 18. Box Drawing
The principle behind the boxing feature is shown below.
HDOT0 DOTLINE_ H DOTLINE_ H DOTLINE_ H
HDOT11
DOTLINE_ H
DOTLINE_ H
DOTLINE_ H
17
17
17
0
0
0
BOX<1:0> 01
BOX<1:0> 10
BOX<1:0> 11
Out of the 12 horizontal dots and 18 vertical lines that make 1 character, make the first and 12th horizontal dots to HDOT0/HDOT11, and the first and 18th vertical lines to DOTLINE-0H/DOTLINE-17H in order to carry out box drawing for 1 dot outside the character.
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
*
Bordering/Shadowing The character border and shadow can only be black. Character border is the effect where you make 1 pixel around the character, and character shadow is making 1 pixel to the right and below the character.
Bordering
Shadowing
Figure 19. Character Bordering/Shdowing
*
Scrolling Scrolling is slowly displaying or erasing a character from the top line to the bottom. This effect makes it look as if 1 character line is scrolling up or down.
Figure 20. Scrolling
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
*
Fade-In/Fade-Out Fade-in/fade-out is displaying from the center to the outside in units of font when OSD display is on/off. Each font's display is turned on/of without regard to size, in units of (12 x 18) dot. Also, to control the fade in/out time, the V_PULSE's 1/4, 1/8 clocks are used for counting. In other words, as control data, it takes 0.5sec if the frame control register - 0's 'FdeT' bit is 1, and 1sec if 0. If it is difficult to visualize the fade-in / fade-out feature with the explanation and diagrams in this document, write the control data to the OSD IC and verify the IC's operations. Like the scrolling feature, fade in/out can only be verified when OSD is enabled/disabled.
Fade in/out Unit: Font
6CK_Time
6CK_Time + 3CK_Time Display at 9CK_Time
row Space
Figure 21. Fade-In/Fade-Out
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
PLL CONTROL * Introduction PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a reference signal and an oscillator output signal. Generally, PLL is composed as follow Figure.
Reference Signal PFD (Phase Frequency Detector) LF (Loop Filter) VCO (Voltage Controlled Oscillator)
FD (Frequency Detector)
Figure 22. Block Diagram of General PLL
- PFD (Phase Frequency Detector) PFD compares the phase of the VCO output frequency, with the phase of a reference signal frequency output pulse is generated in proportion to that phase difference. - LF (Loop Filter) LF smooths the output pulse of the phase detector and the resulting DC component is the VCO input. - VCO (Voltage Controlled Oscillator) VCO is controlled by loop filter output. The output of the VCO is fed back to the phase frequency detector input for comparison which in turn controls the VCO oscillating frequency to minimize the phase difference. - FD (Frequency Divider) FD divides too much different frequency that is oscillated from the VCO to compare it with reference signal frequency.
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
*
PLL of the S1D2502A01 PLL is composed of the phase detector, charge pump, VCO, and N-divider as 4 sub-blocks.
Loop Filter CP_out (Pin4)
# Composed of External Components VCO_in (Pin3)
HFLB (Pin32)
Phase Detector
Charge Pump
VCO
VCO_out
Div_out N-Divider
CP0
CP1
DOT0
DOT1
HF0 HF1 HF2
Figure 23. Block Diagram of the PLL Built in S1D2502A01
The following is the description of the input/output signals. - HFLB (Input) Horizontal flyback signal is refrence signal of the PLL built in S1D2502A01. The HFLB signal's frequency range is 15 ~ 90kHz, so the PLL block must be a wide range PLL that can cover HFLB's entire frequency range.
> 4.2V fHFLB ~2us < 0.4V
- VCO (Input) Error signal that passes through an external loop filter is input into VCO. Operation voltage range is 1-4V. You can raise immunity towards external noise by lowering VCO sensitivity. You can do this by making it have the maximum operation voltage range possible in the 5V power voltage.
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
- DOT0, 1 (Input) Mode control signal that controls the number of dots per line in the frame control register. There are 4 modes: 320, 480, 640, and 800 dots/line. According to your choice of mode, the OSD_PLL block's N-Divider is controlled by one of /320, /480, /640, or /800 Divider. - HF0, 1, 2 (Input) The horizontal Sync frequency information is received from the micro controller through the frame control registers-1's bit C-A. - CP0, 1 (Input) Charge Pump's output sourcing (or sinking) current control pin. This control data is received through frame control registers-1's bits E-D. - VCO_OUT (Output) VCO output that becomes a system clock. It is the OSD R, G, B output signal's dot frequency, and the standard signal for OSD's various timings. Also, it is input into the N-Divider and makes a PLL loop
> 4.2V < 0.4V fclk Rise Time : < 4nS Fall Time : < 4nS
- CP_OUT (Output) Charge Pump circuit's output. input into external loop filter. It becomes one of 3 states according to the standard signal input into the phase detector (HFLB) and the divider output (Div_Out). - HFLB Div_Out is lead: Current sink - HFLB Lag: Current source - HFLB In-Phase: High impedence
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
TUNNING FACTORS OF THE S1D2502A01 PLL * PLL External Circuit You may follow the recommendations for PCB art work and input/output signal characteristic improvement in recommendation. The external circuit that has the most influence on S1D2502A01 PLL block operation is pin 3 (VCO_IN) and pin 4 (CP_OUT)'s surrounding circuit. Refer to OSD PLL block.
3
4
C1
R1
R3
(option)
R2
Figure 24. PLL External Circuit
Because the PLL circuit is basically a feedback circuit, there are many components that influence the characteristics. C1, R1, R2, and R3 do not have a localized effect. As you can see, they are connected to the PLL control bits and influence the characteristics through their complicated relationships. The main functions of the time canstant and their reference values are as follows. Table 14. Main Function of Time Constant in PLL External Circuit Time Canstant C1 R1 R2 R3 (Option) Recommended Value 562 (or 103, 223) 5.6K(7.5K) 27K (or 33K) 30M (or 20M) Main Function Influences the damping ratio and controls the PLL response time Same as C1 Charge pump current adjustment Extend frequency range
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S1D2502A01
Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
*
PLL Control Bit After configuring an external circuit using the recommended values, carry out programming using the recommended values for frequency range and control bits given in the Table below. Table 15. Recommend Values of PLL Control Bit Register Set Freq. Range Below 40kHz 40 - 50kHz 50 - 70kHz Above 70kHz CP1 0 1 1 1 CP0 0 0 0 0 FPLL 0 0 0 0 PLL Control Bit HF2 0 1 1 1 HF1 1 0 0 1 HF0 0 0 1 1 DOT1 1 1 1 1 DOT0 1 1 1 1 Hex 0B 93 97 9F
(Ref: 800 x 600, C1: 562, R1: 5.6K, R2: 27K, R3: 30M) * Locking Range As you can see the figure below, it is 2.35V that measured voltage at pin-3 to optimize OSD quality. The proper voltage range is 1.5 ~ 3.25V.
Locking Range 4V 3.25V fmax Ve (max)
1.625V
2.37V 1.625V 1.5V Ve (min) f0 -2 0.75V fC fL 2
Figure 25. Locking Range
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
*
HF Bits Selection HF bits is not selecting from out of 8 (23) steps uniformly, but selecting the step shown in figure below. In example, at 800 mode, there are 5 steps that the frequency range is controlled by HF bits. Table 16. HF Bits Selection DIV 320 DOT1 0 DOT0 0 HF2 HF1 HF0
480
0
1
640
1
0
800
1
1
After fixing time constants of the external circuit and PLL control bits except HF bits, if HF bits are stepped up, the voltage measured at pin-3 drops. On the contrary, if HF bits are stepped down, the voltage rises. The voltage measured at pin-3 don't change by changing CP bits.
*
External Register at pin-4
The external register at pin-4 is the factor that changes greatly at PLL tunning. The initial value of this external register value is decided as follows. At first, the external register is replaced variable-register (about 50K range). and then, set the lowest PLL control bits at the lowest frequency allowed by set. and then, change variable-register to be 2.35V that optimum voltage is locking. and then, measure register value at this time. also, set the highest PLL control bits at the highest frequency allowed by set. and then, change variable-register to be 2.35V that optimum voltage is locking. and then, measure register value at this time. You may decide the average of these two registers' value to initial value.
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
The table below shows that other factors change as changing external register's value. Fixing Factor Time constants of the external circuit and PLL control bits except Variable Factor Rext Change Voltage Current Lock Range (shift) (shift)
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
RECOMMENDATION
5V Power Routing S1D2502A01's OSD part power is composed of analog VDD and digital VDD. To eliminate clock noise influence in the digital block, you need to separate the analog VDDA and digital VDD. (BD102 use: Refer to Application Circuit ) 12V Power Routing Because S1D2502A01 is a wideband AMP of above 150MHz, 12V power significantly affects the video characteristics. The effects from the inductance and capacitance are different for each board, and , therefore, some tuning is required to obtain the optimum performance. The output power, VCC2, must be separated from VCC1 and VCC3 using a coil, which is parallel-connected to the damping resistor.The appropriate coil value is between 20uH - 200uH. Parallel-connected a variable resistor to the coil and control its resistance to obtain the optimum video waveform. (Moreover, BD103 can tune using a coil and variable resistor to obtain the optimum video waveform. L103, R124, BD103: Refer to application circuit) VCC1, VCC3 12V Power Use a 104 capacitor and large capacitor greater than 470uH for the power filter capacitor. 12V Output Stage Power VCC2 Do not use the power filter capacitor. 5V Digital Power VDD Don't use a coil or magnetic core to the VDD input. Make the power filter capacitor, an electric capacitor of greater than 50uF, single and connect it to VSS, the digital GND. Output Stage GND2 Care must be taken during routing because it ,as an AMP output stage GND, is an important factor of video oscillation. R/G/B clamp cap and R/G/B load resistor must be placed as close as possible to the GND2 pin. GND2 must be arranged so that it has the minimum GND loop, which at one point must be connected to the main GND. Digital GND VSS When this is to be connected directly to the GND2, it can cause the OSD clock noise, so the loop connection should be routed as far away as possible. If the OSD clock noise affects the screen, separate VSS GND from all GND and connect it to the main board using a bead. Again, the bead connection point should be placed as far away as possible to the GND2. Analog Block The PLL built in to S1D2502A01 is sensitive to noise due to the wide range PLL characteristics. Therefore, you need to isolate the analog block in the following manner. First make a separate land for the analog block (pin2 pin6)'s ground, and connect it to the main ground through a 1M resistor. The analog GND of both sides of a double faced PCB must be separated from the main ground. (Separate pin 2's 5V analog GND, which is the GND for OSD PLL, from the main and digital GNDs and connect it to the main GND using about 1M resistor. GND for pins 2 - 6 is the No. 2 VSSA GND.)
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
I2C Control Line (SCL, SDA Line) I2C communication noise (noise generated in the OSD display pattern when data is transmitted in the I2C line) may be generated because of an I2C control line that passes near the analog block. The I2C control lines near S1D2502A01 must be separated from the analog block as much as possible. Furthermore, the I2C bus interference can be prevented by inserting a series resistor in the line. Horizontal Flyback Signal Display jittering can be generated if the horizontal signal (HFLB) input to S1D2502A01 is not a clean signal. We recommend a short path and shielded cable for obtaining a clean signal. Generally, the input horizontal signal (HFLB) is generated by using a high voltage horizontal flyback signal. The effect from the high voltage flyback signal can be reduced by separating the R115 and R117 GND, which determines the flyback signal slice level, from the transistor GND, which generates the actual S1D2502A01 input horizontal signal. Furthermore, the flyback signal sharpness must be maintained by minimizing the values of R115, R116 and R117 resistors, which set the horizontal signal slice level. values. (R115, R116, R117: Refer to application circuit ) HFLB Input Signal Generator You can correct the circuit by reducing the resistors that sets the slice level of the horizontal signal in the HFLBgenerating circuit.
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Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
APPLICATION BOARD CIRCUIT
CN2
CN1
R101 4.7K R102 C119 102 100
1uF
1uF
R103 390
SK101
WSP-401M GOUT ROUT GND2 BCLP BOUT GCLP VCC2 RCLP
C126 C117 1nF C116 1nF 1.8nF
R117 150
C118 330pF R116
R118 R119 560 560 C160 47uF
D102 1N4148
10K
R115 2K
1
3
Q102 2N3904 CB02 104 CG02 104 CR02 104
RG03 RB03 470 RB15 47 RG15 47 470
RR03 470 RR15 47
RB04 CB08 100 270pF
RG04 CG08 100 270pF
RR04 CR08 100 270pF
RB11 100 RB20 4.7K RG20 4.7K
RG11 100 RR20 4.7K
RR11 100 C106 104
2
QB01 2N5551C-Y
2
QG01 2N5551C-Y
2
C107 QR01 220uF 2N5551C-Y
CB05 104
CG05 104
CR05 104 RR08 RG08 RB08 CR07 56 CG07 56 CB07 56 37pF 37pF 37pF RR14 75 RG14 75 RB14 75
CB05 104 RB12 2.2K
CG05 104 RG12 2.2K
CR05 104 RR12 2.2K
LR01 0.15uH 3 2 1SS244
RR13 82K
LG01 0.15uH
LB01 0.15uH DB03
QB02 2N5401C-Y
2
QG02 2N5401C-Y
2
QR02 2N5401C-Y
DB04 DG03 DG04 DR03 DR04 1SS244
CB04 1uF RR09 RG09 RB09 75K 75K 75K
RB13 82K
RG13 82K
1SS244 VDD 1SS244
1SS244
DB05 1N4148
DG05 1N4148
DR05 1N4148
+
CR04 1uF
+
CG04 1uF
+
R104 390
SK102 DMS-200D DMS-200D
C120 1nF
SKB01 SKG01 DMS-200D SKR01 DMS-200D G2
RR10 39
RG10 39
RB10 39
Figure 26. Application Board Circuit
+
14 2
13
12 5V
11 3 1
10
9 1 3
8
7
6 G1
5 3 1
4 1 3
3
2
1
C123 103
6 1N4148 1N4148 1N4148
5
4
3
2
1 DR01 DG01 DB01 1N4148
C114 103
DR02 70V 6.3V DG02 DB02
1N4148 12V 1N4148
R123 1M C109 103
C124 103 RB01 75 RB02 75 RG01 75 RG02 75 RR01 75
C110 C111
L101
100uH
+
+
RR02 75
R107 1K C102 CB02 104 CG02 104 CR01 104 C112 R109 27K R120 30M C113 562 R108 5.6K
12V BIN 12V +
4.7uF
100uF
BD102
5V
+
12_1V
16 17
15 GND1 18
14 GIN 19
13 VCC1 20
12 RIN 21 ROUT
11 VCC3 22 8 VBB GOUT 6 BIN BOUT
10 CLP_IN 23 7 GIN VCC
9 GND 24 9 RIN GND DRIVER IC
8 ABL_IN BCT 25
7 CONT_CAP
6 VDDA
5 VREF
4 VREF1
3 VCO_IN
2 VSSA
1
C152
VFLB
104
KB2502
470uF
C103 BD103
+
HFLB
GCT 26
VDD
RR04 CR08 100 270pF
RCT 27
VSS 28
104
C121
C108 47uF
SCL 29
L103
SDA 30 +
R124
C151
32
220
27uH
R114 470
31
104 C128 104
12V 5V
1 3
+
5
3
1
2
4
70V
1 G2
1SS244
B_OUT
R_OUT
G_OUT
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S1D2502A01
Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
TYPICAL APPLICATION CIRCUIT
CN2 CN1
R101 4.7K R102 C119 102 100
1uF
1uF
R103 390
SK101
WSP-401M GOUT ROUT BOUT GND2 GCLP BCLP VCC2 RCLP
C126 C117 1nF R117 150 C118 330pF R116 C116 1nF 1.8nF
R118 R119 560 560 C160
D102 1N4148
10K
R115 2K
1
3
Q102 2N3904 CB02 104 CG02 104 CR02 104
RG03 RB03 470 RB15 47 RG15 47 470
RR03 470 RR15 47
RB11 100 RB20 4.7K RG20 4.7K
RG11 100 RR20 4.7K
RR11 100 C106 104
C107
2
QB01 2N5551C-Y
2
QG01 2N5551C-Y
2
QR01 220uF 2N5551C-Y
CB05 104
CG05 104
CR05 104
CB05 104 RB12 2.2K
CG05 104 RG12 2.2K
CR05 104 RR12 2.2K RR14 75 RG14 75 RB14 75
QB02 2N5401C-Y
2
QG02 2N5401C-Y
2
QR02 2N5401C-Y
2 1SS244
RR13 82K
DB04 DG03 DG04 DR03 DR04 1SS244 +
CR04 1uF
RB13 82K
RG13 82K
1SS244 VDD 1SS244
1SS244
DB05 1N4148
DG05 1N4148
DR05 1N4148
+
CG04 1uF
+
CB04 1uF RR09 RG09 RB09 75K 75K 75K
LR01 0.15uH
R104 390
LG01 0.15uH
LB01 0.15uH
SK102 DMS-200D DMS-200D
C120 1nF
SKB01 SKG01 DMS-200D SKR01 DMS-200D G2
RR10 39
RG10 39
RB10 39
Figure 27. Typical Application Circuit
56
+
14 2
13
12 5V
11 3 1
10
9 1 3
8
7
6 G1
5 3 1
4 1 3
3
2
1
C123 103
6 1N4148 1N4148 1N4148
5
4
3
2
1 1N4148 12V
DR02 70V 6.3V DG02 DB02
DR01 DG01 DB01
1N4148
R123 1M C114 103
C109 103
C124 103 RB01 75 RB02 75 RG01 75 RG02 75 RR01 75
1N4148
C110 C111
L101
100uH
+
+
RR02 75
R107 1K C102 CB02 104 CG02 104 CR01 104 C112 R108 5.6K R109 27K R120 30M C113 562
12V BIN 12V +
4.7uF
100uF
BD102
5V
+
12_1V
16 17
15 GND1 18
14 GIN 19
13 VCC1 20
12 RIN 21 ROUT
11 VCC3 22 8 VBB GOUT 6 BIN BOUT
10 CLP_IN 23 7 GIN VCC
9 GND 24 9 RIN GND DRIVER IC
8 ABL_IN
7 CONT_CAP
6 VDDA
5 VREF
4 VREF1
3 VCO_IN
2 VSSA
1
C152
VFLB
104
KB2502
BCT 25
470uF
C103 BD103
+
HFLB
VDD
GCT 26
RCT 27
VSS 28
104
C121
C108 47uF
SCL 29
47uF R124
L103
SDA 30 +
C151
32
220
27uH
R114 470
31
104 C128 104
12V 5V
1 3
+
4
5
3
2
1
70V
3 DB03 1 G2 R_OUT 1SS244 B_OUT G_OUT

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