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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal Bus Buffer
Inverting
The MC74VHCT540A is an advanced high speed CMOS inverting octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHCT540A features inputs and outputs on opposite sides of the package and two AND-ed active-low output enables. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT540A input and output (when disabled) structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. * * * * * * * * * * * High Speed: tPD = 3.7ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 1.2V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 124 FETs or 31 Equivalent Gates LOGIC DIAGRAM
A1 A2 A3 A4 A5 A6 A7 A8 OUTPUT ENABLES OE1 OE2 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
MC74VHCT540A
DW SUFFIX 20-LEAD SOIC WIDE PACKAGE CASE 751D-05
DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02
M SUFFIX 20-LEAD SOIC EIAJ PACKAGE CASE 967-01 ORDERING INFORMATION MC74VHCTXXXADW SOIC WIDE MC74VHCTXXXADT TSSOP MC74VHCTXXXAM SOIC EIAJ
PIN ASSIGNMENT
OE1 A1 A2 A3 A4 A5 A6 A7 A8 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
DATA INPUTS
INVERTING OUTPUTS
GND
FUNCTION TABLE
Inputs Output Y OE1 L L H X OE2 L L X H A L H X X H L Z Z
4/99
(c) Motorola, Inc. 1999
1
REV 0
MC74VHCT540A
II I I I I I I I I I I I II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I I I I I I I I I IIIIIIIII IIIIIIII IIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIII IIIIIIII I I II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I I I I IIIIIIIII I I IIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIII IIIIIIII I I II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIII IIIIIIII I I II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I II IIIIIIIII I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII III I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIII II I I III III I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
II I I IIIIIIIIIIIIIIIIIIIIIII I I I I I I III I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage - 0.5 to + 7.0 - 0.5 to + 7.0 Vout IIK DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 75 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW Tstg - 65 to + 150
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
v
v
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Parameter Min 4.5 0 0 0 Max 5.5 5.5 Unit V V V
DC Supply Voltage DC Input Voltage
Vout TA
DC Output Voltage
Outputs in 3-State High or Low State
5.5 VCC + 85 20
Operating Temperature
- 40 0
_C
tr, tf
Input Rise and Fall Time
VCC =5.0V 0.5V
ns/V
DC ELECTRICAL CHARACTERISTICS
S bl Symbol VIH
P Parameter
T Test C di i Conditions
VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5
TA = 25C
TA 85C
TA 125C
MinIIIMaxIII TypIIIMin Max 1.2 2.0 2.0 1.2 2.0 2.0
Min 1.2 2.0 2.0
Max
Ui Unit V
Minimum High-Level Input Voltage
VIL
Maximum Low-Level Input Voltage Minimum High-Level Output Voltage VIN = VIH or VIL
0.53 0.8 0.8
0.53 0.8 0.8
0.53 0.8 0.8
V
VOH
VIN = VIH or VIL IOH = - 50A VIN = VIH or VIL IOH = - 4mA IOH = - 8mA
2.9 4.4
3.0 4.5
2.9 4.4
2.9 4.4
V
2.58 3.94
2.48 3.80
2.34 3.66
VOLIIIIIIII VIN = VIH or VIL Maximum Low-Level IOL = 50A Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 4mA IOL = 8mA IIN Maximum Input Leakage Current
0.0 0.0
0.1 0.1
0.1 0.1
0.1 0.1
V
0.36 0.36
0.44 0.44
0.52 0.52
Vin = 5.5 V or GND Vin = VCC or GND Input: VIN = 3.4V VOUT = 5.5V
0 to 5.5 5.5 5.5 0.0
0.1 2.0
1.0 20
1.0 40
A A
ICC
Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current
ICCT IOPD
1.35 0.5
1.50 5.0
1.65 10
mA A
MOTOROLA
2
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT540A
I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIII I I II I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I IIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIII I I I II I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIII I I I I II I I I I I I I IIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIII I I II I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I I II I I I I I I I IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I III I I I I I I II I I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C TA = - 40 to 85C TA 125C Symbol S bl tPLH, tPHL Parameter P Test C di i Conditions T MinIIIMaxIII TypIIIMin Max 4.8 7.3 3.7 5.2 6.8 9.3 4.7 6.2 7.0 10.5 5.0 7.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Min Max Unit Ui ns Maximum Propagation Delay, A to Y (Figures 1 and 3) VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V (Note 1.) VCC = 5.0 0.5V (Note 1.) CL = 15pF CL = 50pF CL = 15pF CL = 50pF 8.5 12.0 6.0 8.0 10.5 14.0 8.0 10.0 tPZL, tPZH Output Enable TIme, OEn to Y (Figures 2 and 4) CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 10.5 14.0 7.2 9.2 12.5 16.0 15.0 19.0 10.5 13.0 20.0 11.5 2.0 1.5 10 ns 8.5 10.5 tPLZ, tPHZ Output Disable Time, OEn to Y (Figures 2 and 4) 11.2 6.0 15.4 8.8 1.5 1.0 10 17.5 10.0 1.5 1.0 10 ns tOSLH, tOSHL Output to Output Skew ns ns Cin Maximum Input Capacitance 4 6 pF pF Cout Maximum Three-State Output Capacitance (Output in High Impedance State) Typical @ 25C, VCC = 5.0V 17 CPD Power Dissipation C P Di i i Capacitance (N i (Note 2 ) 2.) pF F 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol S bl VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter P Typ 0.9 - 0.9 Max 1.2 - 1.2 3.5 1.5 Unit Ui V V V V
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
3
MOTOROLA
MC74VHCT540A
SWITCHING WAVEFORMS
3.0V 3.0V A tPHL 1.5V VOL Y 1.5V HIGH IMPEDANCE 1.5V GND tPLH VOH Y tPZH tPHZ VOH -0.3V Y 1.5V VOL +0.3V OE1 or OE2 1.5V tPZL tPLZ 50% GND HIGH IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST OUTPUT TEST POINT 1k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
MOTOROLA
4
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT540A
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC WIDE PACKAGE CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
DIM A A1 B C D E e H h L
L
18X
e
A1
q
T
C
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
5
MOTOROLA
MC74VHCT540A
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
2X
L/2
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
MOTOROLA
6
IIII IIII IIII
SECTION N-N M DETAIL E
20
11
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT540A
OUTLINE DIMENSIONS
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
7
MOTOROLA
MC74VHCT540A
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MOTOROLA 8
MC74VHCT540A/D VHC Data - Advanced CMOS Logic DL203 -- Rev 2

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