View ICS852911I_284871.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
FEATURES
* 9 HSTL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * HSTL_CLK, nHSTL_CLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL * PECL_CLK, nPECL_CLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 500MHz * Output skew: 100ps (maximum) * Part-to-part skew: 300ps (maximum) * Propagation delay: 1.7ns (maximum) * VOH = 1.4V (maximum) * 3.3V core, 1.6V to 3.6V output supply range * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS852911I is a low skew, 1-to-9 DifferenICS tial-to-HSTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS852911I has two selectable clock inputs which can accept most differential input levels. Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS852911I ideal for today's most advanced applications, such as IA64 and static RAMs.
BLOCK DIAGRAM
HSTL_CLK nHSTL_CLK PECL_CLK nPECL_CLK CLK_SEL 0 1 Q1 nQ1 Q2 nQ2 Q0 nQ0
PIN ASSIGNMENT
VDDO nQ0 nQ1 nQ2 Q0 Q1 Q2
25 GND CLK_SEL HSTL_CLK VDD 26 27 28 1 2 3 4 5
nQ8
24
23 22
21
20
19 18 17 16 Q3 nQ3 Q4 VDDO nQ4 Q5 nQ5
ICS852911I
15 14 13
Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 nHSTL_CLK PECL_CLK nPECL_CLK
6
Q8
7
nQ7
8
VDDO
9
Q7
10
nQ6
12 11
Q6
28-Lead PLCC 11.6mm x 11.4mm x 4.1mm package body V Package Top View
852911AVI
www.icst.com/products/hiperclocks.html
1
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 6 7, 9 8, 15, 22 10, 11 12, 13 14, 16 17, 18 19, 20 21, 23 24, 25 26 27 28 Name VDD nHSTL_CLK PECL_CLK nPECL_CLK nQ8, Q8 nQ7, Q7 VDDO nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3 Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 GND CLK_SEL HSTL_CLK Power Input Input Input Output Output Power Output Output Output Output Output Output Output Power Input Input Core supply pin. Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Differential output pair. HSTL interface level. Differential output pair. HSTL interface level. Output supply pins. Differential output pair. HSTL interface level. Differential output pair. HSTL interface level. Differential output pair. HSTL interface level. Differential output pair. HSTL interface level. Differential output pair. HSTL interface level. Differential output pair. HSTL interface level. Differential output pair. HSTL interface level. Power supply ground. Clock select input. When HIGH, selects PECL_CLK, nPECL_CLK inputs. Pulldown When LOW, selects HSTL_CLK, nHSTL_CLK. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs CLK_SEL 0 1 Selected Sourced HSTL_CLK, nHSTL_CLK PECL_CLK, nPECL_CLK
852911AVI
www.icst.com/products/hiperclocks.html
2
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V 50mA 100mA 37.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V0.3V, VDDO = 1.6V TO 3.6V, TA = -40C TO 85C
Symbol VDD VDDO IDD Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.0 1.6 Typical 3.3 3.3 Maximum 3.6 3.6 95 Units V V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V0.3V, VDDO = 1.6V TO 3.6V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter CLK_SEL CLK_SEL Input High Current Input Low Current CLK_SEL CLK_SEL VIN = VDD = 3.6V VIN = 0V, VDD = 3.6V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V0.3V, VDDO = 1.6V TO 3.6V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current PECL_CLK nPECL_CLK PECL_CLK nPECL_CLK Test Conditions VDD = VIN = 3.6V VDD = VIN = 3.6V VDD = 3.6V, VIN = 0V VDD = 3.6V, VIN = 0V -5 -150 0.3 1 Minimum Typical Maximum 150 150 Units A A A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 1.5 VDD NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PECL_CLK and nPECL_CLK is VDD + 0.3V.
852911AVI
www.icst.com/products/hiperclocks.html
3
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Test Conditions HSTL_CLK nHSTL_CLK HSTL_CLK nHSTL_CLK VIN = VDD = 3.6V VIN = VDD = 3.6V VIN = 0V, VDD = 3.6V VIN = 0V, VDD = 3.6V -5 -150 0.15 0.5 1.0 0 40 1.3 VDD - 0.85 1.4 0.4 60 Minimum Typical Maximum 150 150 Units A A A A V V V V % V
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V0.3V, VDDO = 1.6V TO 3.6V, TA = -40C TO 85C
Symbol IIH IIL VPP VCMR VOH VOL VOX Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3 Output Crossover Voltage; NOTE 4
Peak-to-Peak Output Voltage Swing 0.6 1.1 VSWING NOTE 1: For single ended applications, the maximum input voltage for HSTL_CLK and nHSTL_CLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: Outputs terminated with 50 to ground. NOTE 4: Defined with respect to output voltage swing at a given condition.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V0.3V, VDDO = 1.6V TO 3.6V, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 200 1.3 1.5 Test Conditions Minimum Typical Maximum 500 1. 7 100 300 600 53 Units MHz ns ps ps ps %
t sk(o) t sk(pp)
tR / tF
odc Output Duty Cycle 47 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured from VDD/2 to the output differential crossing point for single ended input levels. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
852911AVI
www.icst.com/products/hiperclocks.html
4
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V0.3V 1.6V to 3.6V VDD
VDD VDDO
Qx
SCOPE
nHSTL_CLK, nPECL_CLK
HSTL
GND
nQx
V
HSTL_CLK, PECL_CLK
PP
Cross Points
V
CMR
GND 0V
3.3V CORE/1.6V
TO
3.6V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nHSTL_CLK, nPECL_CLK
80%
HSTL_CLK, PECL_CLK nQ0:nQ8 Q0:Q8
tPD
80% VOD
Clock Outputs
20% tR tF
20%
PROPAGATION DELAY
nQ0:nQ8 Q0:Q8
OUTPUT RISE/FALL TIME
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
852911AVI
www.icst.com/products/hiperclocks.html
5
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
852911AVI
www.icst.com/products/hiperclocks.html
6
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The HSTL_CLK/nHSTL_CLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS HSTL_CLK/nHSTL_CLK input driven by the most common driver types. The input interfaces suggested here are examples
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 2A. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY ICS HIPERCLOCKS HSTL DRIVER
FIGURE 2B. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
852911AVI
www.icst.com/products/hiperclocks.html
7
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PECL_CLK/nPECL_CLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PECL_CLK/ nPECL_CLK input driven by the most common driver types.
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 3A. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84
Zo = 50 Ohm R5 100 C2 3.3V
3.3V 3.3V Zo = 50 Ohm LVDS C1 R3 1K R4 1K PCLK
R4 125
nPCLK
HiPerClockS Input
HiPerClockS PC L K/n PCL K
R1 1K
R2 1K
FIGURE 3C. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 3E. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
852911AVI
www.icst.com/products/hiperclocks.html
8
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
driver. The decoupling capacitors should be physically located near the power pin.
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of ICS852911I. In this example, the input is driven by an ICS HiPerClockS HSTL
Zo = 50 + Zo = 50 VCCO R2 50 R1 50
U1
Zo = 50 Ohm VCC Zo = 50 Ohm HSTL Driv er R9 50 R10 50 C9 0.1u
26 27 28 1 2 3 4
Q0 nQ0 Q1 VCCO nQ1 Q2 nQ2
25 24 23 22 21 20 19
VCCO
VEE CLK_SEL HSTL_CLK VCC nHSTL_CLK PECL_CLK nPECL_CLK nQ8 Q8 nQ7 VCCO Q7 nQ6 Q6
Q3 nQ3 Q4 VCCO nQ4 Q5 nQ5
18 17 16 15 14 13 12
R12 1K
5 6 7 8 9 10 11
ICS852911I
(U1-8)
VCCO
(U1-15)
(U1-22)
Zo = 50 +
C1 0.1uF
C2 0.1uF
C3 0.1uF
Zo = 50
VCC=3.3V VCCO=1.6V to 3.6V
R8 50 R7 50
-
FIGURE 4. ICS852911I HSTL BUFFER SCHEMATIC EXAMPLE
852911AVI
www.icst.com/products/hiperclocks.html
9
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS852911I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS852911I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.6V * 95mA = 342mW Power (outputs)MAX = 87.2mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 87.2mW = 784.8mW
Total Power_MAX (3.6V, with all outputs switching) = 342mW + 784.8mW = 1126.8mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 1.127W * 31.1C/W = 120C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 28-pin PLCC, Forced Convection
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.8C/W
200
31.1C/W
500
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
852911AVI
www.icst.com/products/hiperclocks.html
10
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT
RL 50
FIGURE 5. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R ) * (V
L DDO_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
-V
OL_MAX
Pd_H = (1.4V/50) * (3.6V - 1.4V) = 61.6mW Pd_L = (0.4V/50) * (3.6V - 0.4V) = 25.6mW Total Power Dissipation per output pair = Pd_H + Pd_L = 87.2mW
852911AVI
www.icst.com/products/hiperclocks.html
11
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 28 LEAD PLCC
JA by Velocity (Linear Feet per Minute)
0 200
31.1C/W
500
28.3C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS852911I is: 726 Pin compatible with MPC911
852911AVI
www.icst.com/products/hiperclocks.html
12
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
28 LEAD PLCC
PACKAGE OUTLINE - V SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 4.19 2.29 1.57 0.33 0.19 12.32 11.43 4.85 12.32 11.43 4.85 MINIMUM 28 4.57 3.05 2.11 0.53 0.32 12.57 11.58 5.56 12.57 11.58 5.56 MAXIMUM
Reference Document: JEDEC Publication 95, MS-018
852911AVI
www.icst.com/products/hiperclocks.html
13
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Marking ICS852911AVI ICS852911AVI Package 28 Lead PLCC 28 Lead PLCC Shipping Packaging Tube 500 Tape & Reel Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS852911AVI ICS852911AVIT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
852911AVI
www.icst.com/products/hiperclocks.html
14
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS852911I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Block Diagram - corrected drawing. Date 5/23/05
Rev A
Table
Page 1
852911AVI
www.icst.com/products/hiperclocks.html
15
REV. A MAY 23, 2005

▲Up To Search▲

Price & Availability of ICS852911I

	To Download ICS852911I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .