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CS8952 CrystalLANTM 100BASE-X and 10BASE-T Transceiver
Features
! Single-Chip IEEE 802.3 Physical Interface IC ! Six
for 100BASE-TX, 100BASE-FX and 10BASE-T ! Adaptive Equalizer provides Extended Length Operation (>160 m) with Superior Noise Immunity and NEXT Margin ! Extremely Low Transmit Jitter (<400 ps) ! Low Common Mode Noise on TX Driver for Reduced EMI Problems ! Integrated RX and TX Filters for 10BASE-T ! Compensation for Back-to-Back "Killer Packets" ! Digital Interfaces Supported
- Media Independent Interface (MII) for 100BASE-X and 10BASE-T - Repeater 5-bit code-group interface (100BASE-X) - 10BASE-T Serial Interface
!
LED drivers (LNK, COL, FDX, TX, RX, and SPD) ! Low power (135 mA Typ) CMOS design operates on a single 5 V supply
Description
The CS8952 uses CMOS technology to deliver a highperformance, low-cost 100BASE-X/10BASE-T Physical Layer (PHY) line interface. It makes use of an adaptive equalizer optimized for noise and near end crosstalk (NEXT) immunity to extend receiver operation to cable lengths exceeding 160 m. In addition, the transmit circuitry has been designed to provide extremely low transmit jitter (<400 ps) for improved link partner performance. Transmit driver common mode noise has been minimized to reduce EMI for simplified FCC certification. The CS8952 incorporates a standard Media Independent Interface (MII) for easy connection to a variety of 10 and 100 Mb/s Media Access Controllers (MACs). The CS8952 also includes a pseudo-ECL interface for use with 100Base-FX fiber interconnect modules. ORDERING INFORMATION CS8952-CQ 0 to 70 C CDB8952 100-pin TQFP Evaluation Board
Register Set Compatible with DP83840A ! IEEE 802.3 Auto-Negotiation with Next Page Support
CS8952 10BaseT/100Base-X Transceiver
TX_EN TX_ER/TXD4 TXD[3:0] TX_CLK
10/100 Manchester Encoder 10BaseT Filter MLT-3 Encoder Slew Rate Control
4B/5B Encoder
M U X
TX+, TX-
Scrambler
MDC MII_IRQ MDIO
Media Independent Interface (MII)
Fiber NRZI Interface Fiber NRZI Interface 10/100 4B/5B Decoder Descrambler MLT-3 Decoder 100BaseT Slicer
ECL Driver
TX_NRZ+, TX_NRZRX_NRZ+, RX_NRZ-
ECL Receiver
CRS COL RX_ER/RXD4 RX_DV RXD[3:0] RX_CLK RX_EN
M U X
Adaptive Eq. & Baseline Wander Compensation
RX+, RX-
Manchester Decoder
10BaseT Slicer
10BaseT Filter
MII Control/Status Registers
Link Management
Timing Recovery
Auto Negotiation
LED Drivers
LED1 LED2 LED3 LED4 LED5
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved)
DS206PP3 1 OCT `01
CS8952
TABLE OF CONTENTS
SPECIFICATIONS AND CHARACTERISTICS............................................................. 4 ABSOLUTE MAXIMUM RATINGS ....................................................................... 4 RECOMMENDED OPERATING CONDITIONS ................................................... 4 QUARTZ CRYSTAL REQUIREMENTS ............................................................... 4 DC CHARACTERISTICS ..................................................................................... 5 10BASE-T CHARACTERISTICS ......................................................................... 7 100BASE-X CHARACTERISTICS ....................................................................... 8 100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES ........................ 9 100BASE-TX MII RECEIVE TIMING - 5B BYPASS ALIGN MODE ................... 10 100BASE-TX MII TRANSMIT TIMING - 4B/5B ALIGN MODES ........................ 11 100BASE-TX MII TRANSMIT TIMING - 5B BYPASS ALIGN MODE ................ 12 10BASE-T MII RECEIVE TIMING ...................................................................... 13 10BASE-T MII TRANSMIT TIMING ................................................................... 14 10BASE-T SERIAL RECEIVE TIMING .............................................................. 15 10BASE-T SERIAL TRANSMIT TIMING ............................................................ 16 AUTO NEGOTIATION / FAST LINK PULSE TIMING ........................................ 17 SERIAL MANAGEMENT INTERFACE TIMING ................................................. 18 INTRODUCTION .......................................................................................................... 19 High Performance Analog ................................................................................... 19 Low Power Consumption .................................................................................... 19 Application Flexibility ........................................................................................... 19 Typical Connection Diagram ............................................................................... 19 FUNCTIONAL DESCRIPTION .................................................................................... 21 Major Operating Modes ....................................................................................... 21 100BASE-X MII Application (TX and FX) ..................................................... 21 Symbol Encoding and Decoding ........................................................... 22 100 Mb/s Loopback ............................................................................... 23 100BASE-X Repeater Application ............................................................... 23 10BASE-T MII Application ........................................................................... 24 Full and Half Duplex operation .............................................................. 24 Collision Detection ................................................................................. 24 Jabber ................................................................................................... 24 Link Pulses ............................................................................................ 24 Receiver Squelch .................................................................................. 25 10BASE-T Loopback ............................................................................. 25 Carrier Detection ................................................................................... 25
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
10BASE-T Serial Application ....................................................................... 25 Auto-Negotiation ................................................................................................. 25 Reset Operation .................................................................................................. 26 LED Indicators..................................................................................................... 26 MEDIA INDEPENDENT INTERFACE (MII) ................................................................. 27 MII Frame Structure ............................................................................................ 27 MII Receive Data................................................................................................. 28 MII Transmit Data................................................................................................ 28 MII Management Interface .................................................................................. 29 MII Management Frame Structure ...................................................................... 29 CONFIGURATION ...................................................................................................... 30 Configuration At Power-up/Reset Time............................................................... 30 Configuration Via Control Pins ............................................................................ 30 Configuration via the MII ..................................................................................... 30 CS8952 REGISTERS .................................................................................................. 31 Basic Mode Control Register - Address 00h ..................................................... 32 Basic Mode Status Register - Address 01h ...................................................... 34 PHY Identifier, Part 1 - Address 02h ................................................................. 36 PHY Identifier, Part 2 - Address 03h ................................................................. 37 Auto-Negotiation Advertisement Register - Address 04h .................................. 38 Auto-Negotiation Link Partner Ability Register - Address 05h ........................... 39 Auto-Negotiation Expansion Register - Address 06h ........................................ 40 Auto-Negotiation Next-Page Transmit Register - Address 07h ......................... 41 Interrupt Mask Register - Address 10h ............................................................. 42 Interrupt Status Register - Address 11h ............................................................ 45 Disconnect Count Register - Address 12h ........................................................ 48 False Carrier Count Register - Address 13h ..................................................... 49 Scrambler Key Initialization Register - Address 14h ......................................... 50 Receive Error Count Register - Address 15h .................................................... 51 Descrambler Key Initialization Register - Address 16h ..................................... 52 PCS Sub-Layer Configuration Register - Address 17h ..................................... 53 Loopback, Bypass, and Receiver Error Mask Register - Address 18h ............. 56 Self Status Register - Address 19h ................................................................... 59 10BASE-T Status Register - Address 1Bh ........................................................ 61 10BASE-T Configuration Register - Address 1Ch ............................................ 62 DESIGN CONSIDERATIONS ...................................................................................... 64 Twisted Pair Interface ......................................................................................... 64 100BASE-FX Interface........................................................................................ 64 Internal Voltage Reference ................................................................................. 64 Clocking Schemes .............................................................................................. 65 Recommended Magnetics .................................................................................. 66 Power Supply and Decoupling ............................................................................ 66 General Layout Recommendations..................................................................... 66 PIN DESCRIPTIONS ................................................................................................... 69 PACKAGE DIMENSIONS ........................................................................................... 81
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
3
CS8952
1. SPECIFICATIONS AND CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.)
Parameter Power Supply Input Current Input Voltage Ambient Temperature Storage Temperature WARNING: Except Supply Pins Power Applied Symbol VDD VDD_MII Min -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 +/-10.0 VDD + 0.3 +125 +150 Unit V mA V C C
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS = 0 V, all voltages with respect
to 0 V.) Parameter Power Supply Operating Ambient Temperature Core MII Symbol VDD VDD_MII TA Min 4.75 3.0 0 Max 5.25 5.25 70 Unit V V C
QUARTZ CRYSTAL REQUIREMENTS (If a 25 MHz quartz crystal is used, it must meet the following specifications.) Parameter Parallel Resonant Frequency Resonant Frequency Error (CL = 15 pF) Resonant Frequency Change Over Operating Temperature Crystal Load Capacitance Motional Crystal Capacitance Series Resistance Shunt Capacitance Min -50 -40 Typ 25.0 15 0.021 Max +50 +40 18 7 Unit MHz ppm ppm pF pF pF
4
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
DC CHARACTERISTICS
(Over recommended operating conditions) Symbol VIXH VIXH IIXL IIXH CL tIXC tIXL tXH IDD Min -0.3 3.5 -40 39.996 18 18 Typ 135 90 80 900 20 900 Max 0.5 VDD+0.5 40 35 40.004 22 22 145 Unit V V A A pF ns ns ns mA
Parameter External Oscillator XTAL_I Input Low Voltage XTAL_I Input High Voltage XTAL_I Input Low Current XTAL_I Input High Current XTAL_I Input Capacitance XTAL_I Input Cycle Time XTAL_I Input Low Time XTAL_I Input High Time Power Supply Power Supply Current 100BASE-TX (Note 1) 100BASE-FX (Note 1) 10BASE-T (Note 1) Hardware Power-Down (Note 1) Software Power-Down (Note 1) Low Power Power-Up (Note 1) Digital I/O Output Low Voltage CLK25, MII_IRQ, SPD10, SPD100 IOL = 4.0mA
IDDHPDN IDDSPDN IDDSLPUP VOL
A mA A V
-
-
0.4 0.4
LED[4:0]
IOL = 10.0mA VOL VOL IOL = 4.0mA VOH IOH = -4.0mA VOH 2.4 1.1 1.1 2.4 V 0.4 V 0.4 3.05 2.1 V V
Output Low Voltage (MII_DRV = 1) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK IOL = 4.0mA VDD_MII = 5V; IOL = 43.0mA VDD_MII = 3.3V, IOL = 26.0mA Output Low Voltage (MII_DRV = 0) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK Output High Voltage CLK25, SPD10, SPD100
Output High Voltage (MII_DRV = 1) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK IOH= -4.0mA VDD_MII = 5V; IOH = -20.0mA VDD_MII = 3.3V, IOH = -20.0mA
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
5
CS8952
DC CHARACTERISTICS
(CONTINUED) (Over recommended operating conditions) Symbol VOH Min Typ Max Unit V
Parameter Output High Voltage (MII_DRV = 0) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK IOH = -4.0mA Input Low Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0] Input High Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0] Tri-Level Input Voltages AN[1:0], TCM, TXSLEW[1:0]
2.4 VIL VIH VIL VIM VIH 2.0 -
-
0.8 1/3 VDD_MII - 20% 2/3 VDD_MII - 20% A V V V
1/3 VDD_MII + 20% 2/3 VDD_MII + 20%
-
-
Input Low Current MDC, TXD[3:0], TX_CLK, TX_EN, TX_ER
IIL VI = 0.0V -20 -3800 -
MDIO Input High Current MDC, TXD[3:0], TX_CLK, TX_EN, TX_ER
VI = 0.0V IIH VI = 5.0V 200 20 A
MDIO Input Leakage Current All Other Inputs
VI = 5.0V ILEAK 0<=V<=VDD -10 +10 A
Notes: 1. With digital outputs connected to CMOS loads.
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
10BASE-T CHARACTERISTICS
Parameter 10BASE-T Interface Transmitter Differential Output Voltage (Peak) Receiver Normal Squelch Level (Peak) Receiver Low Squelch Level (LoRxSquelch bit set) 10BASE-T Transmitter TXD Pair Jitter into 100 Load TXD Pair Return to 50 mV after Last Positive Transition TXD Pair Positive Hold Time at End of Packet 10BASE-T Receiver Allowable Received Jitter at Bit Cell Center Allowable Received Jitter at Bit Cell Boundary 10BASE-T Link Integrity First Transmitted Link Pulse after Last Transmitted Packet Time Between Transmitted Link Pulses Width of Transmitted Link Pulses Minimum Received Link Pulses Separation Maximum Received Link Pulse Separation Last Receive Activity to Link Fail (Link Loss Timer) 10Base-T Jabber/Unjabber Timing Maximum Transmit Time Unjabber Time Symbol VOD VISQ VSQL Min 2.2 300 125 Typ Max 2.8 525 290 Unit V mV mV
tTTX1 tTTX2 tTTX3 tTRX1 tTRX2 tLN1 tLN2 tLN3 tLN4 tLN5 tLN6
250 15 15 60 2 25 50
16 16 5 52 52
8 4.5 +/-13.5 +/-13.5 17 17 200 7 150 150
ns s ns ns ns ms ms ns ms ms ms
-
105 406
t TTX2
-
ms ms
TXD t TTX1 t TTX3
RXD t RTX3 Carrier Sense (Internal)
t LN1 TXD t LN4 RXD t LN6 LINKLED t LN5 t LN2 t LN3
t RTX1
t RTX4
t RTX2
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
7
CS8952
100BASE-X CHARACTERISTICS
Parameter 100BASE-TX Transmitter TX Differential Output Voltage (Peak) Signal Amplitude Symmetry Signal Rise/Fall Time Rise/Fall Symmetry Duty Cycle Distortion Overshoot/Undershoot Transmit Jitter TX Differential Output Impedance 100BASE-TX Receiver Receive Signal Detect Assert Threshold Receive Signal Detect De-assert Threshold Receive Signal Detect Assert Time Receive Signal Detect De-assert Time 100BASE-FX Transmitter TX_NRZ+/- Output Voltage - Low TX_NRZ+/- Output Voltage - High Signal Rise/Fall Time 100Base-FX Receiver RX_NRZ+/- Input Voltage - Low RX_NRZ+/- Input Voltage - High Common Mode Input Range Symbol VOP VSYM tRF tRFS tDCD tOS tJT ZOUT Min 0.95 98 3.0 0.2 V1 V2 TRF V3 V4 VCMIP -1.830 -1.035 -1.830 -1.035 Typ 400 100 3.56 Max 1.05 102 5.0 0.5 +/-0.5 5 1400 1.0 1000 350 -1.605 -0.880 1.6 -1.605 -0.880 Unit V % ns ns ns % ps ohms Vp-p Vp-p s s V V ns V V V
RX/TX Signaling for 100Base-FX VDD TX_NRZ+/V1 V2 RX_NRZ+/V3 V4
0
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES
Parameter RX_CLK Period RX_CLK Pulse Width RXD[3:0],RX_ER/RXD4,RX_DV setup to rising edge of RX_CLK RXD[3:0],RX_ER/RXD4,RX_DV hold from rising edge of RX_CLK CRS to RXD latency 4B Aligned 5B Aligned "Start of Stream" to CRS asserted "End of Stream" to CRS de-asserted "Start of Stream" to COL asserted "End of Stream" to COL de-asserted RX_EN asserted to RX_DV, RXD[3:0] valid RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER/RXD4 in high impedance state Symbol tP tWL, tWH tSU tHD tDLAT tCRS1 tCRS2 tCOL1 tCOL2 tEN tDIS Min 10 10 2 2 Typ 40 20 3-6 3-6 10 TBD TBD Max 8 8 11 21 11 21 Unit ns ns ns ns BT BT BT BT BT ns ns
RX+/-
Start of Stream
End of Stream
IN tCRS2 tCOL2 OUT
tCRS1 CRS tCOL1 COL RX_EN tRLAT RX_DV RXD[3:0], RX_ER/RXD4 RX_CLK tWL tWH tSU tHD tEN
OUT tDIS IN
OUT OUT
tP OUT
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
9
CS8952
100BASE-TX MII RECEIVE TIMING - 5B BYPASS ALIGN MODE
Parameter RX_CLK Period RX_CLK Pulse Width RXD[4:0] setup to rising edge of RX_CLK RXD[4:0] hold after rising edge of RX_CLK Start of 5B symbol to symbol output on RX[4:0] 5B Mode Symbol tP tWL, tWH tSU tHD tRLAT Min 10 10 5 Typ 40 20 Max 9 Unit ns ns ns ns BT
RX+/-
RX Symbol 0
RX Symbol N-1
RX Symbol N
IN
tRLAT RXD[4:0], tP RX_CLK tWL tWH
tSU
tHD
RX Data 1
RX Data 0
OUT
OUT
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
100BASE-TX MII TRANSMIT TIMING - 4B/5B ALIGN MODES
Parameter TXD[3:0] Setup to TX_CLK High TX_EN Setup to TX_CLK High TXD[3:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TX_EN Hold after TX_CLK High TX_EN "high" to CRS asserted latency TX_EN "low" to CRS de-asserted latency TX_EN "high" to TX+/- output (TX Latency) Symbol tSU1 tSU2 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT Min 10 10 0 0 0 6 7 Typ Max 8 8 8 Unit ns ns ns ns ns BT BT BT
TX_CLK tSU2 TX_EN tSU1 TXD[3:0], TX_ER/TXD4 CRS tLAT TX+/Symbol Out Data IN
Input/Output tHD2 Input tHD1 Input tCRS1 tCRS2 Output
Output
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
11
CS8952
100BASE-TX MII TRANSMIT TIMING - 5B BYPASS ALIGN MODE
Parameter TXD[4:0] Setup to TX_CLK High TXD[4:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TXD[4:0] Sampled to TX+/- output (TX Latency) Symbol tSU1 tHD1 tHD2 tLAT Min 10 0 0 Typ 6 Max 7 Unit ns ns ns ns
TX_CLK tSU1 TXD[4:0]
Data IN
Input/Output tHD1 Input tLAT
TX+/-
Symbol OUT
Output
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
10BASE-T MII RECEIVE TIMING
Parameter RX_CLK Period RX_CLK Pulse Width RXD[3:0], RX_ER, RX_DV setup to rising edge of RX_CLK RXD[3:0], RX_ER, RX_DV hold from rising edge of RX_CLK RX data valid from CRS RX+/- preamble to CRS asserted RX+/- end of packet to CRS de-asserted RX+/- preamble to COL asserted RX+/- end of packet to COL de-asserted RX_EN asserted to RX_DV, RXD[3:0], RX_ER valid RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER in high impedance state Symbol tP tWL, tWH tSU tHD tRLAT tCRS1 tCRS2 tCOL1 tCOL2 tEN tDIS Min 30 30 0 Typ 400 200 8 5 2.5 Max 10 7 3 7 3 60 60 Unit ns ns ns ns BT BT BT BT BT ns ns
RX+/tCRS1 CRS tCOL1 COL RX_EN tRLAT RX_DV RXD[3:0], RX_ER RX_CLK tWL tWH tP tSU tHD tEN tDIS tCRS2 tCOL2
IN
OUT
OUT IN
OUT OUT
OUT
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
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CS8952
10BASE-T MII TRANSMIT TIMING
Parameter TXD[3:0] Setup to TX_CLK High TX_ER Setup to TX_CLK High TX_EN Setup to TX_CLK High TXD[3:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TX_EN Hold after TX_CLK High TX_EN "high" to CRS asserted latency TX_EN "low" to CRS de-asserted latency TX_EN "high" to TX+/- output (TX Latency) SQE Timing COL (SQE) Delay after CRS de-asserted COL (SQE) Pulse Duration Symbol tSU1 tSU2 tSU3 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT tCOL tCOLP Min 10 10 10 0 0 0 0 0 6 0.65 0.65 Typ 0.9 1.0 Max 4 16 14 1.6 1.6 Unit ns ns ns ns ns ns BT BT BT s s
10BASE-T Transmit Timing TX_CLK tSU3 TX_EN tSU2 TX_ER tSU1 TXD[3:0] tCRS1 CRS tLAT TX+/Valid Data
Input/Output tHD3 Input tHD2 Input tHD1 Input tCRS2 Output
Output SQE Timing
TX_CLK
Input/Output tSQE tSQEP
COL
Output
14
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
10BASE-T SERIAL RECEIVE TIMING
Parameter RX+/- active to RXD[0] active RX+/- active to CRS active RXD[0] setup from RX_CLK RXD[0] hold from RX_CLK RX_CLK hold after CRS off RXD[0] throughput delay CRS turn off delay Symbol tDATA tCRS tRDS tRDH tRCH tRD tCRSOFF Min 35 50 5 Typ Max 1200 600 250 400 Unit ns ns ns ns ns ns ns
RX+/tCRS CRS RX_CLK tRD tCRSOFF tRCH
IN
OUT
OUT tDATA RXD[0] tSU tHD OUT
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
15
CS8952
10BASE-T SERIAL TRANSMIT TIMING
Parameter TX_EN Setup from TX_CLK TX_EN Hold after TX_CLK TXD[0] Setup from TX_CLK TXD[0] Hold after TX_CLK Transmit start-up delay Transmit throughput delay Symbol tEHCH tCHEL tDSCH tCHDU tSTUD tTPD Min 10 10 10 10 Typ Max 500 500 Unit ns ns ns ns ns ns
TX_CLK tEHCH TX_EN tDSCH TXD[3:0] tSTUD TX+/Valid Data
Input/Output tCHEL Input tCHDU Input tPD Output
16
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
AUTO NEGOTIATION / FAST LINK PULSE TIMING
Parameter FLP burst to FLP burst FLP burst width Clock/Data pulses per burst Clock/Data pulse width Clock pulse to Data pulse Clock pulse to clock pulse Symbol tBTB tFLPW
-
tPW tCTD tCTC
Min 15 17 55.5 111
Typ 16 2 100 64 128
Max 17 33 69.5 139
Unit ms ms ea. ns s s
TX+/tFLPW tBTB Clock Pulse tPW tCTD tCTC Data Pulse tPW Clock Pulse
TX+/-
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
17
CS8952
SERIAL MANAGEMENT INTERFACE TIMING
Parameter MDC Period MDC Pulse Width MDIO Setup to MDC (MDIO as input) MDIO Hold after MDC (MDIO as input) MDC to MDIO valid (MDIO as output) Symbol tp tWL,tWH tMD1 tMD2 tMD3 Min 60 40 10 10 0 Typ Max 60 40 Unit ns % ns ns ns
DIRECTION: IN or OUT of chip MDC t MD1 t MD2 MDIO Valid Data Valid Data t MD3 MDIO Valid Data OUT IN IN
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
2. INTRODUCTION
The CS8952 is a complete physical-layer transceiver for 100BASE-TX and 10BASE-T applications. Additionally, the CS8952 can be used with an external optical module for 100BASE-FX. to the Analog Design Considerations section for detailed information on power supply requirements and decoupling, crystal and magnetics requirements, and twisted-pair and fiber transceiver connections.
2.1
High Performance Analog
3. FUNCTIONAL DESCRIPTION
The CS8952 is a complete physical-layer transceiver for 100BASE-TX and 10BASE-T applications. It provides a Physical Coding Sub-layer for communication with an external MAC (Media Access Controller). The CS8952 also includes a complete Physical Medium Attachment layer and a 100BASE-TX and 10BASE-T Physical Medium Dependent layer. Additionally, the CS8952 provides a PECL interface to an external optical module for 100BASE-FX applications. The primary digital interface to the CS8952 is an enhanced IEEE 802.3 Media Independent Interface (MII). The MII supports parallel data transfer, access to the CS8952 Control and Status registers, and several status and control pins. The CS8952's operating modes can be tailored to support a wide variety of applications, including low-latency 100BASE-TX repeaters, switches and MII-based network interface cards. For 100BASE-TX applications, the digital data interface can be either 4-bit parallel (nibbles) or 5-bit parallel (code-groups). For 10BASE-T applications, the digital data format can be either 4-bit parallel (nibbles) or one-bit serial. The CS8952 is controlled primarily by configuration registers via the MII Management Interface. Additionally, a number of the most fundamental register bits can be set at power-up and reset time by connecting pull-up or pull-down resistors to external pins. The CS8952's MII interface is enhanced beyond IEEE requirements by register extensions and the addition of pins for MII_IRQ, RX_EN, and ISODEF signals. The MII_IRQ pin provides an inter19
The highly integrated mixed-signal design of the CS8952 eliminates the need for external analog circuitry such as external transmit or receive filters. The CS8952 builds upon Cirrus Logic's experience in pioneering the high-volume manufacturing of 10BASE-T integrated circuits with "true" internal filters. The CS8952, CS8920, CS8904, and CS8900 include fifth-order, continuous-time Butterworth 10BASE-T transmit and receive filters, allowing those products to meet 10BASE-T wave shape, emission, and frequency content requirements without external filters.
2.2
Low Power Consumption
The CS8952 is implemented in low power CMOS, consuming only 135 mA typically. Three low-power modes are provided to make the CS8952 ideal for power sensitive applications such as CardBus.
2.3
Application Flexibility
The CS8952's digital interface and operating modes can be tailored to efficiently support a wide variety of applications. For example, the Media Independent Interface (MII) supports 100BASE-TX, 100BASE-FX and 10BASE-T NIC cards, switch ports and router ports. Additionally, the low-latency "repeater" interface mode minimizes data delay through the CS8952, facilitating system compliance with overall network delay budgets. To support 10BASE-T applications, the CS8952 provides a 10BASE-T serial port (Seven-wire ENDEC interface).
2.4
Typical Connection Diagram
Figure 1 illustrates a typical MII to CS8952 application with twisted-pair and fiber interfaces. Refer
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
VDD_MII 25 MHz 4.7 k 4.7 k 1.5 k
XTAL_I XTAL_O VSS18 RES VSS17
4.99 k 0.1 F
4
MII I/F
33 33 33 33 33 33 33 33 33 33
MDIO MDC TXD TX_ER/TXD[4] TX_EN TX_CLK RX_CLK RXD[0] RXD[1]/PHYAD[1] RXD[2] RXD[3]/PHYAD[3] RX_ER/RXD[4]/PHYAD[4] RX_DV/MII_DRV COL/PHYAD0 CRS/PHYAD[2]
49.9 RX+
49.9 51 51 51 51 SHLD 8 7 6 5 RJ45 4 3 2 1 SHLD
75
51
RX-
75
51
TX+
TX0.1 F 0.1 F 0.01 F 2KV
CS8952
VDD_MII
4.7 k
CONTROL I/F
LPSTRT RX_EN PWRDN REPEATER BPSCR BP4B5B BPALIGN LPBK ISODEF 10BT_SER RESET MII_IRQ 680 SPEED10 680 SPEED100
+5 V
0.1 F SIGNAL+ SIGNAL+5 V 82 68 FIBER TRANSCEIVER 63.4 VEE SD+ TDTD+ VCC VCC RDRD+ VEE 130 191 0.1 F
82
0.1 F 82
49.9 TX_NRZTX_NRZ+ RX_NRZRX_NRZ+ 130
49.9
VDD_MII 680 LED1 680 LED2 680 LED3 680 LED4 680 LED5 3 +5 V 10 F 0.1 F 11 10 F 0.1 F RSVD 7 VSS 21 TEST0 TEST1 VDD AN0 AN1 TCM NC NC TXSLEW0 TXSLEW1 NC NC
130
+5 V
0.1 F
0.1 F
VDD_MII
Figure 1. Typical Connection Diagram 20 CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
rupt signal to the controller when a change of state has occurred in the CS8952, eliminating the need for the system to poll the CS8952 for state changes. The RX_EN signal allows the receiver outputs to be electrically isolated. The ISODEF pin controls the value of register bit ISOLATE in the Basic Mode Control Register (address 00h) which in turn electrically isolates the CS8952's MII data path.
Operating Mode BPALIGN BP4B5B 10BT_SER 100BASE-X 1 Don't 0 Repeater Care 0 1 0 10BASE-T Serial Don't Don't 1 Care Care Table 1.
3.1.1
3.1
Major Operating Modes
100BASE-X MII Application (TX and FX)
The following sections describe the four major operating modes of the CS8952: 100BASE-X MII Modes (TX and FX) 100BASE-X Repeater Modes 10BASE-T MII Mode 10BASE-T Serial Mode
The CS8952 provides an IEEE 802.3-compliant MII interface. Data is transferred across the MII in four-bit parallel (nibble) mode. TX_CLK and RX_CLK are nominally 25 MHz for 100BASE-X. The 100BASE-X mode includes both the TX and FX modes, as determined by pin BPSCR (bypass scrambler), or the BPSCR bit (bit 13) in the Loopback, Bypass, and Receiver Error Mask Register (address 18h). In FX mode, an external optical module is connected to the CS8952 via pins TX_NRZ+, TX_NRZ-, RX_NRZ+, RX_NRZ-, SIGNAL+, and SIGNAL-. In FX mode, the MLT3/NRZI conversion blocks and the scrambler/descrambler are bypassed.
The choice of operating speed (10 Mb/s versus 100 Mb/s) is made using the auto-negotiation input pins (AN0, AN1) and/or the auto-negotiation MII registers. The auto-negotiation capability also is used to select a duplex mode (full or half duplex). Both speed and duplex modes can either be forced or negotiated with the far-end link partner. The digital interface mode (MII, repeater, or 10BASE-T serial) is selected by input pins BPALIGN, BP4B5B and 10BT_SER as shown in Table 1. Speed and duplex selection are made through the AN[1:0] pins as shown in Table 5.
Operating Mode BPALIGN BP4B5B 10BT_SER 100BASE-X MII 0 0 0 10BASE-T MII 0 0 0 Table 1.
3.1.1.1
Symbol Encoding and Decoding
In 100BASE-X modes, 4-bit nibble transmit data is encoded into 5-bit symbols for transmission onto the media as shown in Tables 2 and 3. The encoding is necessary to allow data and control symbols to be sent consecutively along the same media transparent to the MAC layer. This encoding causes the symbol rate transmitted across the wire (125 symbols/second) to be greater than the actual data rate of the system (100 symbols/second).
DATA and CONTROL Codes (RX_ER = 0 or TX_ER = 0) Name DATA (Note 1) 0 1 5-bit Symbol 11110 01001 4-bit Nibble 0000 0001 Comments
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
21
CS8952
DATA and CONTROL Codes (RX_ER = 0 or TX_ER = 0) Name 5-bit Symbol 4-bit Nibble Comments 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 CONTROL (Note 2) I 11111 0101 IDLE (Note 3) J 11000 0101 First Start of Stream Symbol K 10001 0101 Second Start of Stream Symbol T 01101 0000 First End of Stream Symbol R 00111 0000 Second End of Stream Symbol 1. DATA code groups are indicated by RX_DV = 1 2. CONTROL code groups are inserted automatically during transmission in response to TX_EN. They are not generated through any combination of TXD[3:0] or TX_ER. 3. IDLE is indicated by RX_DV = 0. Table 2. 4B5B Symbol Encoding/Decoding Code Violations (RX_ER = 1 or TX_ER = 1) Normal Mode 4-bit Nibble 0000 0000 0000 0000 0000 0000 0110 or 0101 (Note 2) 0110 or 0101 (Note 2) 0110 or 0101 (Note 2) 0110 or 0101 (Note 2) 0110 or 0101 (Note 2) 0110 or 0101 (Note 2) Error Report Mode 4-bit Nibble 0000 0000 0000 0000 0000 0000 0001 0111 1000 1001 1010 1011 CrystalLANTM 100BASE-X and 10BASE-T Transceiver
Name 5-bit Symbol CONTROL (Note 1) I 11111 J 11000 K 10001 T 01101 R 00111 CODE VIOLATIONS H 00100 V0 00000 V1 00001 V2 00010 V3 00011 V4 00101 V5 00110 22
Comments This portion of the table relates received 5-bit symbols to received 4-bit nibbles only. The control code groups may not be transmitted in the data portion of the frame.
CS8952
Code Violations (RX_ER = 1 or TX_ER = 1) Error Report Normal Mode 4-bit Mode 4-bit Name 5-bit Symbol Nibble Nibble Comments V6 01000 0110 or 0101 (Note 2) 1100 V7 01100 0110 or 0101 (Note 2) 1101 V8 10000 0110 or 0101 (Note 2) 1110 V9 11001 0110 or 0101 (Note 2) 1111 1. CONTROL code groups become violations when found in the data portion of the frame. 2. Invalid code groups are mapped to 5h unless the Code Error Report select bit in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) is set, in which case invalid code groups are mapped to 6h. Table 3. 4B5B Code Violation Decoding
3.1.1.2
100 Mb/s Loopback
3.1.2
100BASE-X Repeater Application
One of two internal 100BASE-TX loopback modes can be selected. Local loopback redirects the TXD[3:0] input data to RXD[3:0] data outputs through the 4B5B coders and scramblers. Local loopback is selected by asserting pin LPBK, by setting the LPBK bit (bit 14) in the Basic Mode Control Register (address 00h) or by setting bits 8 and 11 in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) as shown in Table 4. Remote loopback redirects the analog line interface inputs to the analog line driver outputs. Remote loopback is selected by setting bit 9 in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) as shown in Table 4.
Remote PMD Function Loopback Loopback (bit 9) (bit 8) 0 0 No Loopback 0 1 Local Loopback (toward MII) 1 0 Remote Loopback (toward line) 1 1 Operation is undefined Table 4.
The CS8952 provides two low latency modes for repeater applications. These are selected by asserting either pin BPALIGN or BP4B5B. Both pins have the effect of bypassing the 4B5B encoder and decoder. Bypassing the coders decreases latency, and uses a 5-bit wide parallel code group interface on pins RXD[4:0] and TXD[4:0] instead of the 4bit wide MII nibble interface on pins RXD[3:0] and TXD[3:0]. In repeater mode, pin RX_ER is redefined as the fifth receive data bit (RXD4), and pin TX_ER is redefined as the fifth transmit data bit (TXD4). BPALIGN can also be selected by setting bit 12 in Loopback, Bypass, and Receiver Error Mask Register (address 18h). BP4B5B can be selected by setting bit 14 of the same register. Pin BPALIGN causes more of the CS8952 to be bypassed than the BP4B5B pin. BPALIGN also bypasses the scrambler/descrambler, and the NRZI to NRZ converters (see Figure 1). Also, for repeater applications, pin REPEATER should be asserted to redefine the function of the CRS (carrier sense) pin. The REPEATER function may also be invoked by setting bit 12 in the PCS Sublayer Configuration Register (address 17h). For repeater applications, the RX_EN pin can be used to gate the receive data pins (RXD[4:0],
When changing between local and non-loopback modes, the data on RXD[3:0] will be undefined for approximately 330 s.
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
23
CS8952
RX_CLK, RX_DV, COL, and CRS) onto a shared, external repeater system bus. packet transmission to prevent "blind" transmissions onto the network (link pulses are still sent while packet transmission is disabled). To reactivate transmission, the receiver must detect a single packet (the packet itself is ignored), or two normal link pulses separated by more than 6 ms and no more than 50 ms. The CS8952 automatically checks the polarity of the receive half of the twisted pair cable. To detect a reversed pair, the receiver examines received link pulses and the End-of-Frame (EOF) sequence of incoming packets. If it detects at least one reversed link pulse and at least four frames in a row with negative polarity after the EOF, the receive pair is considered reversed. If the polarity is reversed and bit 1 of the 10BASE-T Configuration Register (address 1Ch), is set, the CS8952 automatically corrects a reversal. In the absence of transmit packets, the transmitter generates link pulses in accordance with Section 14.2.1.1 of the Ethernet standard. Transmitted link pulses are positive pulses, one bit time wide, typically generated at a rate of one every 16 ms. The 16 ms timer also starts whenever the transmitter completes an End-of-Frame (EOF) sequence. Thus, a link pulse will be generated 16 ms after an EOF unless there is another transmitted packet.
3.1.3
10BASE-T MII Application
The digital interface used in this mode is the same as that used in the 100BASE-X MII mode except that TX_CLK and RX_CLK are nominally 2.5 MHz. The CS8952 includes a full-featured 10BASE-T interface, as described in the following sections.
3.1.3.1
Full and Half Duplex operation
The 10BASE-T function supports full and half duplex operation as determined by pins AN[1:0] and/or the corresponding MII register bits. (See Table 5).
3.1.3.2
Collision Detection
If half duplex operation is selected, the CS8952 detects a 10BASE-T collision whenever the receiver and transmitter are active simultaneously. When a collision is present, the collision is reported on pin COL. Collision detection is undefined for full-duplex operation.
3.1.3.3
Jabber
The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater than approximately 105 ms. The transmitter stays disabled until approximately 406 ms after the internal transmit request is no longer enabled.
3.1.3.5
Receiver Squelch
3.1.3.4
Link Pulses
To prevent disruption of network operation due to a faulty link segment, the CS8952 continually monitors the 10BASE-T receive pair (RXD+ and RXD-) for packets and link pulses. After each packet or link pulse is received, an internal Link-Loss timer is started. As long as a packet or link pulse is received before the Link-Loss timer finishes (between 50 and 100 ms), the CS8952 maintains normal operation. If no receive activity is detected, the CS8952 disables
The 10BASE-T squelch circuit determines when valid data is present on the RXD+/RXD- pair. Incoming signals passing through the receive filter are tested by the squelch circuit. Any signal with amplitude less than the squelch threshold (either positive or negative, depending on polarity) is rejected.
3.1.3.6
10BASE-T Loopback
When Loopback is selected, the TXD[3:0] pins are looped back into the RXD[3:0] pins through the
24
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
Manchester Encoder and Decoder. Selection is made via: setting bit 14 in the Basic Mode Control Register (address 00h) or setting bits 8 and 11 in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) or asserting the LPBK pin. a 10 MHz RX_CLK and TX_CLK. Receive data is framed by CRS rather than RX_DV.
3.2
Auto-Negotiation
-
3.1.3.7
Carrier Detection
The carrier detect circuit informs the MAC that valid receive data is present by asserting the Carrier Sense signal (CRS) as soon it detects a valid bit pattern (1010b or 0101b for 10BASE-T). During normal packet reception, CRS remains asserted while the frame is being received, and is de-asserted within 2.3 bit times after the last low-to-high transition of the End-of-Frame (EOF) sequence. Whenever the receiver is idle (no receive activity), CRS is de-asserted.
The CS8952 supports auto-negotiation, which is the mechanism that allows the two devices on either end of an Ethernet link segment to share information and automatically configure both devices for maximum performance. When configured for auto-negotiation, the CS8952 will detect and automatically operate full-duplex at 100 Mb/s if the device on the other end of the link segment also supports full-duplex, 100 Mb/s operation, and auto-negotiation. The CS8952 auto-negotiation capability is fully compliant with the relevant portions of section 28 of the IEEE 802.3u standard. The CS8952 can auto-negotiate both operating speed (10 versus 100 Mb/s), duplex mode (half duplex versus full duplex), and flow control (pause frames), or alternatively can be set not to negotiate. At power-up and reset times, the auto-negotiation mode is selected via the auto-negotiation input pins (AN[1:0]). This selection can later be changed using the Auto-Negotiation Advertisement Register (address 04h). Pins AN[1:0] are three level inputs, and have the function shown in Table 5.
3.1.4
10BASE-T Serial Application
This mode is selected when pin 10BT_SERis asserted during power-up or reset, and operates similar to the 10BASE_T MII mode except that data is transferred serially on pins RXD0 and TXD0 using
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
25
CS8952
SET bit (bit 15 of the Basic Mode Control Register (address 00h)) is set.
AN1 Low High Floating Floating Floating Low Low High High AN0 Floating Floating Low High Floating Low High Low High Forced/ Auto Forced Forced Forced Forced Auto-Neg Auto-Neg Auto-Neg Auto-Neg Auto-Neg Table 5. Speed (Mb/s) 10 10 100 100 100/10 10 10 100 100 Full/Half Duplex Half Full Half Full Full/Half Half Full Half Full
4) Digital circuitry is reset whenever bit 0 of the PCS Sub-Layer Configuration Register (address 17h) is set. Analog circuitry is unaffected. 5) Analog circuitry is reset and recalibrated whenever the CS8952 enters or exits the powerdown state, as requested by pin PWRDN. 6) Analog circuitry is reset and recalibrated whenever the CS8952 changes between 10 Mb/s and 100 Mb/s modes. After a reset, the CS8952 latches the signals on various input pins in order to initialize key registers and goes through a self configuration. This includes calibrating on-chip analog circuitry. Time required for the reset calibration is typically 40 ms. External circuitry may access registers internal to the CS8952 during this time. Reset and calibration complete is indicated when bit 15 of the Basic Mode Control Register (address 00h) is clear.
Auto-Negotiation encapsulates information within a burst of closely spaced Link Integrity Test Pulses, referred to as a Fast Link Pulse (FLP) Burst. The FLP Burst consists of a series of Link Integrity Pulses which form an alternating clock / data sequence. Extraction of the data bits from the FLP Burst yields a Link Code Word which identifies the capability of the remote device. In order to support legacy 10 and 100 Mb/s devices, the CS8952 also supports parallel detection. In parallel detection, the CS8952 monitors activity on the media to determine the capability of the link partner even without auto-negotiation having occurred.
3.4
LED Indicators
3.3
Reset Operation
Reset occurs in response to six different conditions: 1) There is a chip-wide reset whenever the RESET pin is high for at least 200 ns. During a chip-wide reset, all circuitry and registers in the CS8952 are reset. 2) When power is applied, the CS8952 maintains reset until the voltage at the VDD supply pins reaches approximately 3.6 V. The CS8952 comes out of reset once VDD is greater than approximately 3.6 V and the crystal oscillator has stabilized. 3) There is a chip-wide reset whenever the RE26
The LEDx, SPD100, and SPD10 output pins provide status information that can be used to drive LEDs or can be used as inputs to external control circuitry. Indication options include: receive activity, transmit activity, collision, carrier sense, polarity OK, descrambler synchronization status, autonegotiation status, speed (10 vs. 100), and duplex mode.
4. MEDIA INDEPENDENT INTERFACE (MII)
The Media Independent Interface (MII) provides a simple interconnect to an external Media Access Controller (MAC). This connection may be chip to chip, motherboard to daughterboard, or a connection between two assemblies attached by a limited length of shielded cable and an appropriate connector. The MII interface uses the following pins:
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
STATUS Pins COL - Collision indication, valid only for half duplex modes. CRS - Carrier Sense indication MDIO - a bi-directional serial data path MDC - clock for MDIO (16.7 MHz max) MII_IRQ - Interrupt indicating change in the Interrupt Status Register (address 11h) RXD[3:0] - Parallel data output path RX_CLK - Recovered clock output RX_DV - Indicates when receive data is present and valid RX_ER - Indicates presence of error in received data RX_EN - Can be used to tri-state receiver output pins TXD[3:0] - Parallel data input path TX_CLK - Transmit clock TX_EN - Indicates when transmit data is present and valid TX_ER - Request to transmit a 100BASET HALT symbol, ignored for 10BASE-T operation.
MAC's Serial Bit Stream First Bit LSB D0 D1 D2 D3 D4 D5 D6 D7 MSB First Nibble LSB D0 MII D1 Nibble D2 Stream MSB D3 Second Nibble
4.1
MII Frame Structure
Data frames transmitted through the MII have the following format:
Preamble (7 Bytes) Start of Frame Delimiter (1 Byte) Data End of Frame Delimiter
SERIAL MANAGEMENT Pins
RECEIVE DATA Pins -
Each frame is preceded by an inter-frame gap. The inter-frame gap is an unspecified time during which no data activity occurs on the media as indicated by the de-assertion of CRS for the receive path and TX_EN for the transmit path. The Preamble consists of seven bytes of 10101010. The Start of Frame Delimiter consists of a single byte of 10101011. Data may be any number of bytes. The End of Frame Delimiter is conveyed by the deassertion of RX_DV and TX_EN for receive and transmit paths, respectively. Transmission and/or reception of each byte of data is done one nibble at a time in the following order:
TRANSMIT DATA Pins -
The interface uses TTL signal levels, which are compatible with devices operating at a nominal supply voltage of either 5.0 or 3.3 volts. It is capable of supporting either 10 Mb/s or 100 Mb/s data rates transparently. That is, all signaling remains identical at either data rate; only the nominal clock frequency is changed.
4.2
MII Receive Data
The presence of recovered data on the RXD[3:0] bus is indicated by the assertion of RX_DV. RX_DV will remain asserted from the beginning of the preamble (or Start of Frame Delimiter if preamble is not used) to the End of Frame Delimiter. Once RX_DV is asserted, valid data will be driven
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
27
CS8952
onto RXD[3:0] synchronously with respect to RX_CLK. Receive errors are indicated during frame reception by the assertion of RX_ER. It indicates that an error was detected somewhere in the frame currently being transferred across the MII. RX_ER will transition synchronously with respect to the RX_CLK, and will be held high for one cycle for each error received. It is up to the MAC to ensure that a CRC error is detected in that frame by the Logical Link Control. Figure 2 illustrates reception without errors, and Figure 3 illustrates reception with errors. presented to the CS8952. When TX_EN is not asserted, data on TXD[3:0] is ignored. Transmit errors should be signaled by the MAC by asserting TX_ER for one or more TX_CLK cycles. TX_ER must be synchronous with TX_CLK. This will cause the CS8952 to replace the nibble with a HALT symbol in the frame being transmitted. This invalid data will be detected by the receiving PHY and flagged as a bad frame. Figure 4 illustrates transmission without errors, and Figure 5 illustrates transmission with errors.
4.4
MII Management Interface
4.3
MII Transmit Data
TX_EN is used by the MAC to signal to the CS8952 that valid nibbles of data are being presented across the MII via TXD[3:0]. TX_EN must be asserted synchronously with the first nibble of preamble, and must remain asserted as long as valid data is being presented to the MII. TX_EN must be de-asserted within one TX_CLK cycle after the last nibble of data (CRC) has been
RX_CLK RX_DV RXD[3:0] Preamble/SFD RX_ER
The CS8952 provides an enhanced IEEE 802.3 MII Management Interface. The interface consists of three signals: a bi-directional serial data line (MDIO), a data clock (MDC), and an optional interrupt signal (MII_IRQ). The Management Interface can be used to access status and control registers internal to the CS8952. The CS8952 implements an extended set of 16-bit MII registers. Eight of the registers are defined by the IEEE 802.3
DATA
Figure 2. Reception without errors
RX_CLK RX_DV RXD[3:0] Preamble/SFD RX_ER DATA XX DATA
Figure 3. Reception with errors
28
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
TX_CLK TX_EN TXD[3:0] Preamble/SFD TX_ER DATA
Figure 4. Transmission without errors
TX_CLK TX_EN TXD[3:0] Preamble/SFD TX_ER DATA HALT
Figure 5. Transmission with errors
specification, while the remaining registers provide enhanced monitoring and control capabilities. As many as 31 devices may share a single Management Interface. A unique five-bit PHY address is associated with each device, with all devices responding to PHY address 00000. The CS8952 determines its PHY address at power-up or reset through the PHYAD[4:0] pins.
When the management interface is idle, the MDIO signal will be tri-stated, and the MAC is required to keep MDIO pulled to a logic ONE. At the beginning of each transaction, the MAC will typically send a sequence of 32 contiguous logic ONE bits on MDIO with 32 corresponding clock cycles on MDC to provide the CS8952 with a pattern that it can use to establish synchronization. Optionally, the CS8952 may be configured to operate without the preamble through bit 9 of the PCS Sub-Layer Configuration Register (address 17h).
4.5
MII Management Frame Structure
Frames transmitted through the MII Management Interface have the following format (Table 6):
Preamble (32 bits) Start of Frame (2 bits) Opcode (2 bits) PHY Address (5 bits)
Register Address (5 bits)
Turnaround (2 bits)
Data (16 bits)
Idle
Table 6. Format for Frame Transmitted through the MII Management Interface
The Start of Frame is indicated by a 01 bit pattern.
CrystalLANTM 100BASE-X and 10BASE-T Transceiver 29
CS8952
A read transaction is indicated by an Opcode of 10 and a write by 01. The PHY Address is five bits, with the most significant bit sent first. If the PHY address included in the frame is not 00000 or does not match the PHYAD field of the Self Status Register (address 19h), the rest of the frame is ignored. The register address is five bits, with the most significant bit sent first, and indicates the CS8952 register to be written to/read from. The Turnaround time is a two bit time spacing between when the MAC drives the last register address bit onto MDIO and the data field of a management frame in order to avoid contention during a read transaction. For a read transaction, the MAC should tri-state the MDIO pin beginning on the first bit time, and the CS8952 will begin driving the MDIO signal to a logic ZERO during the second bit time. During write transactions, since the MDIO direction does not need to be reversed, the MAC will drive the MDIO to a logic ONE for the first bit time and a logic ZERO for the second. The data field is always 16 bits in length, with the most significant bit sent first.
Function Select 10BASE-T serial mode Select auto-negotiation mode Bypass 4B5B coders Bypass 4B5B coders and scramblers Bypass scramblers, enter FX mode Electrically isolate MII after reset Start in low power mode Set MII PHY address Control definition of CRS pin, enable carrier integrity monitor and SQE function MII_DRV Set MII driver strength TCM Set TX_CLK mode TXSLEW[1:0] Set 100BASE-TX transmitter output slew rate Pin Name 10BT_SER AN[1:0] BP4B5B BPALIGN BPSCR ISODEF LPSTRT PHYAD[4:0] REPEATER
5.2
Configuration Via Control Pins
The following pins are for dedicated control signals and can be used at any time to configure the CS8952.
Pin Name LPBK PWRDN RESET Function Enter loopback mode Enter power-down mode Reset
5.3
Configuration via the MII
5. CONFIGURATION
The CS8952 can be configured in a variety of ways. All control and status information can be accessed via the MII Serial Management Interface. Additionally, many configuration options can be set at power-up or reset times via individual control lines. Some configuration capabilities are available at any time via individual control lines.
The CS8952 supports configuration by software control through the use of 16-bit configuration and status registers accessed via the MDIO/MDC pins (MII Management Interface). The first seven registers are defined by the IEEE 802.3 specification. Additional registers extend the register set to provide enhanced monitoring and control capabilities.
6. CS8952 REGISTERS
The CS8952 register set is comprised of the 16-bit status and control registers described below. A detailed description each register follows.
5.1
Configuration At Power-up/Reset Time
At power-up and reset time, the following pins are
Register Address 0h 1h 30 Description Basic Mode Control Register Basic Mode Status Register Type Read/Write Read-Only
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
Register Address 2h 3h 4h 5h 6h 7h 8h through Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh through 1Fh Description PHY Identifier #1 PHY Identifier #2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Reserved by IEEE 802.3 Working Group Interrupt Mask Register Interrupt Status Register Disconnect Count Register False Carrier Count Register Scrambler Key Initialization Register Receive Error Count Register Descrambler Key Initialization Register PCS Sub-Layer Configuration Register Loopback, Bypass and Receiver Error Mask Register Self-Status Register Reserved 10BASE-T Status Register 10BASE-T Configuration Register Reserved Type Read-Only Read-Only Read/Write Read-Only Read-Only Read/Write Read/Write Read-Only Read-Only Read-Only Read/Write Read-Only Read/Write Read/Write Read/Write Read/Write Read-Only Read/Write -
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
31
CS8952
6.1 Basic Mode Control Register - Address 00h
14 Loopback 6 13 Speed Selection 5 12 Auto-Neg Enable 4 11 Power Down 3 Reserved 10 Isolate 2 9 Restart Auto-Neg 1 8 Duplex Mode 0
15 Software Reset 7 Collision Test
BIT 15
NAME Software Reset
TYPE Read/Set
RESET 0
DESCRIPTION Setting this bit performs a chip-wide reset. All status and control registers are set to their default states, and the analog circuitry is re-calibrated. This bit is an Act-Once bit which is cleared once the reset and recalibration have completed. This bit will also be set automatically while the analog circuitry is reset and re-calibrated during mode changes. When set, the CS8952 is placed in a loop back mode. Any data sent on the transmit data path is returned on the receive data path. Loopback mode is entered regardless of whether 10 Mb/s or 100 Mb/s operation has been configured.
14
Loopback
Read/Write 0
13
Speed Selection
12
Auto-Neg Enable
11
Power Down
This bit will be set upon the assertion of the LPBK pin, and will be automatically cleared upon its deassertion. Read/Write If auto-negotiation When bit 12 is clear, setting this bit configures the is enabled via the CS8952 for 100 Mb/s operation. Clearing this bit sets AN[1:0] pins, reset the configuration at 10 Mb/s. When bit 12 is set, this bit is ignored. to 1; otherwise, reset to 0 Read/Write If auto-negotiation Setting this bit enables the auto-negotiation process. is enabled via the When this bit is set, bits 13 and 8 have no affect on AN[1:0] pins, reset the link configuration. The link configuration is determined by the auto-negotiation process. Clearing this to 1; otherwise, bit disables auto-negotiation. reset to 0 Read/Write 0 When this bit is set, the CS8952 enters a low power consumption state. Clearing this bit allows normal operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. Setting this bit causes the MII data path to be electriRead/Write If PHYAD = 00000, reset to 1; cally isolated by tri-stating all data outputs (i.e. otherwise reset to TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS). In addition the CS8952 will not respond to the value on the the TXD[3:0], TX_EN, and TX_ER inputs. It will, howISODEF pin ever, respond to MDIO and MDC. Clearing this bit allows normal operation.
10
Isolate
32
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
BIT 9 NAME Restart Auto-Neg TYPE Read/Set DESCRIPTION Setting this bit causes auto-negotiation to be restarted. It is an Act-Once bit which is cleared once auto-negotiation has begun. Clearing this bit has no effect on the auto-negotiation process. If auto-negotiation When bit 12 is clear, this bit controls the Fullis enabled via the Duplex/Half-Duplex operation of the part. When set, AN[1:0] pins, reset the part is configured for Full-Duplex operation, and when clear the part is configured for Half Duplex to 0; otherwise, operation. The setting of this bit is superseded by reset to 1 auto-negotiation, and thus has no effect if bit 12 is set. 0 When set, the COL pin will be asserted within 10 bit times in response to the assertion of TX_EN. Upon the deassertion of TX_EN, COL will be deasserted within 4 bit times. When Collision Test is clear, COL functions normally. 000 0000 RESET
0
8
Duplex Mode
R/W
7
Collision Test
R/W
6:0
Reserved
Read Only
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
33
CS8952
6.2 Basic Mode Status Register - Address 01h
15 12 10BASE-T/ Full Duplex 4 Remote Fault 11 10BASE-T/ Half Duplex 3 Auto-Neg Ability 10 9 Reserved 2 Link Status 1 Jabber Detect 0 Extended Capability 8
14 13 100BASE-TX/ 100BASE-TX/ 100BASE-T4 Full Duplex Half Duplex 7 Reserved 6 MF Preamble Suppression 5 Auto-Neg Complete
BIT 15 14
NAME 100BASE-T4 100BASE-TX/Full Duplex
TYPE Read Only Read Only
RESET 0 1
13
100BASE-TX/Half Duplex
Read Only
1
12
10BASE-T/Full Duplex
Read Only
1
11
10BASE-T/Half Duplex
Read Only
1
DESCRIPTION The CS8952 does not support 100BASE-T4 operation, so this bit will always read 0. When this bit is set, it indicates that the CS8952 is capable of 100BASE-TX Full-Duplex operation. This bit reflects the status of the 100BASE-TX/Full-Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). When this bit is set, it indicates that the CS8952 is capable of 100BASE-TX Half-Duplex operation. This bit reflects the status of the 100BASE-TX/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). When this bit is set, it indicates that the CS8952 is capable of 10BASE-T Full-Duplex operation. This bit reflects the status of the 10BASE-T/Full Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). When this bit is set, it indicates that the CS8952 is capable of 10BASE-T Half-Duplex operation. This bit reflects the status of the 10BASE-T/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). When set, this bit indicates that the CS8952 is capable of accepting management frames regardless of whether they are preceded by the preamble pattern. When clear, it indicates that the management frame must be preceded by the preamble pattern to be considered valid. This bit reflects the status of the MR Preamble Enable bit in the PCS Sub-Layer Configuration Register (address 17h). This bit is set to a 1 when the auto-negotiation process has completed. This is an indication that data is valid in the Auto-Negotiation Advertisement Register (address 04h), the Auto-Negotiation Link Partner Ability Register (address 05h), and the Auto-Negotiation Expansion Register (address 06h). When auto-negotiation is enabled, this bit is set if the Remote Fault bit is set in the Auto-Negotiation Link Partner Ability Register (address 05h). When autonegotiation is disabled, this bit will be set when a FarEnd Fault Indication for 100BASE-TX is detected. CrystalLANTM 100BASE-X and 10BASE-T Transceiver
10:7 6
Reserved Read Only MF Preamble Sup- Read Only pression
0000 1
5
Auto-Neg Complete Read Only
0
4
Remote Fault
Read Only
0
34
CS8952
BIT 3 NAME Auto-Neg Ability TYPE Read Only RESET 1 DESCRIPTION This bit indicates that the CS8952 has auto-negotiation capability. Therefore this bit will always read back a value of 1. When set, this bit indicates that a valid link has been established. Upon a link failure, this bit is cleared and latched. It will remain cleared until this register is read. In 10BASE-T mode, if the last transmission is longer than 105 ms, then the packet output is terminated by the jabber logic and this bit is set. If JabberiE (Interrupt Mask Register (address 10h), bit 3) is set, an MII Interrupt will be generated. This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this register, a read to the Interrupt Status Register (address 11h), or a reset. No jabber detect function has been defined for 100BASE-TX. This bit indicates that an extended register set may be accessed (registers beyond address 01h). This bit always reads back a value of 1.
2
Link Status
Read Only
0
1
Jabber Detect
Read Only
0
0
Extended Capability Read Only
1
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
35
CS8952
6.3 PHY Identifier, Part 1 - Address 02h
15 7 14 6 13 5 12 11 10 Organizationally Unique Identifier: Bits[3:10] 4 3 2 Organizationally Unique Identifier: Bits[11:18] 9 1 8 0
BIT 15:0
NAME Organizationally Unique Identifier (bits 3:18)
TYPE RESET Read/Write 001Ah
DESCRIPTION This identifier is assigned to PHY manufacturers by the IEEE. Its intention is to provide sufficient information to support 10/100 Management as defined in Clause 30.1.2 of the IEEE 802.3 specification. This register contains bits [3:18] of the OUI. Bit 3 of the OUI is located in bit 15 of the PHY Identifier, bit 4 of the OUI is in bit 14, and so on. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
36
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.4 PHY Identifier, Part 2 - Address 03h
15 7 14 13 12 11 Organizationally Unique Identifier - Bits[19:24] 6 Part Number 5 4 3 10 9 Part Number 2 1 Revision Number 0 8
BIT NAME 15:10 Organizationally Unique Identifier (bits 19:24)
TYPE RESET Read/Write 00 1000
DESCRIPTION This identifier is assigned to PHY manufacturers by the IEEE. Its intention is to provide sufficient information to support 10/100 Management as defined in Clause 30.1.2 of the IEEE 802.3 specification. This register contains bits [19:24] of the OUI. Bit 19 of the OUI is located in bit 15 of this register, bit 20 of the OUI is in bit 14, and so on. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. These bits indicate the CS8952 part number. It has been set to a value of 100000. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. These bits indicate the CS8952 part revision. Rev. A Rev. B etc. 0000 0001
9:4
Part Number
Read/Write 10 0000
3:0
Revision Number
Read/Write 0001
Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
37
CS8952
6.5 Auto-Negotiation Advertisement Register - Address 04h
14 Acknowledge 13 Remote Fault 5 12 4 11 3 10 Technology Ability Field 2 Protocol Selector Field 9 1 8 0
15 Next Page 7
6 Technology Ability Field
BIT 15
NAME Next Page
TYPE Read/Write 0
RESET
DESCRIPTION When set, this bit enables the ability to exchange Next-Pages with the link partner. This bit should be cleared if it is not desired to engage in Next Page exchange. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, this bit indicates consistent reception of the link partner's data. This bit may be used to indicate a fault condition to the link partner. Setting this bit will signal to the link partner that a fault condition has occurred. This field determines the advertised capabilities of the CS8952 as shown below. When the bit is set, the corresponding technology will be advertised during auto-negotiation. BIT Capability 12 Reserved 11 Reserved 10 PAUSE operation for full duplex links. Set only if supported by the host MAC. 9 100BASE-T4 (Note: this technology is not supported and can not be set. 8 100BASE-TX Full Duplex 7 100Base-TX Half Duplex 6 10BASE-T Full Duplex 5 10BASE-T Half Duplex This field is used to identify the type of message being sent by auto-negotiation. This field defaults to a value of "00001" for IEEE 802.3 messages.
14 13
Acknowledge Remote Fault
Read Only
0
Read/Write 0
12:5
Technology Ability Field
Read/Write 0000 1111
4:0
Protocol Selector Field
Read/Write 0 0001
38
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.6 Auto-Negotiation Link Partner Ability Register - Address 05h
14 Acknowledge 13 Remote Fault 5 12 4 11 3 10 Technology Ability Field 2 Protocol Selector Field 9 1 8 0
15 Next Page 7
6 Technology Ability Field
BIT 15 14 13
NAME Next Page Acknowledge Remote Fault
TYPE Read Only Read Only Read Only
RESET 0 0 0
12:5
Technology Ability Field
Read Only
0000 0000
4:0
Protocol Selector Field
Read Only
0 0000
DESCRIPTION When set, this bit indicates that the link partner is capable of participating in the Next Page exchange. When set, this bit indicates that the link partner has received consistent data from the CS8952. This bit indicates that a fault condition occurred on the far end. When this bit is set and auto-negotiation is enabled, the Remote Fault bit in the Basic Mode Status Register (address 01h) will also be set. This field indicates the advertised capabilities of the link partner as shown below. When the bit is set, the corresponding technology has been advertised during auto-negotiation. BIT Capability 12 Reserved 11 Reserved 10 PAUSE operation for full duplex links. 9 100BASE-T4 (Note: this technology is not 8 100BASE-TX Full Duplex 7 100Base-TX Half Duplex 6 10BASE-T Full Duplex 5 10BASE-T Half Duplex This field is used to identify the type of message being received during auto-negotiation.
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
39
CS8952
6.7 Auto-Negotiation Expansion Register - Address 06h
15 7 14 6 Reserved 13 5 12 Reserved 3 Link Partner Parallel Next Page Detection Fault Able 4 2 Next Page Able 1 Page Received 0 Link Partner Auto-Neg Able 11 10 9 8
BIT 15:5 4
NAME Reserved Parallel Detection Fault
TYPE Read Only Read Only
RESET 000 0000 0000 0
DESCRIPTION When set, this bit indicates an error condition in which both the 10BASE-T and 100BASE-TX links came up valid, or that one of the technologies established a link but was unable to maintain the link. This bit is self-clearing. When set, this bit indicates that the link partner is capable of Next Page exchange. This bit is a status bit which indicates to the Management Layer that the CS8952 supports Next Page capability. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, this bit indicates that a valid word of autonegotiation data has been received and its integrity verified. The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing. When set, this bit indicates that the link partner has auto-negotiation capability.
3 2
Link Partner Next Page Able Next Page Able
Read Only Read Only
0 1
1
Page Received
Read Only
0
0
Link Partner AutoNeg Able
Read Only
0
40
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.8 Auto-Negotiation Next-Page Transmit Register - Address 07h
14 13 12 Acknowledge Message Page Acknowledge 2 6 5 11 Toggle 10 9 8 Message/Unformatted Code Field 2 1 0
15 Next Page 7
4 3 Message/Unformatted Code Field
BIT 15
NAME Next Page
TYPE Read/Write 0
RESET
DESCRIPTION When set, this bit indicates that more Next Pages follow. When clear, the current page is the last page of data to be sent. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. This bit is used for Link Code Word verification. When set, it indicates that consistent data has been successfully read from the link partner. When set, this bit indicates that the data in the Message/Unformatted Code Field is one of the predefined message pages. When low, the data is unformatted data. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, this bit indicates to the link partner that the CS8952 can comply with the last received message. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. This bit is used to maintain synchronization with the link partner during Next Page exchange. This field contains the 11 bit data for the Message or Unformatted Page. It defaults to the Null Message. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
14
Acknowledge
Read Only
0
13
Message Page
Read/Write 1
12
Acknowledge 2
Read/Write 0
11 10:0
Toggle
Read Only
0
Message/Unformat- Read/Write 000 0000 0001 ted Code Field
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
41
CS8952
6.9 Interrupt Mask Register - Address 10h
15 CIM Link Unstable 7 Reset Complete 14 Link Status Change 6 Jabber Detect 13 12 11 DCR Rollover 3 Parallel Fail 10 FCCR Rollover 2 Remote Fault 9 RECR Rollover 1 Page Received 8 Remote Loopback Fault 0 Reserved
Descrambler Premature End Lock Change Error 5 Auto-Neg Complete 4 Parallel Detection Fault
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ pin to be asserted. When clear, the event will not affect the MII_IRQ pin, but the status will still be reported via the Interrupt Status Register (address 11h). BIT 15 NAME CIM Link Unstable TYPE Read/Write 0 RESET DESCRIPTION When set, an interrupt will be generated if an unstable link condition is detected by the Carrier Integrity Monitor function. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated each time the CS8952 detects a change in the link status. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated each time the 100BASE-TX receive descrambler loses or regains synchronization with the far-end. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated when two consecutive IDLES are detected in a 100BASE-TX frame without the ESD sequence. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
14
Link Status Change Read Write 1
13
Descrambler Lock Change
Read/Write 0
12
Premature End Error
Read/Write 0
42
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
BIT 11 NAME DCR Rollover TYPE Read/Write 0 RESET DESCRIPTION When set, an interrupt will be generated if the MSB in the DCR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated if the MSB in the FCCR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated if the MSB in the RECR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated if the elastic buffer in the PMA is under-run or over-run during Remote Loopback. This should not occur for normal length 802.3 frames. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated once the digital and analog sections have been reset, and a calibration cycle has been performed. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated when a Jabber condition is detected by the 10BASE-T MAU. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
10
FCCR Rollover
Read/Write 0
9
RECR Rollover
Read/Write 0
8
Remote Loopback Fault
Read/Write 0
7
Reset Complete
Read/Write 1
6
Jabber Detect
Read/Write 0
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
43
CS8952
BIT 5 NAME TYPE Auto-Neg Complete Read/Write 0 RESET DESCRIPTION When set, an interrupt will be generated once autonegotiation has completed successfully. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated if auto-negotiation determines that unstable legacy link signaling was received. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated when parallel detection has occurred for a technology that is not currently advertised by the local device. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt will be generated if a remote fault condition is detected either by auto-negotiation or by the Far-End Fault Detect state machine. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, an interrupt is generated each time a page is received during auto-negotiation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 0 Reserved Read Only 0
4
Parallel Detection Fault
Read/Write 0
3
Parallel Fail
Read/Write 0
2
Remote Fault
Read/Write 0
1
Page Received
Read/Write 0
44
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.10 Interrupt Status Register - Address 11h
15 CIM Link Unstable 7 Reset Complete 14 Link Status Change 6 Jabber Detect 13 12 11 DCR Rollover 3 Parallel Fail 10 FCCR Rollover 2 Remote Fault 9 RECR Rollover 1 Page Received 8 Remote Loopback Fault 0 Reserved
Descrambler Premature End Lock Change Error 5 Auto-Neg Complete 4 Parallel Detection Fault
This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All bits are selfclearing, and will thus be cleared upon readout. BIT 15 NAME CIM Link Unstable TYPE Read Only RESET 0 DESCRIPTION When set, this bit indicates that an unstable link condition was detected by the Carrier Integrity Monitor function. When set, this bit indicates that a change has occurred to the status of the link. The Self Status Register (address 19h) may be read to determine the current status of the link. When set, this bit indicates that a change has occurred in the status of the descrambler. The Self Status Register (address 19h) may be read to determine the current status of the scrambler lock. This bit is set when a premature end of frame is detected for 100 Mb/s operation. A premature end is defined as two consecutive IDLE patterns detected in a frame prior to the End of Stream Delimiter. This bit is set when the MSB of the Disconnect Count Register (address 12h) becomes set. This should provide ample warning to the management layer so that the DCR may be read before rolling over. This bit is set when the MSB of the False Carrier Count Register (address 13h) becomes set. This should provide ample warning to the management layer so that the FCCR may be read before saturating. This bit is set when the MSB of the Receive Error Count Register (address 15h) becomes set. This should provide ample warning to the management layer so that the RECR may be read before rolling over.
14
Link Status Change Read Only
0
13
Descrambler Lock Change
Read Only
0
12
Premature End Error
Read Only
0
11
DCR Rollover
Read Only
0
10
FCCR Rollover
Read Only
0
9
RECR Rollover
Read Only
0
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
45
CS8952
BIT 8 NAME Remote Loopback Fault TYPE Read Only RESET 0 DESCRIPTION When set, this bit indicates that the Elastic Buffer has detected an over-run or an under-run condition. In any case, the frame generating this fault will be terminated. This should never happen since the depth of the elastic buffer (10 bits) is greater than twice the maximum number of bit times the receive and transmit clocks may slip during a maximum length packet assuming clock frequency tolerances of 100 ppm or less. When set, this bit indicates that the internal analog calibration cycle has completed, and all analog and digital circuitry is ready for normal operation. In 10BASE-T mode, if the last transmission is longer than 105 ms, then the packet output is terminated by the jabber logic and this bit is set. This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this register, a read to the Basic Mode Status Register (address 01h), or a reset. No jabber detect function has been defined for 100BASE-TX. This bit is the same as in the Basic Mode Status Register (address 01h). This bit is set when the auto-negotiation process has completed. This is an indication that the Auto-Negotiation Advertisement Register (address 04h), the Auto-Negotiation Link Partner Ability Register (address 05h), and the Auto-Negotiation Expansion Register (address 06h) are valid. This bit is the same as in the Basic Mode Status Register (address 01h). When set, this bit indicates an error condition in which auto-negotiation has detected that unstable 10BASE-T or 100BASE-TX link signalling was received. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h) When set, this bit indicates that a parallel detection has occurred for a technology that is not currently advertised by the local device.
7
Reset Complete
Read Only
0
6
Jabber Detect
Read Only
0
5
Auto-Neg Complete Read Only
0
4
Parallel Detection Fault
Read Only
0
3
Parallel Fail
Read Only
0
46
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
BIT 2 NAME Remote Fault TYPE Read Only RESET 0 DESCRIPTION When auto-negotiation is enabled, this bit is set if the Remote Fault bit is set in the Auto-Negotiation Link Partner Ability Register (address 05h). When autonegotiation is disabled, this bit will be set when the Far-End Fault Indication for 100BASE-TX is detected. When set, this bit indicates that a valid word of autonegotiation data has been received and its integrity verified. The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h). 0 Reserved Read Only 0
1
Page Received
Read Only
0
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
47
CS8952
6.11 Disconnect Count Register - Address 12h
15 7 14 6 13 5 12 11 Disconnect Counter 4 3 Disconnect Counter 10 2 9 1 8 0
BIT 15:0
NAME TYPE RESET Disconnect Counter Read/Write 0000h
DESCRIPTION This field contains a count of the number of times the CS8952 has lost a Link OK condition. This counter is cleared upon readout and will roll-over to 0000h.
48
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.12 False Carrier Count Register - Address 13h
15 7 14 6 13 5 12 11 False Carrier Counter 4 3 False Carrier Counter 10 2 9 1 8 0
BIT 15:0
NAME False Carrier Counter
TYPE Read Only
RESET 0000h
DESCRIPTION This field contains a count of the number of times the CS8952 has detected a false-carrier -- that is, the reception of a poorly formed Start-of-Stream Delimiter (SSD). The counter is incremented at the end of such events to prevent multiple increments. This counter is cleared upon readout and will saturate at FFFFh.
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
49
CS8952
6.13 Scrambler Key Initialization Register - Address 14h
15 Load 7 14 6 13 Reserved 5 4 3 Scrambler Initialization Key 2 12 11 10 9 8 Scrambler Initialization Key 1 0
DESCRIPTION When this bit is set, the scrambler will be loaded with the value in the Scrambler Initialization Key field. When the load is complete, this bit will clear automatically. 14:11 Reserved Read Only 0000 These bits should be read as don't cares and, when written, should be written to 0. This field allows the Scrambler to be loaded with a 10:0 Scrambler Initializa- Read/Write Reset value is tion Key dependent on the user-definable key sequence. A value of 000h has PHY Address field the effect of bypassing the scrambler function. of the Self Status Register (address This is valuable for testing purposes to allow a deterministic response to test stimulus without a synchro19h). nization delay. Load 0 Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
BIT 15
NAME
TYPE Read/Set
RESET
50
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.14 Receive Error Count Register - Address 15h
15 7 14 6 13 5 12 11 Receive Error Counter 4 3 Receive Error Counter 10 2 9 1 8 0
BIT 15:0
NAME Receive Error Counter
TYPE Read Only
RESET 0000h
DESCRIPTION This counter increments for each packet in which one or more receive errors is detected that is not due to a collision event. This counter is cleared upon readout and will roll-over to 0000h.
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
51
CS8952
6.15 Descrambler Key Initialization Register - Address 16h
15 Load 7 14 6 13 Reserved 5 4 3 Descrambler Initialization Key 12 11 10 9 8 Descrambler Initialization Key 2 1 0
DESCRIPTION When this bit is set, the descrambler will be loaded with the value in the Descrambler Initialization Key field. When the load is complete, this bit will clear automatically. 14:11 Reserved Read Only 0000 These bits should be read as don't cares and, when written, should be written to 0. This register allows the Descrambler to be loaded 10:0 Descrambler Initial- Read/Write Reset value is ization Key dependent on the with a user-definable key sequence. A value of 000h PHY Address field has the effect of bypassing the descrambler function. of the Self Status Register (address This is valuable for testing purposes to allow a deterministic response to test stimulus without a synchro19h). nization delay. Load 0 Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
BIT 15
NAME
TYPE Read/Set
RESET
52
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.16 PCS Sub-Layer Configuration Register - Address 17h
15 NRZI Enable 14 Time-Out Select 13 Time-Out Disable 5 CIM Disable 12 Repeater Mode 4 Tx Disable 11 LED5 Mode 3 Rx Disable 10 Unlock Regs 2 LED1 Mode 9 MR Preamble Enable 1 LED4 Mode 8 Fast Test 0 Digital Reset
7 6 CLK25 Disable Enable LT/100
BIT 15
NAME NRZI Enable
TYPE Read/Write 1
14
Time-Out Select
13
Time-Out Disable
12
Repeater Mode
11
LED5 Mode
DESCRIPTION When this bit is set, the NRZI encoder and decoder are enabled. When this bit is clear, NRZI encoding and decoding are disabled. Read/Write 0 When this bit is set, the time-out counter in the receive descrambler is set to time-out after 2 ms without IDLES. When clear the counter is set to timeout after 722 s without IDLES. Read/Write 0 When this bit is set, the time-out counter in the receive descrambler is disabled. When this bit is clear, the time-out counter is enabled. Read/Write Reset to the value This bit defines the mode of the Carrier Sense (CRS) on the signal. When this bit is set, CRS is asserted due to REPEATER pin. receive activity only. When this bit is clear, CRS is asserted due to either transmit or receive activity. Read/Write 0 This bit defines the mode of Pin LED5. When this bit is set, pin LED5 indicates the synchronization status of the 100BASE-TX descrambler. When this bit is clear, LED5 indicates a collision. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, this bit unlocks certain read only control registers for factory testing. Leave clear for proper operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
RESET
10
Unlock Regs
Read/Write 0
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
53
CS8952
BIT 9 NAME MF Preamble Enable TYPE Read/Write 0 RESET DESCRIPTION When set, this bit will force all management frames (via MDIO, MDC) to be preceded by a 32 bit preamble pattern of contiguous ones to be considered valid. When cleared, it allows management frames with or without the preamble pattern. The status of this register is (inversely) reflected in the MF Preamble bit in the Basic Mode Status Register (address 01h). Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When set, internal timers are sped up significantly in order to facilitate production test. Leave clear for proper operation.
8
Fast Test
Read/Write 0
7
CLK25 Disable
Read/Write
6
Enable LT/100
Read/Write
5
CIM Disable
Read/Write
4
Tx Disable
Read/Write
Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. When TCM pin is Setting this bit will disable (tri-state) the CLK25 output pin, reducing digital noise and power consumplow, reset to 1; otherwise, reset to tion. 0 1 When set, normal link status checking is enabled. When clear, this bit forces the link status to Link OK (at 100 Mb/s), and will assert the LINK_OK LED. Reset to the logic When set, this bit forces the Carrier Integrity Monitor function to be disabled. When low, the Carrier Integinverse of the rity Monitor function is enabled, and detection of an value on the REPEATER pin. unstable link will disable the receive and transmit functions. 0 When set, this bit forces the 10 Mb/s and 100 Mb/s outputs to be inactive. When clear, normal transmission is enabled. If Tx Disable is set while a packet is being transmitted, transmission is completed and no subsequent packets are transmitted until Tx Disable is cleared again. Also, if Tx Disable is cleared while TX_EN is high, the transmitter will remain disabled until TX_EN is deasserted. This prevents fragments from being transmitted onto the network.
54
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
BIT 3 NAME Rx Disable TYPE Read/Write 0 RESET DESCRIPTION When set, the receiver is disabled and no incoming packets pass through the receiver. The link will remain established and, if operating at 100 Mb/s, the descrambler will remain locked. When clear, the receiver is enabled. If Rx Disable is set while a packet is being received, reception is completed and no subsequent receive packets are allowed until Rx Disable is cleared again. Also, if Rx Disable is cleared while a packet is being received, the receiver will remain disabled until the end of the incoming packet. This prevents fragments from being sent to the MAC. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. This bit defines the mode of Pin LED1. When this bit is set, pin LED1 indicates Carrier Integrity Monitor status as determined by the CIM Status bit in the Self Status Register (address 19h). When this bit is clear, LED1 indicates 10 Mb/s or 100 Mb/s transmission activity. This bit defines the mode of Pin LED4. When this bit is set, pin LED4 indicates full duplex mode for 10 Mb/s or 100 Mb/s. When this bit is clear, LED4 indicates Polarity in 10 Mb/s mode or full-duplex in 100 Mb/s mode. When set, this bit will reset all digital logic and registers to their initial values. The analog circuitry will not be affected. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
2
LED1 Mode
Read/Write 0
1
LED4 Mode
Read/Write 0
0
Digital Reset
Read/Write 0
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
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CS8952
6.17 Loopback, Bypass, and Receiver Error Mask Register - Address 18h
15 Bad SSD Enable 7 Strip Preamble 14 Bypass 4B5B 6 Alternate FDX CRS 13 Bypass Scrambler 5 Loopback Transmit Disable 12 Bypass Symbol Alignment 4 11 ENDEC Loopback 10 FX Drive 9 Remote Loopback 8 PMD Loopback
3 2 1 0 Premature End Link Error Packet Error Code Error Code Error Error Report Report Enable Report Enable Report Enable Report Select Select
BIT 15
NAME Bad SSD Enable
TYPE Read/Write 1
RESET
DESCRIPTION When set, this bit enables the reporting of a bad SSD (False-Carrier event) on the MII. These events will be reported by setting RX_ER=1, RX_DV=0, and RXD[3:0]=1110.
14
Bypass 4B5B
Read/Write
13
Bypass Scrambler
Read/Write
12
Bypass Symbol Alignment
Read/Write
11
ENDEC Loopback
Read/Write
10
FX Drive
Read/Write
9
Remote Loopback
Read/Write
If the 4B5B encoders are being bypassed, this event will be reported by setting RX_DV=0 and RXD[4:0]=11110. If symbol alignment is bypassed, the CS8952 does not detect carrier, and thus will not report bad SSD events. Reset to the value When set, this bit causes the receive 5B4B decoder on the BP4B5B and the transmit 4B5B encoder to be bypassed. pin. Reset to the value When set, this bit causes the receive descrambler and the transmit scrambler blocks to be bypassed, on the BPSCR and the CS8952 accepts NRZI data from an external pin. 100BASE-FX optical module through pins RX_NRZ+ and RX_NRZ-. Reset to the value When set, this bit causes the following functions to on the BPALIGN be bypassed: receiver descrambling, symbol alignment and decoding, transmit symbol encoding, and pin. transmit scrambling. 0 When set, the 10BASE-T internal Manchester encoder output is connected to the decoder input. When clear, the CS8952 is configured for normal operation. 0 This bit controls the drive strength of the 100BASEFX PECL interface drivers. When clear, the drivers are optimized for a 50 load. When set, the drivers are optimized for a 150 load. 0 When set, data received from the link is looped back at the MII and sent back out to the link. Received data will be presented on the MII pins. Transmit data at the MII will be ignored. Note: Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done.
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CS8952
BIT 8 NAME PMD Loopback TYPE Read/Write 0 RESET DESCRIPTION When set, the scrambled NRZI transmit data is connected directly to the NRZI receive port on the descrambler. The loopback includes all of the 100BASE-TX functionality except for the MLT-3 encoding/decoding and the analog line-interface blocks. When clear, the CS8952 is configured for normal operation. Note: Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done. When set this bit causes the 7 bytes of MAC preamble to be stripped off of incoming 100 Mb/s frames. The data received across the MII will begin with the 1 byte Start of Frame Delimiter (SFD). Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. This bit changes the behavior of the CRS pin only in the full-duplex (FDX) mode of operation. When set, CRS will be asserted for transmit data only. When clear, CRS will be asserted only for receive data. This bit controls whether loopback data is transmitted onto the network. When set, any data transmitted during PMD or ENDEC loopback mode will NOT be transmitted onto the network. When clear, data will be transmitted on the TX+/- pins as well as looped back onto the MII pins. When set, this bit causes code errors to be reported by a value of 5h on RXD[3:0] and the assertion of RX_ER. When clear, this bit causes code errors to be reported by a value of 6h on RXD[3:0] and the assertion of RX_ER. This bit is superseded by the Code Error Report Enable bit. When set, this bit causes premature end errors to be reported by a value of 4h on RXD[3:0] and the assertion of RX_ER. When clear, this bit causes premature end errors to be reported by a value of 6h on RXD[3:0] and the assertion of RX_ER. A premature end error is caused by the detection of two IDLE symbols in the 100 Mb/s receive data stream prior to the End of Stream Delimiter.
7
Strip Preamble
Read/Write 0
6
Alternate FDX CRS Read/Write 0
5
Loopback Transmit Read/Write 1 Disable
4
Code Error Report Select
Read/Write 0
3
Premature End Read/Write 0 Error Report Select
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
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CS8952
BIT 2 NAME Link Error Report Enable TYPE Read/Write 0 RESET DESCRIPTION When set, this bit causes link errors to be reported by a value of 3h on RXD[3:0] and the assertion of RX_ER. When clear, link errors are not reported across the MII. When set, this bit causes packet errors to be reported by a value of 2h on RXD[3:0] and the assertion of RX_ER. When clear, packet errors are not reported across the MII. When set, code errors are reported and transmitted on RXD[3:0]. When clear, this bit enables the Code Error Report values on RXD[3:0] as selected by the Code Error Report Select bit and also causes the assertion of TX_ER to transmit a HALT code group. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
1
Packet Error Report Read/Write 0 Enable
0
Code Error Report Enable
Read/Write 0
58
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.18 Self Status Register - Address 19h
15 Link OK 7 Full Duplex 14 Power Down 6 10BASE-T Mode 13 Receiving Data 5 CIM Status 12 Descrambler Lock 4 11 Disable CRS on Time-out 3 10 Auto-Neg Enable Status 2 PHY Address 9 PAUSE 1 8 FEFI Enable 0
BIT 15
NAME Link OK
TYPE Read Only
RESET 0
14 13
Power Down Receiving Data
Read Only Read Only
1 0
12
Descrambler Lock
Read Only
0
11
Disable CRS on Time-out
Read/Write Reset to the logic inverse of the value on the REPEATER pin. Read Only If auto-negotiation is enabled via the AN[1:0] pins, reset to 1; otherwise, reset to 0. 0
10
Auto-Neg Enable Status
9
PAUSE
Read Only
8
FEFI Enable
Read/Write 0
7
Full Duplex
Read Only
6
10BASE-T Mode
Read Only
If a full duplex mode is enabled via the AN[1:0] pins, reset to 1; otherwise, reset to 0. 0 When set, this bit indicates that the CS8952 has been configured for 10 Mb/s operation.
DESCRIPTION When set, this bit indicates that a valid link connection has been detected. The type of link established may be determined from bits 6, 7, and 9. When clear, this bit indicates that a valid link connection does not exist. This bit may be used to determine the current status of the link. When high, this bit indicates that the CS8952 is in a low power state. This bit is high whenever the CS8952 is receiving valid data. It is a direct copy of the state of the RX_DV pin accessible by software. When high, this bit indicates that the descrambler has successfully locked to the scrambler seed of the far-end transmitter and is able to descramble received data. This bit controls the state of the CRS pin upon a descrambler time-out. When set, CRS will be forced low upon a descrambler time-out, and will not be released until the descrambler has re-acquired synchronization. This bit reflects the value of bit 12 in the Basic Mode Control Register (address 00h). When set, it indicates that auto-negotiation has been enabled. When clear, this bit indicates that the mode of the CS8952 has been forced to that indicated by bits 6, and 7. When set, this bit indicates that the Flow-Control PAUSE function has been negotiated. This indicates that both the local device and the link partner have advertised this capability. This bit controls the Far-End Fault Generate and Detect state machines. When this bit is set and autonegotiation is disabled (bit 10 is clear), both state machines are enabled. When clear, this bit disables both state machines. When set, this bit indicates that the CS8952 has been configured for Full-Duplex operation.
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CS8952
BIT 5 DESCRIPTION When clear, this bit indicates that a stable link connection has been detected. When an unstable link is detected and the Carrier Integrity Monitor Disable bit in the PCS Sub-Layer Configuration Register (address 17h) is clear, this bit is set and latched. It will remain set until this register is read. PHY Address Field Read/Write Reset to the val- The value on pins PHYAD[4:0] are latched into this ues on the field at power-up or reset. These bits define the PHY PHYAD[4:0] pins. address used by the management layer to address the PHY. The external logic must know this address in order to select this particular CS8952's registers individually via the MDIO and MDC pins. 0 NAME CIM Status TYPE Read Only RESET
4:0
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
6.19 10BASE-T Status Register - Address 1Bh
15 14 13 Reserved 7 6 5 4 Reserved 3 12 11 10 Polarity OK 2 9 10BASE-T Serial 1 8 Reserved 0
BIT NAME 15:11 Reserved 10 Polarity OK
TYPE Read Only Read Only
9
10BASE-T Serial
8:0
Reserved
When high, the polarity of the receive signal (at the RXD+/RXD- inputs) is correct. If clear, the polarity is reversed. If the Polarity Disable bit of 10BASE-T Configuration Register (address 1Ch) is clear, then the polarity is automatically corrected, if needed. The Polarity OK status bit shows the true state of the incoming polarity independent of the Polarity Disable bit. Read/Write Reset to the value When set, this bit selects 10BASE-T serial mode. on the 10BT_SER When low, this bit selects 10BASE-T nibble mode. pin. This bit will only affect the CS8952 if it has been configured for 10 Mb/s operation. Read Only 0 0000 0000
RESET 0 0000 0
DESCRIPTION
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
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CS8952
6.20 10BASE-T Configuration Register - Address 1Ch
15 7 National Compatibility Mode 14 6 LED3 Blink Enable 13 5 Enable LT/10 12 Reserved 4 SQE Enable 3 Reserved 2 Low Rx Squelch 1 Polarity Disable 0 Jabber Enable 11 10 9 8
BIT 15:8 7
NAME Reserved National Compatibility Mode
TYPE RESET Read Only 0000 0000 Read/Write 1
DESCRIPTION When set, registers and bits that are not compatible with the National DP83840 are disabled and writes to these registers are ignored. When set, LED3 will blink during auto-negotiation and will indicate Link Good status upon completion of auto-negotiation. When clear, LED3 indicates Link Good status only. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit (bit 7) is set. When set, this bit enables the transmission of link pulses.
6
LED3 Blink Enable Read/Write 0
5
Enable LT/10
Read/Write 1
4
SQE Enable
3 2
Reserved Low Rx Squelch
1
Polarity Disable
When clear, link pulses are disabled and a good link condition is forced. If link pulses are disabled during 100 Mb/s operation with auto-negotiation enabled, the CS8952 will go into 10 Mb/s mode. If operating in 100 Mb/s mode with no auto-negotiation, then clearing this bit has no effect. Read/Write Reset to the logic When set, and if the CS8952 is in half-duplex mode, this bit enables the 10BASE-T SQE function. When inverse of the the part is in repeater mode, this bit is cleared and value on the REPEATER pin. may not be set. Read Only 1 This bit should be read as a don't care and, when written, should be written to 1. Read/Write 0 When clear, the 10BASE-T receiver squelch thresholds are set to levels defined by the ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approximately 6 dB. This is useful for operating with "quiet" cables that are longer than 100 meters. Read/Write 0 The 10BASE-T receiver automatically determines the polarity of the received signal at the RXD+/RXDinput. When this bit is clear, the polarity is corrected, if necessary. When set, no effort is made to correct the polarity. Polarity correction will only be performed during 10BASE-T packet reception. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit (bit 7) is set.
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
BIT 0 NAME Jabber Enable TYPE Read/Write 1 RESET DESCRIPTION When set, the jabber function is enabled. When clear, and if the CS8952 is in 10BASE-T full-duplex or 10BASE-T ENDEC loopback mode, the jabber function is disabled. Note: When the National Compatibility Mode bit (bit 7) is set, the Jabber function may also be disabled for 10BASE-T half-duplex, although this is not recommended.
7. DESIGN CONSIDERATIONS
The CS8952 is a mixed-signal device containing the high-speed digital and analog circuits required to implement Fast Ethernet communication. It is important the designer adhere to the following guidelines and recommendations for proper and reliable operation of the CS8952. These guidelines will also benefit the design with good EMC performance.
and TX input circuits to the DC-isolated ground plane. The 0.01 F capacitor C1 must provide 2KV (1,500 Vrms for 60 seconds) of isolation to meet 802.3 requirements. If a shielded RJ45 connector is used (recommended), the shield should be connected to chassis ground.
7.2
100BASE-FX Interface
7.1
Twisted Pair Interface
The recommended connection of the twisted-pair interface is shown if Figure 6. The unused cable pairs are terminated to increase the common-mode performance. Common-mode performance is also improved by connecting the center taps of the RX
Figure 7 shows the recommended connection for a 100BASE-FX interface to a Hewlett-Packard HFBR-5103 fiber transceiver. Termination circuitry may need to be revised for other fiber transceivers. The FX Drive bit in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) may be used to tailor the PECL interface for 50 or 150 loads.
T1 TG22-3506
TX+
CS8952
80
16
14
10
12
TXRX+
81 91
15 2
11 6 5
51 51
1 2 3 4 5 6
SHLD
RJ-45
51 51 75 51 51
7
8
RX-
92
1
7
SHLD
49.9
0.1 F
49.9
0.1 F
3 NC
75
0.01 F
2KV
Figure 6. Recommended Connection of Twisted-Pair Ports (Network Interface Card) CrystalLANTM 100BASE-X and 10BASE-T Transceiver 63
CS8952
+5
CS8952
68 8 9 191
82
HFBR-5103 FIBER TRANS.
SIGNALSIGNAL+
4 130 +5 1 H Ferrite Bead 5 +5
0.1 F 0.1 F
SD
RxVCC
0.1 F
63.4
1 H Ferrite Bead 6 TxVCC
49.9 TX_NRZTX_NRZ+ 4 5 +5
49.9
0.1 F
0.1 F 7 8 TDTD+
82 RX_NRZRX_NRZ+ 6 7 130
82 3 2 130 1 9 RDRD+ RxVEE TxVEE
Figure 7. Recommended Connection of Fiber Port
TX_NRZ+/- termination components should be placed as close to the fiber transceiver as possible, while RX_NRZ+/- and SIGNAL+/- termination components should be placed close to the CS8952. The CS8952 100BASE-FX interface IO pins (TX_NRZ+, TX_NRZ-, RX_NRZ+, RX_NRZ-, SIGNAL+, and SIGNAL-) may be left unconnected if a fiber interface is not used.
tor biases the internal analog circuits of the CS8952 and should be placed as close as possible to RES pin. Connect the other end of this resistor directly to the ground plane. Connect the adjacent CS8952 ground pins (pins 85 and 87) to the grounded end of the resistor forming a "shield" around the RES connection.
7.4
Clocking Schemes
7.3
Internal Voltage Reference
A 4.99 k biasing resistor must be connected between the CS8952 RES pin and ground. This resis64
The CS8952 may be clocked using one of three possible schemes: using a 25 MHz crystal and the internal oscillator, using an external oscillator sup-
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
with transformers meeting these requirements. However, the designer should evaluate the magnetics for suitability in their specific design.
CS8952
VSS RES VSS
87 86 85 4.99 k Via to Ground Plane
7.6
Power Supply and Decoupling
Figure 8. Biasing Resistor Connection and Layout
plied through the XTAL_I pin, or using an external clock source supplied through the TX_CLK pin. When a 25 MHz crystal is used, it should be placed within one inch of the XTAL_I and XTAL_O pins of the CS8952. The crystal traces should be short, have no vias, and run on the component side. Table 7 lists examples of manufacturers of suitable crystals. The designer should evaluate their crystal selection for suitability in their specific design. An external CMOS clock source may be connected to the XTAL_I pin, with the XTAL_O pin left open. The input capacitance of the XTAL_I pin is larger than the other inputs (a maximum of 35pF), since it includes the additional load capacitance of the crystal oscillator. Care should be taken to assure any external clock source attached to XTAL_I is capable of driving higher capacitive loads. The clock signal should be 25 MHz 0.01% with a duty cycle between 45% and 55%. When the XTAL_I pin load is a problem, or only a TTL level clock source is available, the CS8952 can be clocked through the TX_CLK pin, providing the TX_CLK mode is set appropriately using the TCM pin. The clock frequency will be dependent on the operating mode.
The CS8952 supports connection to either a 3.3 V or 5.0 V MII. When connected to a +5.0 V MII, all power pins should be provided +5.0 V +/- 5%, and all signal inputs should be referenced to +5.0V. When interfaced with a 3.3 V MII, VDD_MII power pins should be provided +3.3 V +/- 5%, VDD power pins should be provided +5.0 V +/- 5%, and all signal inputs should be referenced to +3.3 V.
Component Manufacturer
Raltron Electronics Corp. 10651 NW 19th St. Miami, FL 33172 Crystal (305) 593-6033 www.raltron.com Halo Electronics, Inc. P.O. Box 5826 Redwood City, CA 94063 USA (650) 568-5800 www.haloelectronics.com Bel Fuse, Inc. 198 Van Vorst Street Jersey City, NJ 07302 Transformer USA (201) 432-0463 www.belfuse.com Pulse Engineering 12220 World Trade Drive San Diego, CA 92128 USA (619) 674-8100 www.pulseeng.com Hewlett Packard Component Sales Fiber Response Center Interface (408) 654-8675 www.hp.com/HP-COMP
Part Number AS-25.000-15-FEXT-SMD-TRCIR TG22-3506ND
S5558-5999-46
PE-68515
HFBR-5103
Table 7. Support Component Manufactures
7.5
Recommended Magnetics
The CS8952 requires an isolation transformer with a 1:1 turns ratio for both the transmit and receive signals. Table 7 lists examples of manufacturers
Each CS8952 power pin should be connected to a 0.1 F bypass capacitor and then to the power plane. The bypass capacitors should be located as close to its corresponding power pin as possible. Connect ground pins directly to the ground plane.
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
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CS8952
7.7 General Layout Recommendations
transmission lines (100 differential, 50 single-ended). The MII signals should be 68 microstrip transmission lines. (For short MII signal paths one may standardize on a given trace width for all traces without significant degradation in signal integrity.) * Avoid routing traces other than the TX and RX signals under transformer T1 and the RJ45 connector. Signals may run on the bottom side underneath the CS8952 as long as they stay away from critical analog traces. Connect all CS8952 ground and power pins directly to the ground and power planes, respectively. Note: The VDD_MII power pins may need their own power plane or plane segment in +3.3 V MII applications. Depending on the orientation and location of the transformer, the CS8952, and the RJ-45, and on whether the application is for a NIC or a switch, the RX and TX pairs may need to cross. This should be done by changing layers on a pair by pair basis only, using the minimum number of vias, and making sure that each trace within a pair "sees" the same path as its peer. Figure 6 shows the CS8952 in a NIC or adapter configuration. It may be configured for a hub or repeater application by changing the wiring to the RJ-45 as shown in Table 8. * Differential pair transmission lines should be routed close together (one trace width spacing edge-to-edge) and kept at least two trace widths away from other traces, components, etc. TX and RX pairs should be routed away from each other and may use opposite sides of the PCB as necessary, Each member of the differential pair should "see" the same PCB terrain as its peer. Unused spaces on the signal layers should be filled with ground fill (pour). Vias should connect the ground patches to the ground plane. This is especially recommended (symmetrical-
The following PCB layout recommendations will help ensure reliable operation of the CS8952 and good EMC performance. * Use a multilayer Printed Circuit Board with at least one ground and one power plane. A typical +5V MII application would be as follows: Layer 1: (top) Components and first choice signal routing Layer 2: Ground Layer 3: Power (+5V) Layer 4: (bottom) Second choice signal routing, bypass components Place transformer TI as close to the RJ45 connector as possible with the secondary (network) side facing the RJ45 and the primary (chip) side facing the analog side (pins 76-100) of CS8952. Place the CS8952 in turn as close to T1 as possible. Use the bottom layer for signal routing as a second choice. You may place all components on the top layer. However, bypass capacitors are optimally placed as close to the chip as possible and may be best located underneath the CS8952 on the bottom layer. Termination components at the RJ-45 and fiber transceiver may also be optimally placed on the bottom layer. Connect a 0.1 F bypass capacitor to each CS8952 VDD and VDD_MII pin. Place it as close to its corresponding power pin as possible and connect the other lead directly to the ground plane. The 4.99K reference resistor should be placed as close to the RES pin as possible. Connect the other end of this resistor to the ground plane using a via. Connect the adjacent VSS pins (pins 85 and 87) to the grounded end of the resistor forming a shield as illustrated in Figure 8. Controlled impedance is necessary for critical signals TX+/-, RX+/-, TX_NRZ+/-, and RX_NRZ+/-. These should be run as microstrip *
*
*
*
*
*
*
*
66
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
ly) on both sides of the TX+/- traces.
CS8952 Pin Assignment 91 (RX+) 92 (RX-) 81 (TX-) 80 (TX+) T1 Primary Pin T1 Secondary Assignment Pin Assignment 1 (RX+) 2 (RX-) 16 (TX-) 15 (TX+) 7 (RX+) 6 (RX-) 10 (TX-) 11 (TX+) Table 8. RJ-45 Wiring RJ-45 Pin Assignment Adapter/NIC Configuration 3 (RD+) 6 (RD-) 2 (TD+) 1 (TD+) Hub/Repeater Configuration 1 (RD+) 2 (RD-) 6 (TD-) 3 (TD+)
*
No signal current carrying planes, i.e. no ground or power plane, should be present underneath the region between the transformer secondary (network) side and the RJ-45. However, a chassis plane may be added in this region to pick up the metal tabs of a shielded RJ45. This chassis plane should be separated from the ground and power planes by at least 50 mils. That is, all other ground and power planes should be "cookie cuttered" so they are voided in the area of the chassis plane. Generally speaking, parts should not cross the moat except for the transformer. Proper termination practices must be used with all transmission lines, especially if sending and receiving high speed signals on and off the board. Series terminations must be kept close to the source and load terminations close to the load. Thus the TX_NRZ+/- termination components must be kept close to the fiber optic
transceiver, and the RX_NRZ+/- and SIGNAL+/- termination components must be kept close to the CS8952. * Locate the crystal as close to the CS8952 as possible, running short traces on the component side in order to reduce parasitic load capacitance. Add bulk capacitance at each connector where power may be supplied. For example, MII power may be provided at the MII connector and at a separate connector for test purposes. If so, and the two connectors are not adjacent, then the bulk capacitors should be duplicated in each locations. Use wide traces to connect the "Bob Smith" termination resistors at T1 and the RJ-45 to the 2 KV capacitor or capacitors in order to minimize their lead inductance.
*
*
*
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CS8952
8. PIN DESCRIPTIONS
Pin Diagram
VDD RSVD RSVD XTAL_O XTAL_I VSS VDD VSS RXRX+ VSS VDD VDD VSS RES VSS RSVD VSS VDD TXTX+ VDD VSS RSVD RSVD VSS VDD VSS TX_NRZTX_NRZ+ RX_NRZRX_NRZ+ SIGNALSIGNAL+ VSS VDD VSS VSS RX_EN RESET REPEATER CLK25 VSS VDD VSS VDD_MII VSS 10BT_SER TEST0 TEST1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CS8952 100-pin TQFP (14 mm x 14 mm)
68
MII_IRQ MDIO MDC RXD3/PHYAD3 RXD2 RXD1/PHYAD1 RXD0 RX_DV/MII_DRV VDD_MII VSS RX_CLK RX_ER/RXD4/PHYAD4 TX_ER/TXD4 VSS VDD VSS TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL/PHYAD0 CRS/PHYAD2 LPSTRT
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RSVD RSVD LED5 LED4 LED3 LED2 LED1 SPD10 SPD100 VDD_MII VSS PWRDN ISODEF BPSCR TXSLEW1 TXSLEW0 TCM AN1 AN0 BP4B5B VSS VDD VSS BPALIGN LPBK
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CS8952
MII Interface Pins COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48.
Asserted active-high to indicate a collision on the medium during half-duplex operation. In full-duplex operation, COL is undefined and should be ignored. When configured for 10 Mb/s operation, COL is also used to indicate a Signal Quality Error (SQE) condition. At power-up or at reset, the logic value on this pin is latched into bit 0 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-up (> 150 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
CRS/PHYAD2 - Carrier Sense/PHY Address 2. Input/Tri-State Output, Pin 49.
The operation of CRS is controlled by the REPEATER pin as follows: REPEATER pin high low low DUPLEX mode don't care full duplex half duplex CRS Indicates receive activity only receive activity only receive or transmit activity
At power-up or at reset, the logic value of this pin is latched into bit 2 of the PHY Address Field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
MDC - Management Data Clock. Input, Pin 28.
Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67 MHz. This clock may be asynchronous to RX_CLK and TX_CLK.
MDIO - Management Data Input/Output. Bi-Directional, Pin 27.
Bi-directional signal used to transfer management data between the CS8952 and the Ethernet controller. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the MDIO pin should have an external 1.5 K pull-up resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external pull-up resistor may not be necessary.
MII_IRQ - MII Interrupt. Open Drain Output, Pin 26.
Asserted low to indicate the status corresponding to one of the unmasked interrupt status bits in the Interrupt Status Register (address 11h) has changed. It will remain low until the ISR is read, clearing all status bits. This open drain pin requires a 4.7 k pull-up resistor.
RX_CLK - Receive Clock. Tri-State Output, Pin 36
Continuous clock output used as a reference clock for sampling RXD[3:0], RX_ER, and RX_DV. RX_CLK will have the following nominal frequency: Speed 100 Mb/s 10 Mb/s 10 Mb/s 10BT_SER pin n/a low (parallel) high (serial) Nominal frequency 25 MHz 2.5 MHz 10 MHz
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
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CS8952
In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_CLK pin should have an external 33 series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistor may not be necessary.
RX_DV/MII_DRV - Receive Data Valid/MII Drive Strength. Input/Tri-State Output, Pin 33.
Asserted high to indicate valid data nibbles are present on RXD[3:0]. At power-up or at reset, this pin is used as an input to determine the drive strength of the MII output drivers. When the pin is low, all MII output drivers will be standard 4 mA CMOS drivers. When high, additional drive strength will be added to the MII output drivers. This pin includes a weak internal pulldown (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, this pin should be pulled high during power-up or reset and should have an external 33 series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, it may be possible to reduce overall power consumption by pulling the pin low at power-up or reset, and the external series resistor may not be necessary.
RX_EN - Receive Enable. Input, Pin 14.
When high, signals RXD[3:0], RX_CLK, RX_DV, and RX_ER are enabled. When low, these signals are tri-stated. RX_EN allows the received data signals of multiple PHY transceivers to share the same MII bus. This pin includes a weak internal pull-up (> 150 K), or the value may be set by an external 10 K pullup or pull-down resistor.
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RX_ER/PHYAD4/RXD4 - Receive Error/PHY Address 4/Receive Data 4. Input/Tri-State Output, Pin 37.
During normal MII operation, this pin is defined as RX_ER (Receive Error). When RX_DV is high, RX_ER asserted high indicates that an error has been detected in the current receive frame. When RX_DV is low and RXD[3:0] = "1110", RX_ER high indicates a False Carrier condition. If either BPALIGN or BP4B5B is asserted, then this pin is re-defined as RXD4 (Receive Data 4), the most-significant bit of the received five-bit code-group. If the 4B5B encoder is being bypassed, receive data is present when RX_DV is asserted. If alignment is being bypassed, data reception is continuous. At power-up or at reset, the logic value on this pin is latched into bit 4 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_ER pin should have an external 33 series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistor may not be necessary.
RXD3/PHYAD3 - Receive Data 3/PHY Address 3. Tri-State Output, Pin 29. RXD2 - Receive Data 2. Tri-State Output, Pin 30. RXD1/PHYAD1 - Receive Data 1/PHY Address 1. Tri-State Output, Pin 31. RXD0 - Receive Data 0. Tri-State Output, Pin 32.
Receive data output. Receive data is present when RX_DV is asserted. RXD0 is the least-significant bit. For MII modes, nibble-wide data (synchronous to RX_CLK) is transferred on pins RXD[3:0]. In 10 Mb/s serial mode, pin RXD0 is used as the serial output pin, and RXD[3:1] are ignored. When either BP4B5B or BPALIGN is selected, pin RXD4 contains the most-significant bit of the five-bit code-group. At power-up or at reset, the value on RXD1/PHYAD1 is latched into bit 1 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor. At power-up or at reset, the logic value on RXD3/PHYAD3 is latched into bit 3 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RXD[3:0] pins should have external 33 series resistors. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistors may not be necessary.
TX_CLK - Transmit Clock. Input/Tri-State Output, Pin 42.
Continuous clock signal used by the CS8952 as a reference clock to sample TXD[3:0], TX_ER, and TX_EN. TX_CLK can be referenced either internally (Output Mode) or externally (Input Mode) based upon the value of the TCM pin at power-up or at reset. TCM pin high floating low TX_CLK mode TX_CLK is input TX_CLK is input TX_CLK is output CLK25 status CLK25 pin is an output CLK25 is disabled CLK25 is disabled
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When the TCM pin is high on power-up or reset, the CLK25 pin may be used as a source for the TX_CLK pin. When the TCM pin is floating on power-up or reset, TX_CLK must be supplied externally. TX_CLK should have the following nominal frequency: Speed 100 Mb/s 10 Mb/s 10 Mb/s 10BT_SER pin n/a low (parallel) high (serial) Nominal frequency 25 MHz 2.5 MHz 10 MHz
TX_EN - Transmit Enable. Input, Pin 43.
Asserted high to indicate valid data nibbles are present on TXD[3:0]. When BPALIGN is selected, TX_EN must be pulled up to VDD_MII.
TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38.
When high, TX_ER indicates to the CS8952 that a transmit error has occurred. If TX_ER is asserted simultaneously with TX_EN in 100 Mb/s mode, the CS8952 will ignore the data on the TXD[3:0] pins and transmit one or more 100 Mb/s HALT symbols in its place. In 10 Mb/s mode, TX_ER has no effect on the transmitted data. If BP4B5B or BPALIGN are set, TX_ER/TXD4 is used to transmit the most-significant bit of the five-bit code group.
TXD[3:0] - Transmit Data. Input, Pins 47, 46, 45, and 44.
Transmit data input pins. For MII modes, nibble-wide data (synchronous to TX_CLK) must be presented on pins TXD[3:0] when TX_EN is asserted high. TXD0 is the least significant bit. In 10 Mb/s serial mode, pin TXD0 is used as the serial input pin, and TXD[3:1] are ignored. When either BP4B5B or BPALIGN is selected, pin TXD4 contains the most significant bit of the five-bit code-group.
Control and Status Pins 10BT_SER - 10 Mb/s Serial Mode Select. Input, Pin 23.
When asserted high during power-up or reset and 10 Mb/s operation is selected, serial data will be transferred on pins RXD0 and TXD0. When low during power-up or reset and 10 Mb/s operation is selected, data is transferred a nibble at a time on RXD[3:0] and TXD[3:0]. This pin is ignored during 100 Mb/s operation. 10 Mb/s serial mode may also be entered under software control through bit 9 of the 10BASE-T Status Register (address 1Bh). At power-up or at reset, the value on this pin is latched into bit 9 of the 10BASE-T Status Register (address 1Bh). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57.
These three-level input pins are sampled during power-up or reset. They control the forced or advertised auto-negotiation operating modes. If one of these pins is left unconnected, internal logic pulls its signal to a mid-range value, 'M'. AN1 pin 0 AN0 pin M Speed 10 Mb/s Forced/Auto Forced Full/Half Duplex Half
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AN1 pin 1 M M M 0 0 1 1 AN0 pin M 0 1 M 0 1 0 1 Speed 10 Mb/s 100 Mb/s 100 Mb/s 100/10 Mb/s 10 Mb/s 10 Mb/s 100 Mb/s 100 Mb/s Forced/Auto Forced Forced Forced Auto-Neg Auto-Neg Auto-Neg Auto-Neg Auto-Neg Full/Half Duplex Full Half Full Full/Half Half Full Half Full
Auto-Negotiation may also be enabled and the advertised capabilities modified under software control through bit 8 of the Basic Mode Control Register (address 00h), and bits 5, 6, 7, 8, and 10 of the AutoNegotiation Advertisement Register (address 04h). These pins are pulled to `M' through weak internal resistors (> 150 K). Other values may be set by tying them directly to VDD_MII or VSS, or through external 10 K pull-up or pull-down resistors.
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BP4B5B - Bypass 4B5B Coders. Input, Pin 56.
When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The 4B5B Coders may also be bypassed under software control through bit 14 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 14 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
BPALIGN - Bypass Symbol Alignment. Input, Pin 52.
When driven high during power-up or reset, the following blocks are bypassed: 4B5B encoder, 5B4B decoder, scrambler, descrambler, NRZI encoder, and NRZI decoder. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The receiver will output five-bit data with no attempt to identify code-group boundaries; therefore, the data in one RXD[4:0] word may contain data from two code groups. Symbol alignment may also be bypassed under software control through bit 12 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 12 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
BPSCR - Bypass Scrambler. Input, Pin 62.
When driven high during power-up or reset, the scrambler and descrambler is bypassed and NRZI FX mode is selected. The 100BASE-FX mode may also be entered under software control through bit 13 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 13 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
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ISODEF - Isolate Default. Input, Pin 63.
When asserted high during power-up or reset, the MII will power-up electrically isolated except for the MDIO and MDC pins. When low, the part will exit reset fully electrically connected to the MII. The MII may also be isolated under software control through bit 10 of the Basic Mode Control Register (address 00h). At power-up or at reset, the value on this pin is latched into bit 10 of the Basic Mode Control Register (address 00h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
LED1 - Transmit Active LED. Open Drain Output, Pin 69.
This active-low output indicates transmit activity. It contains a pulse stretcher to insure that the transmit events are visible when the pin is used to drive an LED. The definition of this pin may be modified to indicate Disconnect Detection (bit 5 of the Self Status Register (address 19h)) by setting bit 2 of the PCS Sub-layer Configuration Register (address 17h). This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED2 - Receive Activity LED. Open Drain Output, Pin 70.
This active-low output indicates receive activity. It contains a pulse stretcher to insure that the receive events are visible when the pin is used to drive an LED. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED3 - Link Good LED. Open Drain Output, Pin 71.
This active-low output indicates the CS8952 has detected a valid link. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED4 - Polarity/Full Duplex LED. Open Drain Output, Pin 72.
This active-low output indicates: 1) for 100 Mb/s operation, the CS8952 is in full-duplex operation, 2) for 10 Mb/s operation, either good polarity exists or full duplex is selected (see bit 1 in the PCS Sublayer Configuration Register (address 17h)). This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED5 - Collision/Descrambler Lock LED. Open Drain Output, Pin 73.
This active-low output is asserted when either the CS8952 detects a collision (bit 11 of the PCS SubLayer Configuration Register (address 17h) is clear), or the 100BASE-TX descrambler is synchronized (bit 11 of the PCS Sub-Layer Configuration Register (address 17h) is set). It contains a pulse stretcher to insure that the collision events are visible when the pin is used to drive an LED. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LPBK - Loopback Enable. Input, Pin 51.
When this pin is asserted high and the CS8952 is operating in 100 Mb/s mode, the CS8952 will perform a local loopback inside the PMD block, routing the scrambled NRZI output to the NRZI input port on the descrambler. The loopback includes all CS8952 100 Mb/s functionality except the MLT-3 coders and the analog line interface blocks. When asserted high and the CS8952 is operating in 10 Mb/s mode, the CS8952 will perform a local ENDEC loopback.
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LPSTRT - Low Power Start. Input, Pin 50.
When this active-low input is asserted during power-up or reset, the CS8952 will exit reset in a low power configuration, where the only circuitry enabled is that necessary to maintain the media impedance. The CS8952 will remain in a low power state until RESET pin is asserted or the MDC pin toggles. This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
PWRDN - Power Down. Input, Pin 64.
When this pin is asserted high, the CS8952 powers down all circuitry except that circuitry needed to maintain the network line impedance. This is the lowest power mode possible. The CS8952 will remain in low power mode until the PWRDN pin is deasserted. A slightly higher power power-down mode may also be entered under software control through bit 11 of the Basic Mode Control Register (address 00h).
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REPEATER - REPEATER Mode Select. Input, Pin 16.
This pin controls the operation of the CRS (Carrier Sense) pin as shown below: REPEATER pin high low low DUPLEX mode don't care full duplex half duplex CRS Indicates receive activity only receive activity only receive or transmit activity
At power-up or at reset, the value on this pin is latched into bit 12 of the PCS Sub-Layer Configuration Register (address 17h). This pin includes a weak internal pull-down (> 20 K), or the value may be set by an external 4.7 K pull-up or pull-down resistor.
SPD10 - 10 Mb/s Speed Indication. Output, Pin 68.
This pin is asserted high when the CS8952 is configured for 10 Mb/s operation. This pin can be used to drive a low-current LED to indicate 10 Mb/s operation.
SPD100 - 100 Mb/s Speed Indication. Output, Pin 67.
This pin is asserted high when the CS8952 is configured for 100 Mb/s operation. This pin can be used to drive a low-current LED to indicate 100 Mb/s operation.
TCM - Transmit Clock Mode Initialization. Input, Pin 59.
The logic value on this three-level pin during power-up or reset determines whether TX_CLK is used as an input or an output, and whether an external 25 MHz clock reference is provided on the CLK25 output pin. TCM pin high floating low TX_CLK mode TX_CLK is input TX_CLK is input TX_CLK is output CLK25 status CLK25 pin is an output CLK25 is disabled CLK25 is disabled
TEST[1:0] - Factory Test. Input, Pins 24 and 25.
These pins are for factory test only. They include weak internal pull-downs (> 20 K), and should be tied directly to VSS for normal operation.
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TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60.
These three-level pins allow adjustment to the rise and fall times of the 10BASE-TX transmitter output waveform. The rise and fall times are symmetric. TXSLEW0 pin low low low floating floating floating high high high TXSLEW1 mode low floating high low floating high low floating high Rise/Fall time 0.5 ns 1.0 ns 1.5 ns 2.0 ns 2.5 ns 3.0 ns 3.5 ns 4.0 ns 4.5 ns
Media Interface Pins RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92.
Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer primary.
TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81.
Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer primary.
RX_NRZ+, RX_NRZ- - FX Receive. Differential Input Pair, Pins 6 and 7.
PECL output pair receives 100 Mb/s NRZI-encoded data from an external optical module.
SIGNAL+, SIGNAL- - Signal Detect. Differential Input Pair, Pins 9 and 8.
PECL input pair receives signal detection indication from an external optical module.
TX_NRZ+, TX_NRZ- - FX Transmit. Differential Output Pair, Pins 5 and 4.
PECL output pair drives 100 Mb/s NRZI-encoded data to an external optical module.
General Pins CLK25 - 25 MHz Clock. Output, Pin 17.
A 25 MHz Clock is output on this pin when the CS8952 is configured to use an external reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating modes. CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-layer Configuration Register (address 17h).
RES - Reference Resistor. Input, Pin 86.
This input should be connected to ground with a 4.99 k +/-1% series resistor. The resistor is needed for the biasing of internal analog circuits.
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RESET - Reset. Input, Pin 15.
This active high input initializes the CS8952, and causes the CS8952 to latch the input signal on the following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4, 10BT_SER, BP4B5B, BPALIGN, BPSCR, ISODEF, REPEATER, RXD[1]/PHYAD1, and RXD[3]/PHYAD3.
XTAL_I - Crystal Input, Pin 96. XTAL_O - Crystal Output, Pin 97.
A 25 MHz crystal should be connected across pins XTAL_I and XTAL_O. If a crystal is not used, a 25 MHz CMOS level clock may be connected to XTAL_I and XTAL_O left open. NOTE: The XTAL_I pin capacitive load may be as high as 35pF. Any external clock source connected to this pin must be capable of driving larger capacitive loads.
RSVD - Reserved. Pins 74, 75, 76, 77, 84, 98, and 99.
These seven pins are reserved and should be tied to VSS.
VDD_MII - MII Power. Pins 21, 34, and 66.
These pins provide power to the CS8952 MII interface. Typically VDD_MII will be either +5V or +3.3V.
VDD - Core Power. Pins 2, 11, 19, 40, 54, 79, 82, 88, 89, 94, and 100.
These pins provide power to the CS8952 core. Typically, VDD should be +5V.
VSS - Ground. Pins 1, 3, 10, 12, 13, 18, 20, 22, 35, 39, 41, 53, 55, 65, 78, 83, 85, 87, 90, 93, and 95.
These pins provide a ground reference for the CS8952.
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9. PACKAGE DIMENSIONS
100L TQFP PACKAGE DRAWING
E E1
D D1
1 e A1 L
INCHES MIN MAX --0.063 0.002 0.006 0.007 0.011 0.618 0.642 0.547 0.555 0.618 0.642 0.547 0.555 0.016 0.024 0.018 0.030 0.000 7.000 * Nominal pin pitch is 0.50 mm DIM A A1 B D D1 E E1 e* L Controlling dimension is mm. JEDEC Designation: MS026 MILLIMETERS MIN MAX --1.60 0.05 0.15 0.17 0.27 15.70 16.30 13.90 14.10 15.70 16.30 13.90 14.10 0.40 0.60 0.45 0.75 0.00 7.00
B A
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CrystalLANTM 100BASE-X and 10BASE-T Transceiver
* Notes *

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