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| Silicon N Channel MOS FET Triode Preliminary Data q q BF 543 For RF stages up to 300 MHz preferably in FM applications IDSS = 4 mA, gfs = 12 mS ESD: Electrostatic discharge sensitive device, observe handling precautions! Type BF 543 Marking LDs Ordering Code (tape and reel) Q62702-F1372 Pin Configuration 1 2 3 G D S Package1) SOT-23 Maximum Ratings Parameter Drain-source voltage Drain current Gate-source peak current Total power dissipation, TA 60 C Storage temperature range Channel temperature Ambient temperature range Thermal Resistance Junction - ambient2) Rth JA Symbol VDS ID IGSM Values 20 30 10 200 150 - 55 ... + 150 Unit V mA mW Ptot Tstg Tch TA - 55 ... + 150 C 450 K/W 1) 2) For detailed information see chapter Package Outlines. Package mounted on alumina 15 mm x 16.7 mm x 0.7 mm. Semiconductor Group 1 07.94 BF 543 Electrical Characteristics at TA = 25 C, unless otherwise specified. Parameter Symbol min. DC Characteristics Drain-source breakdown voltage ID = 10 A, - VGS = 4 V Gate-source breakdown voltage IGS = 10 mA, VDS = 0 Values typ. max. Unit V(BR)DS V(BR)GSS IGSS 20 7 - 2.0 - - - - 4 0.7 - 12 50 6.0 1.5 V Gate cutoff current VGS = 6 V, VDS = 0 nA mA V Drain current VDS = 10 V, VGS = 0 Gate-source pinch-off voltage VDS = 10 V, ID = 20 A AC Characteristics Forward transconductance VDS = 10 V, ID = 4 mA, f = 1 kHz Gate-1 input capacitance VDS = 10 V, ID = 4 mA, f = 1 MHz Reverse transfer capacitance VDS = 10 V, ID = 4 mA, f = 1 MHz Output capacitance VDS = 10 V, ID = 4 mA, f = 1 MHz Power gain (test circuit) VDS = 10 V, ID = 4 mA, f = 200 MHz GG = 2 mS, GL = 0.5 mS Noise figure (test circuit) VDS = 10 V, ID = 4 mA, f = 200 MHz GG = 2 mS, GL = 0.5 mS IDSS - VGS(p) gfs Cgss Cdg Cdss Gp 9.5 - - - - 12 2.7 18 0.9 22 - - - - - mS pF fF pF dB F - 1 - Semiconductor Group 2 BF 543 Total power dissipation Ptot = f (TA) Typ. output characteristics ID = f (VDS) Gate transconductance gfs = f (VGS) VDS = 10 V, IDSS = 4 mA, f = 1 kHz Drain current ID = f (VGS) VDS = 10 V Semiconductor Group 3 BF 543 Gate input capacitance Cgss = f (VGS) VDS = 10 V, IDSS = 4 mA, f = 1 MHz Output capacitance Cdss = f (VDS) VGS = 0, IDSS = 4 mA, f = 1 MHz Reverse transfer capacitance Cdg = f (VDS) VGS = 0, IDSS = 4 mA, f = 1 MHz Gate 1 input admittance y11s VDS = 10 V, IDSS = 4 mA, VGS = 0 (source circuit) Semiconductor Group 4 BF 543 Gate 1 transconductance y21s VDS = 10 V, IDSS = 4 mA, VGS = 0 (source circuit) Output admittance y22s VDS = 10 V, IDSS = 10 mA, VGS = 0 (source circuit) Test circuit for power gain Gp and noise figure F f= 200 MHz, GG = 2 mS, GL = 0.5 mS Semiconductor Group 5 |
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