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74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs
April 2001 Revised June 2002
74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs
General Description
These 36-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The LCX32500 is designed for low voltage (2.5V or 3.3V) VCC applications with the capability of interfacing to a 5V signal environment. The LCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power.
Features
s 5V tolerant inputs and outputs s 2.3V-3.6V VCC specifications provided s 6.0 ns tPD max (VCC = 3.3V), 20 A ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s 24 mA output drive (VCC = 3.0V) s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX32500G (Note 2)(Note 3) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2: Ordering code "G" indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2002 Fairchild Semiconductor Corporation
DS500406
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74LCX32500
Connection Diagram
Pin Descriptions
Pin Names 1A1 - 1A18 2A1 - 2A18 1B1 - 1B18 2B1 - 2B18 CLKAB1, CLKBA1 Clock Pulse Inputs CLKAB2, CLKBA2 LEAB1, LEBA1 LEAB2, LEBA2 OEAB1, OEBA1 OEAB2, OEBA2 Output Enable Inputs Latch Enable Inputs Data Register B Inputs/3-STATE Outputs Description Data Register A Inputs/3-STATE Outputs
FBGA Pin Assignments
1 A B (Top Thru View) C D E Output An X L H L H X X Bn Z L H L H B0 (Note 5) B0 (Note 6) F G H J K L M N P R T U V W 1A2 1A4 1A6 1A8 1A10 1A12 1A14 1A15 1A17 NC 2A2 2A4 2A6 2A8 2A10 2A12 2A14 2A15 2A17 2 1A1 1A3 1A5 1A7 1A9 1A11 1A13 1A16 1A18 2A1 2A3 2A5 2A7 2A9 2A11 2A13 2A16 2A18 3 4 5 1B1 1B3 1B5 1B7 1B9 1B11 1B13 1B16 1B18 CLKAB2 2B1 2B3 2B5 2B7 2B9 2B11 2B13 2B16 2B18 6 1B2 1B4 1B6 1B8 1B10 1B12 1B14 1B15 1B17 NC 2B2 2B4 2B6 2B8 2B10 2B12 2B14 2B15 2B17 LEAB1 CLKAB1 OEAB1 GND VCC GND GND VCC GND GND GND VCC GND GND VCC GND
Truth Table (Note 4)
Inputs OEABn L H H H H H H LEABn X H H L L L L CLKABn X X X
OEBA1 CLKBA1 GND GND GND VCC GND GND VCC GND OEAB2 GND VCC GND GND VCC GND

H L
LEAB2 LEBA1
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 4: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 5: Output level before the indicated steady-state input conditions were established. Note 6: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.
OEBA2 CLKBA2 LEBA2 GND
Functional Description
For A-to-B data flow, the LCX32500 operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-HIGH. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW).
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74LCX32500
Logic Diagrams
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74LCX32500
Absolute Maximum Ratings(Note 7)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 8) VI < GND VO < GND VO > VCC mA mA mA mA mA V
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150
C
Recommended Operating Conditions (Note 9)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V VCC = 2.3V - 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V
24 12 8 -40
0 85 10 mA
C
ns/V
t/V
Note 7: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 8: IO Absolute Maximum Rating must be observed. Note 9: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -8 mA IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF Input Leakage Current 3-STATE I/O Leakage Power-Off Leakage Current 0 VI 5.5V 0 VO 5.5V VI = VIH or VIL VI or VO = 5.5V Conditions VCC (V) 2.3 - 2.7 2.7 - 3.6 2.3 - 2.7 2.7 - 3.6 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 - 3.6 0 VCC - 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 5.0 5.0 10 A A A V V TA = -40C to +85C Min 1.7 2.0 0.7 0.8 Max Units V V
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74LCX32500
DC Electrical Characteristics
Symbol ICC ICC Parameter Quiescent Supply Current Increase in ICC per Input
(Continued)
VCC (V) 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 TA = -40C to +85C Min Max 20 20 500 A A
Conditions VI = VCC or GND 3.6V VI, VO 5.5V (Note 10) VIH = VCC -0.6V
Units
Note 10: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter VCC = 3.3V 0.3V CL = 50 pF Min fMAX tPHL tPLH tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW Setup Time Hold Time Pulse Width Output Disable Time Maximum Clock Frequency Propagation Delay Bus to Bus Propagation Delay Clock to Bus Propagation Delay LE to Bus Output Enable Time 170 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 6.0 6.0 6.7 6.7 7.0 7.0 7.2 7.2 7.0 7.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 7.0 7.0 8.0 8.0 8.0 8.0 8.2 8.2 8.0 8.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 7.2 7.2 8.4 8.4 8.4 8.4 9.4 9.4 8.4 8.4 Max VCC = 2.7V CL = 50 pF Min Max VCC = 2.5V 0.2V CL = 30 pF Min Max MHz ns ns ns ns ns ns ns ns Units
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25C Typical 0.8 0.6 -0.8 -0.6 V V Units
Capacitance
Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF
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74LCX32500
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC = 3.3 0.3V, and 2.7V VCC x 2 at VCC = 2.5 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
trise and tfall
2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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74LCX32500
Schematic Diagram Generic for LCX Family
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74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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