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3 Volt Advanced+ Boot Block Flash Memory 28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16) Preliminary Datasheet Product Features s s s s s s Flexible SmartVoltage Technology -- 2.7 V-3.6 V Read/Program/Erase -- 12 V for Fast Production Programming High Performance -- 2.7 V-3.6 V: 70 ns Max Access Time Optimized Architecture for Code Plus Data Storage -- Eight 4-Kword Blocks, Top or Bottom Locations -- Up to One Hundred-Twenty-Seven 32Kword Blocks -- Fast Program Suspend Capability -- Fast Erase Suspend Capability Flexible Block Locking -- Lock/Unlock Any Block -- Full Protection on Power-Up -- WP# Pin for Hardware Block Protection -- VPP = GND Option -- VCC Lockout Voltage Low Power Consumption -- 9 mA Typical Read Power -- 7 A Typical Standby Power with Automatic Power Savings Feature Extended Temperature Operation -- -40 C to +85 C s s s s s s s s Improved 12 V Production Programming -- Faster Production Programming -- No Additional System Logic 128-bit Protection Register -- 64-bit Unique Device Identifier -- 64-bit User Programmable OTP Cells Extended Cycling Capability -- Minimum 100,000 Block Erase Cycles Supports Intel(R) Flash Data Integrator Software -- Flash Memory Manager -- System Interrupt Manager -- Supports Parameter Storage, Streaming Data (e.g., voice) Automated Word/Byte Program and Block Erase -- Command User Interface -- Status Registers Cross-Compatible Command Support -- Intel Basic Command Set -- Common Flash Interface x16 I/O for Various Applications -- 48-Ball BGA* Package -- 48-Ball VF BGA Package -- 64-Ball Easy BGA Package -- 48-Lead TSOP Package 0.18 ETOXTM VII Flash Technology The 3 Volt Advanced+ Boot Block Flash memory, manufactured on Intel's latest 0.18 technology, represents a feature-rich solution for low power applications. 3 Volt Advanced+ Boot Block Flash memory devices incorporate low voltage capability (2.7 V read, program and erase) with high-speed, low-power operation. Flexible block locking allows any block to be independently locked or unlocked. Add to this the Intel(R) Flash Data Integrator (IFDI) software and you have a cost-effective, flexible, monolithic code plus data storage solution. Intel(R) 3 Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 48-ball BGA*, 48-ball Very Thin Profile Fine Pitch BGA (VF BGA), and 64-ball Easy BGA packages. Additional information on this product family can be obtained by accessing the Intel(R) Flash website: http:// www.intel.com/design/flash. Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 290645-009 April 2000 Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1998, 2000 *Other brands and names are the property of their respective owners. 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Contents 1.0 2.0 Introduction .................................................................................................................. 1 1.1 2.1 2.2 Product Overview .................................................................................................. 2 Package Pinouts ................................................................................................... 3 Block Organization ................................................................................................ 7 2.2.1 Parameter Blocks ..................................................................................... 7 2.2.2 Main Blocks .............................................................................................. 7 Bus Operation ....................................................................................................... 7 3.1.1 Read......................................................................................................... 7 3.1.2 Output Disable.......................................................................................... 8 3.1.3 Standby .................................................................................................... 8 3.1.4 Reset ........................................................................................................8 3.1.5 Write ......................................................................................................... 9 Modes of Operation............................................................................................... 9 3.2.1 Read Array ............................................................................................... 9 3.2.2 Read Configuration ................................................................................10 3.2.3 Read Status Register .............................................................................10 3.2.4 Read Query ............................................................................................11 3.2.5 Program Mode........................................................................................11 3.2.6 Erase Mode ............................................................................................12 Flexible Block Locking.........................................................................................15 3.3.1 Locking Operation ..................................................................................16 3.3.2 Unlocked State .......................................................................................16 3.3.3 Lock-Down State ....................................................................................16 3.3.4 Reading a Block's Lock Status ...............................................................17 3.3.5 Locking Operations during Erase Suspend............................................17 3.3.6 Status Register Error Checking..............................................................17 128-Bit Protection Register .................................................................................18 3.4.1 Reading the Protection Register ............................................................18 3.4.2 Programming the Protection Register ....................................................19 3.4.3 Locking the Protection Register .............................................................19 VPP Program and Erase Voltages .......................................................................19 3.5.1 Improved 12 Volt Production Programming ...........................................19 3.5.2 VPP VPPLK for Complete Protection.....................................................20 Power Consumption ............................................................................................20 3.6.1 Active Power (Program/Erase/Read) .....................................................20 3.6.2 Automatic Power Savings (APS)............................................................21 3.6.3 Standby Power .......................................................................................21 3.6.4 Deep Power-Down Mode .......................................................................21 Power-Up/Down Operation .................................................................................21 3.7.1 RP# Connected to System Reset...........................................................21 3.7.2 VCC, VPP and RP# Transitions ...............................................................22 Power Supply Decoupling ...................................................................................22 Product Description .................................................................................................. 3 3.0 Principles of Operation............................................................................................7 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3UHOLPLQDU\ iii 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.0 Electrical Specifications........................................................................................ 23 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Absolute Maximum Ratings ................................................................................ 23 Operating Conditions .......................................................................................... 24 Capacitance ........................................................................................................ 24 DC Characteristics .............................................................................................. 25 AC Characteristics--Read Operations--Extended Temperature ....................... 28 AC Characteristics--Write Operations................................................................ 33 Erase and Program Timings ............................................................................... 37 Reset Operations ................................................................................................ 39 5.0 6.0 Ordering Information.............................................................................................. 40 Additional Information ........................................................................................... 41 WSM Current/Next States................................................................................ 42 Program/Erase Flowcharts ............................................................................. 44 Common Flash Interface Query Structure ............................................... 50 Architecture Block Diagram ........................................................................... 57 Word-Wide Memory Map Diagrams............................................................. 58 Device ID Table.................................................................................................... 62 Protection Register Addressing ................................................................... 63 Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G iv 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Revision History Date of Revision 05/12/98 Version -001 Original version 48-Lead TSOP package diagram change BGA package diagrams change 32-Mbit ordering information change (Section 6) CFI Query Structure Output Table Change (Table C2) CFI Primary-Vendor Specific Extended Query Table Change for Optional Features and Command Support change (Table C8) Protection Register Address Change IPPD test conditions clarification (Section 4.3) BGA package top side mark information clarification (Section 6) Byte-Wide Protection Register Address change VIH Specification change (Section 4.3) VIL Maximum Specification change (Section 4.3) ICCS test conditions clarification (Section 4.3) Added Command Sequence Error Note (Table 7) Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory Family. Added tBHWH/tBHEH and tQVBL (Section 4.6) Programming the Protection Register clarification (Section 3.4.2) Removed all references to x8 configurations Removed reference to 40-Lead TSOP from front page Added Easy BGA package (Section 1.2) Removed 1.8 V I/O references Locking Operations Flowchart changed (Appendix B) Added tWHGL (Section 4.6) CFI Primary Vendor-Specific Extended Query changed (Appendix C) Max ICCD changed to 25 A Table 10, added note indicating VCCMax = 3.3 V for 32-Mbit device Added specifications for 0.18 micron product offerings throughout document Added 64-Mbit density Description 07/21/98 -002 10/03/98 -003 12/04/98 12/31/98 02/24/99 -004 -005 -006 06/10/99 -007 03/20/00 04/24/00 -008 -009 3UHOLPLQDU\ v 28F800C3, 28F160C3, 28F320C3, 28F640C3 1.0 Introduction This document contains the specifications for the 3 Volt Advanced+ Boot Block flash memory family. These flash memories add features which can be used to enhance the security of systems: instant block locking and a protection register. Throughout this document, the term "2.7 V" refers to the full voltage range 2.7 V-3.6 V (except where noted otherwise) and "VPP = 12 V" refers to 12 V 5%. Section 1.0 and Section 2.0 provide an overview of the flash memory family including applications, pinouts, pin descriptions and memory organization. Section 3.0 describes the operation of these products, with Section 4.0 providing the operating specifications. Ordering information is outlined in Section 5.0, and additional reference material is located in Section 6.0. The 3 Volt Advanced+ Boot Block flash memory features: * Zero-latency, flexible block locking * 128-bit Protection Register * Simple system implementation for 12 V production programming with 2.7 V in-field programming * Ultra-low power operation at 2.7 V * Minimum 100,000 block erase cycles * Common Flash Interface for software query of device specs and features Table 1. Feature VCC Operating Voltage VPP Voltage VCCQ I/O Voltage Bus Width 3 Volt Advanced+ Boot Block Feature Summary 8 Mbit(1), 16 Mbit, 32 Mbit(2) 2.7 V - 3.6 V(3) Provides complete write protection with optional 12 V Fast Programming 2.7 V- 3.6 V 16-bit 8 Mbit: 90, 110 @ 2.7 V and 80, 100 @ 3.0 V 16 Mbit: 70, 80, 90, 110 @ 2.7 V and 70, 80, 100 @ 3.0 V 32 Mbit: 80, 90, 100, 110 @ 2.7 V and 80, 90, 100 @ 3.0 V 64 Mbit: 90, 100 @ 2.7 V and 90, 100 @ 3.0 V 8 x 4-Kword parameter 8-Mb: 15 x 32-Kword main 16-Mb: 31 x 32-Kword main 32-Mb: 63 x 32-Kword main 64-Mb: 127 x 32-Kword main Extended: -40 C to +85 C 100,000 cycles 48-Lead TSOP 48-Ball BGA* CSP(1), 48-Ball VF BGA, Easy BGA Flexible locking of any block with zero latency 64-bit unique device number, 64-bit user programmable Table 2 Reference Table 8 Table 8 Speed (ns) Section 4.4 Blocking (top or bottom) Appendix 2.2 Appendix E Operating Temperature Program/Erase Cycling Packages Block Locking Protection Register Table 8 Table 8 Figure 1, 2 and 3 Section 3.3 Section 3.4 NOTES: 1. 8-Mbit density not available in BGA* CSP. 2. See Specification Update for changes to 32-Mbit devices (order 297938). 3. VCCMax = 3.3 V on 32-Mbit and 64-Mbit devices. 3UHOLPLQDU\ 1 28F800C3, 28F160C3, 28F320C3, 28F640C3 1.1 Product Overview Intel provides secure low voltage memory solutions with the Advanced Boot Block family of products. A new block locking feature allows instant locking/unlocking of any block with zerolatency. A 128-bit protection register allows unique flash device identification. Discrete supply pins provide single voltage read, program, and erase capability at 2.7 V while also allowing 12 V VPP for faster production programming. Improved 12 V, a new feature designed to reduce external logic, simplifies board designs when combining 12 V production programming with 2.7 V in-field programming. The 3 Volt Advanced+ Boot Block flash memory products are available in x16 packages in the following densities: (see Section 5.0, "Ordering Information" on page 40) * * * * 8-Mbit (8,388,608 bit) flash memories organized as 512 Kwords of 16 bits each 16-Mbit (16,777,216 bit) flash memories organized as 1024 Kwords of 16 bits each 32-Mbit (33,554,432 bit) flash memories organized as 2048 Kwords of 16 bits each 64-Mbit (67,108,864 bit) flash memories organized as 4096 Kwords of 16 bits each Eight 4-Kword parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The remaining memory is grouped into 64-Kbyte main blocks (see Appendix E). All blocks can be locked or unlocked instantly to provide complete protection for code or data (see Section 3.3, "Flexible Block Locking" on page 15 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status. Program and erase automation allows program and erase operations to be executed using an industry-standard two-write command sequence to the CUI. Program operations are performed in word increments. Erase operations erase all locations within a block simultaneously. Both program and erase operations can be suspended by the system software in order to read from any other block. In addition, data can be programmed to another block during an erase suspend. The 3 Volt Advanced+ Boot Block flash memories offer two low power savings features: Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode following the completion of a read cycle. Standby mode is initiated when the system deselects the device by driving CE# inactive. Combined, these two power savings features significantly reduce power consumption. The device can be reset by lowering RP# to GND. This provides CPU-memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/down sequences (see Section 3.5 and Section 3.6). Refer to Section 4.4, "DC Characteristics" on page 25 for complete current and voltage specifications. Refer to Section 4.5 and Section 4.6 for read and write performance specifications. Program and erase times and shown in Section 4.7. 2 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 2.0 Product Description This section provides device pin descriptions and package pinouts for the 3 Volt Advanced+ Boot Block flash memory family, which is available in 48-lead TSOP (x16) and 48-ball BGA and Easy BGA packages (Figures 1, 2 and 3, respectively). 2.1 Package Pinouts Figure 1. 48-Lead TSOP Package A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 0645_02 64 M 32 M Advanced+ Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW 16 M NOTE: Lower densities will have NC on the upper address pins. For example, a 16-Mbit device will have NC on Pins 9 and 10. 3UHOLPLQDU\ 3 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 2. 48-Ball BGA* and 48-Ball Very Thin Profile Fine Pitch BGA Chip Size Package (Top View, Ball Down) 1 2 3 4 5 16M A A13 A11 A8 VPP WP# A19 A7 A4 6 7 8 B A14 A10 WE# 64M RP# 32M A21 A18 A17 A5 A2 C A15 A12 A9 A20 A6 A3 A1 D A16 D14 D5 D11 D2 D8 CE# A0 E VCCQ D15 D6 D12 D3 D9 D0 GND F GND D7 D13 D4 VCC D10 D1 OE# NOTES: 1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit device. 2. 8-Mbit not available on BGA* CSP. 4 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 3. 8 x 8 Easy BGA Package 1 A A1 B A2 C A3 D A4 E DQ 8 DQ1 DQ9 DQ3 DQ 12 DQ6 F CE# DQ0 DQ10 DQ11 DQ5 DQ14 DU G A0 H A22(2) OE# VCCQ VCC VSSQ DQ7 VCCQ DU VSSQ DQ2 DQ4 DQ 13 DQ15 GND A16 H DU VCCQ D7 VSSQ VCC VCCQ OE# A22(2) DU G A16 GND D15 D13 DQ4 DQ 2 VSSQ A0 DU DU F DU DU DQ14 DQ5 DQ11 DQ10 DQ0 CE# A5 DU DU DU DU A8 A9 E DU DU DQ6 DQ12 DQ3 DQ 9 DQ1 DQ8 A7 WP# WE# DU A21(1) A12 A13 D A9 A8 DU DU DU DU A5 A4 A17 A19(1) RP# DU A20(1) A11 A14 C A13 A12 A21(1) DU WE# WP# A7 A3 A6 A18 VPP VCC GND A10 A15 B A14 A11 A20(1) DU RP# A19(1) A17 A2 2 3 4 5 6 7 8 A A15 A10 GND VCC VPP A18 A6 A1 8 7 6 5 4 3 2 1 Top View - Ball Side Down Bottom View - Ball Side Up 16fast NOTES: 1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 2. A22 indicates future density upgrade path to128 Mbit (not yet available). 3UHOLPLQDU\ 5 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 2. Symbol A0-A21 3 Volt Advanced+ Boot Block Pin Descriptions Type INPUT Name and Function ADDRESS INPUTS: Memory addresses are internally latched during a program or erase cycle. 8-Mbit: A[0-18], 16-Mbit: A[0-19], 32-Mbit: A[0-20], 64-Mbit: A[0-21] DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, configuration and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and configuration data. The data pins float to tri-state when the chip is de-selected. CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OUTPUT ENABLE: Enables the device's outputs through the data buffers during a read operation. OE# is active low. WRITE ENABLE: Controls writes to the command register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep powerdown mode. DQ0-DQ7 INPUT/ OUTPUT DQ8-DQ15 INPUT/ OUTPUT CE# INPUT OE# WE# INPUT INPUT RP# INPUT When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. WRITE PROTECT: Controls the lock-down function of the flexible Locking feature. When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. WP# INPUT When WP# is logic high, the lock-down mechanism is disabled and blocks previously lockeddown are now locked and can be unlocked and locked through software. After WP# goes low, any blocks previously marked lock-down revert to that state. See Section 3.3 for details on block locking. DEVICE POWER SUPPLY: [2.7 V-3.6 V] Supplies power for device operations. I/O POWER SUPPLY: Supplies power for input/output buffers. [2.7 V-3.6 V] This input should be tied directly to VCC. PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.6 V or 11.4 V-12.6 V] Operates as a input at logic levels to control complete device protection. Supplies power for accelerated program and erase operations in 12 V 5% range. This pin cannot be left floating. Lower VPP VPPLK, to protect all contents against Program and Erase commands. Set VPP = VCC for in-system read, program and erase operations. In this configuration, VPP can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note that if VPP is driven by a logic signal, VIH = 1.65. That is, VPP must remain above 1.65 V to perform insystem flash modifications. Raise VPP to 12 V 5% for faster program and erase in a production environment. Applying 12 V 5% to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details on VPP voltage configurations. VCC VCCQ SUPPLY INPUT VPP INPUT/ SUPPLY GND NC SUPPLY GROUND: For all internal circuitry. All ground inputs must be connected. NO CONNECT: Pin may be driven or left floating. 6 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 2.2 Block Organization The 3 Volt Advanced+ Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 100,000 times. For the address locations of each block, see the memory maps in Appendix E. 2.2.1 Parameter Blocks The 3 Volt Advanced+ Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (i.e., data that would normally be stored in an EEPROM). Each device contains eight parameter blocks of 4 Kwords (4,096 words). 2.2.2 Main Blocks After the parameter blocks, the remainder of the array is divided into 32-Kword (32,768 words) main blocks for data or code storage. Each 8-Mbit, 16-Mbit, 32-Mbit, or 64-Mbit device contains 15, 31, 63, or 127 main blocks, respectively. 3.0 Principles of Operation The 3 Volt Advanced+ Boot Block flash memory family utilizes a CUI and automated algorithms to simplify program and erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and programming. The internal WSM completely automates program and erase operations while the CUI signals the start of an operation and the status register reports status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation. 3.1 Bus Operation The 3 Volt Advanced+ Boot Block flash memory devices read, program and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3 on page 8. 3.1.1 Read The flash memory has four read modes available: read array, read configuration, read status and read query. These modes are accessible independent of the VPP voltage. The appropriate read mode command must be issued to the CUI to enter the corresponding mode. Upon initial device powerup or after exit from reset, the device automatically defaults to read array mode. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output control and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at VIH. Figure 8, "AC Waveform: Read Operations" on page 32 illustrates a read cycle. 3UHOLPLQDU\ 7 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.1.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a high-impedance state. 3.1.3 Standby Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. Table 3. Bus Operations Mode Notes 1, 2,3 1 1 1,4 1,4,5,6 RP# VIH VIH VIH VIL VIH CE# VIL VIL VIH X VIL OE# VIL VIH X X VIH WE# VIH VIH X X VIL DQ0-7 DOUT High Z High Z High Z DIN DQ8-15 DOUT High Z High Z High Z DIN Read (Array, Status, Configuration, or Query) Output Disable Standby Reset Write NOTES: 1. X must be VIL, VIH for control pins and addresses. 2. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, voltages. 3. Manufacturer and device codes may also be accessed in read configuration mode (A1-A20 = 0). See Table 4 on page 10. 4. To program or erase the lockable blocks, hold WP# at VIH. 5. Refer to Table 5 on page 13 for valid DIN during a write operation. 6. RP# must be at GND 0.2 V to meet the maximum deep power-down current specified. 8-bit devices use only DQ [0:7], 16-bit devices use DQ [0:15]. 3.1.4 Reset From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a highimpedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required until the initial read access outputs are valid. A delay (tPHWL or tPHEL) is required after return from reset before a write can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, the status register is set to 80H, and all blocks are locked. This case is shown in Figure 10, "AC Waveform: Reset Operations" on page 39 (section A). If RP# is taken low for time tPLPH during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: When RP# goes low, the device shuts down the operation in progress, a process which takes time tPLRH to complete. After this time tPLRH, the part will either reset to read array mode (if RP# has gone high during tPLRH, Figure 10, section B) or enter reset mode (if RP# is still logic low after tPLRH, Figure 10, section C). In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL must be observed before a read or write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. 8 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Similar to any automated device, it is important to assert RP# during system reset. When the system comes out of reset, the processor expects to read from the flash memory. Automated flash memories provide status information when read during program or block erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel(R) Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3.1.5 Write A write takes place when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control flash operations. The CUI does not occupy an addressable memory location. The address and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. See Figure 9, "AC Waveform: Program and Erase Operations" on page 38. The available commands are shown in Table 6 on page 14, and Appendix A provides detailed information on moving between the different modes of operation using CUI commands. There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to VIL for tPLRH or an appropriate suspend command). 3.2 Modes of Operation The flash memory has four read modes and two write modes. The read modes are read array, read configuration, read status, and read query. The write modes are program and erase. Three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are reached using the commands summarized in Tables 5 and 6. For a comprehensive chart showing the state transitions, see Appendix A. 3.2.1 Read Array When RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the device is in read array mode, four control signals control data output: * * * * WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH) In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place. 3UHOLPLQDU\ 9 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.2.2 Read Configuration The Read Configuration mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. The device is switched to this mode by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses shown in Table 4 retrieve the specified information. To return to read array mode, write the Read Array command (FFH). Table 4. Read Configuration Table Item Manufacturer Code (x16) Device ID (See Appendix F) Block Lock Configuration(1) * Block Is Unlocked * Block Is Locked * Block Is Locked-Down Protection Register Lock(3) Protection Register (x16) 80 81-88 Address 00000 00001 XX002(2) Data 0089 ID LOCK DQ0 = 0 DQ0 = 1 DQ1 = 1 PR-LK PR NOTES: 1. See Section 3.3.4 for valid lock status outputs. 2. "XX" specifies the block address of lock configuration being read. 3. See Section 3.4 for protection register information. 4. Other locations within the configuration address space are reserved by Intel for future use. 3.2.3 Read Status Register The status register indicates the status of device operations, and the success/failure of that operation. The Read Status Register (70H) command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the array, issue a Read Array (FFH) command. The status register bits are output on DQ0-DQ7. The upper byte, DQ8-DQ15, outputs 00H during a Read Status Register command. The contents of the status register are latched on the falling edge of OE# or CE#, whichever occurs last. This prevents possible bus errors which might occur if status register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the desired operation (see Table 7, "Status Register Bit Definition" on page 15). 3.2.3.1 Clearing the Status Register The WSM sets status bits 1 through 7 to "1," and clears bits 2, 6 and 7 to "0," but cannot clear status bits 1 or 3 through 5 to "0." Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the use of the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) 10 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 before reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. Note that this is different from a burst device. The Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the status register. 3.2.4 Read Query The read query mode outputs Common Flash Interface (CFI) data when the device is read. This can be accessed by writing the Read Query Command (98H). The CFI data structure contains information such as block size, density, command set and electrical specifications. Once in this mode, read cycles from addresses shown in Appendix C retrieve the specified information. To return to read array mode, write the Read Array command (FFH). 3.2.5 Program Mode Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a "0." If the user attempts to program "1"s, the memory cell contents do not change and no error occurs. The status register indicates programming status: while the program sequence executes, status bit 7 is "0." The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the program status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted on a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode. 3.2.5.1 Suspending and Resuming Program The Program Suspend command halts an in-progress program operation so that data can be read from other locations of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status register data after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to "1"). tWHRH1/ tEHRH1 specify the program suspend latency. A Read Array command can now be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands while program is suspended are Read Status Register, Read Configuration, Read Query, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the programming process and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically outputs status register data when read (see Figure 12, "Program Suspend/Resume Flowchart" on page 45) after the Program Resume command is written. VPP must remain at the same VPP level used for program while in program suspend mode. RP# must also remain at VIH. 3UHOLPLQDU\ 11 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.2.6 Erase Mode To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to "0," erase all bits within the block to "1," then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a "0." When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a "1," indicating an erase failure. If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a "1" to identify that VPP supply voltage was not within acceptable limits. After an erase operation, clear the status register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete. 3.2.6.1 Suspending and Resuming Erase Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended. Erase suspend latency is specified by tWHRH2/tEHRH2. A Read Array/Program command can now be written to the CUI to read/program data from/to blocks other than that which is suspended. This nested Program command can subsequently be suspended to read yet another location. The only valid commands while erase is suspended are Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block and Lock-Down Block. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to VIH. This reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. Similar to the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued. 12 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 5. Command Bus Operations First Bus Cycle Command Read Array Read Configuration Read Query Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program X = Don't Care SRD = Status Reg. Data Notes Oper 1 1, 2 1, 2 1 1 1, 3 1 1 1 1 1 1 1 PA = Prog Addr PD = Prog Data Write Write Write Write Write Write Write Write Write Write Write Write Write Addr X X X X X X X X X X X X X Data FFH 90H 98H 70H 50H 40H/10H 20H B0H D0H 60H 60H 60H C0H Write Write Write Write BA BA BA PA 01H D0H 2FH PD Write Write PA BA PD D0H Read Read Read IA QA X ID QD SRD Oper Addr Data Second Bus Cycle BA = Block Addr IA = Identifier Addr. ID = Identifier Data QA = Query Addr. QD = Query Data NOTES: 1. Following the Read Configuration or Read Query commands, read operations output device configuration or CFI query information, respectively. See Section 3.2.2 and Section 3.2.4. 2. Either 40H or 10H command is valid, but the Intel standard is 40H. 3. When writing commands, the upper data bus [DQ8-DQ15] should be either VIL or VIH, to minimize current draw. Bus operations are defined in Table 3, "Bus Operations" on page 8. 3UHOLPLQDU\ 13 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 6. Code FF 40 Command Codes and Descriptions Device Mode Read Array Description This command places the device in read array mode which outputs array data on the data pins. This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.2.5. Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a "1," (b) place the device into the read status register mode, and (c) wait for another command. See Section 3.2.6. If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches and begin erasing the block indicated on the address pins. During program/ erase, the device will respond only to the Read Status Register, Program Suspend and Erase Suspend commands and will output status register data when CE# or OE# is toggled. If a program or erase operation was previously suspended, this command will resume that operation. If the previous command was Configuration Set-Up, the CUI will latch the address and unlock the block indicated on the address pins. If the block had been previously set to Lock-Down, this operation will have no effect. (Section 3.3) Issuing this command will begin to suspend the currently executing program/erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit (SR.7) to a "1" (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if RP# is driven to VIL. See Sections 3.2.5.1 and 3.2.6.1. This command places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a program or erase operation has been initiated. See Section 3.2.3. The WSM can set the block lock status (SR.1) , VPP Status (SR.3), program status (SR.4), and erase status (SR.5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Puts the device into the read configuration mode so that reading the device will output the manufacturer/device codes or block lock status. Section 3.2.2. Prepares the CUI for changes to the device configuration, such as block locking changes. If the next command is not Block Unlock, Block Lock, or Block Lock-Down, then the CUI will set both the program and erase status register bits to indicate a command sequence error. See Section 3.2. If the previous command was Configuration Set-Up, the CUI will latch the address and lock the block indicated on the address pins. (Section 3.3) If the previous command was a Configuration Set-Up command, the CUI will latch the address and lock-down the block indicated on the address pins. (Section 3.3) Puts the device into the read query mode so that reading the device will output Common Flash Interface information. See Section 3.2.4 and Appendix C. This is a two-cycle command. The first cycle prepares the CUI for a program operation to the protection register. The second cycle latches addresses and data information and initiates the WSM to execute the Protection Program algorithm to the protection register. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.4. Operates the same as Program Set-up command. (See 40H/Program Set-Up) Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions. Program Set-Up 20 Erase Set-Up Erase Confirm D0 Program/Erase Resume Unlock Block B0 Program Suspend Erase Suspend 70 Read Status Register Clear Status Register Read Configuration Configuration Set-Up Lock-Block Lock-Down Read Query Protection Program Setup Alt. Prog Set-Up Invalid/ Reserved 50 90 60 01 2F 98 C0 10 00 NOTE: See Appendix A for mode transition information. 14 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 7. WSMS 7 Status Register Bit Definition ESS 6 ES 5 PS 4 VPPS 3 PSS 2 NOTES: BLS 1 R 0 SR.7 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error In Block Erase 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Programming 0 = Successful Programming Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an Erase Resume command is issued. When this bit is set to "1," WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word/byte. The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered, and informs the system if VPP has not been switched on. The VPP is also checked before the operation is verified by the WSM. The VPP status bit is not guaranteed to report accurate feedback between VPPLK and VPP1Min. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a Program Resume command is issued. If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future use and should be masked out when polling the status register. SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = BLOCK LOCK STATUS 1 = Prog/Erase attempted on a locked block; Operation aborted. 0 = No operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTE: A Command Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set. 3.3 Flexible Block Locking Intel 3 Volt Advanced+ Boot Block products offer an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. This locking scheme offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term "state [XYZ]" will be used to specify locking states; e.g., "state [001]," where X = value of WP#, Y = bit DQ1 of the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 9, "Block Locking State Transitions" on page 18 defines all of these possible locking states. 3UHOLPLQDU\ 15 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.3.1 Locking Operation The following concisely summarizes the locking functionality. * All blocks power-up locked, then can be unlocked or locked with the Unlock and Lock commands. * The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0. -- When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down blocks. -- When WP# returns to 0, locked-down blocks return to Lock-Down. -- Lock-Down is cleared only when the device is reset or powered-down. The locking status of each block can be set to Locked, Unlocked, and Lock-Down, each of which will be described in the following sections. A comprehensive state table for the locking functions is shown in Table 9 on page 18, and a flowchart for locking operations is shown in Figure 15 on page 48. 3.3.1.1 Locked State The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any program or erase operations attempted on a locked block will return an error on bit SR.1 of the status register. The status of a locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be locked by writing the Lock command sequence, 60H followed by 01H. 3.3.2 Unlocked State Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 60H followed by D0H. 3.3.3 Lock-Down State Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-down by writing the Lock-Down command sequence, 60H followed by 2FH. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function is dependent on the WP# input pin. When WP# = 0, blocks in LockDown [011] are protected from program, erase, and lock status changes. When WP# = 1, the LockDown function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as desired while WP# remains high. When WP# goes low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state. 16 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.3.4 Reading a Block's Lock Status The lock status of every block can be read in the configuration read mode of the device. To enter this mode, write 90H to the device. Subsequent reads at Block Address + 00002 will output the lock status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by device reset or power-down. Table 8. Block Lock Status Item Block Lock Configuration * Block Is Unlocked * Block Is Locked * Block Is Locked-Down Address XX002 Data LOCK DQ0 = 0 DQ0 = 1 DQ1 = 1 3.3.5 Locking Operations during Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the erase suspend command (B0H), then check the status register until it indicates that the erase operation has been suspended. Next write the desired lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command (D0H). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix A for detailed information on which commands are valid during erase suspend. 3.3.6 Status Register Error Checking Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Since locking changes are performed using a two cycle command sequence, e.g., 60H followed by 01H to lock a block, following the Configuration Setup command (60H) with an invalid command will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status register. If a lock command error occurs during an erase suspend, SR.4 and SR.5 will be set to 1 and will remain at 1 after the erase is resumed. When erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an erase suspend. 3UHOLPLQDU\ 17 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 9. Block Locking State Transitions Current State Lock Command Input Result (Next State) Erase/Prog Allowed? Name "Unlocked" "Locked" (Default) "Locked-Down" "Unlocked" "Locked" Lock-Down Disabled Lock-Down Disabled Yes No No Yes No Yes No Goes To [001] No Change No Change Goes To [101] No Change Goes To [111] No Change No Change Goes To [000] No Change No Change Goes To [100] No Change Goes To [110] Goes To [011] Goes To [011] No Change Goes To [111] Goes To [111] Goes To [111] No Change X WP# 0 0 0 1 1 1 1 Y DQ1 0 0 1 0 0 1 1 Z DQ0 0 1 1 0 1 0 1 Lock Unlock Lock-Down NOTES: 1. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ0 indicates if a block is locked (1) or unlocked (0). DQ1 indicates if a block has been lockeddown (1) or not (0). 2. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the recommended default. 3. The "Erase/Program Allowed?" column shows whether erase and program operations are enabled (Yes) or disabled (No) in that block's current locking state. 4. The "Lock Command Input Result [Next State]" column shows the result of writing the three locking commands (Lock, Unlock, Lock-Down) in the current locking state. For example, "Goes To [001]" would mean that writing the command to a block in the current locking state would change it to [001]. 3.4 128-Bit Protection Register The 3 Volt Advanced+ Boot Block architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution. Additional application information can be found in Intel application note AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture. The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming. 3.4.1 Reading the Protection Register The protection register is read in the configuration read mode. The device is switched to this mode by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses shown in Appendix G retrieve the specified information. To return to read array mode, write the Read Array command (FFH). 18 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.4.2 Programming the Protection Register The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Appendix G. See Figure 16, "Protection Register Programming Flowchart" on page 49. Attempts to address Protection Program commands outside the defined protection register address space should not be attempted. This space is reserved for future use. Attempting to program to a previously locked protection register segment will result in a status register error (program error bit SR.4 and lock error bit SR.1 will be set to 1). 3.4.3 Locking the Protection Register The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program "FFFD" to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1). Protection register lockout state is not reversible. Figure 4. Protection Register Memory Map 88H 4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 80H PR Lock 0645_05 3.5 VPP Program and Erase Voltages Intel 3 Volt Advanced+ Boot Block products provide in-system programming and erase in the 1.65 V-3.6 V range. For fast production programming, it also includes a low-cost, backwardcompatible 12 V programming feature. 3.5.1 Improved 12 Volt Production Programming When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC pin. Note that if VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above 1.65 V to perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device draws program and erase current directly from the V PP pin. This eliminates the need for an external switching transistor to control the voltage VPP. Figure 5 on page 20 shows examples of how the flash power supplies can be configured for various usage models. 3UHOLPLQDU\ 19 28F800C3, 28F160C3, 28F320C3, 28F640C3 The 12 V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. 3.5.2 VPP VPPLK for Complete Protection In addition to the flexible block locking, the VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding status register bit (SR.3) to be set. Figure 5. Example Power Supply Configurations System Supply 12 V Supply 10 K 12 V Fast Programming Absolute Write Protection With V PP VPPLK System Supply (Note 1) System Supply VCC VPP Prot# (Logic Signal) VCC VPP Low-Voltage Programming Absolute Write Protection via Logic Signal System Supply VCC VPP VCC VPP Low-Voltage Programming 12 V Supply Low Voltage and 12 V Fast Programming 0645_06 NOTE: 1. A resistor can be used if the VCC supply can sink adequate current based on resistor value. See AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture for details. 3.6 Power Consumption Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 3.6.1 Active Power (Program/Erase/Read) With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices. 20 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 3.6.2 Automatic Power Savings (APS) Automatic Power Savings provides low-power operation during read mode. After data is read from the memory array and the address lines are quiescent, APS circuitry places the device in a mode where typical current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read. 3.6.3 Standby Power When CE# is at a logic-high level (VIH) and the device is in read mode, the flash memory is in standby mode, which disables much of the device's circuitry and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements. 3.6.4 Deep Power-Down Mode The deep power-down mode is activated when RP# = VIL (GND 0.2 V). During read modes, RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery from deep power-down requires a minimum time of tPHQV for read operations and tPHWL/tPHEL for write operations. During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to VIL or turning off power to the device clears the status register). 3.7 Power-Up/Down Operation The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, VPP or VCC, powers-up first. 3.7.1 RP# Connected to System Reset The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. 3UHOLPLQDU\ 21 28F800C3, 28F160C3, 28F320C3, 28F640C3 By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.7.2 VCC, VPP and RP# Transitions The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after VCC transitions above VLKO (Lockout voltage), is read array mode. After any program or block erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired. 3.8 Power Supply Decoupling Flash memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues: * Standby current levels (ICCS) * Read current levels (ICCR) * Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Twoline control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 22 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.0 4.1 Electrical Specifications Absolute Maximum Ratings Parameter Extended Operating Temperature During Read During Block Erase and Program Temperature under Bias Storage Temperature Voltage On Any Pin (except VCC and VPP) with Respect to GND VPP Voltage (for Block Erase and Program) with Respect to GND VCC and VCCQ Supply Voltage with Respect to GND Output Short Circuit Current -40 C to +85 C -40 C to +85 C -40 C to +85 C -65 C to +125 C -0.5 V to +3.7 V(1) -0.5 V to +13.5 V(1,2,3) -0.2 V to +3.6 V 100 mA(4) Maximum Rating NOTES: 1. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. 3. VPP Program voltage is normally 1.65 V-3.6 V. Connection to a 11.4 V-12.6 V supply can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.5 for details. 4. Output shorted for no more than one second. No more than one output shorted at a time. NOTICE: This datasheet contains preliminary information on new products in production. Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. 3UHOLPLQDU\ 23 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.2 Operating Conditions Table 10. Temperature and Voltage Operating Conditions Symbol TA VCC1 VCC2 VCCQ1 VPP1 VPP2 Cycling Block Erase Cycling I/O Supply Voltage Supply Voltage Parameter Operating Temperature VCC Supply Voltage 1, 2 1, 2 1 1 1, 3 3 Notes Min -40 2.7 3.0 2.7 1.65 11.4 100,000 Max +85 3.6 3.6 3.6 3.6 12.6 Volts Volts Volts Cycles Units C Volts NOTES: 1. VCC and VCCQ must share the same supply when they are in the VCC1 range. 2. VCCMax = 3.3 V for 32-Mbit and 64-Mbit devices. 3. Applying VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.5 for details. 4.3 Capacitance TA = 25 C, f = 1 MHz Sym CIN COUT Parameter Input Capacitance Output Capacitance Notes 1 1 Typ 6 10 Max 8 12 Units pF pF Conditions VIN = 0 V VOUT = 0 V NOTE: 1. Sampled, not 100% tested. 24 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.4 DC Characteristics VCC 2.7 V--3.6 V(2) Unit Typ Max 1 0.2 7 10 7 10 15 25 15 A A A A A VCC = VCCMax, VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax, VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax, CE# = RP# = VCCQ WP# = VCCQ or GND VCC = VCCMax, CE# = RP# = VCCQ WP# = VCCQ or GND VCC = VCCMax, VCCQ = VCCQMax VIN = VCCQ or GND, RP# = GND 0.2 V VCC = VCCMax, VCCQ = VCCQMax VIN = VCCQ or GND, RP# = GND 0.2 V VCC = VCCMax, VCCQ = VCCQMax Test Conditions Sym Parameter VCCQ Note ILI ILO Input Load Current Output Leakage Current VCC Standby Current for 0.18 Micron Product 1,2 1,2 1 1 1,2 ICCS VCC Standby Current for 0.25 Micron and 0.4 Micron Product VCC Deep Power-Down Current for 0.18 Micron Product ICCD VCC Deep Power-Down Current for 0.25 Micron and 0.4 Micron Product VCC Read Current 1,2 7 25 A ICCR 1,2,3 9 18 18 55 15 45 15 15 mA mA mA mA mA A OE# = VIH , CE# = VIL, f = 5 MHz, IOUT = 0 mA, Inputs = VIL or VIH VPP = VPP1, Program in Progress VPP = VPP2 (12 V), Program in Progress VPP = VPP1, Erase in Progress VPP = VPP2 (12 V), Erase in Progress CE# = VIH, Erase Suspend in Progress CE# = VIH, Erase Suspend in Progress CE# = VIH, Program Suspend in Progress CE# = VIH, Program Suspend in Progress RP# = GND 0.2 V, VPP VCC VPP VCC VPP VCC VPP VCC VPP =VPP1, Program in Progress VPP = VPP2 (12 V), Program in Progress VPP = VPP1, Program in Progress VPP = VPP2 (12 V), Program in Progress ICCW VCC Program Current 1,4 8 16 1,4 8 1,4,5 7 ICCE VCC Erase Current VCC Erase Suspend Current for 0.18 Micron Product ICCES VCC Erase Suspend Current for 0.25 Micron and 0.4 Micron Product VCC Program Suspend Current for 0.18 Micron Product 1,4,5 10 25 A 1,4,5 7 15 A ICCWS VCC Program Suspend Current for 0.25 Micron and 0.4 Micron Product VPP Deep Power-Down Current VPP Standby Current VPP Read Current 1,4,5 1 1 1 10 0.2 0.2 2 50 0.05 25 5 5 15 200 0.1 22 0.1 22 A A A A A mA mA mA mA IPPD IPPS IPPR 1,4 1,4 IPPW VPP Program Current 8 0.05 1,4 8 IPPE VPP Erase Current 3UHOLPLQDU\ 25 28F800C3, 28F160C3, 28F320C3, 28F640C3 VCC Sym Parameter VCCQ Note 2.7 V--3.6 V(2) Unit Typ 0.2 Max 5 200 5 200 A A A A VPP = VPP1, Erase Suspend in Progress VPP = VPP2 (12 V), Erase Suspend in Progress VPP = VPP1 Program Suspend in Progress VPP = VPP2 (12 V) Program Suspend in Progress Test Conditions IPPES VPP Erase Suspend Current 1,4 50 0.2 IPPWS VPP Program Suspend Current 1,4 50 DC Characteristics, Continued VCC 2.7 V -- 3.6 V Sym Parameter VCCQ Note VIL VIH VOL Input Low Voltage Input High Voltage Output Low Voltage 2 Min -0.4 2.0 -0.10 Max VCC *0.22 V VCCQ +0.3 V 0.10 V V VCC = VCCMin V VCCQ = VCCQMin IOL = 100 A VCC = VCCMin VOH VPPLK VPP1 VPP2 VLKO VLKO2 Output High Voltage VPP Lock-Out Voltage VPP during Program / Erase Operations VCC Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage 2 6 6 6,7 1.65 11.4 1.5 1.2 VCCQ -0.1 V 1.0 3.6 V 12.6 V V V V VCCQ = VCCQMin IOH = -100 A Complete Write Protection Unit Test Conditions NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 C. 2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column. VCCMax = 3.3 V for 32-Mbit and 64-Mbit devices. 3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 4. Sampled, not 100% tested. 5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR. 6. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2. 7. Applying VPP = 11.4 V-12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details. 26 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 6. Input/Output Reference Waveform VCCQ INPUT 0.0 VCCQ 2 TEST POINTS VCCQ 2 OUTPUT 0645_07 Figure 7. Test Configuration VCCQ R1 Device Under Test Out CL R2 0645_08 Test Configuration 2.7 V-3.6 V Standard Test CL (pF) 50 R1 () 25K R2 () 25K NOTE: CL includes jig capacitance. 3UHOLPLQDU\ 27 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.5 AC Characteristics--Read Operations Density Product 90 ns 3.0 V - 3.6 V Min 80 80 1 1 80 30 150 2 2 2 2 0 0 20 20 0 0 20 20 Max 2.7 V - 3.6 V Min 90 90 90 30 150 0 0 20 20 Max 8 Mbit 110 ns Unit VCC Note 3.0 V - 3.6 V Min 100 100 100 30 150 0 0 20 20 Max 2.7 V - 3.6 V Min 110 110 110 30 150 Max ns ns ns ns ns ns ns ns ns # Sym Parameter R1 R2 R3 R4 R5 R6 R7 R8 R9 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First R10 2 0 0 0 0 ns NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. See Figure 8, "AC Waveform: Read Operations" on page 32. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. 28 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Read Operations, continued Density Parameter Product VCC 70 ns 2.7 V-3.6 V Min R1 R2 R3 R4 R5 R6 R7 R8 R9 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ Read Cycle Time Address to Output Delay CE# to Output Delay(1) OE# to Output Delay(1) RP# to Output Delay CE# to Output in Low Z(2) OE# to Output in Low Z(2) CE# to Output in High Z(2) 0 0 20 20 70 70 70 20 150 0 0 20 20 Max 80 ns 2.7 V-3.6 V Min 80 80 80 20 150 0 0 20 20 Max 16 Mbit 90 ns 3.0 V-3.6 V Min 80 80 80 30 150 0 0 20 20 Max 2.7 V-3.6 V Min 90 90 90 30 150 0 0 20 20 Max 110 ns Unit 3.0 V-3.6 V Min 100 100 100 30 150 0 0 20 20 Max 2.7 V-3.6 V Min 110 110 110 30 150 Max ns ns ns ns ns ns ns ns ns # Sym Output in tGHQZ OE# to(2) High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First(2) R10 tOH 0 0 0 0 0 0 ns NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. See Figure 8, "AC Waveform: Read Operations" on page 32. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. 3UHOLPLQDU\ 29 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Read Operations, continued Density # Sym Par ame ter Product VCC 80 ns 2.7 V-3.3 V Min R1 R2 R3 R4 R5 R6 R7 R8 R9 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ Read Cycle Time Address to Output Delay CE# to Output Delay(1) OE# to Output Delay(1) RP# to Output Delay CE# to Output in Low Z(2) OE# to Output in Low Z(2) CE# to Output in High Z(2) OE# to Output in High Z(2) Output Hold from Address, CE#, or OE# Change, Whichever Occurs First(2) 0 0 20 20 80 80 80 20 150 0 0 20 20 Max 90 ns 2.7 V-3.3 V Min 90 90 90 20 150 0 0 20 20 Max 32 Mbit 100 ns 3.0 V-3.3 V Min 90 90 90 30 150 0 0 20 20 Max 2.7 V-3.3 V Min 100 100 100 30 150 0 0 20 20 Max 110 ns Unit 3.0 V-3.3 V Min 100 100 100 30 150 0 0 20 20 Max 2.7 V-3.3 V Min 110 110 110 30 150 Max ns ns ns ns ns ns ns ns ns R10 tOH 0 0 0 0 0 0 ns NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. See Figure 8, "AC Waveform: Read Operations" on page 32. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. 30 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Read Operations, continued Density Product # Sym Parameter VCC Note R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 2 2 2 2 2 0 0 0 20 20 0 1 1 2.7 V-3.3 V Min 90 90 90 20 150 0 0 20 20 Max 2.7 V-3.3 V Min 100 100 100 20 150 Max ns ns ns ns ns ns ns ns ns ns 90 ns 64 Mbit 100 ns Unit NOTES: 1. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 2. Sampled, but not 100% tested. See Figure 8, "AC Waveform: Read Operations" on page 32. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. 3UHOLPLQDU\ 31 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 8. AC Waveform: Read Operations Standby VIH Device Address Selection Address Stable Data Valid ADDRESSES (A) VIL VIH R1 CE# (E) VIL R8 VIH VIL R9 R4 VIL R7 R3 High Z R6 Valid Output R2 R5 R10 High Z VOH VOL VIH OE# (G) WE# (W) VIH DATA (D/Q) RP# (P) VIL 32 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.6 AC Characteristics--Write Operations Density Product # Sym Parameter 3.0 V - 3.6 V 2.7 V - 3.6 V Note Min 150 0 1 2 2 50 50 50 0 2 2 1 3 3 3 3 3 0 0 30 200 0 0 0 30 80 90 Min 150 0 60 50 60 0 0 0 30 200 0 0 0 30 Min 150 0 70 60 70 0 0 0 30 200 0 0 0 30 90 ns 8 Mbit 110 ns 100 110 Min 150 0 70 60 70 0 0 0 30 200 0 0 0 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5, "Command Bus Operations" on page 13 for valid AIN or DIN. 3. Sampled, but not 100% tested. Write timing characteristics during erase suspend are the same as during write-only operations. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. See Figure 8, "AC Waveform: Read Operations" on page 32. 4. VCCMax = 3.3 V for 32-Mbit and 64-Mbit densities. 3UHOLPLQDU\ 33 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Write Operations, continued Density Product # Sym Parameter 3.0 V - 3.6 V 2.7 V - 3.6 V Note W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low 2 2 1 3 3 3 3 3 1 2 2 70 Min 150 0 45 40 50 0 0 0 25 200 0 0 0 30 80 Min 150 0 50 40 50 0 0 0 30 200 0 0 0 30 Min 150 0 50 50 50 0 0 0 30 200 0 0 0 30 70 ns 80 ns 80 90 Min 150 0 60 50 60 0 0 0 30 200 0 0 0 30 Min 150 0 70 60 70 0 0 0 30 200 0 0 0 30 16 Mbit 90 ns 110 ns 100 110 Min 150 0 70 60 70 0 0 0 30 200 0 0 0 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5, "Command Bus Operations" on page 13 for valid AIN or DIN. 3. Sampled, but not 100% tested. Write timing characteristics during erase suspend are the same as during write-only operations. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. See Figure 8, "AC Waveform: Read Operations" on page 32. 4. VCCMax = 3.3 V for 32-Mbit and 64-Mbit densities. 34 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Write Operations, continued Density Product # Sym Parameter 3.0 V - 3.3 V(4) 2.7 V - 3.3 V(4) Note W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low 2 2 1 3 3 3 3 3 1 2 2 80 Min 150 0 50 40 50 0 0 0 30 200 0 0 0 30 90 Min 150 0 60 40 60 0 0 0 30 200 0 0 0 30 Min 150 0 60 50 60 0 0 0 30 200 0 0 0 30 80 ns 90 ns 90 100 Min 150 0 70 60 70 0 0 0 30 200 0 0 0 30 Min 150 0 70 60 70 0 0 0 30 200 0 0 0 30 32 Mbit 100 ns 110 ns 100 110 Min 150 0 70 60 70 0 0 0 30 200 0 0 0 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5, "Command Bus Operations" on page 13 for valid AIN or DIN. 3. Sampled, but not 100% tested. Write timing characteristics during erase suspend are the same as during write-only operations. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. See Figure 8, "AC Waveform: Read Operations" on page 32. 4. VCCMax = 3.3 V for 32-Mbit and 64-Mbit densities. 3UHOLPLQDU\ 35 28F800C3, 28F160C3, 28F320C3, 28F640C3 AC Characteristics--Write Operations, continued Density Product # Sym Parameter 2.7 V - 3.3 V(4) Note W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low 2 2 1 3 3 3 3 3 1 2 2 90 Min 150 0 60 40 60 0 0 0 30 200 0 0 0 30 100 Min 150 0 70 40 60 0 0 0 30 200 0 0 0 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 64 Mbit 90 ns 100 ns Unit NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5, "Command Bus Operations" on page 13 for valid AIN or DIN. 3. Sampled, but not 100% tested. Write timing characteristics during erase suspend are the same as during write-only operations. See Figure 6, "Input/Output Reference Waveform" on page 27 for timing measurements and maximum allowable input slew rate. See Figure 8, "AC Waveform: Read Operations" on page 32. 4. VCCMax = 3.3 V for 32-Mbit and 64-Mbit densities. 36 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.7 Erase and Program Timings VPP Symbol Parameter Note tBWPB tBWMB 4-KW Parameter Block Word Program Time 32-KW Main Block Word Program Time Word Program Time for 0.18 Micron Product tWHQV1 / tEHQV1 Word Program Time for 0.25 Micron Product 4-KW Parameter Block Erase Time 32-KW Main Block Erase Time Program Suspend Latency Erase Suspend Latency 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 3 3 Typ(1) 0.10 0.8 12 22 0.5 1 5 5 Max 0.30 2.4 200 200 4 5 10 20 Typ(1) 0.03 0.24 8 8 0.4 0.6 5 5 Max 0.12 1 185 185 4 5 10 20 s s s s s s s s 1.65 V-3.6 V 11.4 V-12.6 V Unit tWHQV2 / tEHQV2 tWHQV3 / tEHQV3 tWHRH1 / tEHRH1 tWHRH2 / tEHRH2 NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 3UHOLPLQDU\ 37 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 9. AC Waveform: Program and Erase Operations A VIH VIL CE# (WE#) [E(W)] VIH VIL OE# [G] VIH VIL WE# (CE) [W(E)] VIH VIL W4 W3 W7 DIN DIN Valid SRD DIN High Z W1 W14 W9 (Note 1) W2 W6 B C D E F ADDRESSES [A] AIN W5 AIN W8 (Note 1) DATA [D/Q] VIH VIL RP# [P] WP# VIH VIL VIH VIL W10 W11 W12 W13 VPPH2 V1 VPP [V] PPH VPPLK VIL NOTES: 1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register Data. a. b. c. d. e. f. VCC Power-Up and Standby. Write Program or Erase Setup Command. Write Valid Address and Data (for Program) or Erase Confirm Command. Automated Program or Erase Delay. Read Status Register Data (SRD): reflects completed program/erase operation. Write Read Array Command. 38 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 4.8 Reset Operations Figure 10. AC Waveform: Reset Operations RP# (P) VIH VIL t PLPH (A) Reset during Read Mode t PHQV t PHWL t PHEL Abort Complete t PLRH RP# (P) VIH V IL t PHQV t PHWL t PHEL t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH Abort Deep Complete PowerDown RP# (P) VIH VIL t PLRH t PHQV t PHWL t PHEL t PLPH (C) Reset Program or Block Erase, t PLPH > t PLRH Table 11. Reset Specifications VCC 2.7 V - 3.6 V Symbol Parameter RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) RP# Low to Reset during Block Erase RP# Low to Reset during Program Notes Min tPLPH tPLRH1 tPLRH2 2,4 3,4 3,4 100 22 12 Max ns s s Unit NOTES: 1. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 2. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 3. Sampled, but not 100% tested. See Section 3.1.4 for a full description of these conditions. 3UHOLPLQDU\ 39 28F800C3, 28F160C3, 28F320C3, 28F640C3 5.0 Ordering Information T E2 8 F 3 2 0 C3 T C8 0 Package TE = 48-Lead TSOP GT = 48-Ball BGA* CSP GE = VF BGA CSP RC = Easy BGA Product line designator for all Intel(R) Flash products Device Density 640 = x16 (64 Mbit) 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) Access Speed (ns) (70, 80, 90, 100, 110) Lithography A = 0.25 m C = 0.18 m T = Top Blocking B = Bottom Blocking Product Family C3 = 3 Volt Advanced+ Boot Block VCC = 2.7 V - 3.6 V VPP = 2.7 V - 3.6 V or 11.4 V - 12.6 V VALID COMBINATIONS (All Extended Temperature) 48-Lead TSOP Extended 64 Mbit TE28F640C3TC90 TE28F640C3BC90 TE28F640C3TC100 TE28F640C3BC100 TE28F320C3TC80 TE28F320C3BC80 Extended 32 Mbit TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 TE28F160C3TC70 TE28F160C3BC70 Extended 16 Mbit TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 Extended 8 Mbit TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110 48-Ball BGA* CSP GT28F640C3TC90 GT28F320C3BC90 GT28F320C3TC100 GT28F320C3BC100 48-Ball VF BGA Easy BGA RC28F640C3TC90 RC28F640C3BC90 RC28F640C3TC100 RC28F640C3BC100 GE28F320C3TC80 GE28F320C3BC80 GE28F320C3TC90 GE28F320C3BC90 GT28F320C3TA100 GT28F320C3BA100 GT28F320C3TA110 GT28F320C3BA110 GE28F160C3TC70 GE28F160C3BC70 GE28F160C3TC80 GE28F160C3BC80 GT28F160C3TA90 GT28F160C3BA90 GT28F160C3TA110 GT28F160C3BA110 RC28F320C3TC80 RC28F320C3BC80 RC28F320C3TC90 RC28F320C3BC90 RC28F320C3TA100 RC28F320C3BA100 RC28F320C3TA110 RC28F320C3BA110 RC28F160C3TC70 RC28F160C3BC70 RC28F160C3TC80 RC28F160C3BC80 RC28F160C3TA90 RC28F160C3BA90 RC28F160C3TA110 RC28F160C3BA110 RC28F800C3TA90 RC28F800C3BA90 RC28F800C3TA110 RC28F800C3BA110 NOTE: 1. The second line of the 48-ball BGA package top side mark specifies assembly codes. For samples only, the first character signifies either "E" for engineering samples or "S" for silicon daisy chain samples. All other assembly codes without an "E" or "S" as the first character are production units. 40 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 6.0 Additional Information Order Number 297938 292216 292215 Contact your Intel Representative 297874 Document/Tool 3 Volt Advanced+ Boot Block Flash Memory Specification Update AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture Intel(R) Flash Data Integrator (IFDI) Software Developer's Kit IFDI Interactive: Play with Intel(R) Flash Data Integrator on Your PC NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools. 3UHOLPLQDU\ 41 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix A WSM Current/Next States, Sheet 1 of 2 Command Input (and Next State) Data When Read Array Status Config CFI Status Status Status Status Status Status Status Status Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Read Array Program (Not Done) Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Prog. Setup Ers. Setup Erase (Not Done) Prog. (Not Done) Prog. (Not Done) Prog. (Not Done) Prog. (Not Done) Read Array Prog. Setup Read Array (FFH) Read Array Read Array Read Array Read Array Program Setup (10/ 40H) Prog. Setup Prog. Setup Prog. Setup Prog. Setup Erase Setup (20H) Ers. Setup Ers. Setup Ers. Setup Ers. Setup Lock (Done) Ers. Setup Ers. Setup Erase Confirm (D0H) Prog/Ers Suspend (B0H) Read Array Read Array Read Array Read Array Lock Cmd. Error Read Array Read Array Protection Register Program Protection Register Program (Not Done) Ers. Setup Read Array Program Prog. Sus. Status Prog. Sus. Rd. Array Prog. Sus. Rd. Array Prog. Sus. Rd. Array Prog. Sus. Rd. Array Read Array Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Read Status Erase (Not Done) Prog. Sus. Rd. Array Prog. Sus. Rd. Array Prog. Sus. Rd. Array Prog. Sus. Rd. Array Read Array Read Sts. Read Array Lock (Done) Prog/Ers Resume (D0) Read Status (70H) Read Sts. Read Sts. Read Sts. Read Sts. Clear Status (50H) Read Array Read Array Read Array Read Array Current State SR. 7 "1" "1" "1" "1" "1" "1" "1" "1" "0" "1" "1" "0" Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Oper. (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config Prog. Susp. Read Query Program (Done) Lock Command Error Read Array Read Array Prog. Setup Prog. Setup Lock Cmd. Error Read Sts. Read Sts. Read Array Read Array "1" Status "1" Array "1" Config "1" CFI "1" Status Erase Setup "1" Status Erase Command Error Erase Cmd. Error Erase Command Error Erase Cmd. Error "1" Status Read Array Prog. Setup Ers. Setup Read Array Erase Sus. Status Erase Ers. Sus. Rd. Array Ers. Sus. Rd. Array Ers. Sus. Rd. Array Ers. Sus. Rd. Array Read Array Erase Read Status Erase (Not Done) Erase Sus. Status Erase Sus. Status Erase Sus. Status Erase Sus. Status Read Sts. Read Array Erase (Not Done) "0" Status Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Read Array Erase (Not Done) Ers. Sus. Rd. Array Ers. Sus. Rd. Array Ers. Sus. Rd. Array Ers. Sus. Rd. Array Ers. Setup Ers. Susp. Status "1" Status Prog. Setup Ers. Sus. Rd. Array Ers. Sus. Rd. Array Ers. Sus. Rd. Array Ers. Sus. Rd. Array Read Array Erase Susp. Array Ers. Susp. Read Config Ers. Susp. Read Query Erase (Done) "1" Array Prog. Setup Erase Erase "1" Config Prog. Setup Erase Erase "1" "1" CFI Status Prog. Setup Prog. Setup Erase Erase 42 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix A: WSM Current/Next States, Sheet 2 of 2 Command Input (and Next State) Lock Setup (60H) Lock Down Confirm (2FH) Read Array Read Array Read Array Read Array Lock Operation (Done) Prot. Prog. Setup Prot. Prog. Setup Protection Register Program Protection Register Program (Not Done) Read Array Read Array Current State Read Config (90H) Read Query (98H) Prot. Prog. Setup (C0H) Lock Confirm (01H) Unlock Confirm (D0H) Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Oper. (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config. Prog. Susp. Read Query. Program (Done) Erase Setup Erase Cmd. Error Erase (Not Done) Erase Susp. Status Erase Suspend Array Eras Sus. Read Config Eras Sus. Read Query Ers.(Done) Read Config. Read Config. Read Config. Read Config. Read Query Read Query Read Query Read Query Lock Setup Lock Setup Lock Setup Lock Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Locking Command Error Read Config. Read Config. Read Query Read Query Lock Setup Lock Setup Read Config. Read Query Lock Setup Prot. Prog. Setup Program Program (Not Done) Read Array Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Read Config. Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Read Query Lock Setup Program Suspend Read Array Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Read Array Erase (Not Done) Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Prot. Prog. Setup Erase Command Error Read Config. Read Query Lock Setup Prot. Prog. Setup Erase (Not Done) Ers. Susp. Read Config. Ers. Susp. Read Config. Erase Suspend Read Config. Erase Suspend Read Config. Read Config. Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Read Query Erase (Not Done) Erase (Not Done) Erase (Not Done) Erase (Not Done) Read Array Lock Setup Erase Suspend Read Array Lock Setup Erase Suspend Read Array Lock Setup Erase Suspend Read Array Lock Setup Lock Setup Erase Suspend Read Array Prot. Prog. Setup 3UHOLPLQDU\ 43 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix B Program/Erase Flowcharts Figure 11. Automated Word Programming Flowchart Start Bus Operation Write Write Command Program Setup Program Comments Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 40H Program Address/Data Read Read Status Register Standby SR.7 = 1? Yes Full Status Check if Desired No Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4 = 0 1 SR.1 = 0 Program Successful If an error is detected, clear the status register before attempting retry or other error recovery. Bus Operation Standby Command Comments Check SR.3 1 = VPP Low Detect Check SR.4 1 = VPP Program Error Check SR.1 1 = Attempted Program to Locked Block - Program Aborted VPP Range Error 1 Programming Error Standby Standby SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. Attempted Program to Locked Block - Aborted SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked. 44 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 12. Program Suspend/Resume Flowchart Bus Operation Write Start Command Program Suspend Read Status Comments Data = B0H Addr = X Data=70H Addr=X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed Write B0H Write Write 70H Read Read Status Register Standby SR.7 = 1 SR.2 = 1 0 Standby Write Read Array Data = FFH Addr = X Read array data from block other than the one being programmed. 0 Program Completed Read Program Resume Write Write FFH Data = D0H Addr = X Read Array Data Done Reading Yes Write D0H No Write FFH Program Resumed Read Array Data 3UHOLPLQDU\ 45 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 13. Automated Block Erase Flowchart Start Bus Operation Command Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 20H Write Erase Setup Write D0H and Block Address Write Erase Confirm Read Read Status Register No Suspend Erase Loop 0 Suspend Erase Yes Standby SR.7 = 1 Full Status Check if Desired Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. Write FFH after the last write operation to reset device to read array mode. Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4,5 = 0 1 SR.5 = 0 1 SR.1 = 0 Block Erase Successful Attempted Erase of Locked Block - Aborted SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Bus Operation Standby Command Comments Check SR.3 1 = VPP Low Detect Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted VPP Range Error Standby 1 Command Sequence Error Standby Standby Block Erase Error SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. 46 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 14. Erase Suspend/Resume Flowchart Bus Operation Write Start Command Erase Suspend Read Status Comments Data = B0H Addr = X Data=70H Addr=X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed Write B0H Write Write 70H Read Read Status Register Standby SR.7 = 1 SR.6 = 1 0 Standby Write Read Array Data = FFH Addr = X Read array data from block other than the one being erased. 0 Erase Completed Read Write Erase Resume Write FFH Data = D0H Addr = X Read Array Data Done Reading Yes Write D0H No Write FFH Erase Resumed Read Array Data 3UHOLPLQDU\ 47 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 15. Locking Operations Flowchart Bus Operation Write Start Command Config. Setup Comments Data = 60H Addr = X Data= 01H (Lock Block) D0H (Unlock Block) 2FH (Lockdown Block) Addr=Within block to lock Data = 90H Addr = X Block Lock Status Data Addr = Second addr of block Confirm Locking Change on DQ1, DQ0. (See Block Locking State Table for valid combinations.) Write 60H (Configuration Setup) Write 01H, D0H, or 2FH Write Lock, Unlock, or Lockdown Read Configuration Block Lock Status Write (Optional) Read (Optional) Standby (Optional) Write 90H (Read Configuration) Optional Read Block Lock Status Locking Change Confirmed? No Write FFh (Read Array) Locking Change Complete 48 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Figure 16. Protection Register Programming Flowchart Start Bus Operation Write Write Command Protection Program Setup Protection Program Comments Data = C0H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Standby Read Status Register SR.7 = 1? Yes Full Status Check if Desired No Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1, 1 SR.3, SR.4 = VPP Range Error 0,1 SR.1, SR.4 = Standby Bus Operation Standby Command Comments SR.1 SR.3 SR.4 0 1 1 VPP Low 0 0 1 Prot. Reg. Prog. Error Register Locked: Aborted 1 0 1 Protection Register Programming Error Attempted Program to Locked Register Aborted Standby SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. 1,1 SR.1, SR.4 = SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Program Successful 3UHOLPLQDU\ 49 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix C Common Flash Interface Query Structure This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. C.1 Query Structure Output The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 12. Summary of Query Structure Output As a Function of Device and Mode Device Hex Offset 10: Device Addresses 11: 12: Code 51 52 59 ASCII Value "Q" "R" "Y" 50 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 13. Example of Query Structure Output of x16 and x8 Devices Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Hex Code D15-D0 "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Value Offset A7-A0 10h 11h 12h 13h 14h 15h 16h 17h 18h ... 51 52 59 P_IDLO P_IDLO P_IDHI ... Byte Addressing Hex Code D7-D0 "Q" "R" "Y" PrVendor ID # ID # ... Value C.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. Table 14. Query Structure(1) Offset 00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h P(3) Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Description Manufacturer Code Device Code Block-Specific Information Reserved for Vendor-Specific Information Command Set ID and Vendor Data Offset Device Timing and Voltage Information Flash Device Layout Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table. 3UHOLPLQDU\ 51 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.3 Block Lock Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. This bit is only reset by issuing another erase operation to the block. The Block Status Register is accessed from word address 02h within each block. Table 15. Block Status Register Offset (BA+2)h (1) Length 1 Description Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR.1 Block Lock-Down Status 0 = Not locked down 1 = Locked down BSR 2-7: Reserved for future use Add. BA+2: BA+2: Value --00 or --01 (bit 0): 0 or 1 BA+2: BA+2: (bit 1): 0 or 1 (bit 2-7): 0 NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.) C.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 16. CFI Identification Offset Length Description Add. 10 11: 12: 13: 14: 15: 16: 17: 18: 19: 1A: Hex Code --51 --52 --59 --03 --00 --35 --00 --00 --00 --00 --00 Value "Q" "R" "Y" 10h 3 Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address 0000h means none exists 13h 15h 17h 19h 2 2 2 2 52 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.5 System Interface Information Table 17. System Interface Information Offset Length Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out =2n s "n" such that typical max. buffer write time-out = 2 s "n" such that typical block erase time-out = 2 ms "n" such that typical full chip erase time-out = 2 ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2 times typical "n" such that maximum chip erase time-out = 2 times typical n n n n n Add. Hex Code --27 Value 1Bh 1 1B: 2.7 V 1Ch 1 1C: --36 3.6 V 1Dh 1 1D: --B4 11.4 V 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 1 1 1 1 1 1 1 1 1 1E: 1F: 20: 21: 22: 23: 24: 25: 26: --C6 --05 --00 --0A --00 --04 --00 --03 --00 12.6 V 32 s NA 1s NA 512s NA 8s NA 3UHOLPLQDU\ 53 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.6 Device Geometry Definition Table 18. Device Geometry Definition Offset 27h 28h Length 1 2 Description "n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 2Ah 2 "n" such that maximum number of bytes in write buffer = 2n Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 27: 28: 29: 2A: 2B: --01 --00 --00 --00 0 x16 Code See table below 2Ch 1 2C: --02 2 2Dh 4 2D: 2E: 2F: 30: 31: 32: 33: 34: 31h 4 Device Geometry Definition Address -B 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: --14 --01 --00 --00 --00 --02 --07 --00 --20 --00 --0E --00 --00 --01 8 Mbit -T --14 --01 --00 --00 --00 --02 --0E --00 --00 --01 --07 --00 --20 --00 -B --15 --01 --00 --00 --00 --02 --07 --00 --20 --00 --1E --00 --00 --01 16 Mbit -T --15 --01 --00 --00 --00 --02 --1E --00 --00 --01 --07 --00 --20 --00 -B --16 --01 --00 --00 --00 --02 --07 --00 --20 --00 --3E --00 --00 --01 32 Mbit -T --16 --01 --00 --00 --00 --02 --3E --00 --00 --01 --07 --00 --20 --00 -B --17 --01 --00 --00 --00 --02 --07 --00 --20 --00 --7E --00 --00 --01 64 Mbit -T --17 --01 --00 --00 --00 --02 --7E --00 --00 --01 --07 --00 --20 --00 54 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 C.7 Intel-Specific Extended Query Table Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 19. Primary-Vendor Specific Extended Query Offset(1) P = 35h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Length Description (Optional Flash Features and Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. (P+5)h (P+6)h (P+7)h (P+8)h 4 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant individual block locking supported Protection bits supported Page mode read supported Synchronous read supported Address 35: 36: 37: 38: 39: 3A: 3B: 3C: 3D: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 =0 =1 =1 =0 =0 =1 =1 =0 =0 Hex Code --50 --52 --49 --31 --30 --66 --00 --00 --00 No Yes Yes No No Yes Yes No No Value "P" "R" "I" "1" "0" 3 1 1 (P+9)h 1 Supported functions after suspend: Read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend 3E: --01 bit 0 = 1 3F: --03 --00 bit 0 = 1 bit 1 = 1 Yes (P+A)h (P+B)h 2 Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status Register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/ erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts 40: Yes Yes (P+C)h 1 41: --33 3.3 V (P+D)h 1 42: --C0 12.0 V 3UHOLPLQDU\ 55 28F800C3, 28F160C3, 28F320C3, 28F640C3 Table 20. Protection Register Information Offset(1) P = 35h (P+E)h (P+F)h (P+10)h (P+11)h Length 1 Description (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Address 43: 44: 45: 46: Hex Code --01 --80 --00 --03 Value 01 80h 00h 8 byte Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with deviceunique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and userprogrammable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC -plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user programmable bytes Reserved for future use NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h. 4 (P+12)h 47: --03 8 byte (P+13)h 48: 56 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix D Architecture Block Diagram DQ0-DQ15 VCCQ Output Buffer Input Buffer Output Multiplexer Status Register Data Register Identifier Register I/O Logic Command User Interface CE# WE# OE# RP# WP# Power Reduction Control A0-A19 Y-Decoder Input Buffer 4-KWord Parameter Block Data Comparator Y-Gating/Sensing 4-KWord Parameter Block 32-KWord Main Block Write State Machine 32-KWord Main Block Program/Erase Voltage Switch VPP Address Latch Address Counter X-Decoder VCC GND 3UHOLPLQDU\ 57 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix E Word-Wide Memory Map Diagrams 8-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Bottom Boot Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 8 Mbit 7F000-7FFFF 7E000-7EFFF 7D000-7DFFF 7C000-7CFFF 7B000-7BFFF 7A000-7AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF 8 Mbit 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 58 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF 32 Mbit 64 Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 This column continues on next page 16 Mbit Bottom Boot 32 Mbit 64 Mbit 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 1FF000-1FFFFF 3FF000-3FFFFF 1FE000-1FEFFF 3FE000-3FEFFF 1FD000-1FDFFF 3FD000-3FDFFF 1FC000-1FCFFF 3FC000-3FCFFF 1FB000-1FBFFF 3FB000-3FBFFF 1FA000-1FAFFF 3FA000-3FAFFF 1F9000-1F9FFF 3F9000-3F9FFF 1F8000-1F8FFF 3F8000-3F8FFF 1F0000-1F7FFF 3F0000-3F7FFF 1E8000-1EFFFF 3E8000-3EFFFF 1E0000-1E7FFF 3E0000-3E7FFF 1D8000-1DFFFF 3D8000-3DFFFF 1D0000-1D7FFF 3D0000-3D7FFF 1C8000-1CFFFF 3C8000-3CFFFF 1C0000-1C7FFF 3C0000-3C7FFF 1B8000-1BFFFF 3B8000-3BFFFF 1B0000-1B7FFF 3B0000-3B7FFF 1A8000-1AFFFF 3A8000-3AFFFF 1A0000-1A7FFF 3A0000-3A7FFF 198000-19FFFF 398000-39FFFF 190000-197FFF 390000-397FFF 188000-18FFFF 388000-38FFFF 180000-187FFF 380000-387FFF 178000-17FFFF 378000-37FFFF 170000-177FFF 370000-377FFF 168000-16FFFF 368000-36FFFF 160000-167FFF 360000-367FFF 158000-15FFFF 358000-35FFFF 150000-157FFF 350000-357FFF 148000-14FFFF 348000-34FFFF 140000-147FFF 340000-347FFF 138000-13FFFF 338000-33FFFF 130000-137FFF 330000-337FFF 128000-12FFFF 328000-32FFFF 120000-127FFF 320000-327FFF 118000-11FFFF 318000-31FFFF 110000-117FFF 310000-317FFF 108000-10FFFF 308000-30FFFF 100000-107FFF 300000-307FFF 0F8000-0FFFFF 2F8000-2FFFFF 0F0000-0F7FFF 2F0000-2F7FFF 0E8000-0EFFFF 2E8000-2EFFFF 0E0000-0E7FFF 2E0000-2E7FFF 0D8000-0DFFFF 2D8000-2DFFFF 0D0000-0D7FFF 2D0000-2D7FFF 0C8000-0CFFFF 2C8000-2CFFFF 0C0000-0C7FFF 2C0000-2C7FFF 0B8000-0BFFFF 2B8000-2BFFFF 0B0000-0B7FFF 2B0000-2B7FFF 0A8000-0AFFFF 2A8000-2AFFFF This column continues on next page 3UHOLPLQDU\ 59 28F800C3, 28F160C3, 28F320C3, 28F640C3 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF 64 Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit Bottom Boot 32 Mbit 64 Mbit 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-21FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF This column continues on next page 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F8000-FFFFF F0000-F7FFF F0000-F7FFF E8000-EFFFF E8000-EFFFF E0000-E7FFF E0000-E7FFF D8000-DFFFF D8000-DFFFF D0000-D7FFF D0000-D7FFF C8000-CFFFF C8000-CFFFF C0000-C7FFF C0000-C7FFF This column continues on next page 60 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit 64 Mbit 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 16 Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Bottom Boot 32 Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 64 Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 3UHOLPLQDU\ 61 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix F Device ID Table Read Configuration Addresses and Data Item Manufacturer Code Device Code 8-Mbit x 16-T 8-Mbit x 16-B 16-Mbit x 16-T 16-Mbit x 16-B 32-Mbit x 16-T 32-Mbit x 16-B 64-Mbit x 16-T 64-Mbit x 16-B x16 x16 x16 x16 x16 x16 x16 x16 00001 00001 00001 00001 00001 00001 00001 00001 88C0 88C1 88C2 88C3 88C4 88C5 88CC 88CD x16 Address 00000 Data 0089 NOTE: Other locations within the configuration address space are reserved by Intel for future use. 62 3UHOLPLQDU\ 28F800C3, 28F160C3, 28F320C3, 28F640C3 Appendix G Protection Register Addressing Word-Wide Protection Register Addressing Word LOCK 0 1 2 3 4 5 6 7 Use Both Factory Factory Factory Factory User User User User A7 1 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A21-A8 = 0. 3UHOLPLQDU\ 63 |
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