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TDA7535
DELTA/SIGMA CASCADE 20 BIT STEREO DAC
s s s s s s s s s s
20-bit resolution single ended output Analog reconstruction third order Chebyshev filter I2S input data format On chip PLL System clock: 64 Fs 2 output channels 0.9 VRMS single ended output dynamic 3.3V power supply Reset Sampling rate 36KHz to 48KHz
TSSOP-14
SO-14
ORDERING NUMBER: TDA7535
DESCRIPTION The TDA7535 is a stereo, digital-to-analog converter designed for audio application, including digital interpolation filter, a third order multibit Delta-Sigma DAC, a third order Chebyshev's reconstruction filter and a differential to single ended output converter. This device is fabricated in highly advanced CMOS, where high speed precision analog circuits are combined with high density logic circuits. The TDA7535, according to standard audio converters, can accept any I2S data format. BLOCK DIAGRAM
The TDA7535 is available in SO-14 and TSSOP-14 packages. The total power consumption is less than 75mW. TDA7535 is suitable for a wide variety of applications where high performance are required. Its low cost and single 3.3V power supply make it ideal for several applications, such as CD players, MPEG audio, MIDI applications, CD-ROM drives, CD-Interactive, digital radio applications and so on. An evaluation board is available to perform measurement and to make listening tests.
I2S
I2S
DIGITAL INPUT 20 FS CLKOUT
FIR1
FIR2
FIR3
20 8FS
S&H
23 64FS
MODULATOR
PLL
ALU
4 ANALOG OUTPUT
THERMO DECODER & RANDOMIZER
D02AU1417
3rd CHEBYSHEV SC FILTER
DIFF TO SINGLE CONVERTER
July 2003
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TDA7535
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VCC Vaio Vdio Vdi5 Tj Tstg Power supplies Analog Input and Output Voltage Digital Input and Output Voltage Digital Input Voltage (5V tolerant) Operating Junction Temperature Range Storage Temperature Parameter Digital Analog Value -0.5 to +4.6 -0.5 to +4.6 -0.5 to (VCC+0.5) -0.5 to (VDD+0.5) -0.5 to 6.5 -40 to 125 -55 to 150 Unit V V V V V C C
Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
THERMAL DATA
Symbol Rth j-amb Parameter Thermal resistance junction to ambient
(1)
Value 85
Unit C/W
Note: 1. In still air
PIN CONNECTIONS (Top views)
N.C. SDATA SCK N.C. GND_DIG GND_ANA OUTSR 1 2 3 4 5 6 7
D01AU1276A
14 13 12 11 10 9 8
RESETN FSYNC VDD_DIG N.C. VDD_ANA VCM OUTSL
PIN FUNCTION (SO14/TSSOP14)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name N.C. SDATA SCK N.C. GND_DIG GND_ANA OUTSR OUTSL VCM VDD_ANA N.C. VDD_DIG FSYNC RESETN Input/Output Power I I P P O O P P P I I I2S Digital Data Input I2S Clock Input Digital Ground Analog Ground Right Channel single ended Output Left Channel single ended Output Reference 1.65V externally filtered Analog 3.3V-Supply Digital 3.3V-Supply I2S Left-Right Channel selector Reset (active low) Description
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RECOMMENDED DC OPERATING CONDITIONS
Symbol VDD VCC Parameter 3.3V Digital Power Supply Voltage 3.3V Analog Power Supply Voltage Test Condition Min. 3.15 3.15 Typ. 3.3 3.3 Max. 3.45 3.45 Unit V V
POWER CONSUMPTION
Symbol Idd Parameter Total Maximum Current Test Condition power supply @ 3.3V and Tj = 125C Min. Typ. 21.5 Max. 25 Unit mA
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol lil lih Ilatchup Vesd Parameter Low Level Input Current without pullup device High Level Input Current without pullup device I/O latch-up current Electrostatic Protection Test Condition Vi = 0V (note 1) Vi = Vdd (note 1) V < 0V, V > Vdd Leakage , 1A (note 2) 200 2000 Min. Typ. Max. 1 1 Unit A A mA V
Note: 1. The leakage currents are generally very small, <1nA. The value given here, 1mA, is the maximum that can occur after an Electrostatic Stress on the pin. 2. Human Body Model.
LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS
Symbol Vil Vih Vhyst Parameter Low Level Input Voltage High Level Input Voltage Schmitt trigger hysteresis 0.8*Vdd 0.8 Test Condition Min. Typ. Max. 0.2*Vdd Unit V V V
DAC ELECTRICAL CHARACTERISTICS Vdd = 3.3V; Tamb = 25C; Input signal frequency = sinus wave generated by Audio Precision Sys.2; Input Signal Amplitude = see notes; Noise Integration Bandwidth = 20Hz to 22KHz (A- weighted)
Parameter Noise + Distortion (see note 1) Test Condition @0dB @-6dBb @-40dB @-60dB see note 2 see note 3 see note 4 Vdd = 3.15 to 3.45V Full scale input 0.8 36 Min. Typ. 89 94 96 96 94 96 -95 0.9 1.0 48 Max. Unit dB dB dB dB dB dB dB Vrms kHz
Total Harmonic Distortion Dynamic range Crosstalk Full Scale Output Voltage Input Sampling Rate
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DAC ELECTRICAL CHARACTERISTICS (continued) Vdd = 3.3V; Tamb = 25C; Input signal frequency = sinus wave generated by Audio Precision Sys.2; Input Signal Amplitude = see notes; Noise Integration Bandwidth = 20Hz to 22KHz (A- weighted)
Parameter Passband Ripple Stopband @ 3dB @ 90dB 44.1kHz Sampling Rate 21.53 24.80 0.05 0.1 dB Test Condition Min. Typ. 0.12 Max. Unit dB kHz
Interchannel Gain Mismatch
Note1: Note 2: Note 3: Note 4:
It is the ratio between the maximum input signal and the integration of the in-band noise after deducing the power of signal fundamental. It depends on the input signal amplitude. In this case 0dB means full scale digital, 1kHz frequency used. It is the ratio of the rms value of the signal fundamental component at 0dB (full scale digital) to the rms value of all of the harmonic components in the band. measured using the SNR at -60dB input signal, with 60dB added to compensate for small input signal. Left channel on with 0dB/1kHz input signal, Right channel on with DC input signal.
Figure 1. I2S interface Diagram
Left
FSYNC
Right
32 * SCK SCK
SDATA
32 * SCK
20 Bits
20 Bits
MSB
LSB
MSB
LSB
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TDA7535
Figure 2. I2S Timings
SDATA
Valid
FSYNC tsckr
Valid
tsckf
SCK
tlrwtlrw+ tsds tsckpl tsck tsdh tsckph
Timing tsck tsckpl tsckph tlrwtlrw+ tsds tsdh tsckr tsckf Clock Cycle(1) SCK Phase Low SCK Phase High
Description
Minimum 1/(64*Fs) 150psRMS 0.5*tsck - 1% 0.5*tsck - 1% 0 0 60 30
Maximum 1/(64*Fs) + 150psRMS 0.5*tsck +1% 0.5*tsck +1% 0.125*tsck-10 0.125*tsck-10
Unit ns ns ns ns ns ns ns
FSYNC switching time window before SCK falling edge(2) FSYNC switching time window after SCK falling edge(2) SDATA setup time SDATA hold time SCK rise time SCK fall time
1.5 1.5
ns ns
(1) SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212psRMS (2) FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK
Figure 3. Power Up & Reset Sequence
VDD
RESET TRES TRES Min 50ms
D02AU1418
I2S bit clock (SCK) must be present 20ms before reset release to allow PLL locking.
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Figure 4. Frequency response
Figure 5.
R2 10K +3.3 VDIG C7 10F 10V 14 SW1 P +3.3VANA 10F RESETN 10 VDD_ANA 10H bead inductor VDD_DIG 100nF(*) 100nF(*)
TP1 SDATA TP2 IS TP3 FSYNC
2
U4
2
SCK
3
12
13
10F
TP5 GND_DIG 5 8 OUTSL TP6 6 TP7 9 7 OUTSR TP8
D02AU1419B
(*) AS CLOSE AS POSSIBLE TO THE PIN
J3 BNC OUTSL
GND_ANA
VCM C16 100nF (*) C15 47F 10V (*)
J4 BNC OUTSR
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mm MIN.. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 8.55 5.8 1.27 7.62 4 5.3 1.27 0.68 8 (max.) 0.150 0.181 0.016 0.35 0.19 0.5 45 (typ.) 8.75 6.2 0.336 0.228 0.050 0.300 0.157 0.209 0.050 0.027 0.344 0.244 0.1 TYP. MAX.. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 MIN.. inch TYP.. MAX.. 0.069 0.009 0.063 0.018 0.010
DIM.
OUTLINE AND MECHANICAL DATA
SO14
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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mm DIM. MIN. A A1 A2 b c D (1) E E1 (1) e L L1 k aaa
Note:
inch MAX. 1.200 MIN. TYP. MAX. 0.047 0.002 0.031 0.007 0.005 0.114 0.244 0.170 0.118 0.252 0.173 0.026 0.750 0.018 0.024 0.039 0 (min.) 8 (max.) 0.100 0.004 0.030 0.039 0.006 0.041 0.012 0.009 0.122 0.260 0.177
TYP.
OUTLINE AND MECHANICAL DATA
0.050 0.800 0.190 0.090 4.900 6.200 4.300 5.000 6.400 4.400 0.650 0.450 0.600 1.000 1.000
0.150 1.050 0.300 0.200 5.100 6.600 4.500
1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
TSSOP-14 (Body 4.4mm)
0080337 (Jedec MO-153-AA)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
(R)
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