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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
Rev. 01 -- 29 November 2005 Product data sheet
1. General description
The PCK9448 is a 3.3 V or 2.5 V compatible, 1 : 12 clock fan-out buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. The PCK9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with near zero skew. The output buffers support driving of 50 terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribution systems. The PCK9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic LOW state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient temperature range of -40 C to +85 C.
2. Features
s s s s s s s s s s s 12 LVCMOS compatible clock outputs Selectable LVCMOS and differential LVPECL compatible clock inputs Maximum clock frequency of 350 MHz Maximum clock skew of 150 ps Synchronous output stop in logic LOW state eliminates output runt pulses High-impedance output control 3.3 V or 2.5 V power supply Drives up to 24 series terminated clock lines Tamb = -40 C to +85 C Available in LQFP32 package Supports clock distribution in networking, telecommunications, and computer applications
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
3. Ordering information
Table 1: Ordering information Package Name PCK9448BD LQFP32 Description plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm Version SOT358-1 Type number
4. Functional diagram
PCK9448
VCC
25 k
Q0 Q1 0 CLK STOP 1 Q3
25 k
PCLK PCLK CCLK
Q2
Q4 VCC
25 k
Q5 Q6 Q7 Q8 Q9 Q10
CLK_SEL VCC
25 k
CLK_STOP
SYNC
VCC
25 k
Q11
OE
002aaa720
Fig 1. Functional diagram of PCK9448
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Product data sheet
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
5. Pinning information
5.1 Pinning
32 GND 28 GND 30 VCC 26 VCC 25 Q3 24 GND 23 Q4 22 VCC 21 Q5 20 GND 19 Q6 18 VCC 17 Q7 VCC 10 Q10 11 GND 12 Q9 13 VCC 14 Q8 15 GND 16 9
002aaa721
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29 Q1
31 Q0
CLK_SEL CCLK PCLK PCLK CLK_STOP OE VCC GND
1 2 3 4 5 6 7 8
PCK9448BD
Fig 2. Pin configuration for LQFP32
5.2 Pin description
Table 2: Symbol CLK_SEL CCLK PCLK PCLK OE Q0 to Q11 Pin description Pin 1 2 3 4 6 Type I I I I I I Description clock input select alternative clock signal input clock signal input clock signal input, active LOW clock output enable/disable, active LOW output enable/disable (high-impedance, 3-state) clock outputs
CLK_STOP 5
31, 29, 27, O 25, 23, 21, 19, 17, 15, 13, 11, 9 8, 12, 16, ground 20, 24, 28, 32 7, 10, 14, power 18, 22, 26, 30
GND
negative power supply (GND)
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation.
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Product data sheet
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Q11
27 Q2
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Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
6. Functional description
Refer to Figure 1 "Functional diagram of PCK9448".
6.1 Function table
Table 3: Control CLK_SEL OE CLK_STOP
[1]
Function table Default 1 1 1 Logic 0 outputs disabled (high-impedance state) [1] Logic 1 outputs enabled PECL differential input selected CCLK input selected
outputs synchronously stopped outputs active in logic LOW state
OE = 0 will high-impedance 3-state all outputs independent of CLK_STOP.
7. Limiting values
Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO II IO Tstg Parameter supply voltage input voltage output voltage input current output current storage temperature Conditions Min -0.3 -0.3 -0.3 -65 Max +3.9 VCC + 0.3 VCC + 0.3 20 50 +125 Unit V V V mA mA C
8. Characteristics
8.1 General characteristics
Table 5: Symbol VT Vesd Ilatch(prot) CPD Ci
[1] [2]
General characteristics Parameter termination voltage (output) electrostatic discharge voltage latch-up protection current power dissipation capacitance input capacitance per output inputs Machine Model Human Body Model
[1] [2]
Conditions
Min 200 2000 200 -
Typ
Max
Unit V V V mA pF pF
0.5VCC 10 4.0 -
200 pF capacitor discharged via a 10 resistor and a 0.75 H inductor. 100 pF capacitor discharged via a 1.5 k resistor.
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
8.2 Static characteristics
Table 6: Static characteristics (3.3 V) Tamb = -40 C to +85 C; VCC = 3.3 V 5 %; unless otherwise specified. Symbol VIH VIL VOH VOL Vi(p-p) VICR [1] Zo II Iq(max)
[1] [2]
Parameter HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage peak-to-peak input voltage (PCLK) common-mode input voltage range (PCLK) output impedance input current maximum quiescent current
Conditions LVCMOS LVCMOS IOH = -24 mA IOL = 24 mA IOL = 12 mA LVPECL LVPECL
[2] [2]
Min 2.0 -0.3 2.4 250 1.1 -
Typ 17 -
Max VCC + 0.3 +0.8 0.55 0.30 VCC - 0.6 300 2.0
Unit V V V V V mV V A mA
VI = VCC or GND all VCC pins
[3] [4]
-
VICR (DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the VICR range and the input swing lies within the Vi(p-p) (DC) specification. The PCK9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VT. Alternatively, the device drives up to two 50 series terminated transmission lines (VCC = 3.3 V) or one 50 series terminated transmission line (for VCC = 2.5 V). Inputs have pull-down or pull-up resistors affecting the input current. Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open.
[3] [4]
Table 7: Static characteristics (2.5 V) Tamb = -40 C to +85 C; VCC = 2.5 V 5 %; unless otherwise specified. Symbol VIH VIL VOH VOL Vi(p-p) VICR Zo II Iq(max)
[1] [2]
[1]
Parameter HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage peak-to-peak input voltage (PCLK) common-mode input voltage range (PCLK) output impedance input current maximum quiescent current
Conditions LVCMOS LVCMOS IOH = -15 mA IOL = 15 mA LVPECL LVPECL
[2]
Min 1.7 -0.3 1.8 250 1.0 -
Typ 19 -
Max VCC + 0.3 +0.7 0.6 VCC - 0.7 300 2.0
Unit V V V V mV V A mA
VI = VCC or GND all VCC pins
[3] [4]
-
VICR (DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the VICR range and the input swing lies within the Vi(p-p) (DC) specification. The PCK9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VT. Alternatively, the device drives one 50 series terminated transmission line per output at VCC = 2.5 V. Inputs have pull-down or pull-up resistors affecting the input current. Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open.
[3] [4]
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Product data sheet
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Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
8.3 Dynamic characteristics
Table 8: Dynamic characteristics (3.3 V) Tamb = -40 C to +85 C; VCC = 3.3 V 5 %; unless otherwise specified. [1] Symbol Vi(p-p) VICR [2] fo fi tsk(o) tsk(pr) o tPLH tPHL tPLZ tPHZ tPZL tPZH tsu th tr tf Parameter input voltage (peak-to-peak value) (PCLK, PCLK) common-mode input voltage range (PCLK, PCLK) output frequency input frequency output skew time process skew time output duty cycle LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay LOW to OFF-state propagation delay OFF-state to LOW propagation delay setup time hold time rise time fall time part-to-part fo < 170 MHz; ref = 50 % PCLK to any Q CCLK to any Q PCLK to any Q CCLK to any Q OE to any Q OE to any Q CCLK to CLK_STOP PCLK to CLK_STOP CCLK to CLK_STOP PCLK to CLK_STOP output; 0.55 V to 2.4 V CCLK input; 0.8 V to 2.0 V output; 2.4 V to 0.55 V CCLK input; 2.0 V to 0.8 V
[1] [2] [3] [4] Dynamic characteristics apply for parallel output termination of 50 to VT. VICR (AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the VICR range and the input swing lies within the Vi(p-p) (AC) specification. Violation of VICR or Vi(p-p) impacts static phase offset. Setup and hold times are referenced to the falling edge of the selected clock signal input. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle, and maximum frequency specifications.
[3] [3] [3] [3]
Conditions LVPECL LVPECL
Min 400 1.3 0 0 45 1.6 1.3 1.6 1.3 0.0 0.0 1.0 1.5 0.1 0.1 -
Typ 50 -
Max 1000
Unit mV
VCC - 0.8 V 350 350 150 2.0 55 3.6 3.3 3.6 3.3 11 11 11 11 1.0 1.0 [4] 1.0 1.0 [4] MHz MHz ps ns % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
HIGH to OFF-state propagation delay OE to any Q OFF-state to HIGH propagation delay OE to any Q
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
Table 9: Dynamic characteristics (2.5 V) Tamb = -40 C to +85 C; VCC = 2.5 V 5 %; unless otherwise specified. [1] Symbol Vi(p-p) VICR [2] fi fo tsk(o) tsk(pr) o tPLH tPHL tPLZ tPHZ tPZL tPZH tsu th tr tf Parameter input voltage (peak-to-peak value) (PCLK, PCLK) common-mode input voltage range (PCLK, PCLK) input frequency output frequency output skew time process skew time output duty cycle LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay LOW to OFF-state propagation delay OFF-state to LOW propagation delay setup time hold time rise time fall time output-to-output part-to-part; PCLK or CCLK to any Q ref = 50 % PCLK to any Q CCLK to any Q PCLK to any Q CCLK to any Q OE to any Q OE to any Q CCLK to CLK_STOP PCLK to CLK_STOP CCLK to CLK_STOP PCLK to CLK_STOP input CCLK; 0.8 V to 2.0 V output; 0.6 V to 1.8 V input CCLK; 2.0 V to 0.8 V output; 1.8 V to 0.6 V
[1] [2] [3] [4] Dynamic characteristics apply for parallel output termination of 50 to VT. VICR (AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the VICR range and the input swing lies within the Vi(p-p) (AC) specification. Violation of VICR or Vi(p-p) impacts static phase offset. See Section 9 "Application information" for part-to-part skew calculation. Setup and hold times are referenced to the falling edge of the selected clock signal input.
[4] [4] [4] [4] [3]
Conditions LVPECL LVPECL
Min 400 1.2 0 0 45 1.5 1.7 1.5 1.7 0.0 0.0 1.0 1.5 0.1 0.1
Typ -
Max 1000
Unit mV
VCC - 0.8 V 50 350 350 150 2.7 60 4.2 4.4 4.2 4.4 11 11 11 11 1.0 1.0 1.0 1.0 MHz MHz ps ns % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
HIGH to OFF-state propagation delay OE to any Q OFF-state to HIGH propagation delay OE to any Q
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
CCLK or PCLK
CLK_STOP
Q0 to Q11
002aaa728
Fig 3. Output clock stop (CLK_STOP) timing diagram
tN
tN+1
002aab293
tjit(cc) = | tN - tN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.
Fig 4. Cycle-to-cycle jitter
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
PCLK VICR PCLK tPLH Qn tPHL VCC 0.5VCC GND
002aaa729
VCC CCLK tPLH Qn tPHL VCC 0.5VCC GND
002aab829
0.5VCC GND
Fig 5. Propagation delay test reference (PCLK/PCLK to Qn)
Fig 6. Propagation delay test reference (CCLK to Qn)
VCC CCLK 0.5VCC GND tPLH Qn tsk(p) = | tPLH - tPHL | tPHL VCC 0.5VCC GND
002aab290
Fig 7. Pulse skew time (tsk(p)) test reference
VCC 0.5VCC GND tsk(o) tsk(o) VCC 0.5VCC GND
002aab289
VCC 0.5VCC tp To o = (tp / To x 100 %)
002aab291
GND
The pin-to-pin skew is defined as the worst-case difference in propagation delay between any similar delay path within a single device.
1 T o = ----fo
The time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage.
Fig 8. Output skew time (tsk(o))
(1) (2)
Fig 9. Output duty cycle (o)
tf
tr
002aab292
CCLK PCLK th tsu CLK_STOP
VCC 0.5VCC GND
(1) 2.4 V (VCC = 3.3 V) 1.8 V (VCC = 2.5 V) (2) 0.55 V (VCC = 3.3 V) 0.6 V (VCC = 2.5 V)
VCC 0.5VCC GND
002aaa727
Fig 10. Output transition time test reference
Fig 11. Setup and hold time (tsu, th)
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
9. Application information
9.1 Driving transmission lines
The PCK9448 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC = 3.3 V), the outputs can drive either parallel or series terminated transmission lines. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to 0.5VCC. This technique draws a fairly high level of DC current, and thus only a single terminated line can be driven by each output of the PCK9448 clock driver. For the series terminated case, however, there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 12, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fan-out of the PCK9448 clock driver is effectively doubled due to its capability to drive multiple lines.
PCK9448
OUTPUT BUFFER
Ro Rs = 33 Zo = 50
IN
17
OutA
PCK9448
OUTPUT BUFFER IN
Ro 17
Rs = 33
Zo = 50
OutB0
Rs = 33
Zo = 50
OutB1
002aaa722
Fig 12. Single versus dual transmission lines
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
The waveform plots of Figure 13 show simulation results of an output driving a single line versus two lines. In both cases the drive capability of the PCK9448 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurement in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCK9448. The output waveform in Figure 13 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Zo V L = V S ------------------------------ R s + R o + Z o Z o = 50 || 50 R s = 33 || 33 R o = 17 25 V L = 3.0 ---------------------------------- = 1.28 V 16.5 + 17 + 25 At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns).
002aaa679
3.0 voltage (V) 2.0 IN
OutA td = 3.8956 ns OutB td = 3.9386 ns
1.0
0 -0.5 0 4 8 12 time (ns) 16
Fig 13. Single versus dual line termination waveforms
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 14 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
PCK9448
OUTPUT BUFFER IN
Ro 17
Rs = 16
Zo = 50
Rs = 16
Zo = 50
002aaa723
17 + 16 || 16 = 50 || 50 25 = 25 Fig 14. Optimized dual line termination
9.2 Power consumption of the PCK9448 and thermal management
The PCK9448 dynamic electrical (AC) specification is guaranteed for the entire operating frequency range up to 350 MHz. The PCK9448 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating condition such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCK9448 die junction temperature and the associated device reliability. The long-term device reliability is a function of the die temperature; refer to Table 10.
Table 10: 100 110 120 130 Die junction temperature and MTBF MTBF (years) 20.4 9.1 4.2 2.0
Junction temperature (C)
Increased power consumption will increase the die junctIon temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCK9448 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the PCK9448 is represented in Equation 1. P tot = I q ( max ) + V CC x f clk x N x C PD + C L x V CC
M
(1)
Where Iq(max) is the static current consumption of the PCK9448, CPD is the power dissipation capacitance per output, (M)CL represents the external capacitive output load, N is the number of active outputs (N is always 12 in the case of the PCK9448). The PCK9448 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the limped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from Equation 1. Using parallel termination output termination results in Equation 2 for power dissipation.
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
P tot = V CC x I q ( max ) + V CC x f clk x N x C PD + C L
M
(2)
+ [ o x I OH x ( V CC - V OH ) + ( 1 - DC Q ) x I OL x V OL ]
P
In Equation 2, P stands for the number of outputs with a parallel or Thevenin termination; VOL, IOL, VOH and IOH are a function of the output termination technique; o is the clock signal duty cycle. If transmission lines are used, CL is zero in Equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature Tj as a function of the power consumption. T j = T amb + P tot x R th ( j-a ) (3)
Where Rth(j-a) is the thermal impedance of the package (junction-to-ambient) and Tamb is the ambient temperature. According to Table 10, the junction temperature can be used to estimate the long-term device reliability. Further, combining Equation 1 and Equation 2 results in a maximum operating frequency for the PCK9448 in a series terminated transmission line system, Equation 4. T j ( max ) - T amb 1 f clk ( max ) = ---------------------------------------- x ----------------------------------- - ( I q ( max ) x V CC ) 2 R th ( j-a ) C PD x N x V CC (4)
Tj(max) should be selected according to the MTBF system requirements and Table 10. Rth(j-a) can be derived from Table 11. The Rth(j-a) represent data based on 1S2P boards; using 2S2P boards will result in a lower thermal impedance than indicated below.
Table 11: still air 100 200 300 400 500 Thermal package impedance of the LQFP32 Rth(j-a) (C/W) (1P2S board) 88 76 71 68 66 60 Rth(j-a) (C/W) (2P2S board) 61 56 54 53 52 49
Convection (LFPM)
If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following four derating charts describe the safe frequency operation range for the PCK9448. The charts were calculated for a maximum tolerable die junction temperature of 110 C (120 C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3 V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection, a decision on the maximum operating frequency can be made.
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
10. Test information
PCK9448 D.U.T.
PULSE GENERATOR Z = 50
Zo = 50
Zo = 50
RT = 50
RT = 50
VT
VT
002aaa724
Fig 15. CCLK AC test reference for VCC = 3.3 V and VCC = 2.5 V
DIFFERENTIAL PULSE GENERATOR Z = 50
Zo = 50
PCK9448 D.U.T. Zo = 50
RT = 50
RT = 50
VT
VT
002aaa725
Fig 16. PCLK AC test reference
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
11. Package outline
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1
c
y X
24 25
17 16 ZE
A
e E HE wM bp pin 1 index 32 1 e bp D HD wM B vM B 8 ZD vM A 9 detail X L Lp A A2 A 1 (A 3)
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.4 0.3 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.8 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.25 y 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT358 -1 REFERENCES IEC 136E03 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-25 05-11-09
Fig 17. Package outline SOT358-1 (LQFP32)
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3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 12534 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 29 November 2005
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Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
12.5 Package related soldering information
Table 12: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
9397 750 12534
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 29 November 2005
17 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
13. Abbreviations
Table 13: Acronym ESD HBM MM MTBF LFPM LVPECL LVCMOS Abbreviations Description ElectroStatic Discharge Human Body Model Machine Model Mean Time Between Failures Linear Feet Per Minute Low Voltage Positive Emitter Coupled Logic Low Voltage Complementary Metal Oxide Silicon
14. Revision history
Table 14: Revision history Release date 20051129 Data sheet status Product data sheet Change notice Doc. number 9397 750 12534 Supersedes Document ID PCK9448_1
9397 750 12534
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 29 November 2005
18 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 12534
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 29 November 2005
19 of 20
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
20. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 8.1 8.2 8.3 9 9.1 9.2 10 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General characteristics . . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . 10 Driving transmission lines . . . . . . . . . . . . . . . . 10 Power consumption of the PCK9448 and thermal management . . . . . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17 Package related soldering information . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 29 November 2005 Document number: 9397 750 12534
Published in The Netherlands

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