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19-1314; Rev 0; 10/98
ANUAL N KIT M LUATIO ATA SHEET EVA WS D FOLLO
+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector
____________________________Features
o Single Supply: +3.0V to +5.5V o 3.3mV Input Sensitivity o 1.4ns Output Edge Speed o Loss-of-Signal Detector with Programmable Threshold o Analog Received-Signal-Strength Indicator o Output Squelch Function o Choice of TTL or PECL LOS Outputs o Compatible with 4B/5B Data Coding
________________ General Description
The MAX3964 limiting amplifier, with 3.3mV input sensitivity and PECL data outputs, is ideal for low-cost ATM, FDDI, and Fast Ethernet fiber optic applications. The MAX3964 features an integrated power detector that senses the input-signal power. It provides a received-signal-strength indicator (RSSI), which is an analog indication of the power level and complementary PECL loss-of-signal (LOS) outputs, which indicate when the power level drops below a programmable threshold. The threshold can be adjusted to detect signal amplitudes as low as 2.7mVp-p. An optional squelch function disables switching of the data outputs by holding them at a known state during an LOS condition. The MAX3965 provides the same functionality, but offers TTL-compatible LOS outputs. The MAX3968 provides the same functionality as the MAX3964, but has data-output edge speed suitable for ESCON and 266Mbps fibre channel applications. The MAX3964/MAX3965/MAX3968 are available in die form, as tested wafers, and in 20-pin QSOP packages.
MAX3964/MAX3965/MAX3968
Ordering Information
PART TEMP. RANGE PIN-PACKAGE MAX3964CEP 0C to +70C 20 QSOP MAX3964C/D 0C to +70C Dice* MAX3964C/DW 0C to +70C Wafers* MAX3965CEP 0C to +70C 20 QSOP MAX3965C/D 0C to +70C Dice* MAX3965C/DW 0C to +70C Wafers* MAX3968CEP 0C to +70C 20 QSOP MAX3968C/D 0C to +70C Dice* MAX3968C/DW 0C to +70C Wafers* *Dice and wafers are designed to operate over a 0C to +100C junction temperature (Tj) range, but are tested and guaranteed only at TA = +25C. Pin Configurations appear at end of data sheet.
________________________Applications
125Mbps FDDI Receivers 155Mbps LAN ATM Receivers Fast Ethernet Receivers ESCON Receivers 266Mbps Fibre Channel Receivers
Typical Operating Circuit
VCC VCC FILTER VCC0 CIN 10nF CZP CAZ 27nF CZN RSSI SQUELCH VCC PHOTODIODE VCC LOS+ LOS TERMINATIONS ARE USED ONLY FOR THE MAX3964 AND MAX3968
10nF VCC
FILTER 10nF
MAX3960
OUTOUT+
ININ+ CIN 10nF (MAX3965 ONLY) GNDO INV
MAX3964 MAX3965 MAX3968
LOSOUTOUT+ SUB GND VTH 50 50 50
50
IN GND
VCC - 2V R1 100k R2
________________________________________________________________ Maxim Integrated Products
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For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964/MAX3965/MAX3968
ABSOLUTE MAXIMUM RATINGS
(SUB, GND, GNDO tied to ground) VCC, VCCO .............................................................-0.5V to +7.0V FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH, LOS+, LOS-, INV, VTH, OUT+, OUT- ......-0.5V to (VCC + 0.5V) PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA Differential Voltage Between CZP and CZN..........-1.5V to +1.5V Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V Continuous Power Dissipation (TA = +70C) QSOP (derate 6.7mW/C above +70C) .......................500mW Operating Temperature Range............................-40C to +85C Operating Junction Temperature Range (die) .....-40C to +150C Processing Temperature (die) .........................................+400C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, PECL outputs terminated with 50 to (VCC - 2V), TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Note 1) PARAMETER Supply Current LOS Hysteresis SQUELCH Input Current PECL Output Voltage High PECL Output Voltage Low PECL LOS Output Voltage High PECL LOS Output Voltage Low LOS Assert Accuracy Minimum LOS Assert Input Maximum LOS Deassert Input Input Sensitivity Input Overload Data Output Edge Speed Pulse-Width Distortion TTL Output High TTL Output Low Note 1: Note 2: Note 3: Note 4: 20% to 80% transition time, MAX3964/MAX3965 MAX3968 (Note 4) IOH = -200A IOL = 200A 2.4 0 1.5 0.92 0.4 1.2 0.8 50 3.1 0.3 2.2 1.2 200 VCC 0.4 143 2.0 3.3 (Note 2) VSQUELCH = VCC, TA = +25C (Note 3) (Note 3) (Note 3) (Note 3) Input = 7mVp-p or 90mVp-p -1025 -1810 -1035 -1810 -2.5 CONDITIONS Excludes PECL output current 3.8 MIN TYP 22 5 27 MAX 40 8.0 100 -880 -1620 -880 -1620 2.5 2.7 UNITS mA dB A mV mV mV mV dB mVp-p mVp-p mVp-p Vp-p ns ns ps V V
Dice are tested and guaranteed at TA = +25C only. LOS hysteresis = 20log(VLOS-DEASSERT / VLOS-ASSERT). Input = 3.3mVp-p to 90mVp-p. Voltage measurements are relative to supply voltage (VCC). PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern.
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+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector
__________________________________________Typical Operating Characteristics
(MAX3964 evaluation kit, VCC = +3.3V, decibels (dB) calculated as 20 log V, PECL outputs terminated with 50 to (VCC - 2V), TA = +25C, unless otherwise noted.)
PULSE-WIDTH DISTORTION vs. INPUT AMPLITUDE
MAX3964/65toc02 MAX3964/65toc03
MAX3964/MAX3965/MAX3968
RSSI VOLTAGE vs. INPUT AMPLITUDE
INPUT PATTERN IS 223-1 PRBS
MAX3964/65toc01
RSSI VOLTAGE vs. TEMPERATURE
2.3 2.2 2.1 VRSSI (V) 2.0 1.9 1.8 1.7 1.6 INPUT = 10mV INPUT = 5mV INPUT = 100mV 100 90 80 PWD (ps) 70 60 50 40 30 -40 -20 0 20 40 60 80 100 1
3.00
2.50 LOS DEASSERTED VRSSI (V) 2.00 LOS ASSERTED 1.50
1.00 1 10 100 1k INPUT AMPLITUDE (mV)
1.5 TEMPERATURE (C)
10
100
1k
10k
INPUT AMPLITUDE (mVp-p)
DATA OUTPUT EDGE SPEED (20% to 80%) vs. TEMPERATURE
MAX3964/65toc04
OUTPUT AMPLITUDE vs. INPUT VOLTAGE (DIFFERENTIAL SIGNAL LEVELS)
MAX3964/65toc05
3.0
1600
MAX3964/MAX3965 1.8
OUTPUT AMPLITUDE (mV)
2.4 EDGE SPEED (ns)
1400
1200
1.2 MAX3968 0.6
1000
800
0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
600 0.1 1 10 100 1k 10k INPUT VOLTAGE (mV)
LOS OPERATION WITH SQUELCH
MAX3964 toc06
MAX3964/MAX3965 EYE DIAGRAM (INPUT = 3.3mV)
MAX3964 toc07
DATA INPUT
DATA OUTPUT
100mV/ div
LOS+
10s/div
1ns/div
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+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964/MAX3965/MAX3968
Pin Description
PIN 1 NAME SQUELCH FUNCTION Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high during a loss-of-signal condition. Connect to GND or leave unconnected to disable. Connect to VCC to enable squelching. Output of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a resistor from VTH to INV, and from INV to ground (minimum resistance 100k) to program the desired threshold voltage. Inverting Input of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a resistor from VTH to INV, and from INV to ground (minimum resistance 100k) to program the desired threshold voltage. Filter Output of Full-Wave Logarithmic Detectors (FWDs). The FWD outputs are summed together at FILTER to generate the received-signal-strength indicator (RSSI). Connect a capacitor from FILTER to VCC for proper operation. Received-Signal-Strength Indicator Output. The analog DC voltage at RSSI indicates the input signal power. The RSSI output is reduced approximately 120mV when LOS+ is asserted. Inverting Data Input Noninverting Data Input Substrate. Connect to ground. Ground Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offsetcorrection-loop bandwidth. Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offsetcorrection-loop bandwidth. Output Buffer Supply Voltage. Connect to the same potential as VCC, but filter VCCO and VCC separately. Noninverting PECL Data Output. Terminate with 50 to (VCC - 2V). Inverting PECL Data Output. Terminate with 50 to (VCC - 2V). Inverting Loss-of-Signal Output. LOS- is asserted low when input power drops below the LOS threshold. For the MAX3964/MAX3968, this pin is PECL-compatible and should be terminated with 50 to (VCC 2V). For the MAX3965, this output is TTL-compatible and does not require termination. Noninverting Loss-of-Signal Output. LOS+ is asserted high when input power drops below the LOS threshold. For the MAX3964/MAX3968, this pin is PECL-compatible and should be terminated with 50 to (VCC - 2V). For the MAX3965, this output is TTL-compatible and does not require termination. MAX3964/MAX3968: This pin may be left open or connected to the positive supply. MAX3965: This pin must be connected to ground. +3.0V to +5.5V Supply Voltage
2
VTH
3
INV
4
FILTER
5 6 7 8 9, 10 11 12 13 14 15 16
RSSI ININ+ SUB GND CZP CZN VCCO OUT+ OUTLOS-
17
LOS+ VCCO
18 GNDO 19, 20 VCC
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+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964/MAX3965/MAX3968
VCC CZP CAZ CZN VCCO
OFFSET CORRECTION LIMITER IN+/INLIMITER LIMITER LIMITER
I
I O
OUT+/OUTSQUELCH LOS+
FWD FILTER
FWD
FWD
FWD
RSSI LOS+/LOS-
CFILTER VCC
MAX3964 MAX3965 MAX3968
1.2V REFERENCE
LOS COMPARATOR VTR SUB GND R2 GNDO (MAX3965 ONLY)
INV R1 FWD = FULL-WAVE DETECTOR
Figure 1. Functional Diagram
Detailed Description
The MAX3964 contains a series of limiting amplifiers and power detectors, offset correction, data-squelch circuitry, and PECL output buffers for data and loss-ofsignal (LOS) outputs. The MAX3965 is functionally the same, but it provides TTL buffers on the LOS outputs. The MAX3968 provides PECL LOS outputs with data outputs suitable for 266Mbps. Figure 1 shows a functional diagram of the MAX3964/MAX3965/MAX3968.
This relation translates to a 25mV increase in VRSSI for every 1dB increase in VIN (25mV/dB). The RSSI output is reduced approximately 120mV when LOS+ is asserted.
PECL Outputs
The data outputs (OUT+, OUT-) and the MAX3964/ MAX3968 loss-of-signal outputs (LOS+, LOS-) are supply-referenced PECL outputs. Standard PECL termination at each output of 50 to (V CC - 2V) is recommended for best performance.
Limiting Amplifiers
A series of four limiting amplifiers provides gain of approximately 65dB.
TTL Outputs
The MAX3965 LOS outputs (LOS+, LOS-) are implemented with open-collector Schottky-clamped TTLcompatible outputs. The LOS outputs are pulled to VCC internally with 2k resistors and do not require external pull-up resistors.
Power Detector
Each amplifier stage contains a full-wave logarithmic detector (FWD), which indicates the RMS input signal power. The FWD outputs are summed together at the FILTER pin where the signal is filtered by an external capacitor (CFILTER) connected between FILTER and VCC. The FILTER signal generates the RSSI output voltage, which is proportional to the input power in decibels. When LOS+ is low, VRSSI is approximated by the following equation: VRSSI (V) = 1.2V + 0.5log (VIN) where VIN is measured in mVp-p.
Input Offset Correction
A low-frequency feedback loop around the limiting amplifier improves receiver sensitivity and powerdetector accuracy. The offset-correction loop's bandwidth is determined by an external capacitor (C AZ) connected between the CZP and CZN pins. The offset correction is optimized for data streams with a 50% duty cycle. A different average duty cycle results in increased pulse-width distortion and loss of
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+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964/MAX3965/MAX3968
sensitivity. The offset-correction circuitry is less sensitive to variations of input duty cycle (for example, the 40% to 60% duty cycle encountered in 4B/5B coding) when the input is less than 30mVp-p.
Applications Information
Program the LOS Threshold
Figure 2 provides information for selecting the LOS threshold voltage (V TH ). If R1 is 100k and if the responsivities of the photodiode and preamplifier are known, then the value of R2 can be selected from Figure 2 to provide LOS assert at the desired input power.
Loss-of-Signal Comparator
The LOS comparator indicates when the input signal power is below the programmed LOS threshold. To ensure supply and temperature independence, VTH is generated by a 1.2V bandgap reference. The op amp's external gain-setting resistors (R1 and R2) can be chosen to set VTH between 1.2V and 2.4V. To ensure chatter-free operation, the LOS comparator is designed with approximately 5dB of hysteresis.
Select Capacitors
A typical MAX3964/MAX3965/MAX3968 implementation requires four external capacitors (CAZ, CFILTER, and two input coupling capacitors). For all applications up to 266Mbps, Maxim recommends the following: CAZ = 27nF CFILTER = 10nF CIN = 10nF
Squelch
The squelch function disables the data outputs by forcing OUT- low and OUT+ high during a LOS condition. This function ensures that when there is a loss of signal, the limiting amplifier (and all downstream devices) does not respond to input noise or corrupt data. Connect SQUELCH to GND or leave it unconnected to disable squelch. Connect SQUELCH to VCC to enable data squelching.
Wire Bonding
For high-current density and reliable operation, the MAX3964 series uses gold metalization. Make connections to the dice with gold wire only, using ball-bonding techniques (wedge bonding is not recommended). Diepad size is 4mils square with a 6mil pitch. Die thickness is 15mils.
120 200kV/W
100
VALUE OF R2 (k)
80 100kV/W 60 30kV/W 20kV/W 15kV/W 20 10kV/W
40
0 -40 -38 -36 -34 -32 -30 -28 -26 OPTICAL INPUT POWER AT LOS ASSERT (dBm)
Figure 2. LOS Assert Programming Resistor vs. LOS Assert Power (for various PIN-TIA gains )
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+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector
Pin Configurations
SQUELCH VTH
SQUELCH 1 VTH 2 INV 3 FILTER 4 RSSI 5 IN- 6 IN+ 7 SUB 8 GND 9 GND 10 20 VCC 19 VCC 18 VCCO 17 LOS+
Chip Topographies
MAX3964/MAX3968
MAX3964/MAX3965/MAX3968
TOP VIEW
VCC
VCC
VCC0
INV FILTER RSSI ININ+
LOS+ LOSOUTOUT+ VCCO GND CZP 0.047" (1.19mm)
MAX3964 MAX3968
16 LOS15 OUT14 OUT+ 13 VCCO 12 CZN 11 CZP
SUB
GND
CZN
QSOP
0.057" (1.45mm)
MAX3965
SQUELCH 1 VTH 2 INV 3 FILTER 4 RSSI 5 IN- 6 IN+ 7 SUB 8 GND 9 GND 10 20 VCC 19 VCC 18 GNDO 17 LOS+
SQUELCH VTH VCC
VCC
GNDO
INV FILTER RSSI ININ+ MAX3964
LOS+ LOSOUTOUT+ VCCO GND CZP 0.047" (1.19mm)
MAX3965
16 LOS15 OUT14 OUT+ 13 VCCO 12 CZN 11 CZP
QSOP
SUB
GND
CZN
0.057" (1.45mm)
TRANSISTOR COUNT: 915 SUBSTRATE CONNECTED TO SUB
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+3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964/MAX3965/MAX3968
Package Information
QSOP.EPS
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