View DS2291_276148.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS2291
DS2291 T1 Long Loop Stik
FEATURES
PIN ASSIGNMENT
VDD 1 VDD 2 RCLK 3 RPOS 4 RNEG 5 LCLK 6 LPOS 7 LNEG 8 LB 9 NC 10 NC 11 NC 12 NC 13 RCL 14 BPV 15 LOCK 16 BL 17 NC 18 DJA 19 B8ZS 20 RST21 GND 22 GND 23 NC 24 NC 25 NC 26 NC 27 NC 28 RX+ 29 RX- 30
* Recovers clock and data off of T1 lines from 0 to 6,000
feet in length
* +0 to -30dBSX receiver sensitivity * Built-in Automatic Line Build Out (ALBO) circuitry; no
tuning or external components required
DEJITTER CIRCUITRY
* Dejitters the recovered clock and data * Meets TR 62411 (Dec. 1990) for jitter tolerance and
attenuation
* Companion to the DS2290 T1 Isolation Stik * Connects
connector to a standard 30-pin single in-line
ALBO & CLOCK RECOVERY CIRCUITRY
* Single +5V supply * Compatible with the DS2180A or DS2141A T1 Transceivers
(ACTUAL SIZE)
DESCRIPTION
The DS2291 T1 Long Loop Stik contains all the circuitry necessary to recover clock and data from a T1 line. The DS2291 contains an Automatic Line Build Out (ALBO) circuit that allows it to adapt to T1 lines varying in length from 0 to 6,000 feet. It also will dejitter the recovered clock and data according to the jitter attenuation curves outlined in AT&T Communications Document TR 62411 (Accunet* T1.5 Service Description and Interface specification - December 1990). Applications area include Channel Service Units (CSU), T1 monitoring equipment, and T1 test equipment.
OVERVIEW
The DS2291 contains onboard ALBO circuitry that allows it to recover clock and data from T1 lines up to 6,000 feet in length. (See Figure 1.) Unlike alternative methods of clock and data recovery from T1 lines, the DS2291 does not require any tuning, nor does it need any additional external circuitry. The state of the LOCK pin indicates whether the DS2291 has been able to phase and frequency lock to the incoming T1 signal. If the LOCK pin is high, the DS2291 is properly locked onto the incoming signal. The DS2291 meets the latest T1 specification for jitter tolerance. The jitter tolerance curve in Figure 2 is applicable over the full dynamic input range of the DS2291.
* Service mark of AT&T Communications 022798 1/10
DS2291
Once the Long Loop Stik has recovered data from the T1 line, it can decode B8ZS code words and check for bipolar violations and carrier loss. If the B8ZS pin is tied high, the DS2291 will automatically replace incoming B8ZS code words with eight zeros. If the B8ZS pin is tied low or left open, no replacement occurs. Bipolar violations are reported via the BPV pin. The BPV pin will transition high for a full T1 bit period (648 ns) each time a violation is detected. Bipolar violations inherent in B8ZS code words are not reported if the B8ZS pin is tied high. The DS2291 also checks for carrier loss. The RCL pin will transition high when the DS2291 detects 192 consecutive zeros at RX+ and RX-. The recovered clock and data are passed to the dejitter circuitry. If the DJA is tied low or left open, the DS2291 will attenuate the jitter present at RX+ and RX- according to the curves outlined in Figure 3. These curves meet the latest T1 specifications. If the DJA pin is tied high, the DS2291 will not attenuate jitter. Hence, all the jitter inherent in the signal at RX+ and RX- will be passed to RCLK, RPOS, and RNEG. If the recovered clock at RCLK is used to transmit data onto T1 lines, it is recommended that the dejitter circuitry be enabled (DJA = 0). The dejitter circuitry contains a 128-bit buffer. This buffer can be recentered on command via the RST pin. In normal applications, the RST is left open or tied high. The Buffer Limit (BL) output will transition high when the
DS2291 is receiving more than 120 unit intervals peak-to-peak (Ulpp) of jitter at RX+ and RX-. As long as the incoming jitter is less than 120Ulpp, the BL pin will remain low. The DS2291 contains a data mux that allows data to be routed from either the T1 recovery circuitry or from a local source. The mux is helpful locating faults in a system. For example, it could be used to implement a "local" loopback. Two typical applications with the DS2291 are shown in Figure 4 and Figure 5. In both applications, the DS2291 is used to recover data from T1 lines up to 6,000 feet in length. The application in Figure 4 is with an unprotected interface; it might be used in T1 test equipment. The application in Figure 5 is with the DS2290 T1 Isolation Stik, which provides all the necessary protection as required by FCC Part 68. This could be used in a Channel Service Unit (CSU) or in similar types of equipment in which full surge and isolation protection is required.
SINGLE IN-LINE CONNECTOR
The DS2291 is designed to connect directly into a 30-pin single in-line connector. These connectors are available from a number of vendors.
022798 2/10
DS2291
PIN DESCRIPTION Table 1
PIN 1,2 3 4 5 6 7 8 9 SYMBOL VDD RCLK RPOS RNEG LCLK LPOS LNEG LB I I I I/O O O DESCRIPTION Positive Supply. 5.0 volts. Receive Clock. Recovered 1.544 MHz clock. Receive Bipolar Data. Recovered bipolar data; updated on the rising edge of RCLK. Bipolar violations are not corrected. Loopback Clock. Clock for loopback data. Internally pulled low by 100K ohm. Loopback Bipolar Data. Samples on the falling edge of LCLK if LB is tied high. Internally pulled low by 100K ohm. Loopback Enable. Tie high to loopback data from the LPOS and LNEG inputs to RPOS and RNEG; tie low or leave open to obtain recovered data out of the ALBO circuitry at RPOS and RNEG. Internally pulled low by 100K ohm. Receive Carrier Loss. Transitions high when 192 consecutive zeros have been received at RX+ and RX-; reset on the next ones occurrence. Receive Bipolar Violation. Transitions high for a full bit period when a bipolar violation appears at RX+ and RX-. B8ZS code words are not reported if B8ZS is tied high. Lock Indication. High state indicates that the recovery circuit is phase-and frequency-locked to the signal at RX+ and RX-. Buffer Limit. Transitions high when the incoming jitter at RX+ and RX- is greater than 120Ulpp. Disable Jitter Attenuation. Tie high to disable the jitter attenuation circuitry; tie low to enable the jitter attenuation circuitry. Internally pulled low by 100K ohm. B8ZS Enable. If tied high, incoming B8ZS code words are decoded and replaced with eight zeros. If tied low, B8ZS code words are not decoded. Internally pulled low by 100K ohm. Reset. Active low; a high-low-high transition will recenter the dejitter buffer. Internally pulled high by 100K ohm. Ground. 0.0 volts. Receive Analog Input. Connects to T1 line through a 2:1 transformer. See Figure 4.
14
RCL
O
15
BPV
O
16 17 19
LOCK BL DJA
O O I
20
B8ZS
I
21 22, 23 29 30
RST GND RX+ RX-
I I O
NOTE:
Do not connect any signal to pins 10, 11, 12, 13, 18, 24, 25, 26, 27, or 28.
022798 3/10
DS2291
DS2291 BLOCK DIAGRAM Figure 1
022798 4/10
LOCK(16)
RCL(14) BPV(15) RX+(29) B8ZS(20) PD CARRIER LOSS/ BPV DETECT/ B8ZS DECODE AUTOMATIC LINE BUILD OUT RX-(30) CLOCK & DATA RECOVERY
VDD(1,2) GND(22,23)
RCLK(3) DATA MUX LCLK(6) LPOS(7) LNEG(8) PU RST(21) DJA(19) LB(9) PD PD PD PD PD BL(17) DEJITTER CIRCUITRY RPOS(4) RNEG(5)
DS2291
DS2291 JITTER TOLERANCE Figure 2
1K NOMINAL DS2291 PERFORMANCE 100 UNIT INTERVALS (Ulpp)
TR 62411
10
1
0.1 10
100
1K FREQUENCY (Hz)
10K
100K
DS2291 JITTER ATTENUATION PERFORMANCE Figure 3
20 Hz 0 NOMINAL DS2291 PERFORMANCE
JITTER ATTENUATION (dB)
-20
TR 62411 CURVE B -40
TR 62411 CURVE A
-60 1 10 100 FREQUENCY (Hz) 1K 10K
022798 5/10
DS2291
DS2291 APPLICATION (UNISOLATED INTERFACE) Figure 4
RECEIVE T1 PAIR 2:1
RX+ 25 OHMS DS2291 T1 LONG LOOP Stik RX- B8ZS BPV PCS DJA RST RCLK RPOS RNEG RCLK RPOS RNEG RSER
DS2180A T1 TRANSCEIVER
TRANSMIT T1 PAIR 1:1.4
0.47 F nonpolarized
TTIP TRING TPOS TNEG TCLK LCLK LPOS LNEG LEN0/1/2 TAIS LB 3
LCLK LNEG LPOS LOCK RCL LB
TSER DS2186 TRANSMIT LINE INTERFACE TPOS TNEG SERIAL TCLK PORT
SYSTEM CONTROLLER (DS5000)
DS2291 APPLICATION (ISOLATED INTERFACE) Figure 5
LCLK LPOS LNEG
RX+ RX-
RX+ RX- B8ZS BPV PCS DJA RST DS2291 T1 LONG LOOP Stik
RCLK RPOS RNEG
RCLK RPOS RNEG DS2180A T1 TRANSCEIVER
RSER
B8ZS LB2
LCLK LNEG LPOS LOCK RCL LB TPOS TNEG TCLK LB0 LB1 TAIS LB TPOS TNEG TCLK
RECEIVE T1 PAIR RXTIP RXRING LPWR- LPWR+ TXTIP TXRING TRANSMIT T1 PAIR
TSER SERIAL PORT
DS2250 MICROCONTROLLER Stik
022798 6/10
SYSTEM BACKPLANE
DS2290 T1 ISOLATION Stik
SYSTEM BACKPLANE
DS2291
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature -0.3V to VCC + 0.3V 0C to 70C -55C to +125C
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 4.75 TYP MAX VCC +0.3 +0.8 5.25 UNITS V V V
(0C to 70C)
NOTES 3, 4 3, 4
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 30 50 UNITS pF pF
(tA=25C)
NOTES 3 3
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Current Input Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDD II IOH IOL -100 -1.0 +4.0 MIN TYP 40
(0C to 70C; VDD = 5V + 5%)
MAX 50 +100 UNITS mA A mA mA NOTES 1 2, 3 3 3
NOTES:
1. VDD = 5.25V; output open. 2. VSS < Vin < VDD. 3. Does not apply to RX+ and RX-. 4. Inputs LCLK, LPOS, and LNEG are HC inputs; VIH=3.5V and VIL=1.0V.
022798 7/10
DS2291
DIGITAL ELECTRICAL CHARACTERISTICS
PARAMETER LPOS, LNEG Setup to LCLK Falling LPOS, LNEG Hold from LCLK Falling Propagation Delay from RCLK to RPOS, RNEG Valid RCLK Period RCLK Pulse Width RST Pulse Width SYMBOL tSD tHD tPD tP tWL, tWH tRST 1 648 324 MIN 50 50 TYP
(0C to 70C; VDD = 5V + 5%)
MAX UNITS ns ns 50 ns ns ns s NOTES
ANALOG ELECTRICAL CHARACTERISTICS
PARAMETER Input Signal Range Input Impedance at 772 KHz SYMBOL VIR ZIN MIN -30 1100 TYP
(0C to 70C; VDD = 5V + 5%)
MAX +0 UNITS dBSX ohms NOTES 1 1
NOTE:
1. dBSX = 3Vpk; signal defined at the primary side of a 2:1 transformer with the secondary shunted by 25 and connected to RX+ and RX- (see Figure 4 for an example).
AC TIMING DIAGRAM Figure 6
LCLK t LPOS, LNEG SD t HD
t t
P t WL
WH
RCLK t RPOS, RNEG t RST RST PD
022798 8/10
DS2291
DS2291 T1 LONG LOOP Stik
P SIDE B SIDE A O N
A J B
C D E
G H I
F
PKG DIM A IN. B IN. C IN. D IN. E IN. F IN. G IN. H IN. I IN. J IN. N IN. O IN. P IN. 30-PIN MIN 3.455 3.229 0.845 0.395 0.245 MAX 3.505 3.239 0.855 0.405 0.255
0.100 BSC 0.075 0.295 0.085 0.305
2.900 BSC 0.120 0.130 0.180 0.115 0.054
022798 9/10

▲Up To Search▲

Price & Availability of DS2291

	To Download DS2291 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .