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1CY 7C22 5A
CY7C225A
512 x 8 Registered PROM
Features
* CMOS for optimum speed/power * High speed * TTL-compatible I/O * Direct replacement for bipolar PROMs * Capable of withstanding greater than 2001V static
-- 18 ns address set-up -- 12 ns clock to output
* Low power
discharge
Functional Description
The CY7C225A is a high-performance 512 word by 8 bit electrically programmable read only memory packaged in a slim 300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, and 28-pin PLCC. The memory cells utilize proven EPROM floating gate technology and byte-wide intelligent programming algorithms. The CY7C225A replaces bipolar devices and offers the advantages of lower power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming the product will meet AC specification limits.
-- 495 mW (commercial) -- 660 mW (military)
* Synchronous and asynchronous output enables * On-chip edge-triggered registers * Buffered common PRESET and CLEAR inputs * EPROM technology, 100% programmable * Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC,
or 28-pin PLCC
* 5V 10% VCC, commercial and military
Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 COLUMN ADDRESS O2 O1 ADDRESS DECODER 8-BIT EDGETRIGGERED REGISTER ROW ADDRESS PROGRAMMABLE ARRAY MULTIPLEXER O5 O4 O7
Pin Configurations
DIP Top View
A7 O6 A6 A5 A4 A3 A2 A1 A0 O3 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 PS E CLR ES CP O7 O6 O5 O4 O3 C225A-2
PS CLR CP
S
R
CP
O0
LCC/PLCC Top View
ES E C225A-1
A4 A3 A2 A1 A0 NC O0
4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 13 141516 17 18
E CLR ES CP NC O7 O6
C225A-3
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 December 1992 - Revised March 1995
CY7C225A
Selection Guide
7C225A-18 Minimum Address Set-Up Time (ns) Maximum Clock to Output (ns) Maximum Operating Current (mA) Commercial Military 18 12 90 7C225A-25 25 12 90 120 7C225A-30 30 15 90 120 120 7C225A-35 35 20 7C225A-40 40 25 90 120
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage .................................................-3.0V to +7.0V DC Program Voltage (Pins 7, 18, 20)............................13.0V
Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial[1] Military[2] Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[3,4]
Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Input Clamp Diode Voltage Output Leakage Current Output Short Circuit Current Power Supply Current Test Conditions VCC = Min., IOH = -4.0 mA VIN = VIH or VIL VCC = Min., IOL = 16 mA VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for All Inputs Guaranteed Input Logical LOW Voltage for All Inputs GND < VIN < VCC Note 4 GND < VOUT < VCC, Output Disabled[5] VCC = Max., VOUT = IOUT = 0 mA VCC = Max. 0.0V[6] Commercial Military 12 -10 -20 +10 -90 90 120 13 50 3.0 0.4 V mA V V A mA mA -10 2.0 0.8 +10 Min. 2.4 0.4 Max. Unit V V V V A
VPP IPP VIHP VILP
Notes:
1. 2. 3. 4. 5. 6.
Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage
Contact a Cypress representative for industrial temperature range specifications. TA is the "instant on" case temperature. See the last page of this specification for Group A subgroup testing information. See the "Introduction to CMOS PROMs" section of the Cypress Data Book for general information on testing. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
2
CY7C225A
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC =5.0V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms[4]
5V OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 167 R1 250 5V OUTPUT 5pF INCLUDING JIG AND SCOPE R2 167
C225A-4
R1 250 ALL INPUT PULSES 3.0V GND < 5 ns 90% 10% 90% 10% < 5 ns
C225A-5
(a) Normal Load
Equivalent to: THEVENIN EQUIVALENT 100
(b) High Z Load
OUTPUT
2.0V
C225A-6
Operating Modes
The CY7C225A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with synchronous (ES) and asynchronous (E) output enables and CLEAR and PRESET inputs. Upon power-up, the synchronous enable (ES) flip-flop will be in the set condition causing the outputs (O0 - O7) to be in the OFF or high-impedance state. Data is read by applying the memory location to the address inputs (A0 - A8) and a logic LOW to the enable (ES) input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (O 0 - O7) provided the asynchronous enable (E) is also LOW. The outputs may be disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. Regardless of the condition of E, the outputs will go to the OFF or high-impedance state upon the next positive clock edge after the synchronous enable (ES) input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW,
the subsequent positive clock edge will return the output to the active state if E is LOW. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C225A decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs. System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers available in the market. The CY7C225A has buffered asynchronous CLEAR and PRESET inputs. Applying a LOW to the PRESET input causes an immediate load of all ones into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). Applying a LOW to the CLEAR input, resets the flip-flops to all zeros. The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW. When power is applied, the (internal) synchronous enable flip-flop will be in a state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur and the ES input pin must be LOW at least a set-up time prior to the clock LOW-to-HIGH transition. The E input may then be used to enable the outputs.
3
CY7C225A
Switching Characteristics Over the Operating Range[3,4]
7C225A-18 Parameter tSA tHA tCO tPWC tSES tHES tDP, tDC tRP, tRC tPWP, tPWC tCOS tHZC tDOE tHZE
Note:
7. Applies only when the synchronous (ES) function is used.
7C225A-25 Min. 25 0 Max.
7C225A-30 Min. 30 0 Max.
7C225A-35 Min. 35 0 Max.
7C225A-40 Min. 40 0 Max. Unit ns ns 25 20 10 5 ns ns ns ns 20 20 20 ns ns ns 30 30 30 30 ns ns ns ns
Description Address Set-Up to Clock HIGH Address Hold from Clock HIGH Clock HIGH to Valid Output Clock Pulse Width ES Set-Up to Clock HIGH ES Hold from Clock HIGH Delay from PRESET or CLEAR to Valid Output PRESET or CLEAR Recovery to Clock HIGH PRESET or CLEAR Pulse Width Valid Output from Clock HIGH[7]
Min. 18 0
Max.
12 10 10 0 20 15 15 15 15 15 15 15 15 10 10 0
12 15 10 5 20 20 20 20 20 20 20
15 20 10 5 20 20 20 20 20 20 20
20
20
25 25 25 25
Inactive Output from Clock HIGH[7] Valid Output from E LOW Inactive Output from E HIGH
Switching Waveforms[4]
tHA A0 - A10 tSES ES tSES tHES tHES tSES tHES tSA tHA
CP
tPWC tPWC
tPWC tPWC
tPWC tPWC
O0 - O7 tCO tHZC
tCOS
tCO tHZE tDOE
E tDP tDC PS or CLR tPWP tPWC
C225A-7
tRP tRC ,
4
CY7C225A
Programming Information
Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed Table 1. Mode Selection Pin Function[8] Read or Output Disable Mode Read Output Disable Output Disable Clear Preset Program Program Verify Program Inhibit Intelligent Program Blank Check
Note:
8. X = "don't care" but not to exceed VCC 5%.
programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative.
A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0 A8 - A0
CP PGM X X X X X VILP VIHP VIHP VILP VIHP
ES VFY VIL VIH X VIL VIL VIHP VILP VIHP VIHP VILP
CLR VPP VIH VIH VIH VIL VIH VPP VPP VPP VPP VPP
E E VIL X VIH VIL VIL VIHP VIHP VIHP VIHP VIHP
PS PS VIH VIH VIH VIH VIL VIHP VIHP VIHP VIHP VIHP
O7 - O0 D7 - D0 O7 - O0 High Z High Z Zeros Ones D7 - D0 O7 - O0 High Z D7 - D0 Zeros
Other
DIP Top View
A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 PS E VPP VFY PGM D7 D6 D5 D4 D3 A4 A3 A2 A1 A0 NC D0
LCC/PLCC Top View
4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 1314151617 18
E VPP VFY PGM NC D7 D6
C225A-9
C225A-8
Figure 1. Programming Pinouts
5
CY7C225A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.6 1.4 1.1 1.2 1.0 1.0 0.8 0.6 4.0 TA =25C f = fMAX 4.5 5.0 5.5 6.0 0.9 1.0 0.8 TA =25C 0.8 -55 25 125 0.6 4.0 4.5 5.0 5.5 6.0 1.2
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
1.6 1.4 1.2
CLOCK TO OUTPUT TIME vs. VCC
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME vs. TEMPERATURE
1.6 1.4 1.2 0.8 1.0 0.8 0.6 - 55 0.6 1.2 1.0
NORMALIZED SET-UP TIME vs. SUPPLY VOLTAGE
1.6 1.4 1.2 1.0 0.8 0.6 - 55
NORMALIZED SET-UP TIME vs. TEMPERATURE
TA =25C 25 125 0.4 4.0 4.5 5.0 5.5 6.0
25
125
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD
1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0 25 50 75 100 15.0 10.0 5.0 0.0 VCC =5.5V TA =25C 30.0 25.0 20.0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
175 150 125 100 75 50 TA =25C VCC =4.5V 0 200 400 600 800 1000 25
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V TA =25C
0 0.0
1.0
2.0
3.0
4.0
CLOCK PERIOD (ns)
CAPACITANCE (pF)
OUTPUT VOLTAGE (V)
C225A-10
6
CY7C225A
Ordering Information[9]
Speed (ns) tSA 18 tCO 12 Ordering Code CY7C225A-18DC CY7C225A-18JC CY7C225A-18PC 25 12 CY7C225A-25DC CY7C225A-25JC CY7C225A-25PC CY7C225A-25DMB CY7C225A-25LMB 30 15 CY7C225A-30DC CY7C225A-30JC CY7C225A-30PC CY7C225A-30DMB CY7C225A-30LMB 35 20 CY7C225A-35DMB CY7C225A-35LMB 40 25 CY7C225A-40DC CY7C225A-40JC CY7C225A-40PC CY7C225A-40DMB CY7C225A-40LMB Package Type D14 J64 P13 D14 J64 P13 D14 L64 D14 J64 P13 D14 L64 D14 L64 D14 J64 P13 D14 L64 Package Type 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier Military Commercial Military Military Commercial Military Commercial Operating Range Commercial
Notes: 9. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability.
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC Document #: 38-00228-C Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter tSA tHA tCO tDP tRP Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
7
CY7C225A
Package Diagrams
18-Lead (300-Mil) CerDIP D4
MIL-STD-1835 D-8Config.A
28-Lead Plastic Leaded Chip Carrier J64
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
8
CY7C225A
Package Diagrams (Continued)
24-Lead (300-Mil) Molded DIP P13/P13A
(c) Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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