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| CXG1122EN SP5T GSM Triple-Band/GPRS Antenna Switch Description The CXG1122EN is one of a range of low insertion loss, high power MMIC antenna switches for GSM/ GPRS triple-band, dual-band (CXG1121TN) and applications. The low insertion loss on transmit means increased talk time as the Tx power amplifier can be operated at a lower output level. On-chip logic reduces the component count and simplifies the PCB layout by allowing the direct connection of the switch to digital baseband control lines with the CMOS logic levels. This switch is an SP5T, one antenna can be routed to either of the 2 Tx or 3 Rx ports. It requires 3 CMOS control lines (CTL1, CTL2 and Tx ON). The Sony's GaAs JFET process is used for low insertion loss. An evaluation PCB is available. Features * Insertion loss: (Tx) 0.5dB typ. at 34dBm (GSM900) * 3 CMOS compatible control lines * Low second harmonic: -40dBm typ. at 34dBm (GSM900) * Small package size: 16-pin VSON (2.7mm x 3.5mm x 0.9mm) Applications Triple-band handsets using the combinations of followings: * GSM900/DCS1800/PCS1900 * GPRS * DECT Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25C) * Bias voltage VDD 7 * Control voltage VCTL 5 * Operating temperature Topr -20 to +80 16 pin VSON (Plastic) V V C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E01Z20-PS CXG1122EN Pin Configuration Rx1 9 8 ANT GND 10 7 GND Rx2 11 6 Tx1 GND 12 5 GND Rx3 13 4 Tx2 GND 14 3 GND CTL1 15 2 VDD CTL2 16 1 Tx ON Truth Table On Pass ANT - Tx1 GSM900 ANT - Tx2 DCS1800 & PCS1900 ANT - Rx1 GSM900/DCS1800/PCS1900 ANT - Rx2 GSM900/DCS1800/PCS1900 ANT - Rx3 GSM900/DCS1800/PCS1900 CTL1 H L H L L CTL2 Don't care Don't care L L H Tx ON H H L L L -2- CXG1122EN Electrical characteristics Item Symbol Path Tx1, Tx2 - ANT Tx1, Tx2 - ANT Insertion loss IL Rx1 - ANT Rx2 - ANT Rx3 - ANT ANT - Tx1, Tx2 Isolation ISO Tx - Rx1, Rx2, Rx3 Tx - Rx1, Rx2, Rx3 VSWR Harmonics P1dB compression input power Control current Supply current for Tx and Rx modes VSWR 2fo 3fo P1dB ICTL ITX/IRX Tx1, Tx2 - ANT Tx1, Tx2 - ANT 1, 2 1, 2 VCTL = 3.0V VDD = 3.3V Condition 1 2 3 4 5 3 4, 5 1 2 18 14 23 18 Min. Typ. 0.5 1.0 0.65 1.2 1.2 20 16 25 20 1.2 -40 -34 36 80 0.3 (Ta = 25C) Max. 0.7 1.2 0.85 1.4 1.4 Unit dB dB dB dB dB dB dB dB dB -36 -30 dBm dBm dBm 120 1 A mA Electrical characteristics are measured with all the RF ports terminated in 50. Harmonics measured with Tx inputs harmonically matched. It is recommended that the harmonic matching is used to ensure the optimum performance. 1 2 3 4 5 Power Power Power Power Power incident incident incident incident incident on GSM Tx, Pin = 34dBm, 880 to 915MHz, VDD = 3.3V, GSM Tx enabled on DCS/PCS Tx, Pin = 32dBm, 1710 to 1910MHz, VDD = 3.3V, DCS/PCS Tx enabled on ANT, Pin = 10dBm, 925 to 960MHz, VDD = 3.3V, GSM Rx enabled on ANT, Pin = 10dBm, 1805 to 1880MHz, VDD = 3.3V, DCS Rx enabled on ANT, Pin = 10dBm, 1930 to 1990MHz, VDD = 3.3V, PCS Rx enabled Supply Voltage Value (VDD) Mode GSM/DCS Tx GSM/DCS/PCS Rx Min. 3.0 2.7 Typ. 3.3 3.0 Max. 3.5 3.5 Unit V V CMOS Logic Value Logic High Low Min. 2.4 0 Typ. 2.8 Max. 3.2 0.4 Unit V V -3- CXG1122EN DC Block Capacitors and Decoupling Capacitors 9 47pF Rx1 ANT 8 47pF 10 GND GND 7 11 Rx2 22pF 12 GND Tx1 6 47pF GND 5 13 Rx3 22pF 14 GND 15 CTL1 100pF 16 CTL2 100pF Tx2 4 22pF GND 3 VDD 2 100pF Tx ON 1 100pF Note) Capacitors are required on all the RF ports for DC blocking (22pF - 47pF). Decoupling capacitors are required on VDD and on control lines. -4- CXG1122EN Application Note Impedance Matching for Harmonic Minimization This note outlines the method used to find the source impedance to present to a transmit port at the second harmonic frequency (2fo) to reduce the second harmonic level at the antenna. This should be carried out for a set of devices that represent the process variants. This way a compromise can be found that suits all the variants. The necessary equipment is shown immediately below. Power Meter Fundamental, fo Second Harmonic, 2fo Signal Generator B.P.F. 10dB Coupler Diplexer Load Pull Tuner DC Block D.U.T. DC Block Spectrum Analyzer The device should be mounted on a PCB with 50 tracks running from all the RF pins to SMA connectors on the PCB edge (DUT). All the ports should be externally DC blocked and the unused ports should be terminated in 50. All the measurements should be performed at the incident powers for which the harmonic levels are specified in this document. The 2nd harmonic level at the antenna port is measured using the spectrum analyzer and the vertical and horizontal position of the load pull stub adjusted such that this level is minimized. The device should then be removed from the board and an SMA connector mounted such that the source impedance seen by the transmit port at 2fo can be measured using a VNA. Measurements should be de-embedded to the end of the SMA center pin. A network should then be designed to match the impedance of the low pass filter (LPF), which usually comes in front of the device, to the 2fo source impedance that gives sufficiently reduced 2fo levels for all the devices measured. The network should be designed to maintain a good match and insertion loss at the fundamental frequency. -5- CXG1122EN Package Outline Unit: mm 16PIN VSON (PLASTIC) + 0.1 0.8 - 0.05 0.6 3.5 A S 0.35 0.1 2.5 0.05 S B 0.4 1.4 x4 x2 0.15 S B 0.35 0.1 0.15 S A B 0.2 0.01 0.05 M S A-B 0.03 0.03 (Stand Off) Solder Plating 0.13 0.025 + 0.09 0.14 - 0.03 TERMINAL SECTION NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VSON-16P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02 g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m 0.23 0.02 -6- Sony Corporation 0.5 0.2 2.7 |
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