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a
FEATURES 170 MSPS Update Rate TTL/High-Speed CMOS-Compatible Inputs Wideband SFDR: 66 dB @ 2 MHz/50 dB @ 65 MHz Pin-Compatible, Lower Cost Replacement for Industry Standard AD9721 DAC Low Power: 439 mW @ 170 MSPS Fast Settling: 3.8 ns to 1/2 LSB Internal Reference Two Package Styles: 28-Lead SOIC and SSOP APPLICATIONS Digital Communications Direct Digital Synthesis Waveform Reconstruction High Speed Imaging 5 MHz-65 MHz HFC Upstream Path
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLOCK TTL DRIVE LOGIC DECODERS AND DRIVERS
10-Bit, 170 MSPS D/A Converter AD9731
FUNCTIONAL BLOCK DIAGRAM
ANALOG RETURN
REGISTER
SWITCH NETWORK
IOUT IOUT
REF IN CONTROL AMP INTERNAL VOLTAGE REFERENCE RSET DIGITAL DIGITAL ANALOG -VS +VS -VS AMP OUT
REF OUT
CONTROL AMP IN
GENERAL DESCRIPTION
The AD9731 is a 10-bit, 170 MSPS, bipolar D/A converter that is optimized to provide high dynamic performance, yet offer lower power dissipation and more economical pricing than afforded by previous bipolar high performance DAC solutions. The AD9731 was designed primarily for demanding communications systems applications where wideband spurious-free dynamic range (SFDR) requirements are strenuous and could previously only be met by using a high performance DAC such as the industry-standard AD9721. The proliferation of digital communications into basestation and high volume subscriberend markets has created a demand for excellent DAC performance delivered at reduced levels of power dissipation and cost. The AD9731 is the answer to that demand.
Optimized for direct digital synthesis (DDS) waveform reconstruction, the AD9731 provides 50 dB of wideband harmonic suppression over a dc-to-65 MHz analog output bandwidth. This signal bandwidth addresses the transmit spectrum in many of the emerging digital communications applications where signal purity is critical. Narrowband, the AD9731 provides an SFDR of greater than 79 dB. This excellent wideband and narrowband ac performance, coupled with a lower pricing structure, make the AD9731 the optimum high performance DAC value. The AD9731 is packaged in 28-lead SOIC (same footprint as the industry standard AD9721) and super space-saving 28-lead SSOP; both are specified to operate over the extended industrial temperature range of -40C to +85C.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
5/27/99 8 PM
AD9731-SPECIFICATIONS V
Parameter RESOLUTION THROUGHPUT RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity INITIAL OFFSET ERROR Zero-Scale Offset Error Full-Scale Gain Error1 Offset Drift Coefficient REFERENCE/CONTROL AMP Internal Reference Voltage2 Internal Reference Voltage Drift Internal Reference Output Current3 Amplifier Input Impedance Amplifier Bandwidth REFERENCE INPUT4 Reference Input Impedance Reference Multiplying Bandwidth5 OUTPUT PERFORMANCE Output Current4, 6 Output Compliance Output Resistance Output Capacitance Voltage Settling Time to 1/2 LSB (tST)7 Propagation Delay (tPD)8 Glitch Impulse9 Output Slew Rate10 Output Rise Time10 Output Fall Time10 DIGITAL INPUTS Input Capacitance Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Minimum Data Setup Time (tS)11 Minimum Data Hold Time (tH)12 Clock Pulsewidth Low (pwMIN) Clock Pulsewidth High (pwMAX) SFDR PERFORMANCE (Wideband) 13 2 MHz AOUT 10 MHz AOUT 20 MHz AOUT 40 MHz AOUT 65 MHz AOUT (Clock = 170 MHz) 70 MHz AOUT (Clock = 170 MHz)
(+VS = +5 V, -VS = -5.2 V, CLOCK = 125 MHz, RSET = 1.96 k REF = -1.25 V, unless otherwise noted.)
Test Level Min Typ 10
for 20.4 mA IOUT,
Max Units Bits MHz 1 1.5 1 1.5 70 100 5 5 LSB LSB LSB LSB A A % FS % FS A/C V V/C A k MHz k MHz mA V pF ns ns pVs V/s ns ns pF V V A A ns ns ns ns ns ns dB dB dB dB dB dB
Temp
+25C +25C Full +25C Full +25C Full +25C Full
IV I VI I VI I VI I VI V I IV VI V V V V V IV V V V V V V V V IV VI VI VI VI IV IV IV IV IV IV V V V V V V
165
170 0.25 0.35 0.6 0.7 35 40 2.5 2.5 0.04
+25C Full Full +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C Full Full Full +25C +25C +25C Full +25C Full +25C +25C +25C +25C +25C +25C +25C +25C
-1.35 -50
-1.25 100 50 2.5 4.6 75 20
-1.15 +500
-1.5 240 5 3.8 2.9 4.1 400 1 1 2 2.0 8 30 1.2 1.5 0.1 0.1 2 2 66 62 61 55 50 47
+3
0.8 50 100 2 2.5 1.0 1.0
-2-
REV. A
5/27/99 8 PM
AD9731
Parameter SFDR PERFORMANCE (Narrowband) 2 MHz; 2 MHz Span 25 MHz, 2 MHz Span 10 MHz, 5 MHz Span (Clock = 170 MHz) INTERMODULATION DISTORTION14 F1 = 800 kHz, F2 = 900 kHz POWER SUPPLY Digital -V Supply Current Analog -V Supply Current Digital +V Supply Current Power Dissipation PSRR
15 13
Temp +25C +25C +25C +25C +25C Full +25C Full +25C Full +25C Full +25C
Test Level V V V V I VI I VI I VI V V V
Min
Typ 79 61 73 58 27 27 45 45 13 15 439 449 100
Max
Units dB dB dB dB
37 42 53 66 20 22
mA mA mA mA mA mA mW mW A/V
NOTES 1 Measured as an error in ratio of full-scale current to current through R SET (640 A nominal); ratio is nominally 32. DAC load is virtual ground. 2 Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification. 3 Internal reference output current defines load conditions applied during Internal Reference Voltage test. 4 Full-scale current variations among devices are higher when driving REFERENCE IN directly. 5 Frequency at which a 3 dB change in output of DAC is observed; R L = 50 ; 100 mV modulation at midscale. 6 Based on IFS = 32 (CONTROL AMP IN/R SET) when using internal control amplifier. DAC load is virtual ground. 7 Measured as voltage settling at midscale transition to 0.1%; RL = 50 . 8 Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal. 9 Peak glitch impulse is measured as the largest area under a single positive or negative transient. 10 Measured with RL = 50 and DAC operating in latched mode. 11 Data must remain stable for specified time prior to rising edge of CLOCK. 12 Data must remain stable for specified time after rising edge of CLOCK. 13 SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window. The frequency span is dc-to-Nyquist unless otherwise noted. 14 Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products created will manifest themselves at sum and difference frequencies of the two tones. 15 Supply voltages should remain stable within 5% for nominal operation. Specifications subject to change without notice.
pw MIN CLOCK
pw MAX
tS
DATA CODE 1 DATA
tH
CODE 2 DATA CODE 2 CODE 4 CODE 3 DATA CODE 4 DATA
ANALOG OUTPUT CODE 1 CODE 3
DETAIL OF SETTLING TIME
CLOCK
GLITCH AREA = 1/2 HEIGHT WIDTH
t PD
ANALOG OUTPUT
SPECIFIED ERROR BAND
H
W
t ST
Figure 1. Timing Diagrams
REV. A
-3-
AD9731
ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS to +VS +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7 V to +VS -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Control Amplifier Input Voltage Range . . . . . . . . . 0 V to -4 V Reference Input Voltage Range . . . . . . . . . . . . . . . . 0 V to -VS Maximum Junction Temperature . . . . . . . . . . . . . . . . +150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Internal Reference Output Current . . . . . . . . . . . . . . . 500 A Lead Temperature (10 sec Soldering) . . . . . . . . . . . . . +300C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +165C Control Amplifier Output Current . . . . . . . . . . . . . 2.5 mA
*Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
Test Level I II III IV V VI
Definition 100% Production Tested. The parameter is 100% production tested at +25C; sampled at temperature production. Sample Tested Only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range devices.
ORDERING GUIDE Temperature Range Package Description Package Options
Model
AD9731BR AD9731BRS AD9731-PCB
-40C to +85C -40C to +85C 0C to +70C
28-Lead Wide Body (SOIC) 28-Lead Shrink Small (SSOP) PCB
R-28 RS-28
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9731 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD9731
PIN FUNCTION DESCRIPTION
Pin # 1 2-9 10 11 12, 13 14 15, 18, 28 16 17 19 20
Pin Name D9(MSB) D8-D1 D0(LSB) CLOCK NC DIGITAL +VS GND DIGITAL -VS RSET ANALOG RETURN IOUT
Pin Description Most significant data bit of digital input word. Eight bits of 10-bit digital input word. Least significant data bit of digital input word. TTL-compatible edge-triggered latch enable signal for on-board registers. No internal connection to this pin. +5 V supply voltage for digital circuitry. Converter Ground. -5.2 V supply voltage for digital circuitry. Connection for external reference set resistor; nominal 1.96 k. Full-scale output current = 32 (Control Amp in V/RSET). Analog Return. This point and the reference side of the DAC load resistors should be connected to the same potential (nominally ground). Analog current output; full-scale current occurs with a digital word input of all "1s." With external load resistor, output voltage = IOUT (RLOAD RINTERNAL). RINTERNAL is nominally 240 . Complementary analog current output; full-scale current occurs with a digital word input of all "0s." Negative analog supply, nominally -5.2 V. Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current source network. Voltage changes (noise) at this point have a direct effect on the full-scale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/RSET) when using the internal amplifier. DAC load is virtual ground. Normally connected to REF IN (Pin 23). Output of internal control amplifier which provides a reference for the current switch network. Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference, nominally -1.25 V. Normally connected to REF Out (Pin 25) if not connected to external reference. Negative digital supply, nominally -5.2 V.
21 22 23
IOUTB ANALOG -VS REF IN
24 25 26 27
CONTROL AMP OUT REF OUT CONTROL AMP IN DIGITAL -VS
PIN CONFIGURATION
D9(MSB) 1 D8 2 D7 3 D6 4 D5 5 D4 6 D3 7 GND DIGITAL -VS CONTROL AMP IN REF OUT CONTROL AMP OUT REF IN
28 27 26 25 24
AD9731
23 22
ANALOG -VS TOP VIEW D2 8 (Not to Scale) 21 IOUTB 20 I D1 9 OUT D0(LSB) 10 CLOCK 11 NC 12 NC 13 DIGITAL +VS 14
19 18 17 16 15
ANALOG RETURN GND RSET DIGITAL -VS GND
NC = NO CONNECT
REV. A
-5-
AD9731-Typical Performance Characteristics
80
60
75
55
70 SFDR - dB
SFDR - dB
65
50
60
45
55
50 10
40
20
30
40 50 AOUT - MHz
60
70
80
20
18
16
14
10 12 IOUT - mA
8
6
4
2
Figure 2. Narrowband SFDR (Clock = 170 MHz) vs. AOUT Frequency
Figure 5. SFDR vs. IOUT (Clock =125 MHz/AOUT = 40 MHz)
85 80
0.4 0.3 0.2
75
0.1
SFDR - dB
LSB
70
0 -0.1
65
60
-0.2 -0.3 -0.4
55 50 10
20
30 40 AOUT - MHz
50
60
Figure 3. Narrowband SFDR (Clock = 125 MHz) vs. AOUT Frequency
Figure 6. Typical Differential Nonlinearity Performance (DNL)
65
0.6
0.4
60
0.2
SFDR - dB
55
LSB 0
50
-0.2
45
-0.4
40 10
-0.6
20
30
40
50 60 AOUT - MHz
70
80
90
Figure 4. Wideband SFDR (170 MHz Clock) vs. AOUT
Figure 7. Typical Integral Nonlinearity Performance (INL)
-6-
REV. A
AD9731
1 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0Hz START 6.25MHz 62.5MHz STOP 1 -70 -80 -90 -100 0Hz START 6.25MHz 62.5MHz STOP 1AP -40 -50 -60 1 ENCODE = 125MHz AOUT = 2MHz SPAN = 62.5MHz -10 -20 -30 1AP ENCODE = 125MHz AOUT = 40MHz SPAN = 62.5MHz 1
Figure 8. Wideband SFDR 2 MHz AOUT; 125 MHz Clock
Figure 11. Wideband SFDR 40 MHz AOUT; 125 MHz Clock
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0Hz START
1 0 ENCODE = 125MHz AOUT = 10MHz SPAN = 62.5MHz 1AP -10 -20 -30 -40 1 PRN -50 -60 -70 -80 -90 6.25MHz 62.5MHz STOP 0Hz START 8.5MHz 85MHz STOP 1 1AP 1
Figure 9. Wideband SFDR 10 MHz AOUT; 125 MHz Clock
Figure 12. Wideband SFDR 65 MHz AOUT; 170 MHz Clock
1 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0Hz START 6.25MHz 62.5MHz STOP 1 1AP -40 -50 -60 -70 -80 -90 -100 0Hz START 8.5MHz 1 ENCODE = 125MHz AOUT = 20MHz SPAN = 62.5MHz -10 -20 -30 ENCODE = 170MHz AOUT = 70MHz SPAN = 85MHz
1
1AP
85MHz STOP
Figure 10. Wideband SFDR 20 MHz AOUT; 125 MHz Clock
Figure 13. Wideband SFDR 70 MHz AOUT; 170 MHz Clock
REV. A
-7-
AD9731
1 -10 -20 -30 -40 -50 -60 1 -70 -80 -90 -100 0Hz START 200kHz 2MHz STOP ENCODE = 125MHz AOUT1 = 800kHz AOUT2 = 900kHz SPAN = 2MHz
1AP
The on-board register is rising-edge triggered and should be used to synchronize data to the current switches by applying a pulse with proper data setup and hold times as shown in the timing diagram. Although the AD9731 is designed to provide isolation of the digital inputs to the analog output, some coupling of digital transitions is inevitable. Digital feedthrough can be minimized by forming a low-pass filter at the digital input by using a resistor in series with the capacitance of each digital input. This common high speed DAC application technique has the effect of isolating digital input noise from the analog output.
References
Figure 14. Wideband Intermodulation Distortion F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 2 MHz
1 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0Hz START 6.25MHz 62.5MHz STOP 1 PRN ENCODE = 125MHz AOUT1 = 800kHz AOUT2 = 900kHz SPAN = 62.5MHz
The internal bandgap reference, control amplifier and reference input are pinned out to provide maximum user flexibility in configuring the reference circuitry for the AD9731. When using the internal reference, REF OUT (Pin 25) should be connected to CONTROL AMP IN (Pin 26). CONTROL AMP OUT (Pin 24) should be connected to REF IN (Pin 23). A 0.1 F ceramic capacitor connected from Pin 23 to Analog -VS (Pin 22) improves settling time by decoupling switching noise from the current sink baseline. A reference current cell provides feedback to the control amplifier by sinking current through RSET (Pin 17). Full-scale current is determined by CONTROL AMP IN and RSET according to the following equation:
1AP
IOUT (FS) = 32(CONTROL AMP IN/RSET) The internal reference is nominally -1.25 V with a tolerance of 8% and typical drift over temperature of 100 ppm/C. If greater accuracy or temperature stability is required, an external reference can be used. The AD589 reference features 10 ppm/C drift over the 0C to +70C temperature range. Two modes of multiplying operation are possible with the AD9731. Signals with bandwidths up to 2.5 MHz and input swings from -0.6 V to -1.2 V can be applied to the CONTROL AMP IN pin as shown in Figure 16. Because the control amplifier is internally compensated, the 0.1 F capacitor discussed above can be reduced to maximize the multiplying bandwidth. However, it should be noted that output settling time, for changes in the digital word, will be degraded.
AD9731
RSET
Figure 15. Wideband Intermodulation Distortion F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 62.5 MHz
THEORY AND APPLICATIONS
The AD9731 high speed digital-to-analog converter utilizes most significant bit decoding and segmentation techniques to reduce glitch impulse and deliver high dynamic performance on lower power consumption than previous bipolar DAC technologies. The design is based on four main subsections: the decoder/ driver circuits, the edge-triggered data register, the switch network and the control amplifier. An internal bandgap reference is included to allow operation of the device with minimum external support components.
Digital Inputs/Timing
-0.6 TO -1.2V 2.5MHz TYPICAL
RSET
CONTROL AMP IN RT CONTROL AMP OUT
The AD9731 has TTL/high speed CMOS-compatible singleended inputs for data inputs and clock. The switching threshold is +1.5 V. In the decoder/driver section, the three MSBs are decoded to seven "thermometer code" lines. An equalizing delay is included for the seven least significant bits and the clock signals. This delay minimizes data skew and data setup and hold times at the register inputs.
REFERENCE IN 0.1 F ANALOG -VS
Figure 16. Low Frequency Multiplying Circuit
-8-
REV. A
AD9731
The REFERENCE IN pin can also be driven directly for wider bandwidth multiplying operation. The analog signal for this mode of operation must have a signal swing in the range of -3.3 V to -4.25 V. This can be implemented by capacitively coupling into REFERENCE IN a signal with a dc bias of -3.3 V (IOUT 22.5 mA) to -4.25 V (IOUT 3 mA), as shown in Figure 17, or by dividing REFERENCE IN with a low impedance op amp whose signal swing is limited to the stated range. NOTE: When using an external reference, the external reference voltage must be applied prior to applying -VS. An operational amplifier can also be used to perform the I-to-V conversion of the DAC output. Figure 18 shows an example of a circuit that uses the AD9617, a high speed, current feedback amplifier. The resistor values in Figure 18 provide a 4.096 V swing, centered at ground, at the output of the AD9617 amplifier.
10k 10k
1/2 AD708
1/2 AD708
IFS R1 200 R2 100
AD9731
REF CONTROL AMP IN OUT
APPROX -3.8V
IFS RL 25
RFF 25
RFB 400 2048V
IOUT
AD9617
VOUT
REFERENCE IN -VS -VS
AD9731
IOUTB 25
Figure 17. Wideband Multiplying Circuit
Analog Output
Figure 18. I-to-V Conversion Using a Current Feedback Amplifier
EVALUATION BOARD
The switch network provides complementary current outputs IOUT and IOUTB. The design of the AD9731 is based on statistical current source matching, which provides a 10-bit linearity without trim. Current is steered to either IOUT or IOUTB in proportion to the digital input word. The sum of the two currents is always equal to the full-scale output current minus 1 LSB. The current can be converted to a voltage by resistive loading as shown in the block diagram. Both IOUT and IOUTB should be equally loaded for best overall performance. The voltage that is developed is the product of the output current and the value of the load resistor.
The performance characteristics of the AD9731 make it ideally suited for direct digital synthesis (DDS) and other waveform synthesis applications. The AD9731 evaluation board provides a platform for analyzing performance under optimum layout conditions. The AD9731 also provides a reference for high speed circuit board layout techniques.
REV. A
-9-
C37DRPF CON1 +V DIG +VD PWR3 4 PWR OUT GND 2 DGND DGND 11 1 12 J1 3 BNC DGND +V DIG +V DIG
AD9731
OPTIONAL RP1 4.9k C5 0.1 F
OPTIONAL RP2 4.9k
E1
E2
+5V1 +5V2 +12V -12V -5V -VD -V DIG DGND +V DIG Y1 OSCILLATOR OPTIONAL -V GND +V
20 18 16 14 12
E3
E4
BNC1
+V DIG 2 13 D1 D2 D3 D4 GND3 DIGITAL -VS 3 14 4 15 5 16 6 17 7 18 8 19 +V DIG 14 NOTE: R1-R10 = 50 U1
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
29 28 27 26 25 24 23 22
AD9731
DGND -V DIG
R11 4.9k
R12 50
21 GND1 19 GND2 17 GND3 E6
BNC
DGND
C1 0.1 F
C2 10 F -V ANA BNC1J2 AGND
E5
E7 E10
E8
U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 CONTROL AMP IN REF OUT CONTROL AMP OUT REF IN ANALOG -VS IOUT IOUT ANA RETURN GND1 RSET DIGITAL -VS GND
E9
U21 1 U20 2 U19 3 U18 4 U17 5 U16 6 U15 7 U14 8 U13 9 U12 10 11 12 13 D5 D6 D7 D8 D9 D10 DAC CLOCK NC1 NC2 +5 DIG 28 27 26 25 24 23 22 21 20 19 18 17 16 15
R15 25 -V DIG AGND R14 1960 DGND AGND
R16 50 AGND
Figure 19. AD9731-PCB Evaluation Board Schematic
-10-
R13 50 9 20 10 DGND -V DIG C7 10 F DGND CLOCK SWITCH MATRIX JUMPER E5 TO E7 E6 TO E8 E6 TO E8 E8 TO E10 EXT. CLK TO E7 EXT. GND TO E9 GENERATOR DG2020 DATA Y1 J1 BNC CON 1 PIN 10 REMOVE Y1 REMOVE R12 SOURCE NOTES COMPUTER PROVIDES CLOCK
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
10 9 8 7 6 5 4 3
DGND
P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1
15 GND4 13 GND5 11 GND6
DGND
DGND -VA C8 0.1 F C9 0.1 F C6 0.1 F +VD C3 10 F C4 0.1 F
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
37 36 35 34 33 32 31 30
AGND
DGND
2 IEN 1 II
REV. A
AD9731
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC Wide Body (SOIC) (R-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
28-Lead Shrink Small Outline (SSOP) (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.311 (7.9) 0.301 (7.64)
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
8 0.015 (0.38) SEATING 0.009 (0.229) 0 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
REV. A
-11-

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