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| MC54/74F85 4-BIT MAGNITUDE COMPARATOR The MC54/74F85 is a 4-Bit Magnitude Comparator which compares two 4-Bit words (A0-A3, B0-B3), A3, B3 being the most significant inputs. Operation is not restricted to binary codes; the device will work with any monotonic code. Three Outputs are provided: "A greater than B" (0A > B), "A less than B" (0A < B), "A equal to B" (0A = B). Three Expander Inputs, IA > B, IA < B, IA = B, allow cascading without external gates. For proper compare operation, the Expander Inputs to the least significant position must be connected as follows: IA < B = IA > B = L, IA = B = H. For serial (ripple) expansion the 0A > B, 0A < B Outputs are connected respectively to the IA > B and IA = B inputs of the next most significant comparator, as shown in Figure 1. Refer to applications section of data sheet for high speed method of comparing large words. 4-BIT MAGNITUDE COMPARATOR FASTTM SCHOTTKY TTL * High Impedance NPN Base Inputs for Reduced Loading (20 A in HIGH and LOW States) * Magnitude Comparison of any Binary Words * Serial or Parallel Expansion Without Extra Gating * ESD > 4000 Volts CONNECTION DIAGRAM VCC 16 A3 15 B2 14 A2 13 A1 12 B1 11 A0 10 B0 9 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 B3 2 IA 4 IA>B 5 A>B 6 A=B 7 A 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC74FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54, 74 54 74 IOH IOL Output Current High Output Current Low 54, 74 54, 74 Min 4.5 -55 0 Typ 5.0 25 25 Max 5.5 125 70 -1.0 20 mA mA Unit V C FAST AND LS TTL DATA 4-36 MC54/74F85 FUNCTION TABLE Comparing Inputs A3, B3 A3 > B3 A3 < B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A2, B2 X X A2 > B2 A2 < B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A1, B1 X X X X A1 > B1 A1 < B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A0, B0 X X X X X X A0 > B0 A0 < B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 IA > B X X X X X X X X H L L X H L Expansion Inputs IA < B X X X X X X X X L H L X H L IA = B X X X X X X X X L L H H L L A>B H L H L H L H L H L L L L H Outputs AH = HIGH Voltage Level L = LOW Voltage Level X = Don't Care DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54, 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 2.7 0.5 20 0.1 IIL IOS Input LOW Current Output Short Circuit Current (Note 2) Total Supply Current ICC HIGH VIN = HIGH LOW An = Bn = IA-B = GND: IA>B = IANOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-37 MC54/74F85 (MSB) B23 A23 B22 A22 B21 A21 B20 A20 B19 A19 B3 A3 B2 A2 B1 A1 B0 A0 L IA < B IA = B IA > B AB NC B18 A18 B17 A17 B16 A16 B15 A15 B14 L A14 B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B AB NC The parallel expansion scheme shown in Figure 1 demonstrates the most efficient general use of these comparators. In the parallel expansion scheme, the expansion inputs can be used as a fifth input bit position except on the least significant device which must be connected as in the Serial Scheme. The expansion inputs are used by labelling IA>B as an "A" input, IAB13 A13 B12 A12 B11 A11 B10 A10 B9 L A9 B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B AB NC B3 A3 B2 A2 B1 A1 B0 A0 AB AB OUTPUTS B8 A8 B7 A7 B6 A6 B5 A5 B4 L A4 B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B AB NC Table 1 Word Length 1-4 Bits Number of Packages 1 2-6 8-31 Typical Speeds 74F 12 ns 22 ns 34 ns B3 A3 B2 A2 B1 A1 (LSB) B0 A0 L H L B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B AB 5-25 Bits 25-120 Bits Figure 1. Comparison of Two 24-Bit Words FAST AND LS TTL DATA 4-38 MC54/74F85 AC ELECTRICAL CHARACTERISTICS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter A or B Input to A < B, A > B Output A or B Input to A = B Output IAB Output IA=B Input to A = B Output IA>B and IA=B Input to AThe expansion inputs IA>B, IA=B, and IAB, A=B, and AB, IA=B, and IAis added with each additional stage. For proper operation the expansion inputs of the least significant word should be tied as follows: IA>B = LOW, IA=B = HIGH, and IAA3 (15) B3 (1) (5) A2 (13) B2 (14) (2) IA < B IA = B (3) IA > B (4) A1 (12) B1 (11) (7) A>B (6) A=B A NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 2. Logic Diagram FAST AND LS TTL DATA 4-39 |
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