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PD-93839A IRLR8503 IRLR8503
* * * * N-Channel Application-Specific MOSFET Ideal for CPU Core DC-DC Converters Low Conduction Losses Minimizes Parallel MOSFETs for high current applications
HEXFET(R) MOSFET for DC-DC Converters
D
Description This new device employs advanced HEXFET Power MOSFET technology to achieve very low on-resistance. The reduced conduction losses makes it ideal for high efficiency DC-DC converters that power the latest generation of microprocessors. The IRLR8503 has been optimized and is 100% tested for all parameters that are critical in synchronous buck converters including RDS(on), gate charge and Cdv/dtinduced turn-on immunity. The IRLR8503 offers an extremely low combination of Qsw & RDS(on) for reduced losses in control FET applications. The package is designed for vapor phase, infra-red, convection, or wave soldering techniques. Power dissipation of greater than 2W is possible in a typical PCB mount application.
G S
D-Pak
DEVICE RATINGS (MAX. Values) IRLR8503 VDS RDS(on) QG Qsw Qoss 30V 18 m 20 nC 8 nC 29.5 nC
Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain or Source Current (VGS 10V)U Pulsed Drain CurrentQ Power DissipationU TC = 25C TC = 90C Junction & Storage Temperature Range Continuous Source Current (Body Diode) Pulsed source Current Q Thermal Resistance Parameter Maximum Junction-to-AmbientS Maximum Junction-to-Lead Symbol R JA R JL Max. 50 2.0 Units C/W C/W TJ, TSTG IS ISM TC = 25C TC = 90C IDM PD Symbol VDS VGS ID IRLR8503 30 20 44 32 196 62 30 -55 to 150 15 196 C A W A Units V
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IRLR8503
Electrical Characteristics
Parameter Drain-to-Source Breakdown Voltage* Static Drain-Source on Resistance* Gate Threshold Voltage* Drain-Source Leakage Current VGS(th) IDSS Symbol V(BR)DSS RDS(on) Min 30 - - 1.0 - - Gate-Source Leakage Current* Total Gate Charge Control FET* Total Gate Charge Sync FET* Pre-Vth Gate-Source Charge Post-Vth Gate-Source Charge Gate to Drain Charge Switch Charge* (Qgs2 + Qgd) Output Charge* Gate Resistance Turn-on Delay Time Drain Voltage Rise Time Turn-off Delay Time Drain Voltage Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance IGSS Qg Qg Qgs1 Qgs2 Qgd Q SW Qoss Rg td (on) trv td (off) tfv Ciss Coss Crss - - - - - - - - - - - - - - - - - - - 15 13 3.7 1.3 4.1 5.4 23 1.7 10 18 11 3 1650 650 58 30* 150 100 20 17 - - - 8 29.5 - - - - - - - - pF VDS = 25V, VGS = 0 ns VDD = 16V, ID = 15A VGS = 5V Clamped Inductive Load See test diagram Fig 14. VDS = 16V, VGS = 0 nC nA Typ - 11 13 Max - 16 18 V A Units V m Conditions VGS = 0V, ID = 250A VGS = 10V, ID =15AR VGS = 4.5V, ID =15A VDS = VGS, ID = 250A VDS = 24V, VGS = 0 VDS = 24V, VGS = 0, Tj = 100C VGS = 12V VGS= 5V, ID= 15A, VDS=16V, VGS = 5V, VDS< 100mV VDS = 16V, ID = 15A
Source-Drain Rating & Characteristics
Parameter Diode Forward Voltage* Reverse Recovery ChargeT Reverse Recovery Charge (with Parallel Schottky)T Symbol VSD Q rr Qrr(s) Min - - - 76 67 Typ Max 1.0 Units V nC Conditions IS = 15AR, VGS = 0V di/dt = 700A/s VDS = 16V, VGS = 0V, IS = 15A
di/dt = 700A/s (with 10BQ040) VDS = 16V, VGS = 0V, IS = 15A
Notes:
Q R S *
T Typ = measured - Qoss Repetitive rating; pulse width limited by max. junction temperature. UCalculated continuous current based on maximum allowable Pulse width 300 s; duty cycle 2%. Junction temperature; switching and other losses will When mounted on 1 inch square copper board, t < 10 sec. decrease RMS current capability; package limitation current = 20A. Devices are 100% tested to these parameters.
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IRLR8503
Power MOSFET Optimization for DC-DC Converters While the IRLR8103V and IRLR8503 can and are being used in a variety of applications, they were designed and optimized for low voltage DC-DC conversion in a synchronous buck converter topology, specifically, microprocessor power applications. The IRLR8503 (Figure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function.
Table 2 - New Charge Parameters
New Charge Parameter QGS1 QGS2 Q GCONT QSWITCH Q OSS Description Pre-Threshold Gate Charge Post-Threshold Gate Charge Control FET Total QG Charge during control FET switching Combines QGS2 and QGD Output charge Charge supplied to COSS during the QGD period of control FET switching Synchronous FET Total QG (VDS 0) Figure 5 Figure 6 Figure 4 Figure 3 Waveform
QGSYNC IRLR8503 (Cont FET) CGD
Drain Voltage Drain Voltage CDS VGTH QG (Control FET) QSwitch QGD Gate Voltage 0V Dead Time
IRLR8103V (Sync FET)
CGS
Gate Voltage VGTH QG (Sync FET) 0A
Figure 1 - Application Topology
Figure 2 - Inter-electrode Capacitance
QGS1 QGS2
Drain Current
Because of the inter-electrode capacitance (Figure 2) of the Power MOSFET, specifying the RDSON of the device is not enough to ensure good performance. An optimization between RDSON and charge must be performed to insure the best performing MOSFET for a given application. Both die size and device architecture must be varied to achieve the minimum possible in-circuit losses. This is independently true for both control FET and synchronous FET. Unfortunately, the capacitances of a FET are non-linear and voltage dependent. Therefore, it is inconvenient to specify and use them effectively in switching power supply power loss estimations. This was well understood years ago and resulted in changing the emphasis from capacitance to gate charge on Power MOSFET data sheets.
Table 1 - Traditional Charge Parameters
Device Capacitance C GS CGS + CGD CGD Corresponding Charge Parameter QGS QG QGD
Body Diode Current
Drain Current
Figure 3 - Control FET Waveform
Figure 4 - Sync FET Waveform
The waveforms are broken into segments corresponding to charge parameters. These, in turn, correspond to discrete time segments of the switching waveform.
VIN g1 N1 Cont FET Coss1 2n SN g2 N2 Sync FET Coss2 2n Switch node voltage (VSN)
N1 Gate Voltage N1 Current N1 Coss Discharge + N2 Coss Charge
Figure 5 - QOSS Equivalent Circuit
Figure 6 - QOSS Waveforms
International Rectifier has recently taken the industry a step further by specifying new charge parameters that are even more specific to DC-DC converter design (Table 2). In order to understand these parameters, it is best to start with the in-circuit waveforms in Figure 3 & Figure 4.
Losses may be broken into four categories: conduction loss, gate drive loss, switching loss, and output loss. The following simplified power loss equation is true for both MOSFETs in a synchronous buck converter: PLOSS = PCONDUCTION + PGATE DRIVE + PSWITCH + POUTPUT For the synchronous FET, the PSWITCH term becomes virtually zero and is ignored.
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IRLR8503
Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that period. Table 3 - Control FET Losses Description Segment Losses 2 Conduction Losses associated with MOSFET on time. IRMS is a function of load P COND = I RMS x R DS (on ) current and duty cycle. Loss Gate Drive Losses associated with charging and discharging the gate of the PIN = VG x QG x MOSFET every cycle. Use the control FET QG. Loss Switching Losses during the drain voltage and drain current transitions for every full cycle. Q GS 2 x Losses occur during the QGS2 and QGD time period and can be simplified by using PQGS 2 VIN x IL x Loss IG Qswitch. Q PQGD VIN x IL x GD x IG
PSWITCH VIN x IL Q SW x IG
Output Loss
Losses associated with the QOSS of the device every cycle when the control Q FET turns on. Losses are caused by both FETs, but are dissipated by the control POUTPUT = OSS x VIN x F 2 FET. Table 4 - Synchronous FET Losses Description Losses associated with MOSFET on time. IRMS is a function of load current and duty cycle. Losses associated with charging and discharging the gate of the MOSFET every cycle. Use the Sync FET QG. Generally small enough to ignore except at light loads when the current reverses in the output inductor. Under these conditions various light load power saving techniques are employed by the control IC to maintain switching losses to a negligible level. Segment Losses
Conduction Loss Gate Drive Loss Switching Loss
PCOND = IRMS x RDSon
2
PIN = VG x QG x
PSWITCH 0
Output Loss
Losses associated with the QOSS of the device every cycle when the control FET Q turns on. They are caused by the synchronous FET, but are dissipated in the control POUTPUT = OSS x VIN x 2 FET.
Typical PC Application The IRLR8103V and the IRLR8503 are suitable for Synchronous Buck DC-DC Converters, and are optimized for use in next generation CPU applications. The IRLR8103V is primarily optimized for use as the low side synchronous FET (Q2) with low RDS(on) and high CdV/dt immunity.The IRLR8503 is primarily optimized for use as the high side control FET (Q2) with low cobmined Qsw and RDS(on) , but can also be used as a synchronous FET. The IRLR8503 is also tested for Cdv/dt immunity, critical for the low side socket. The typical configuration in which these devices may be used in shown in Figure 7.
IRLR8503 Control FET (Q1)
1 x IRLR8103V or or 2 x IRLR8503 Synchronous FET (Q2)
Figure 7. 2 & 3-FET solution for Synchronous Buck Topology.
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IRLR8503
2.5
Typical Characteristics IRLR8503 6.0
ID = 15A
VGS, Gate-to-Source Voltage (V)
RDS(on) , Drain-to-Source On Resistance
ID = 15A V DS = 20V
VGS = 4.5V
2.0
4.0
(Normalized)
1.5
2.0
1.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160
0.0 0 4 8 12 16
T J , Junction Temperature ( C )
QG, Total Gate Charge (nC)
Figure 8. Normalized On-Resistance vs. Temperature
R DS(on) , Drain-to -Source On Resistance ()
0.015
Figure 9. Gate-to-Source Voltage vs. Typical Gate Charge
2500
0.014
2000
V GS Ciss Crss Coss = = = = 0V, f = 1MHz Cgs + C gd , Cds SHORTED Cgd Cds + C gd
C, Capacitance (pF)
0.013
Ciss
1500
0.012
1000
ID = 15A
0.011
C oss
500
0.010 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
0 1
C rss
10 100
VGS, Gate -to -Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage
100
1000.0
Figure 11. Typical Capacitance vs. Drain-to-Source Voltage
ID, Drain-to-Source Current ( )
100.0
T J = 150C
10.0
T J = 25C VDS = 15V 20s PULSE WIDTH
2.5 3.0 3.5 4.0 4.5 5.0 5.5
1.0
VGS, Gate-to-Source Voltage (V)
Figure 12. Typical Transfer Characteristics
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IRLR8503
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Thermal Response (Z thJC )
1
D = 0.50 0.20 0.10 0.05
0.1
0.02 0.01
0.0001
SINGLE PULSE (THERMAL RESPONSE)
0.01 0.00001
Notes: 1. Duty factor D =t 1 / t 2 2. Peak TJ = P DM x ZthJC + TC 0.1 0.001 0.01 1
PDM t1 t2
t1 , Rectangular Pulse Duration (sec)
Figure 13. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Inductive Load Circuit
Figure 15. Switching waveform
Figure 14. Clamped Inductive Load test diagram
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IRLR8503
Package Outline
TO-252AA Outline Dimensions are shown in millimeters (inches)
6 .7 3 (.2 6 5 ) 6 .3 5 (.2 5 0 ) -A5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 ) 1 .0 2 (.0 4 0 ) 1 .6 4 (.0 2 5 ) 1 2 3 0 .5 1 (.0 2 0 ) M IN . 1 0 .4 2 (.4 1 0 ) 9 .4 0 (.3 7 0 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 ) 2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 1 .1 4 ( .0 4 5 ) 0 .8 9 ( .0 3 5 ) 0.5 8 (.0 2 3 ) 0.4 6 (.0 1 8 )
-B1 .5 2 ( .0 6 0 ) 1 .1 5 ( .0 4 5 ) 3X 2X 1 .1 4 (.0 4 5) 0 .7 6 (.0 3 0) 2 .2 8 (.0 9 0 ) 4 .5 7 (.1 8 0 ) 0 .8 9 (.0 3 5 ) 0 .6 4 (.0 2 5 ) 0 .2 5 ( .0 1 0 ) M AMB
0 .5 8 (.0 23 ) 0 .4 6 (.0 18 )
NO TES : 1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 2 C O N TR O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0 .16 (.0 0 6 ).
Part Marking Information
TO-252AA (D-PAK)
E X A M P L E : T H IS IS A N IR F R 1 20 W IT H A S S E M B L Y LOT CODE 9U1P IN T E R N A T IO N A L R E C T IF IE R LO GO
A
IR F R 120 9U 1P
F IR S T P O R T IO N OF PART NUMBER
ASSEMBLY LOT CODE
S E C O N D P O R T IO N O F PART NUM BER
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IRLR8503
Tape & Reel Information
TO-252AA
TR
TRR
TRL
1 6.3 ( .6 41 ) 1 5.7 ( .6 19 )
16 .3 ( .64 1 ) 15 .7 ( .61 9 )
12 .1 ( .4 7 6 ) 11 .9 ( .4 6 9 )
F E E D D IR E C T IO N
8 .1 ( .3 18 ) 7 .9 ( .3 12 )
F E E D D IR E C T IO N
NOTES : 1 . C O N T R O LL IN G D IM E N S IO N : M ILL IM E T E R . 2 . A LL D IM E N S IO N S A R E S H O W N IN M ILL IM E T E R S ( IN C H E S ). 3 . O U T L IN E C O N F O R M S T O E IA -4 81 & E IA -54 1.
1 3 IN C H
16 m m NO TES : 1. O U T L IN E C O N F O R M S T O E IA -4 81 .
Data and specifications subject to change without notice. This product has been designed and qualified for the commercial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/00
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