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| SAA8200HL Ensation Base integrated wireless audio baseband Rev. 02 -- 17 October 2005 Preliminary data sheet 1. General description The Ensation Base, SAA8200HL, is part of the integrated wireless audio system chip set offered by Philips. This chip set enables the development of low cost wireless digital audio systems. The chip set contains: * An integrated wireless audio baseband chip (SAA8200HL) * An integrated wireless audio radio chip (TEA7000). RF CHIP RF CHIP TEA7000 TEA7000 analog audio/voice in/out SPDIF I 2 S-bus I 2 C-bus GPIO BASEBAND CHIP BASEBAND CHIP analog audio/voice in/out I 2 S-bus I 2 C-bus GPIO SAA8200 SAA8200 data in/out peripherals/UI data in/out peripherals/UI 001aab062 Fig 1. Ensation Link system example using two integrated wireless audio baseband and radio ICs Integrating a wireless audio link in a home theatre system to remove part of the wiring is a logical application of wireless audio transmission. A very important property of this wireless audio system is the low end-to-end (audio-in at transmit side to audio-out at receive side) system latency, which is below 20 ms. A second important property is the robustness and reliability of the wireless audio link, the SAA8200HL which is handling the signal processing and the system control enables this. Furthermore, the SAA8200HL provides the flexibility to allow designers to make trade-offs between air bit-rate, number of transported audio channels, audio formats, audio coding bit-rates, range, number of receiving-slaves and more. Due to its low power consuming design, the SAA8200HL enables battery powered applications. The SAA8200HL does this all with a minimum of external components due to its high level of integration. Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Together with the TEA7000, the SAA8200HL can be used to implement an indoor wireless link for audio applications (system specific). Together with an AV-compliant Bluetooth radio module, the SAA8200HL can be used to implement a Bluetooth wireless audio functionality. The SAA8200HL enables a low power, low cost two-chip solution with a maximum amount of functions integrated on the SAA8200HL, taking into account strict time-to-market constraints. 2. Features 2.1 General s Programmable baseband processor and system controller for cable replacement wireless audio s Supports various audio compression formats s Wireless audio protocol can make trade-off between quality, number of channels, bandwidth and range s Supports various transmission frequencies s High integration allows for two-chip applications s Embedded ROM with wireless audio software library. 2.2 Hardware s s s s s Audio PLL and system PLL Read-Solomon encoder and decoder SPDIF interface Low cost low power EPICS7B DSP core with hardware debugger and JTAG interface Integrated memories: x 24/6 kWords program ROM/RAM (bit width: 32 bits) x 12 kWords X data RAM (bit width: 24 bits) x 12/2 kWords Y data ROM/RAM (bit width: 12 bits). Interrupt controller DMA controller Oscillator and time base unit with programmable clocks Embedded LDO regulators and DC-to-DC converters for on-chip and off-chip supply voltage needs Power control unit Power on and power off switching with battery supply Reed-Solomon codec unit Serial radio interface unit High speed UART General purpose digital I/O block with 14 inputs, all of which generate interrupts I2C-bus master/slave I2C-bus for radio chip control Control 10-bit ADC with four inputs s s s s s s s s s s s s s SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 2 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband s Two serial (I2S-bus/Japanese) digital audio inputs with independent clocks and word-select s Two serial (I2S-bus/Japanese) digital audio outputs with shared clock and word-select s Integrated 16-bit stereo DAC (line output) s Integrated stereo headphone amplifier s Programmable Gain Amplifier (PGA) (line input) s Low noise microphone amplifier (microphone input) s Integrated 16-bit stereo ADC s Watchdog timer. 2.3 Software s s s s s s s s s s s s Stereo Sub Band Coding (SBC) encoder/decoder Stereo MPEG layer 3 (MP3) decoder Reed-Solomon encoder/decoder driver Sample rate converter I2C-bus master/slave driver Serial radio interface driver RF radio chip driver UART driver Control 10-bit ADC driver Power consumption management ADC, DAC and headphone driver Wireless audio protocol library. 3. Applications s s s s Wireless front speakers or wireless surround speakers for home theatre Wireless indoor headphones Wireless second room audio sets Wireless headsets. 4. Ordering information Table 1: Ordering information Package Name SAA8200HL LQFP100 Description plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm Version SOT407-1 Type number SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 3 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 5. Block diagram HARDWARE DEBUGGER AUDIO CONFIGURATION SPDIF_IN I2SIN_1_DATA I2SIN_1_WS I2SIN_1_BCK I2SIN_2_DATA I2SIN_2_WS I2SIN_2_BCK 29 72 73 74 84 87 7 78 76, 77 79 2 SPDIF JTAG 64 65 66 67 68 JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TCK JTAG_TRST_N MEMORIES 2 3 I2SIN_2 DMA CONTROLLER I2SIN_1 SYSTEM I2C IIC_MS_SCL IIC_MS_SDA RSC I2SOUT_2_DATA I2SOUT_WS, I2SOUT_BCK I2SOUT_1_DATA I2SOUT_2 SRI 94 95 96 97 98 99 SRI_FSYNC_P SRI_FSYNC_N SRI_GCHCLK_P SRI_GCHCLK_N SRI_DATA_P SRI_DATA_N I2SOUT_1 EPICS7B SRI I2C 100 1 39 40 41 42 IIC_SRI_SCL IIC_SRI_SDA ADC10B_GPA0 ADC10B_GPA1 ADC10B_GPA2 ADC10B_GPA3 TIMESTAMP COUNTER CONTROL ADC DAC_OUTL DAC_OUTR HP_OUTL HP_OUTR ADC_INR ADC_INL ADC_MIC_PGA ADC_MIC_LNA ADC_MIC_IN 14 15 AUDIO DAC 16 20 23 24 25 26 27 LNA AUDIO PLL HEADPHONE AMPLIFIER WATCHDOG VPB BRIDGE EVENT ROUTER 80 81 82 83 80 81 82 83 7 8 9 10 47 48 49 50 84 87 55 63 UART_NRTS UART_NCTS UART_RXS UART_TXS GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_10 GPIO_11/SRI_INT GPIO_12 GPIO_13 GPIO_03 GPIO_02/MODE_1 GPIO_01/MODE_0 GPIO_00 GPIO_08 GPIO_09 3.3 V/1.8 V SUPPLY VBAT(DCDC) VUSB(DCDC) PGA AUDIO ADC UART SYSTEM PLL 71 75 92 91 CGU CLK_OUT1 CLK_OUT2 XTALH_IN XTALH_OUT CRYSTAL OSCILLATOR IO CONFIGURATION RSTIN_N 4 SAA8200HL DC/DC CONVERTOR 001aab054 Pins 7, 80 to 84 and 87 are multiplexed functions pins. Fig 2. Block diagram SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 4 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 6. Pinning information 6.1 Pinning 84 GPIO_08/I2SIN_2_DATA 81 GPIO_05/UART_NCTS 80 GPIO_04/UART_NRTS 87 GPIO_09/I2SIN_2_WS 82 GPIO_06/UART_RXS 83 GPIO_07/UART_TXS 93 VDDA(1V8_XTALH) 79 I2SOUT_1_DATA 78 I2SOUT_2_DATA 97 SRI_GCHCLK_N 96 SRI_GCHCLK_P 95 SRI_FSYNC_N 94 SRI_FSYNC_P 100 IIC_SRI_SCL 77 I2SOUT_BCK 99 SRI_DATA_N 98 SRI_DATA_P 91 XTALH_OUT IIC_SRI_SDA IIC_MS_SCL IIC_MS_SDA RSTIN_N VSSI1 VDDI1 GPIO_10/I2SIN_2_BCK GPIO_11/SRI_INT GPIO_12 1 2 3 4 5 6 7 8 9 76 I2SOUT_WS 90 VSSA(XTALH) 92 XTALH_IN 89 VDDE2 88 VSSE2 85 VDDI3 86 VSSI3 75 CLK_OUT2 74 I2SIN_1_BCK 73 I2SIN_1_WS 72 I2SIN_1_DATA 71 CLK_OUT1 70 VDDE1 69 VSSE1 68 JTAG_TRST_N 67 JTAG_TCK 66 JTAG_TDO 65 JTAG_TMS 64 JTAG_TDI GPIO_13 10 DAC_REFN 11 DAC_REFP 12 VDDA(3V3_DAC) 13 DAC_OUTL 14 DAC_OUTR 15 HP_OUTL 16 VSSA(HP) 17 HP_OUTC 18 VDDA(3V3_HP) 19 HP_OUTR 20 HP_COM 21 VSSA(ADC) 22 ADC_INR 23 ADC_INL 24 ADC_MIC_PGA 25 SAA8200HL 63 VUSB(DCDC) 62 DCDC_OUT3V3 61 DCDC_LX1 60 VSS12(DCDC) 59 DCDC_LX2 58 DCDC_SW 57 DCDC_IN3V3 56 DCDC_OUT1V8 55 VBAT(DCDC) 54 VSSA(DCDC) 53 DCDC_PLAY 52 DCDC_STOP 51 DCDC_DOWNSEL ADC_MIC_LNA 26 ADC_MIC_IN 27 VSSA(SPDIF) 28 SPDIF_IN 29 VDDA(3V3_SPDIF) 30 VDDA(3V3_ADC) 31 VDDA(1V8_ADC) 32 ADC_REF 33 ADC_REFN 34 ADC_REFP 35 ADC_COM 36 VSSA(PLL) 37 VDDA(1V8_PLL) 38 ADC10B_GPA0 39 ADC10B_GPA1 40 ADC10B_GPA2 41 ADC10B_GPA3 42 VDDA(3V3_ADC10B) 43 VSSA(ADC10B) 44 VDDI2 45 VSSI2 46 GPIO_03 47 GPIO_02/MODE_1 48 GPIO_01/MODE_0 49 GPIO_00 50 001aab020 Fig 3. Pin configuration SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 5 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 6.2 Pin description Table 2: Symbol VSSI1 VDDI1 VSSE1 VDDE1 VSSE2 VDDE2 VDDI2 VSSI2 VDDI3 VSSI3 DC-to-DC converter VUSB(DCDC) DCDC_OUT3V3 DCDC_LX1 VSSI2(DCDC) DCDC_LX2 DCDC_SW DCDC_IN3V3 DCDC_OUT1V8 VBAT(DCDC) VSSA(DCDC) DCDC_PLAY DCDC_STOP DCDC_DOWNSEL Crystal oscillator VSSA(XTALH) XTALH_OUT XTALH_IN VDDA(1V8_XTALH) PLL VDDA(1V8_PLL) VSSA(PLL) Serial radio interface SRI_FSYNC_P SRI_FSYNC_N SRI_GCHCLK_P SAA8200HL_2 Pin description Pin Special [1] Type 5 6 69 70 88 89 45 46 85 86 63 62 61 60 59 58 57 56 55 54 53 52 51 90 91 92 93 38 37 94 95 96 A A A A A A A A A A A A A A A A VSSI VDDI VSSE3V3 VDDE3V3 VSSE3V3 VDDE3V3 VDDCO VSSCO VDDCO VSSCO VDDCO VDDCO VDDCO VSSCO VDDCO VDDCO VDDCO VDDCO VDDCO VSSCO APIO APIO APIO VSSCO APIO APIO VDDCO VDDCO VSSCO APIO APIO APIO Description core ground core supply voltage core ground core supply voltage core ground core supply voltage core supply voltage core ground core supply voltage core ground USB supply voltage (linear regulator) 3.3 V output voltage coil connection for 3.3 V converter ground for switches 1.8 V and 3.3 V converter coil connection for 1.8 V converter switch node 3.3 V input voltage 1.8 V output voltage battery supply voltage ground double bonded clean and substrate play button signal stop button signal one ore two battery selection analog ground 11.025 MHz clock output 11.025 MHz clock input analog supply voltage analog supply voltage analog ground frame sync positive frame sync negative gated channel clock positive (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Digital supply voltage pins Preliminary data sheet Rev. 02 -- 17 October 2005 6 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Pin description ...continued Pin Special [1] Type 97 98 99 I2C-bus 100 1 36 35 34 33 31 32 22 23 24 25 26 27 11 12 13 14 15 21 20 19 18 17 16 30 29 28 72 73 74 A A A A A A A A A A A A A A A A A A A A A A A A A A I I/O I/O IIC400KT5V IIC400KT5V APIO APIO APIO APIO VDDCO VDDCO VSSCO APIO APIO APIO APIO APIO APIO APIO VDDCO APIO APIO APIO APIO VDDCO APIO VSSCO APIO VDDCO APIO VSSCO IPTHT5V clock input data input or output common mode reference voltage positive reference voltage negative reference voltage reference voltage analog supply voltage (3.3 V) analog supply voltage (1.8 V) analog ground right input voltage left input voltage PGA input for AC coupling LNA output for AC coupling microphone input negative reference voltage positive reference voltage analog supply voltage left line output voltage right line output voltage common mode reference voltage right output voltage analog supply voltage common output voltage analog ground left output voltage analog supply voltage input voltage analog ground serial data channel 1 A A A APIO APIO APIO Description gated channel clock negative data positive data negative Table 2: Symbol SRI_GCHCLK_N SRI_DATA_P SRI_DATA_N Serial radio interface IIC_SRI_SCL IIC_SRI_SDA Audio ADC ADC_COM ADC_REFP ADC_REFN ADC_REF VDDA(3V3_ADC) VDDA(1V8_ADC) VSSA(ADC) ADC_INR ADC_INL ADC_MIC_PGA ADC_MIC_LNA ADC_MIC_IN Audio DAC DAC_REFN DAC_REFP VDDA(3V3_DAC) DAC_OUTL DAC_OUTR Headphone HP_COM HP_OUTR VDDA(3V3_HP) HP_OUTC VSSA(HP) HP_OUTL SPDIF VDDA(3V3_SPDIF) SPDIF_IN VSSA(SPDIF) I2S-bus input I2SIN_1_DATA I2SIN_1_WS I2SIN_1_BCK BPTS10THT5V word select channel 1 BPTS10THT5V bit clock channel 1 SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 7 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Pin description ...continued Pin Special [1] Type 7 87 84 I/O I/O I/O Description BPTS10THT5V general purpose IO/I2S-bus input bit clock channel 2 BPTS10THT5V general purpose IO/I2S-bus input word select channel 1 BPTS10THT5V general purpose IO/I2S-bus input serial data channel 2 BPTS10THT5V word select BPTS10THT5V bit clock OTS10CT5V OTS10CT5V VSSCO VDDCO APIO APIO APIO APIO serial data channel 2 serial data channel 1 analog ground analog supply voltage analog general purpose input 3 analog general purpose input 2 analog general purpose input 1 analog general purpose input 0 Table 2: Symbol GPIO_10/I2SIN_2_BCK GPIO_09/I2SIN_2_WS GPIO_08/I2SIN_2_DATA I2S-bus output I2SOUT_WS I2SOUT_BCK I2SOUT_2_DATA I2SOUT_1_DATA Control ADC VSSA(ADC10B) VDDA(3V3_ADC10B) ADC10B_GPA3 ADC10B_GPA2 ADC10B_GPA1 ADC10B_GPA0 GPIO GPIO_13 GPIO_12 GPIO_11/SRI_INT GPIO_10/I2SIN_2_BCK GPIO_09/I2SIN_2_WS GPIO_08/I2SIN_2_DATA GPIO_07/UART_TXS GPIO_06/UART_RXS GPIO_05/UART_NCTS GPIO_04/UART_NRTS GPIO_03 GPIO_02/MODE_1 GPIO_01/MODE_0 GPIO_00 System I2C-bus IIC_MS_SCL IIC_MS_SDA Other CLK_OUT2 SAA8200HL_2 76 77 78 79 44 43 42 41 40 39 10 9 8 7 87 84 83 82 81 80 47 48 49 50 2 3 75 I/O I/O O O A A A A A A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BPTS10THT5V general purpose IO BPTS10THT5V general purpose IO (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. O OTS10CT5V Preliminary data sheet Rev. 02 -- 17 October 2005 8 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Pin description ...continued Pin Special [1] Type 71 4 68 67 64 65 66 O I I I I I O OTS10CT5V IPTHU5V IPTHDT5V IPTHDT5V IPTHDT5V IPTHDT5V OTS10CT5V Description clock output 1 system reset input reset input clock input data input mode select input data output Table 2: Symbol CLK_OUT1 RSTIN_N JTAG JTAG_TRST_N JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO [1] A = analog. I = input. O = output. Table 3: Cell name IPTHT5V IPTHU5V IPTHDT5V Cell types description Definition input pad; push pull; TTL with hysteresis; 5 V tolerant input pad; push pull; TTL with hysteresis; pull-up; 5 V tolerant input pad; push pull; TTL with hysteresis; pull-down; 5 V tolerant output pad; 3-state; 10 ns slew rate control; 5 V tolerant OTS10CT5V BPTS10THT5V bi-directional pad; plain input; 3-state output; 10 ns slew rate control; TTL with hysteresis; 5 V tolerant IIC400KT5V APIO VDDI VDDCO VDDE3V3 VSSCO VSSE3V3 VSSI I2C-bus pad; 400 kHz I2C-bus specification; 5 V tolerant analog pad; analog input/output VDD pad connected to core VDD and internal VDD supply voltage rail in I/O ring VDD pad connected to core VDD VDD pad connected to external 3.3 V VDD supply voltage rail VSS pad connected to core VSS VSS pad connected to external 3.3 V VSS supply voltage rail VSS pad connected to core VSS; internal VSS supply voltage rail in I/O ring and substrate rail in I/O ring SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 9 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7. Functional description 7.1 EPICS7B The EPICS7B core has only access to four of the five memory spaces, PMEM, XMEM, YMEM and DIO. Memory space IO is only accessible via the DMA. To distinguish between the memory spaces, 18-bit addressing is used, of which the two Most Significant (MS) bits determine which space the address is in, see Table 4. The EPICS7B only knows about the 16 least significant bits and uses special instructions to access DIO space. EPICS7B access: XMEM is accessed by EPICS7B when using X in its instructions YMEM is accessed by EPICS7B when using Y in its instructions PMEM is accessed by EPICS7B when it is fetching instructions DIO is accessed by EPICS7B when using D in its instructions. All 18 bits are used when accessing memory via DMA. Table 4: 00 01 10 11 Memory spaces Memory space XMEM YMEM PMEM DIO or IO Two MS bits The memory map of the system is described in Table 5 and Figure 4. Table 5: Address IO 0x[3]FFFF 0x[3]FFFE DIO 0x[3]FF00 to 0x[3]FF3F PMEM 0x[2]8000 to 0x[2]97FF 0x[2]0000 to 0x[2]5FFF 0x[2]0000 to 0x[2]00FF YMEM 0x[1]8000 to 0x[1]87FF 0x[1]0000 to 0x[1]2FFF XMEM 0x[0]FFC0 to 0x[0]FFFF memory mapped registers 0x[0]0000 to 0x[0]2FFF [1] SAA8200HL_2 Memory map Type DSP control register EPICS7B instruction register 64 Words 64 Bits 32 32 32 24 6144 24576 0x[3]FFC0 to 0x[3]FFFD user defined DIO registers PRAM PROM [1] BIOSROM [1] YRAM YROM 2048 12288 XRAM 12288 DSP control register bit 0 is selecting PROM or BIOSROM. (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 10 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 0x [3] FFFF 0x [3] FFFE 0x [3] FFFD 0x [3] FFC0 0x [3] FFBF DSP control register EPICS instruction register user defined IO and DIO not used 0x [3] FF40 0x [3] FF3F 0x [3] FF00 0x [3] FEFF 0x [3] 0000 0x [2] FFFF DIO register not used not used 0x [2] 9800 0x [2] 97FF 0x [2] 8000 0x [2] 7FFF PRAM PMEM not used 0x [2] 6000 0x [2] 5FFF 0x [2] 0100 0x [2] 00FF 0x [2] 0000 0x [1] FFFF PROM PROM or BIOSROM not used 0x [1] 8800 0x [1] 87FF YRAM 0x [1] 8000 0x [1] 7FFF not used 0x [1] 3000 0x [1] 2FFF YROM 0x [1] 0000 0x [0] FFFF 0x [0] FFC0 0x [0] FFBF memory map YMEM not used XMEM 0x [0] 3000 0x [0] 2FFF XRAM 0x [0] 0000 001aab383 Fig 4. Memory map The control registers are split in two different spaces. One space is accessible only via DMA while the other space is accessible both via DMA and the DSP core. This space is therefore X-memory mapped. The location and definition of the control registers is described in Table 6. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 11 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Control registers description Address 0x0 FFFF 0x0 FFFE 0x0 FFFD 0x0 FFFC 0x0 FFFB 0x0 FFFA 0x3 FFFF 0x3 FFFE 0x0 FFF9 0x0 FFF8 0x0 FFF7 0x0 FFF6 0x0 FFF5 0x0 FFF4 0x0 FFF3 0x0 FFF2 R/W W W W W W W W W W W W R W W W R Description program counter register status register 1 status register 2 interrupt stack register configuration register 1 configuration register 2 control register I/O mapped EPICS7B instruction register polarity select mode select mask status test software clear user flag IRQ counter value Reset undefined undefined undefined undefined 0x00 0000 0x00 0FFD 0x00 0000 0x00 0000 0x03 FFFF 0x03 FFFF 0x03 FFFF undefined 0x00 0001 0x00 0000 0x00 0000 0x00 0000 Table 6: DSP PC SR1 SR2 Register name RTI_STACK IO_DIR IO_MODE CR EIR INTC_POL INTC_MODE INTC_MASK INTC_STATUS INTC_TEST INTC_SWCLR INTC_SLCT DMA controller DMAC_IC Interrupt controller The interrupts and connection order are described in Table 7. Table 7: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SAA8200HL_2 Interrupt flags Symbol FI_DMAC FI_FLSTART FI_EVENTROUTER FI_I2SIN_1 FI_I2SIN_2 FI_SPDIF FI_ADC FI_DACALL FI_RSC_ENCRDY FI_RSC_DECRDY FI_RSC_DMARDY FI_VPB0 FI_VBP1 FI_UART FI_I2C_DMARDY FI_FSLFAST Description DMAC interrupt FSL start interrupt event router interrupt I2S-bus input 1 interrupt I2S-bus input 2 interrupt SPDIF input interrupt ADC input interrupt I2S-bus and DAC outputs interrupt RSC encoder ready interrupt RSC decoder ready interrupt RSC DMA block transfer ready interrupt VPB0 interrupt VPB1 interrupt UART interrupt I2C-bus M/S DMA block transfer interrupt FSL fast interrupt (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Interrupt flag FI_SRI_DMA_RX_RDY SRI RX DMA block transfer interrupt FI_SRI_DMA_TX_RDY SRI TX DMA block transfer interrupt Preliminary data sheet Rev. 02 -- 17 October 2005 12 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband The outputs of the ADC, I2S-bus inputs, SPDIF inputs and VPB buses are mapped to the inputs of the EPICS7B. Table 8: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DIO input registers Register name I2SIN_1L I2SIN_1R I2SIN_2L I2SIN_2R SPDIF L SPDIF R ADC_L ADC_R VPB0_DI1 VPB0_DI2 VPB1_DI TS_COUNTER I2SIN_1TS I2SIN_2TS SPDIF_TS ADC_TS I2SOUT_TS TS_COUNTER time stamp counter i2sin1 time stamp counter i2sin2 time stamp counter spdif time stamp counter adc time stamp counter i2sout Description I2S-bus input 1 left channel I2S-bus input 1 right channel I2S-bus input 2 left channel I2S-bus input 2 right channel SPDIF input left channel SPDIF input right channel ADC input left channel ADC input right channel VPB0 data input 1 (bit 0 to bit 15) VPB0 data input 2 (bit 16 to bit 31) VPB1 data input (UART) DIO input register The control of the DAC, I2S-bus outputs and VPB buses are mapped to the outputs of the EPICS7B. Table 9: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DIO output registers Description I2S-bus output 1 left channel I2S-bus output 1 right channel I2S-bus output 2 left channel I2S-bus output 2 right channel DAC output left channel DAC output right channel I2SOUT_1L I2SOUT_1R I2SOUT_2L I2SOUT_2R DAC_L DAC_R not connected not connected VPB0_DO1 VPB0_DO2 VPB0_ADDR VPB1_DO VPB1_ADDR not connected not connected VPB0 data output 1 (bit 0 to bit 15) VPB0 data output 2 (bit 16 to bit 31) VPB0 address VPB1 data output (UART) VPB1 address DIO output register Register name SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 13 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband DIO output registers ...continued Description not connected not connected not connected Table 9: 15 16 17 DIO output register Register name 7.1.1 User registers The user registers are memory mapped control signals used to control integrated wireless audio baseband functionality. Table 10: User register description Address 0x0 FFDE 0x0 FFDD 0x0 FFDC 0x0FFDB 0x0 FFDA 0x0 FFD9 0x0 FFD8 0x0 FFD7 0x0 FFD6 0x0 FFD5 0x0 FFD4 0x0 FFD3 0x0 FFD2 0x0 FFD1 0x0 FFD0 0x0 FFCF 0x0 FFCE 0x0 FFCD 0x0 FFCC 0x0 FFCB 0x0 FFCA 0x0 FFC9 R/W W W W W W W W W W W W R R R R W R R R W W W Description serial radio interface DMA from MEM start address serial radio interface DMA from MEM block size serial radio interface mode control serial radio interface master mode start time serial radio interface master mode sync-link time serial radio interface master mode idle time Reset 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 Register name SRI_TX_ADDR SRI_TX_BLKSIZE SRI_MODE SRIM_TSTART SRIM_TLINK SRIM_TIDLE SRIM_DLLEN SRIM_ULLEN FSL_MODE APLL_CONTROL APLL_SELECT SPDIF_STATUS FSY_INPERIOD FSY_REFPERIOD FSY_PHASEDIF IWAB_BOOTCFG SRI_STATUS APLL_ACK RSC_STATUS RSC_CONTROL RSC_ADDR RSC_BLKSIZE serial radio interface master 0x000 0000 mode number downlink words serial radio interface master mode number uplink words frame sync lock mode control audio PLL direct control SPDIF status frame sync measured period frame sync reference measured period frame sync phase difference SAA8200HL boot mode configuration serial radio interface status audio PLL direct control acknowledge Reed-Solomon status Reed-Solomon control Reed-Solomon DMA start address Reed-Solomon DMA block size 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x000 0000 audio PLL direct control select 0x000 0000 SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 14 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband User register description ...continued Address 0x0FFC8 0x0FFC7 0x0FFC6 0x0FFC5 0x0FFC4 0x0FFC3 0x0FFC2 0x0FFC1 R/W W W W W W W W W Description serial radio interface DMA to MEM start address serial radio interface DMA to MEM block size direct control of audio PLL M value direct control of audio PLL N value master/slave I2C-bus DMA memory address master/slave I2C-bus DMA block size master/slave I2C-bus control MPI device address Reset 0x000 0000 0x000 0000 0x000 0000 0x000 0000 0x002 8000 0x000 0000 0x000 0002 0x000 0048 Table 10: Register name SRI_RX_ADDR SRI_RX_BLKSIZE APLL_M APLL_N I2C_ADDR I2C_BLKSIZE I2C_CONTROL MPI_DEVADDR 7.2 VPB0 bridge Section 7.2 specifies the interfaces and function of the VPB0 bridge. The VPB0 bridge acts as a bridge between a range of RTG IP blocks using the VPB bus and the EPICS7B DIO interface. Two bridges are used one to connect to several slow blocks and an additional one specifically for the UART. The VPB0 bridge forms the bridge between the EPICS7B and the clock generation unit, SRI I2C-bus, watchdog timer, event router, I/O configuration and the audio configuration respectively. 7.2.1 VPB0 bridge address definitions Table 11: 0x0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 SAA8200HL_2 VPB0 bridge interface description Key SCR_LP0 SCR_HP0 SCR_DCDC SCR_SPDIF SCR_I2SIN_1 SCR_I2SIN_2 SCR_I2SOUT SCR_SRI_GCHCLK SCR_CR_CLK_OUT1 SCR_CR_CLK_OUT2 SCR_SRI_CHCLK FS1_ LP0 FS1_ HP0 FS1_ DCDC FS1_ SPDIF Description clock generation unit switch control register for system PLL clock switch control register for audio PLL clock switch control register for DC-to-DC converter clock switch control register for SPDIF clock switch control register for I2SIN_1 bit clock switch control register for I2SIN_2 bit clock switch control register for I2SOUT bit clock switch control register for SRI gated channel clock switch control register for CR output 1 clock switch control register for CR output 2 clock switch control register for SRI reference channel clock frequency select side 1 for system PLL clock frequency select side 1 for audio PLL clock frequency select side 1 for DC-to-DC converter clock frequency select side 1 for SPDIF clock (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset Preliminary data sheet Rev. 02 -- 17 October 2005 15 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key FS1_ I2SIN_1 FS1_ I2SIN_2 FS1_ I2SOUT FS1_ SRI_GCHCLK FS1_ CR_CLK_OUT1 FS1_ CR_CLK_OUT2 FS1_ SRI_CHCLK FS2_ LP0 FS2_ HP0 FS2_ DCDC FS2_ SPDIF FS2_ I2SIN_1 FS2_ I2SIN_2 FS2_ I2SOUT FS2_ SRI_GCHCLK FS2_ CR_CLK_OUT1 FS2_ CR_CLK_OUT2 FS2_ SRI_CHCLK SSR_ LP0 SSR_ HP0 SSR_ DCDC SSR_ SPDIF SSR_ I2SIN_1 SSR_ I2SIN_2 SSR_ I2SOUT SSR_ SRI_GCHCLK SSR_ CR_CLK_OUT1 SSR_ CR_CLK_OUT2 SSR_ SRI_CHCLK PCR_SPD_SYSCLK PCR_SYSCLK_DIV4 PCR_UART_UCLK PCR_VPB1_PCLK PCR_UART_PCLK PCR_DEBOUNCE_PCLK PCR_CGU_PCLK PCR_WDOG_PCLK PCR_ADC_PCLK PCR_IOCONF_PCLK PCR_EVENT_ROUTER_PCLK PCR_SRI_I2C_PCLK Description frequency select side 1 for I2SIN_1 bit clock frequency select side 1 for I2SIN_2 bit clock frequency select side 1 for I2SOUT bit clock frequency select side 1 for SRI gated channel clock frequency select side 1 for CR output 1 clock frequency select side 1 for CR output 2 clock frequency select side 1 for SRI reference channel clock frequency select side 2 for system PLL clock frequency select side 2 for audio PLL clock frequency select side 2 for DC-to-DC converter clock frequency select side 2 for SPDIF clock frequency select side 2 for I2SIN_1 bit clock frequency select side 2 for I2SIN_2 bit clock frequency select side 2 for I2SOUT bit clock frequency select side 2 for SRI gated channel clock frequency select side 2 for CR output 1 clock frequency select side 2 for CR output 2 clock frequency select side 2 for SRI reference channel clock frequency select status for system PLL clock frequency select status for audio PLL clock frequency select status for DC-to-DC converter clock frequency select status for SPDIF clock frequency select status for I2SIN_1 bit clock frequency select status for I2SIN_2 bit clock frequency select status for I2SOUT bit clock frequency select status for SRI gated channel clock frequency select status for CR output 1 clock frequency select status for CR output 2 clock frequency select status for SRI reference channel clock power control register for system clock power control register for 0.25 x fs system clock power control register for UART clock power control register for VPB1 bus clock power control register for UART bus clock power control register for DEBOUNCE bus clock power control register for CGU bus clock power control register for WDOG bus clock power control register for control ADC bus clock power control register for IO configuration bus clock power control register for event router bus clock power control register for SRI I2C-bus clock (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC SAA8200HL_2 Preliminary data sheet Rev. 02 -- 17 October 2005 16 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key PCR_ADC_CLK PCR_I2C_MS_PCLK PCR_RSC_PCLK PCR_EXTDMACNTR_PCLK PCR_DIO2VPB0 _PCLK PCR_DIO2VPB1_PCLK PCR_I2SIN_1 _PCLK PCR_I2SIN_2 _PCLK PCR_I2SOUT_1 _PCLK PCR_I2SOUT_2_PCLK PCR_ADSS _PCLK PCR_AUDIO_CONFIG _PCLK PCR_SPDIF _PCLK PCR_SRI _PCLK PCR_FRAMESYNCREF PCR_CR_I2SIN_2_BCK PCR_CR_I2SIN_1_BCK PCR_CR_I2SOUT_BCK PCR_CR_I2SIN_2_WS PCR_CR_I2SIN_1_WS PCR_CR_I2SOUT_WS PCR_SDAC_NS_CLK PCR_SDAC_DSPCLK PCR_SADC_DECCLK PCR_SADC_SYSCLK PCR_SPDIF_BCK PCR_I2SIN_1_BCK PCR_I2SIN_2_BCK PCR_I2SOUT_BCK PCR_SRI_GCC_SHO PCR_CR_CLK_OUT1 PCR_CR_CLK_OUT2 PCR_SRI_CHCLK PSR_SPD_SYSCLK PSR_SYSCLK_DIV4 PSR_UART_UCLK PSR_VPB1_PCLK PSR_UART_PCLK PSR_DEBOUNCE_PCLK PSR_CGU_PCLK Description power control register for control ADC system clock power control register for M/S I2C-bus clock power control register for RSC bus clock power control register for external DMA controller clock power control register for DIO2VPB0 bus clock power control register for DIO2VPB1 bus clock power control register for I2SIN_1 bus clock power control register for I2SIN_2 bus clock power control register for I2SOUT_1 bus clock power control register for I2SOUT_2 bus clock power control register for ADSS bus clock power control register for audio configuration bus clock power control register for SPDIF bus clock power control register for SRI bus clock power control register for SRI frame sync reference power control register for I2SIN_2 bit clock power control register for I2SIN_1 bit clock power control register for I2SOUT bit clock power control register for I2SIN_2 word select power control register for I2SIN_1 word select power control register for I2SOUT word select power control register for SDAC new sample power control register for SDAC DSP clock power control register for SADC decimation filter clock power control register for SADC system clock power control register for SPDIF bit clock from pad power control register for I2SIN_1 bit clock from pad power control register for I2SIN_2 bit clock from pad power control register for I2SOUT bit clock from pad power control register for SRI gated channel clock from pad power control register for crystal output 1 from pad power control register for crystal output 2 from pad power control register for SRI channel clock power status register for system clock power status register for 0.25 x fs system clock power status register for UART clock power status register for VPB1 bus clock power status register for UART bus clock power status register for DEBOUNCE bus clock power status register for CGU bus clock (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 0x0128 0x012C 0x030 0x0134 0x0138 0x013C 0x0140 0x0144 0x0148 0x014C 0x0150 0x0154 0x0158 0x015C 0x0160 0x0164 0x0168 0x016C 0x0170 0x0174 0x0178 0x017C 0x0180 SAA8200HL_2 PCR_DCDC_CONVERTER_CLK power control register for DC-to-DC converter clock Preliminary data sheet Rev. 02 -- 17 October 2005 17 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key PSR_WDOG_PCLK PSR_ADC_PCLK PSR_IOCONF_PCLK PSR_EVENT_ROUTER_PCLK PSR_SRI_I2C_PCLK PSR_ADC_CLK PSR_I2C_MS_PCLK PSR_RSC_PCLK PSR_EXTDMACNTR_PCLK PSR_DIO2VPB0 _PCLK PSR_DIO2VPB1_PCLK PSR_I2SIN_1 _PCLK PSR_I2SIN_2 _PCLK PSR_I2SOUT_1 _PCLK PSR_I2SOUT_2_PCLK PSR_ADSS _PCLK PSR_AUDIO_CONFIG _PCLK PSR_SPDIF _PCLK PSR_SRI _PCLK PSR_FRAMESYNCREF PSR_CR_I2SIN_2_BCK PSR_CR_I2SIN_1_BCK PSR_CR_I2SOUT_BCK PSR_CR_I2SIN_2_WS PSR_CR_I2SIN_1_WS PSR_CR_I2SOUT_WS PSR_SDAC_NS_CLK PSR_SDAC_DSPCLK PSR_SADC_DECCLK PSR_SADC_SYSCLK PSR_SPDIF_BCK PSR_I2SIN_1_BCK PSR_I2SIN_2_BCK PSR_I2SOUT_BCK PSR_SRI_GCC_SHO PSR_CR_CLK_OUT1 PSR_CR_CLK_OUT2 PSR_SRI_CHCLK ESR_SPD_SYSCLK ESR_SYSCLK_DIV4 Description power status register for WDOG bus clock power status register for control ADC bus clock power status register for IO configuration bus clock power status register for event router bus clock power status register for SRI I2C-bus clock power status register for control ADC system clock power status register for M/S I2C-bus clock power status register for RSC bus clock power status register for external DMA controller clock power status register for DIO2VPB0 bus clock power status register for DIO2VPB1 bus clock power status register for I2SIN_1 bus clock power status register for I2SIN_2 bus clock power status register for I2SOUT_1 bus clock power status register for I2SOUT_2 bus clock power status register for ADSS bus clock power status register for audio configuration bus clock power status register for SPDIF bus clock power status register for SRI bus clock power status register for SRI frame sync reference power status register for I2SIN_2 bit clock power status register for I2SIN_1 bit clock power status register for I2SOUT bit clock power status register for I2SIN_2 word select power status register for I2SIN_1 word select power status register for I2SOUT word select power status register for SDAC new sample power status register for SDAC DSP clock power status register for SADC decimation filter clock power status register for SADC system clock power status register for SPDIF bit clock from pad power status register for I2SIN_1 bit clock from pad power status register for I2SIN_2 bit clock from pad power status register for I2SOUT bit clock from pad power status register for SRI gated channel clock from pad power status register for crystal output 1 from pad power status register for crystal output 2 from pad power status register for SRI channel clock enable fraction divider for system clock enable fraction divider for 0.25 x fs system clock (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset 0x0184 0x0188 0x018C 0x0190 0x0194 0x0198 0x019C 0x01A0 0x01A4 0x01A8 0x01AC 0x01B0 0x01B4 0x01B8 0x01BC 0x01C0 0x01C4 0x01C8 0x01CC 0x01D0 0x01D4 0x01D8 0x01DC 0x01E0 0x01E4 0x01E8 0x01EC 0x01F0 0x01F4 0x01F8 0x01FC 0x0200 0x0204 0x0208 0x020C 0x0210 0x0214 0x0218 0x021C 0x0220 0x0224 SAA8200HL_2 PSR_DCDC_CONVERTER_CLK power status register for DC-to-DC converter clock Preliminary data sheet Rev. 02 -- 17 October 2005 18 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key ESR_UART_UCLK ESR_VPB1_PCLK ESR_UART_PCLK ESR_DEBOUNCE_PCLK ESR_CGU_PCLK ESR_WDOG_PCLK ESR_ADC_PCLK ESR_IOCONF_PCLK ESR_EVENT_ROUTER_PCLK ESR_SRI_I2C_PCLK ESR_ADC_CLK ESR_I2C_MS_PCLK ESR_RSC_PCLK ESR_EXTDMACNTR_PCLK ESR_DIO2VPB0 _PCLK ESR_DIO2VPB1_PCLK ESR_I2SIN_1 _PCLK ESR_I2SIN_2 _PCLK ESR_I2SOUT_1 _PCLK ESR_I2SOUT_2_PCLK ESR_ADSS _PCLK ESR_AUDIO_CONFIG _PCLK ESR_SPDIF _PCLK ESR_SRI _PCLK ESR_FRAMESYNCREF ESR_CR_I2SIN_2_BCK ESR_CR_I2SIN_1_BCK ESR_CR_I2SOUT_BCK ESR_CR_I2SIN_2_WS ESR_CR_I2SIN_1_WS ESR_CR_I2SOUT_WS ESR_SDAC_NS_CLK ESR_SDAC_DSPCLK ESR_SADC_DECCLK ESR_SADC_SYSCLK ESR_SPDIF_BCK ESR_I2SIN_1_BCK ESR_I2SIN_2_BCK ESR_I2SOUT_BCK ESR_SRI_GCC_SHO Description enable fraction divider for UART clock enable fraction divider for VPB1 bus clock enable fraction divider for UART bus clock enable fraction divider for DEBOUNCE bus clock enable fraction divider for CGU bus clock enable fraction divider for WDOG bus clock enable fraction divider for control ADC bus clock enable fraction divider for IO configuration bus clock enable fraction divider for event router bus clock enable fraction divider for SRI I2C-bus clock enable fraction divider for control ADC system clock enable fraction divider for M/S I2C-bus clock enable fraction divider for RSC bus clock enable fraction divider for external DMA controller clock enable fraction divider for DIO2VPB0 bus clock enable fraction divider for DIO2VPB1 bus clock enable fraction divider for I2SIN_1 bus clock enable fraction divider for I2SIN_2 bus clock enable fraction divider for I2SOUT_1 bus clock enable fraction divider for I2SOUT_2 bus clock enable fraction divider for ADSS bus clock enable fraction divider for audio configuration bus clock enable fraction divider for SPDIF bus clock enable fraction divider for SRI bus clock enable fraction divider for SRI frame sync reference enable fraction divider for I2SIN_2 bit clock enable fraction divider for I2SIN_1 bit clock enable fraction divider for I2SOUT bit clock enable fraction divider for I2SIN_2 word select enable fraction divider for I2SIN_1 word select enable fraction divider for I2SOUT word select enable fraction divider for SDAC new sample enable fraction divider for SDAC DSP clock enable fraction divider for SADC decimation filter clock enable fraction divider for SADC system clock no fractional divider supported for this clock no fractional divider supported for this clock no fractional divider supported for this clock no fractional divider supported for this clock no fractional divider supported for this clock (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C 0x0240 0x0244 0x0248 0x024C 0x0250 0x0254 0x0258 0x025C 0x0260 0x0264 0x0268 0x026C 0x0270 0x0274 0x0278 0x027C 0x0280 0x0284 0x0288 0x028C 0x0290 0x0294 0x0298 0x029C 0x02A0 0x02A4 0x02A8 0x02AC 0x02B0 0x02B4 ESR_DCDC_CONVERTER_CLK enable fraction divider for DC-to-DC converter clock SAA8200HL_2 Preliminary data sheet Rev. 02 -- 17 October 2005 19 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key ESR_CR_CLK_OUT1 ESR_CR_CLK_OUT2 ESR_SRI_CHCLK BCR_LP0 BCR_HP0 FDC_SPD_SYSCLK FDC_SYSCLK_DIV4 FDC_UART_UCLK FDC_DEBOUNCE_PCLK FDC_ADC_CLK FDC_DIO_PCLK FDC_AUDIO_PCLK FDC_FRAMESYNCREF FDC_CR_I2SIN_2_BCK FDC_CR_I2SIN_1_BCK FDC_CR_I2SOUT_BCK FDC_I2S_WS FDC_SDAC_NS_CLK FDC_AUDIO_SYSCLK FDC_CR_CLK_OUT1 FDC_CR_CLK_OUT2 FDC_SRI_CHCLK CNF_POWERMODE CNF_WD_BARK reserved reserved OSC_ON OSC_BYPASS CNF_UART_RST_N CNF_I2SIN_1_RST_N CNF_I2SIN_2_RST_N CNF_I2SOUT_1_RST_N CNF_I2SOUT_2_RST_N CNF_DEC_RST_N CNF_INT_RST_N CNF_SPDIF_RST_N CNF_EPICS7B_RST_N CNF_DIO2VPB0_RST_N CNF_DIO2VPB1_RST_N CNF_MS_I2C_RST_N activate crystal oscillator bypass crystal oscillator reset for UART reset for I2S input 1 reset for I2S input 2 reset for I2S output 1 reset for I2S output 2 reset for decimation filter reset for interpolation filter reset for SPDIF reset for EPICS7B reset for VPB0 bridge reset for UART VPB bridge reset for M/S I2C-bus (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset 0x02B8 0x02BC 0x02C0 0x02C4 0x02C8 0x2CC 0x2D0 0x02D4 0x02D8 0x02DC 0x02E0 0x02E4 0x02E8 0x02EC 0x02F0 0x2F4 0x02F8 0x02FC 0x300 0x0304 0x0308 0x030C 0x0310 0x0C00 0x0C04 0x0C08 0xC0C 0x0C10 0x0C14 0x0C18 0x0C1C 0x0C20 0x0C24 0x0C28 0x0C2C 0x0C30 0x0C34 0xC38 0x0C3C 0x0C40 0x0C44 SAA8200HL_2 Description enable fraction divider for crystal output 1 from pad enable fraction divider for crystal output 2 from pad enable fraction divider for SRI channel clock base control register for system PLL clock base control register for audio PLL clock fractional divider control for system clock fractional divider control for 0.25 x fs system clock fractional divider control for UART clock fractional divider control for DEBOUNCE bus clock fractional divider control for control ADC system clock fractional divider control for DIO interface clock fractional divider control for audio bus clock fractional divider control for SRI frame sync reference fractional divider control for I2SIN_2 bit clock fractional divider control for I2SIN_1 bit clock fractional divider control for I2SOUT bit clock fractional divider control for I2S word select fractional divider control for SDAC new sample fractional divider control for audio system clock fractional divider control for crystal output 1 from pad fractional divider control for crystal output 2 from pad fractional divider control for SRI channel clock power-down CGU watchdog bark register FDC_DCDC_CONVERTER_CLK fractional divider control for DC-to-DC converter clock Preliminary data sheet Rev. 02 -- 17 October 2005 20 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key CNF_SRI _RST_N CNF_RSC_RST_N CNF_SRI_I2C_RST_N CNF_AD10BIT_RST_N CNF_FSL_RST_N CNF_GCC_RST_N CNF_AD10BIT_PRST_N HP0_FIN_SELECT HP0_MDEC HP0_NDEC HP0_PDEC HP0_MODE HP0_STATUS HP0_ACK HP0_REQ HP0_INSELR HP0_INSELI HP0_INSELP HP0_SELR HP0_SELI HP0_SELP LP0_FIN_SELECT LP0_PWD LP0_BYPASS LP0_LOCK LP0_DIRECT LP0_MSEL LP0_PSEL RX TX STS CTL CLKHI CLKLO ADDR TXS ADC_R0 ADC_R1 ADC_R2 Description reset for serial radio interface reset for Reed-Solomon codec reset for SRI I2C-bus reset for control ADC reset for frame sync lock reset for gated channel clock preset for control ADC audio clock PLL input select audio clock PLL M divider audio clock PLL N divider audio clock PLL P divider audio clock PLL mode audio clock PLL status audio clock PLL acknowledge audio clock PLL change request audio clock PLL input bandwidth selection audio clock PLL input bandwidth selection audio clock PLL input bandwidth selection audio clock PLL input bandwidth selection audio clock PLL input bandwidth selection audio clock PLL input bandwidth selection system clock PLL input select system clock PLL power-down system clock PLL bypass system clock PLL in-lock system clock PLL direct CCO control system clock PLL M divider system clock PLL P divider SRI I2C-bus 0x0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0028 receive FIFO transmit FIFO status register control register clock divisor high clock divisor low I2C-bus address slave transmit FIFO control ADC 0x0000 0x0004 0x0008 ADC data channel 0 ADC data channel 1 ADC data channel 2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset 0x0C48 0x0C4C 0x0C50 0x0C54 0x0C58 0x0C5C 0x0C60 0x0C64 0x0C68 0x0C6C 0x0C70 0x0C74 0x0C78 0x0C7C 0x0C80 0x0C84 0x0C88 0x0C8C 0x0C90 0x0C94 0x0C98 0x0C9C 0x0CA0 0x0CA4 0x0CA8 0x0CAC 0x0CB0 0x0CB4 0x1000 0x2000 SAA8200HL_2 Preliminary data sheet Rev. 02 -- 17 October 2005 21 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key ADC_R3 ADC_R4 ADC_R5 ADC_R6 ADC_R7 ADC_CON ADC_CSEL_RES ADC_INT_ENABLE ADC_INT_STATUS ADC_INT_CLEAR IR TCR_REG TC PR_REG PC MCR MR0 MR1 EMR DTR_GP_13_IRQ DTR_GP_12_IRQ DTR_GP_11_IRQ DTR_GP_10_IRQ DTR_GP_9_IRQ DTR_GP_8_IRQ DTR_GP_7_IRQ DTR_GP_6_IRQ DTR_GP_5_IRQ DTR_GP_4_IRQ DTR_GP_3_IRQ DTR_GP_2_IRQ DTR_GP_1_IRQ DTR_GP_0_IRQ PEND INT_CLR INT_SET IOC_PINS IOC_MODE0 Description ADC data channel 3 ADC data channel 4 ADC data channel 5 ADC data channel 6 ADC data channel 7 control register channel and resolution selection register interrupt enable register interrupt status register interrupt clear register watchdog timer 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x003C interrupt register timer control register timer counter pre-scale register pre-scale counter match control register match register 0 match register 1 external match register event router 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0820 0x0824 0x0828 0x082C 0x0830 0x0834 0x0838 0x0C00 0x0C20 0x0C40 de-bounce time register for GP_13_IRQ de-bounce time register for GP_12_IRQ de-bounce time register for GP_11_IRQ de-bounce time register for GP_10_IRQ de-bounce time register for GP_9_IRQ de-bounce time register for GP_8_IRQ de-bounce time register for GP_7_IRQ de-bounce time register for GP_6_IRQ de-bounce time register for GP_5_IRQ de-bounce time register for GP_4_IRQ de-bounce time register for GP_3_IRQ de-bounce time register for GP_2_IRQ de-bounce time register for GP_1_IRQ de-bounce time register for GP_0_IRQ input event pending status interrupt clear interrupt set input/output configuration 0x0000 0x0010 read pin values load mode 0 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Base address Offset 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x3000 0x4000 0x6000 SAA8200HL_2 Preliminary data sheet Rev. 02 -- 17 October 2005 22 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 11: VPB0 bridge interface description ...continued Key IOC_MODE0_SET IOC_MODE0_RESET IOC_MODE1 IOC_MODE1_SET IOC_MODE1_RESET I2S_FORMAT_SETTINGS I2S_MUX_SETTINGS SPDIF_STATUS SPDIF_IRQ_EN SPDIF_IRQ_STATUS SPDIF_IRQ_CLEAR SDAC_CTRL_INTI SDAC_CTRL_INTO SDAC_SETTINGS SADC_CTRL_SDC SADC_CTRL_ADC SADC_CTRL_DECI SADC_CTRL_DECO E7B_IRQ PD_ADC10B SET_DCDC1V8_ADJUST SET_DCDC3V3_ADJUST DCDC_CLOCKSTABLE Description set mode 0 reset mode 0 load mode 1 set mode 1 reset mode 1 audio configuration 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 I2S-bus format settings I2S-bus multiplexer settings SPDIF status SPDIF interrupt enable SPDIF interrupt status SPDIF interrupt clear audio DAC input interpolation filter control audio DAC output interpolation filter control audio DAC control audio ADC amplifiers control audio ADC control audio ADC input decimation filter control audio ADC output decimation filter control EPICS7B interrupt request power-down control ADC DC-to-DC converter adjust output voltage (1.8 V) DC-to-DC converter adjust output voltage (3.3 V) DC-to-DC converter clock stable signal 0x0014 0x0018 0x0020 0x0024 0x0028 Base address Offset 0x7000 7.3 Clock generation unit The Clock Generation Unit (CGU) generates all clock signals required for the SAA8200HL, it contains: * A crystal oscillator * For low power mode the internal DC-to-DC converter clock can be used as system clock * * * * * An audio PLL to generate audio sample frequencies A system PLL to generate the clocks for the VPB bus and the DSP subsystem A clock switch block A configuration register block A reset and power block. An 11.2896 MHz oscillator or an external 11.025 MHz clock (provided by the TEA7000) can be used in combination with the two PLLs and the external clocks to generate the system frequencies. All PLLs are programmed with the registers in the register configuration block. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 23 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.3.1 Crystal oscillator The crystal oscillator is a 50 MHz Pierce crystal oscillator with amplitude control. It can be used in many applications e.g. as a digital reference for digital circuits, A/D and D/A clocking, etc. It is a robust design and can be used across a large frequency range. Features: * * * * * * On-chip biasing resistance Amplitude controlled Large frequency range: 1 MHz to 20 MHz Slave mode Power-down mode Bypass test mode. 7.3.2 Audio PLL The audio PLL is a multi purpose PLL. Features: * Integrated PLL with on-chip Current Controlled Oscillator (CCO), no external components for clock generation * * * * * * * * * * * * * * * Input frequency range: 100 kHz to 150 MHz CCO output frequency: 275 MHz to 550 MHz Output frequency range: 4.3 MHz to 550 MHz Programmable pre-divider, feedback-divider and post-divider On the fly adjustment of the clock possible Positive edge locking Frequency limiter to avoid hang-up of the PLL Lock detector Power-down mode Possibility to bypass whole PLL, the post-divider or the pre-divider Possibility to disable the output clock Skew mode Free running mode Scan mode Maximum peak cycle-to-cycle output jitter = 200 ps. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 24 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.3.3 System PLL The DSP-PLL works in normal operating mode with feedback-divider and with post-divider, this means that the base for the clock signal is the current controlled oscillator (fout = fcco/P), running on 264.6 MHz. The output clock (fout) is divided-by-2 to generate a 132.3 MHz clock. Features: * Integrated PLL with on-chip Current Controlled Oscillator (CCO), no external components for clock generation * * * * * * * * * Functional down to 1.2 V (with reduced frequency range) 10 MHz to 25 MHz input frequency range 9.75 MHz to 160 MHz selectable output frequency with 50 % output duty cycle 156 MHz to 320 MHz CCO frequency range Power-down mode Input clock bypass mode Lock detector available Current consumption maximum 1 mA Maximum peak cycle-to-cycle output jitter = 300 ps. 7.4 Serial radio interface Features: * * * * * * * * Interface between wireless audio baseband processor and wireless audio radio IC Bi-directional 3-wire serial interface Can be locked to audio sample frequencies Enables end-to-end audio clock synchronization Supports master and slave modes Supports continuous and high speed repetitive burst mode Control of the radio IC is handled via a separate I2C-bus interface Designed for minimal interference with the radio chip. 7.5 SRI I2C-bus The I2C-bus master/slave module provides a serial interface that meets the I2C-bus specification and supports all transfer modes from and to the I2C-bus. It supports the following functionality: * It supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL) * It has word (32-bit) access from the CPU side * Interrupt generation on received or sent byte (and some special cases). The purpose of the SRI I2C-bus is to allow the download of program code from an external EEPROM at start-up, configuration and monitoring of the radio IC (TEA7000), and storage/retrieval of application specific parameters in an external data EEPROM. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 25 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.6 System I2C-bus interface A master and slave DMA interface to the EPICS7B sub-system and the means to select one or the other are provided. The I2C-bus master/slave module provides a serial interface that meets the I2C-bus specification and supports all transfer modes from and to the I2C-bus. Features: * * * * Supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL) 32-bit word access from the CPU side Interrupt generation on received or sent byte (and some special cases) Four modes of operation: - master transmitter - master receiver - slave transmitter - slave receiver. 7.7 Control ADC This section describes the multi-channel 10-bit control ADC interface module, a module that connects an ADC to a DSP. The ADC interface module can be used for observing battery voltage. The interface can be divided into two main modules; a 10-bit ADC and an ADC controller. The 10-bit ADC is a 10-bit successive approximation ADC. The ADC controller module is responsible for the communication between the ADC and DSP. Features: * * * * * Four analog input channels, selected by an analog multiplexer Programmable ADC resolution from 2-bit to 10-bit Single ADC scan mode and continuous ADC scan mode Converted digital values are stored in a 2 x 10-bit register Power-down mode. 7.8 Watchdog timer Once the watchdog is enabled, it will monitor the programmed time out period and generates a reset request when the period expires. In normal operation the watchdog is triggered periodically, resetting the watchdog counter and ensuring that no reset is generated. In the event of a software or hardware failure preventing the CPU from triggering the watchdog, the time out will be exceeded and a reset requested from the CGU. The interrupt pin of this watchdog timer is not connected to the interrupt controller. Instead of this, two pins M0 and M1 are used which will generate events. Pins M0 and M1 will generate events when their match register matches the Timer Counter (TC) register. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 26 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband The watchdog timer in the SAA8200HL can be used as follows: * As watchdog, the M1 output is used for generating an event to the CGU, which requests a reset. * As timer, the M0 output is used for generating an event to the event router, which generates an interrupt to the interrupt controller. * As watchdog and as timer, the value of the MCR0 has to be lower than the value of MCR1 (otherwise unwanted resets could be generated by the CGU). 7.9 Reed-Solomon codec The Reed-Solomon codec is an essential part of the baseband IC. It allows redundancy to be added to the transmitted bits so that transmission errors can be corrected at the receiving end. The Reed-Solomon codec will provide some flexibility to the customer to choose packet length. For SBC based applications the Reed-Solomon block length will be such that it contains one or two SBC-encoded audio frames. The Reed-Solomon codec is a hardware block that makes use of a locally attached memory for I/O, work space and temporary storage. The communication between this local RAM and the EPICS7B X-memory space will happen via the external DMA controller. Features: * * * * * 8-bit; 1-byte symbols 256-byte blocks 16 parity bytes No interleaving (for latency reduction) Automatic zero insertion (virtual zero padding). 7.10 Event router This module can be used in low power systems to request power-up or start a clock on an external or internal event. It can also be used to generate interrupts as a result: * Provides bus-controlled routing of input events to multiple outputs for use as interrupts or wake-up signals * Input events can be used either directly or latched (edge detected) as an interrupt source: - Direct interrupts will disappear when the event becomes inactive - Latched interrupts will remain active until they are explicitly cleared. * * * * Interrupt events can be inverted (programmable) Each interrupt can be masked on event level Interrupt event detect status can be read per interrupt type Interrupt detection is fully asynchronous (no active clock required). The event router provides bus control over the interrupt system. The event sources can be defined, their polarity and activation type selected, also each input can be routed to any output(s) at reset. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 27 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Event router connections overview Name SPDIF_IN GP_13_IRQ GP_12_IRQ GP_11_IRQ GP_10_IRQ GP_9_IRQ GP_8_IRQ GP_7_IRQ GP_6_IRQ GP_5_IRQ GP_4_IRQ GP_3_IRQ GP_2_IRQ GP_1_IRQ GP_0_IRQ I2C_SRI_NINTR ADC10B_IRQ FSL_START_IRQ FSL_FAST_IRQ XDMA_I2C_DMARDY XDMA_MPIARDY SRI_TXFIFO_EMPTYLEVEL SRI_RXFIFO_FULLLEVEL SRI_TXFIFO_UNDERRUN SRI_RXFIFO_OVERRUN WDT_NINT WDT_M0 WDT_M1 SRI_ULD_REQ CASCADED_INTERRUPT_0 WATCHDOG_CAP0_INT CGU_WAKEUP CGU wake-up interrupt interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin interrupt from general purpose pin I2C-bus SRI event interrupt Control ADC event interrupt FrameSyncLock (FSL) start of frame FrameSyncLock (FSL) fast interrupt for APLL control block transfer I2C-bus MS ready block transfer I2C-bus MPI ready SRI TXFIFO reached empty level SRI RXFIFO reached full level exception: TXFIFO underrun occurred exception: RXFIFO overrun occurred watchdog timer event interrupt watchdog time match 0 watchdog time match 1 SRI EPICS7B interrupt Description Table 12: Event Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Output 0 1 2 SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 28 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.11 SPDIF inputs One input is provided, this SPDIF input is fed through a bit slicer which is used to re-generate the bitstream signal, allowing for a higher robustness of the link. The SPDIF input hardware consists of a series connection of a bit slicer, which is an analog module, the SPDIF decoder and a SPDIF input block. This SPDIF input block is almost the same as the SPDIF input blocks which are connected to the SPDIF input pads. The only difference between the SPDIF input blocks is that the input format of the SPDIF input block is fixed in hardware to accept only SPD3 format. The SPDIF decoder is running on a dedicated clock, which should lie between 36 MHz and 69 MHz. In this clock domain signal SPD3_BCK is generated, which is treated by the I2S-bus input block as a bit clock. This bit clock is again routed via the CGU to be able to insert the test clock during test mode. The SPDIF input decoder latches it's output data on the negative edge of SPD3_BCK. The I2S-bus input will latch the data on the positive edge of the bit clock. This guarantees reliable data transfer even though the clock is delayed by the path through the CGU. The word select from the SPDIF input decoder is routed to the CGU. This makes it possible to lock the audio PLL to the incoming SPDIF stream. 7.12 I2S-bus The supported audio formats for the control modes are: * * * * * I2S-bus LSB-justified, 16-bit LSB-justified, 18-bit LSB-justified, 20-bit LSB-justified, 24-bit (only for the output interface). The bit clock BCK can be up to 128fs, or in other words the BCK frequency is 128 times the WS frequency or less: fBCK 128fWS. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 29 of 71 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Preliminary data sheet Rev. 02 -- 17 October 2005 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. SAA8200HL_2 Philips Semiconductors WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 MSB I2S-BUS FORMAT WS LEFT 16 BCK 15 2 1 RIGHT 16 15 2 1 DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16-BIT MSB B2 B15 LSB WS LEFT 18 17 16 15 2 1 RIGHT 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18-BIT MSB B2 B3 B4 B17 LSB Ensation Base integrated wireless audio baseband WS LEFT 20 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20-BIT MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 SAA8200HL DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24-BIT MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB 001aab453 30 of 71 The WS edge must coincide with the negative edge of the BCK at all times for proper operation of the digital I/O data interface. Fig 5. Serial interface input and output formats Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.12.1 I2S-bus inputs Two I2S-bus inputs are provided, one of the two has dedicated pins, the second is multiplexed using pin GPIO8 to GPIO10. The I2S-bus inputs can be used in slave and master mode. In slave mode an external I2S-bus source generates the bit clock and in master mode the SAA8200HL generates the bit clock. In slave mode the bit clock arrives on pad I2SIN_x_BCK and is led to the CGU input xt_I2SIN_x_BCK. This input should be switched directly to the CGU output I2SIN_x_BCK which delivers the bit clock for the I2S-bus blocks. In slave mode the audio PLL needs to lock on the incoming source. This can best be done on the bit clock or on the word select. The bit clock is the preferred source because of its higher frequency. The audio PLL has problems with locking on frequencies below 100 kHz. If the ratio between the bit clock and the sample frequency is not known, the source word select can be used. The digital audio source will put out the data and the word select on the negative edge of the bit clock and these will be sampled by the I2S-bus block on the positive edge of the bit clock. 7.12.2 I2S-bus outputs Two I2S-bus outputs are provided, both have dedicated data pins but the word select and bit clock for both outputs are shared. Depending on the application the source of the audio PLL could have an other input, then the fractional dividers should be programmed to account for the difference in clock frequency. The I2S_OUT can only be used in master mode. For this reason the output enable of the I2S_OUT_WS and I2S_OUT_BCK pads is always active in functional mode. The bit clock generated by the CGU is inverted with respect to the word select, such that word select changes on a negative edge of the bit clock. 7.13 Time stamp counters A time stamp counter has been included to allow the software to get an indication of the audio clocks. The time stamp counter output is hardwired to seven EPICS7B input registers. Each input register will be latched by another strobe signal. These strobe signals are generated by the audio interfaces I2SIN, SPDIF, ADC, I2SOUT and DAC. This way each sample of each audio source and sink can be labeled with a time stamp. The time stamp increases by one every DSP clock tick, and will wrap-round at value (224 - 1). SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 31 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.14 DMA controller The purpose of the external DMA controller block is to share the external DMA channel of the EPICS7B DSP sub system between a number of external peripherals: the serial radio interface, the Reed-Solomon codec, the I2C-bus M/S and MPI. The controller needs to arbitrate between those blocks. Features: * Interface between external DMA hardware blocks and the EPICS7B DSP subsystem * Allows hardware blocks to read/write directly to X-, Y-, P-memory and to internal DSP registers. * Supports single word memory access and memory block transfers of programmable length. * Signals block transfer ready per requesting hardware device * Arbiter priority schedule between four requesting sources (SRI, I2C-bus M/S, RSC and MPI). * Each requesting hardware block has its own start address and block transfer size register * Dispatches acknowledges and keeps track of progress of each block transfer * Signals block transfer ready per requesting hardware device. 7.15 I/O configuration The input/output configuration (IOCONF) is designed to provide developers a set of registers. This can be used for configuration of various on chip components especially a pad multiplexer. The IOCONF block is used to provide individual control and visibility for a set of pads. In conjunction with a set of pad multiplexers, individual pads can be switched either in normal operation mode, or in GPIO mode. In GPIO mode, a pad is fully controllable. Through the IOCONF, individual pad levels can be observed in both normal and GPIO modes. Functional pads can be grouped into function blocks. All output values in a function block can be set simultaneously by accessing a single register. Changing modes for all pads within a function block requires at most two register access. All input values in a function block can be read simultaneously by accessing a single register. Input values are not registered and always read directly from the pad's input driver regardless of the mode of the pad. For each function block there are two registers holding the control mode. MODE bit 1 leaves the IOCONF inverted as it is intended to be used as inverted (output-) enable. Each register can be written and read, has configurable pad names per bit (maximum 32) and provides set and clear access methods (SET/CLEAR bit when `1'), and configurable reset value. Configurable pad names are provided in order to enhance readability and consistency of both HDL and generated C header file. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 32 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Mode settings Pin multiplexer mode GPIO; high-impedance normal operation; controlled by subsystem GPIO drive LOW GPIO drive HIGH Table 13: MODE[1:0] 00 01 10 11 7.16 VPB1 bridge This section describes the interfaces and function of the VPB1 bridge. The VPB1 bridge acts as a bridge between the UART and the EPICS7B DIO interface. Two bridges are used; one to connect to several slow blocks and an additional one specifically for the universal synchronous receiver transmitter, which is commonly used to implement a serial interface. In any case where a device needs a low overhead, standard, low performance interface, a UART can be used. The UART includes advanced features like a fractional clock divider. Table 14: 0x0000 0x0000 0x0000 0x0004 0x0008 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0000 0x0004 0x0028 UART_RBR UART_THR UART_IER UART_IIR UART_FCR UART_LCR UART_MCR UART_LSR UART_MSR UART_SCR UART_DLL UART_DLM UART_FDR VPB1 bridge interface description Key Description UART receive FIFO transmit FIFO interrupt enable register interrupt ID register FIFO control register line control register modem control register line status register modem status register scratch pad register divisor latch LSB divisor latch MSB fractional divider register Base address Offset 7.17 UART configuration The UART interface is used to be implemented as a serial interface to, for example a modem and is compatible with the industry standards 16650 UARTs. No full modem interface is included, only the CTS and RTS modem signals are available. The UART interface can also be configured as an IrDA (InfraRed Digital Association) SIR (Serial InfraRed) interface, which has a pulse and polarity compliancy with the IrDA Version 1.0 Physical Layer Specification. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 33 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.18 Audio configuration The audio configuration block gives access to the following system settings: * * * * * * * * * I2S-bus input/output format settings Status of SPDIF module SPDIF interrupt request SDAC control and status registers SADC control and status registers Interrupt request to EPICS7B; with automatically clearing register Power-down of the multi-channel 10-bit control ADC DC-to-DC converter output voltage settings DC-to-DC clock-stable indicator. 7.19 Audio input 7.19.1 ADC analog front-end The analog front-end of the ADC consists of one stereo ADC with a selector in front of it. Using this selector one can either select the microphone input with the microphone amplifier (LNA) with a fixed 30 dB gain or the line input. The microphone input as well as the line inputs have a Programmable Gain Amplifier (PGA) that allows gain control from 0 dB to 24 dB in steps of 3 dB. The input impedance of the PGA (line in) is 12 k, for the LNA this is 5 k. 7.19.1.1 Applications and Power-down modes The following Power-down and functional modes are supported: * Power-down mode in which the current consumption is very low (only leakage currents). In this mode there is no reference voltage at the line input. * Line-in mode, in which the PGA can be used. * Microphone mode in which the rest of the non-used PGAs and ADCs are powered down. In this mode the mono microphone signal can be sent to both left and right input of the decimation filter. This is done with a separate multiplexer in front of the decimation input. This multiplexer is controlled by bit SEL_MIC in the I2C-bus control interface. * Mixed PGA and LNA mode with one line-in and one microphone input. mic LNA PGA SDC ADC left_out left PGA SDC ADC right PGA SDC right_out 001aab455 Fig 6. Analog front-end SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 34 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.19.1.2 LNA LNA, a Low Noise microphone Amplifier with nominal gain of 30 dB. 7.19.1.3 PGA The input signal is amplified with a gain set by control bits CTRL[3:0]. The resulting signal will be available at Vout. If control bit CTRL3 = 1 the gain is set to 24 dB independent of the other bits. If CTRL3 = 0 the gain is set for other (lower) settings. The PGA is based on an inverting amplifier architecture. The feedback resistance exists of a resistor string. By switching between different resistors with the use of a 4-bit digital decoder the gain of the amplifier can be modified. The gain can be set in steps of 3 dB from 0 dB up to 24 dB (see Table 15). The PGA is designed to handle a nominal 1 V (RMS) input level. A systematic gain of -1.94 dB is added to accommodate the 800 mV (RMS) input level of a single-to-differential converter that is normally connected to the PGA output. The power-down signal is controlled by the digital core of the SAA8200HL. Table 15: CTRL3 0 0 0 0 0 0 0 0 1 PGA gain settings CTRL2 0 0 0 0 1 1 1 1 X CTRL1 0 0 1 1 0 0 1 1 X CTRL0 0 1 0 1 0 1 0 1 X Gain 0 dB 3 dB 6 dB 9 dB 12 dB 15 dB 18 dB 21 dB 24 dB 7.19.1.4 Applications with 2 V (RMS) input For the Line-in mode it is preferable to have 0 dB and 6 dB gain setting in order to be able to apply both 1 V (RMS) and 2 V (RMS) (using series resistance). For this purpose a PGA is used which has 0 dB to 24 dB gain with 3 dB steps. external resistor 12 k 12 k PGA input signal 001aab456 Input signal is 2 V (RMS); VDD = 3 V. Fig 7. ADC front-end with PGA (line-in input) In applications in which a 2 V (RMS) input signal is used, a 12 k resistor must be used in series with the input of the ADC. This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the SAA8200HL. Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch must be set to 6 dB. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 35 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 16; the power supply voltage is assumed to be 3 V. Table 16: Present Present Absent Absent Application modes using input gain stage input gain switch 0 dB 6 dB 0 dB 6 dB maximum input voltage 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS) Resistor 12 k 7.19.1.5 SDC The Single-to-Differential Converter (SDC) consists of an inverting amplifier and a filter network. The input is DC coupled, which means that decoupling must be done in front of this module in case the input signal has a different common mode level than the SDC. For optional biasing conditions, the SDC requires a sourcing bias current (into an NMOS transistor) that is preferably proportional to the analog supply voltage. 7.19.2 Decimation filter (ADC) The decimation from 128fs is performed in two stages (see Figure 8). The first stage realizes sin(x)/x characteristics with decimation factor of 16. The second stage consists of three half-band filters, each decimating by a factor of 2. The filter characteristics are shown in Table 17. Table 17: Filter characteristics Conditions up to 0.45fs from 0.55fs DC up to 0.45fs at 0.45fs Value 0.02 -60 3 140 -0.18 none 0 at 0.00045fs up to 0.45fs 0.5 > 40 > 110 none 0 at 0.00045fs up to 0.45fs 0.031 > 40 > 110 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Description Decimation filter Pass band ripple Stop band Overall gain Dynamic range Droop DC blocking filter 1 Pass band ripple Pass band gain Droop DC attenuation Dynamic range DC blocking filter 2 Pass band ripple Pass band gain Droop DC attenuation Dynamic range SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 36 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Filter characteristics ...continued Conditions up to 0.4535fs from 0.5465fs pass band up to 0.4535fs Value 0.02 -72 -1.1 >143 Unit dB dB dB dB Table 17: Description Interpolation filter pass band ripple stop band gain dynamic range 128fs COMB 8fs DC HPF1 8fs VOL. CTRL 8fs HB3 4fs HB2 2fs HB1 1fs DC HPF2 1fs sound features halfband DSP 001aab457 Fig 8. Decimator data path 7.19.2.1 Volume control The decimator is equipped with a digital volume control. This volume control is separate for left and right and can be set via the SADC_CTRL_DECI register. The range is from +24 dB down to -63 dB and mute in steps of 0.5 dB. 7.19.2.2 DC blocking filter Two optional 1st order Infinite Impulse Response (IIR) high-pass filters are provided to remove unwanted DC components from the input (DC offset, DC dither) and/or volume control output to avoid clipping when using large gain settings. These filters may be bypassed by setting bits EN_DCFILTI (SADC_CTRL_DECI[20]) and/or EN_DCFILTO (SADC_CTRL_DECI[19]) to a logic 0, which is necessary when fast settling of the decimator is required. On recovery from power-down or after a reset, the parallel output data on bits dout_l[23:0] and DOUT_R[23:0] is held at logic 0 until valid data is available from the decimation filter. This time depends on which of the DC-blocking filters is selected and if the ENABLE bit of the delay timer is ON (EN_DELAY_DBLIN = SADC_CTRL_DECI[21]): * EN_DELAY_DBLIN OFF: t=0s * DC filter 1 is off, DC filter 2 is off and EN_DELAY_DBLIN is on: t = 44/fs; t = 1 ms at fs = 44.1 kHz * DC filter 1 is ON, DC filter 2 is OFF and EN_DELAY_DBLIN is ON: t = 17066/fs; t = 387 ms at fs = 44.1 kHz * DC filter 2 is ON and EN_DELAY_DBLIN is ON: t = 67473/fs; t = 1.53 s at fs = 44.1 kHz. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 37 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.19.2.3 Soft start-up after reset After a reset of the decimation filter and if bit EN_DBLIN (SADC_CTRL_DECI[21]) is a logic 1, the output gain of the decimator is increased from mute to -63.5 dB and at a rate of 0.5 dB per fs period to 0 dB (dB linear) to avoid harsh audible plops. The time required for a complete soft start-up if bit EN_DBLIN is a logic 1 for 128 fs periods. This time is without the time required if bit EN_DELAY_DBLIN (SADC_CTRL_DECI[21]) is a logic 1, e.g. if bit EN_DBLIN and bit EN_DELAY_DBLIN are a logic 1, bit EN_DCFILTI and bit EN_DCFILTO are logic 0 the total time required is (44 +128) fs periods (see Table 18). The decimator soft start-up function is illustrated in Figure 9. Table 18: 0 0 1 1 1 1 1 1 Required time after reset EN_DCFILTI X X 0 1 X 0 1 X EN_DCFILTO X X 0 0 1 0 0 1 Required time 0s 128 periods of fs 44 periods of fs 17066 periods of fs 67473 periods of fs (44 + 128) periods of fs (17066 + 128) periods of fs (67473 + 128) periods of fs 0 1 0 0 0 1 1 1 EN_DELAY_DBLIN EN_DBLIN 44 periods of fs EN_DCFILTI = 0 EN_DCFILTO = 0 RESET = 0 ENABLE_DBLIN = 1 ABLE_DELAY_DBLIN = 1 128 periods of fs DOUT (analog representation) 001aab463 For readability, the parallel output data is shown in its analog representation. Fig 9. Soft start-up function 7.19.2.4 Signal polarity The polarity of the output signal is controlled by bit EN_POL_INV (SADC_CTRL_DECI[17]). When this bit is enabled, the polarity of the output data is inverted. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 38 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.19.2.5 Mute When the left and right channel of the decimator are muted (bit EN_MUTE is a logic 1), the gain in the decimator is decreased linearly to -63.5 dB with a final step to mute at a rate of 0.5 dB per fs period (dB linear). This is done to avoid harsh audible plops. The time required for a complete mute depends on the initial gain setting. Maximum required time is 256 fs periods. When a complete mute is achieved for both left and right channels, the bit MUTE_STATE (SADC_CTRL_DECO[0]) is made logic 1. When the channels are de-muted (bit EN_MUTE is a logic 0) the gain of the decimator is increased at the same rate until the programmed gain setting is achieved. 7.19.2.6 Overflow detection The output signal is used to indicate whenever the output data, in either the left or right channel, is larger than -1.16 dB of the maximum possible digital swing. When this condition is detected the overflow bit (SADC_CTRL_DECO[1]) is forced to a logic 1 for at least 512 fs cycles (11.6 ms at fs = 44.1 kHz) allowing even a slow microcontroller to poll this event. This time-out is reset for each infringement. 7.19.2.7 AGC function The decimation filter is equipped with an Automatic Gain Control (AGC) block. This function is intended, when enabled, to keep the output signal at a constant level. The AGC can be used for microphone applications in which the distance to the microphone is not always the same. The AGC can be enabled via the control register (SADC_CTRL_DECI[23]). In this case it bypasses the digital volume control. Other features of the AGC, such as the attack, decay and target level can be set via the same register. The DC filter in front of the decimation filter must be enabled when AGC is in operation, otherwise the output will be disturbed by the DC offset added in the ADC. Table 19: AGC_EN 0 1 Table 20: 0 0 1 1 AGC enable control AGC function disabled, manual gain control via the left/right decimator volume control, (default) enabled, with manual microphone gain settings via PGA AGC target level settings AGC_LEVEL0 0 1 0 1 AGC target level value (dB) -5.5 -8.0 -11.5 -14.0 AGC_LEVEL1 SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 39 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 21: AGC time constant settings 44.1 kHz sampling Attack time (ms) Decay time (ms) 100 100 200 200 200 400 400 400 8 kHz sampling Attack time (ms) 61 88.2 61 88.2 116 61 88.2 116 Decay time (ms) 551 551 1102 1102 1102 2205 2205 2205 AGC_TIME2 AGC_TIME1 AGC_TIME0 AGC setting 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 11 16 11 16 21 11 16 21 7.20 Audio output 7.20.1 SDAC The Stereo Digital-to-Analog Converter (SDAC) is a module with interpolation filters and noise shaper for low frequency applications such as audio and TV-audio. In this section the analog and digital part is described. The digital part consists of an interpolation filter that increases the sample rate from 1fs to 128fs and a third order noise shaper that runs on 128fs or 256fs. The inputs to the SDAC are two 24-bit parallel input words, left and right, and a synchronization signal (DIN_VALID) at fs (fs, the sample rate, is typically 44.1 kHz). The output is a stereo analog signal (VOUT_LINEL and VOUT_LINER). 7.20.1.1 Features of the SDAC * * * * * * 24-bit data path with 16-bit coefficients Full FIR filter implementation for all of the upsampling filter Digital dB-linear volume control in 0.25 dB steps Digital de-emphasis for 32 kHz, 44.1 kHz, 48 kHz and 96 kHz Selection for the 2fs to 8fs upsampling filter characteristics (sharp/slow-roll-off) Support for 2fs and 8fs input signals: - 1fs with full feature support, being de-emphasis, master volume control and soft mute - 2fs input with master volume and mute support: required for double speed mode - 8fs input no features supported. This is intended for DSD support (grabbing data at 8fs from an external DSD unit) * Soft mute with a raised cosine function * Controlled power-down sequence comprising a raised cosine mute function followed by a DC ramp down to zero to avoid audible plops or clicks * Integrated digital silence detection for left and right with selectable silence detection time * Polarity control SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 40 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband * * * * Simple switched resistors architecture Data-weighted averaging technique reducing distortion Large supply voltage range (0.8 V to 3.6 V) Low noise (N > 100 dBA). SAA8200HL VDD VSS VDDA(3V3_DAC) VDAC_REFN VDAC_REFP DIN_L [23:0] SOUND CONTROL INTERPOLATION FILTER AND NOISESHAPER DAC 14 DAC_OUTL 16 HP_OUTL HP 18 HP_OUTC 20 HP_OUTR 15 DAC_OUTR DIN_VALID DIN_R [23:0] DAC 001aab465 Fig 10. Block diagram of the SDAC 7.20.1.2 Functional description The SDAC comprises the following functions: * * * * Sound feature processor Digital upsampling filter Noise shaper DAC. Digital de-emphasis can be set by a 3-bit control bus (bits CTRL_INTI[18:16]) for the range of sample frequencies available (32 kHz, 44.1 kHz, 48 kHz and 96 kHz). The de-emphasis filters are only in the signal path for normal speed mode (data input at 1fs). In the interpolation filter a three stage linear digital volume control is provided with a range from 0 dB to -89 dB and - dB. Down to the attenuation of -50 dB the step size equals 0.25 dB, from -50 dB to -83 dB it equals 3 dB and the last step to -89 dB is one of 6 dB. The attenuation for the left channel is controlled by bits CTRL_INTI[15:8]; the attenuation for the right channel is controlled by bits CTRL_INTI[7:0]. When the left and right channels of the interpolator are muted (bit CTRL_INTI[19] = 1), the gain in the interpolator is decreased to - dB conforming to a raised cosine function to avoid harsh audible plops (soft mute). This mute function is completed after a period of 128 samples in normal mode i.e. 2.9 ms at fs = 44.1 kHz. When a complete mute is achieved for both left and right channels, the bit CTRL_INTO[0] is made a logic 1. The interpolator mute function is illustrated in Figure 11. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 41 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband raised cosine roll-off (128 periods of fs) interpolator 4-bit output data (analog representation) CTRL_INTI [19] (mute) TRL_INTO [0] (mute state) 001aab466 Fig 11. Interpolator mute signals 7.20.1.3 Power-down 640 periods of fs interpolator 4-bit output data (analog representation) CTRL_INTI [25] CTRL_INTO [1] TRL_INTO [0] (mute state) raised cosine roll-off (128 periods of fs) DC ramp down (512 periods of fs) 001aab467 Fig 12. Interpolator power-up and power-down sequence When the interpolator is powered down (bit CTRL_INTI[25] = 1), the gain in the interpolator is decreased to - dB to conform to a raised cosine function. This is followed by a DC ramp down to zero output data (000000h). The slope of this DC ramp can be set by bit CTRL_INTI[24] to either 512 fs periods (default) or 1024 fs periods. The power-up follows the reverse procedure, a DC ramp up to mid scale plus DC dither (2 to [6 + 2] to [10 + 2] to 17) followed by a gain increase to conform to a raised cosine function. Total SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 42 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband time required for a full power-up or power-down equals 128 fs periods (raised cosine function) plus 512 fs periods (DC ramp up/down) making 640 fs periods or 14.5 ms for fs = 44.1 kHz. The power-up and power-down function is illustrated in Figure 12. 7.20.1.4 Silence detection The silence detection circuit counts the number of digital input samples equal to zero. It is enabled by the control bit CTRL_INTI[30]. The number of zero samples before signalling silence detected (bit CTRL_INTO[3] for left channel and bit CTRL_INTO[2] for right channel) can be set by bits CTRL_INTI[29:28]. This feature is not used to control the SDAC, it is simply a feature that can be used in the system. 7.20.1.5 Polarity control The stereo output signal polarity of the C18INT can be changed by setting the CTRL_INTI[26] to logic 1. Note that this single control bit affects both channels. 7.20.1.6 Digital upsampling filter The interpolation from 1fs to 128fs is realized in four stages: * The first stage is a 99-tap half band filter (HB) which increases the sample rate from 1fs to 2fs and has a steep transition band to correct for the missing inherent filter function of the SDAC. * The second stage is a 31-tap FIR filter which increases the data rate from 2fs to 8fs, scales the signal and compensates for the roll-off caused by the sample-and-hold function prior to the noise shaper. For this filter three sets of coefficients can be chosen realizing three different transfer characteristics. * The third stage is a simple hardware linear interpolator (LIN) function that increases the sample rate from 8fs to 16fs and removes the 8fs component in the output spectrum. The main reason for upsampling to 16fs is the fact that the SDAC only has a first order roll-off function. * The fourth and last stage is a sample-and-hold function increasing the sample rate from 16fs to a selectable 128fs or 256fs, depending on the actual input data rate. For input sample rates between 8 kHz and 32 kHz the noise shaper and DAC must run on 256fs instead of the typical 128fs to avoid a significant noise increase in the audible frequency band of 0 kHz to 20 kHz. normal speed 1fs DEEM 2 HB 2fs 8fs 16fs 128fs or 256fs double speed 2fs DSD 8fs VC MT 4 FIR LIN S&H 001aab468 Fig 13. Interpolator data path SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 43 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband The SDAC has three modes of operation which are set by the control input bits CTRL_INTI[21:20]: * Normal 1fs input mode used for input data rates between 8 kHz and 96 kHz using sharp filter roll-off. De-emphasis (DEEM), volume control (VC) and mute (MT) functions are all available in this mode * 2fs input mode which may be used as: - Double speed input when the data rate is between 96 kHz and 200 kHz - A means to get slow roll-off by skipping the first half band filter (HB). In this mode the de-emphasis (DEEM) is not available * 8fs or DSD input mode, in which case the input is obtained form an external DSD block. De-emphasis (DEEM), volume control (VC) and mute (MT) features are unavailable in this mode. 7.20.1.7 Noise shaper The 3rd-order noise shaper operates at either 128fs or 256fs depending on the mode of operation defined by bits CTRL_INTI[23:20]. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved at low frequencies. The noise shaper output is converted into an analog signal using a 4-bit switched resistor digital-to-analog converter. 7.20.1.8 SDAC The 4-bit SDAC is based on a switched resistor architecture which is merely a controlled voltage divider between the positive and negative reference supplies VREF_DACP and VREF_DACN. The 4-bit input data from the noise shaper is first decoded to a 15 level thermometer code controlling the 15 taps of the converter. Added to the decoding is a selectable Data Weighted Averaging (DWA) technique which guarantees that there is no correlation between the input signal and the resistors used for that input signal. After decoding and DWA the buffers connect the resistors to either the VREF_DACP or VREF_DACN. In doing this the reference voltage will be divided depending on the input signal. The result is an analog output voltage with a rail-to-rail maximum output swing. The output impedance of this DAC is approximately 1 k. By applying an external capacitor of 3.3 nF to the line output (VOUTLINEL or VOUT_LINER) a low pass post filter is introduced with a -3 dB roll off at 48 kHz (dimensioned for fs = 44.1 kHz). This will thus reduce the 3rd order noise shaped output spectrum of the DAC to a noise spectrum increasing with 2nd order. The value of this capacitor depends on the actual sample frequency used. 7.20.1.9 Data weighting averaging The SDAC features two DWA algorithms which can be selected independently for the left (bit CTRL_DAC[1]) and right (bit CTRL_DAC[0]) channels. By setting these bits to a logic 0 the uni-directional DWA algorithm is chosen which is best suited for good S/N figures. By setting these bits to a logic 1 the bi-directional DWA algorithm is chosen which is best for low distortion. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 44 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.20.2 Headphone 7.20.2.1 Headphone driver The headphone driver can deliver 22 mW (at 3.0 V power supply) into16 load. The headphone driver does not need external DC decoupling capacitors because it can be DC-coupled with respect to a special headphone output reference voltage. This saves two external capacitors. Changes in the load on the DAC outputs influence the output of the headphone. This is because the headphone inputs are directly connected to the DAC outputs. 7.20.2.2 Headphone Limiter To protect the headphone amplifier from serious damage due to short-circuiting of the outputs (e.g. during the connection of a headphone jack plug) a current limiter is incorporated. The activation of this current limiter is signaled by individual logic clip signals (CLIP_L, CLIP_R and CLIP_C). The level at which the current limiter is activated can be set to four different levels for each amplifier. The current level to which the output stage is limited can be set with the bits SET_LIMITER_L/R/C[1:0] inputs from 80 mA to 140 mA for the left and right channels and from 180 mA to 240 mA for the common channel (see Table 22). The maximum current for the common ground channel is larger (double on average) as this channel must be able to sink and source the left and right channel output currents. When the current through the output stage exceeds the programmed current level, the monitor bit CLIP_L, CLIP_R or CLIP_C is set to a logic 1 and the output stage is shut down. These values are based on the worst case situation of two in-phase full scale input signals of 1.0 V (RMS) and a minimum headphone impedance of 16 . This results in left and right channel peak output currents of 1.41 V / 16 = 88.4 mA and a common ground peak output current of 2 x 88.4 mA = 176.8 mA. The maximum current that is actually flowing in the common ground amplifier is always the sum of the left and right channel maximum currents. Table 22: Output current limiter settings Maximal output current Left and right channel OFF 100 mA (default) 120 mA 140 mA Common channel OFF 200 mA (default) 220 mA 240 mA SET_LIMITER_L[1:0], SET_LIMITER_R[1:0], SET_LIMITER_C[1:0] 00 01 10 11 SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 45 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.21 DC-to-DC converter The SAA8200HL needs two supply voltages, 3.3 V for analog functions and 1.7 V for digital functions. For normal operation one or two batteries of 1.5 V will be used as an energy source, from which the DC-to-DC converter must generate the required voltage levels, see Figure 14. Two inductive DC-to-DC converters will be used when the chip is battery operated. The VDDE pins are externally connected to pin DCDC_OUT3V3, The VDDI pins are connected to pin DCDC_OUT1V8. When the SAA8200HL is supplied from USB, the outputs of the DC-to-DC converters will be overruled by two linear regulators. In that case the supply voltages will be 3.3 V and 1.8 V. This is independent from the USB voltage (4.0 V to 5.5 V) so a reference circuit is needed. VBAT(DCDC) DC DC switching regulator 1 DCDC_OUT3V3 VUSB(DCDC) vin LDO1 vout vin LDO2 vout LINEAR REGULATOR 1 LINEAR REGULATOR 2 vusb_present DC DC VBAT(DCDC) < 1.6 V VDD_ALWAYS DC to DC - controller LOW VOLTAGE BANDGAP RING OSC DELAY POR vref ANALOG DIGITAL switching regulator 2 DCDC_OUT1V8 adjust 12 MHz DIGITAL CORE PLL XOSC 001aac002 Fig 14. DC-to-DC converter block schematic During the start-up sequence the DC-to-DC controller uses the RING OSC to control the switching regulators. After start-up the 12 MHz from the digital core is fed to the DC-to-DC controller. In battery operation mode the output voltage DCDC_OUT1V8 and DCDC_OUT3V3 can be controlled by three adjust bits. Care has to be taken with signal levels (level shifters) and the start-up and shut-down from battery to USB and from USB to battery transitions. A delay circuit uses RING OSC clocks to generate a delay of about 1 ms for the RESET_B pulse. In USB mode the delay can be generated otherwise. The DC-to-DC converter has to operate from a single or from two batteries. This has no consequence for the first DC-to-DC converter, this is always an up converter. In case a single battery is used the second converter is also an up converter but it is a down SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 46 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband converter when two batteries are used. Pin DOWNSEL selects the type of converter and thus how many batteries are connected. If pin DOWNSEL is HIGH the SAA8200HL operates from two batteries and the second DC-to-DC converter is a down converter. If pin DOWNSEL is LOW the SAA8200HL operates from one battery and the second DC-to-DC converter is an up converter, see Figure 15 DCDC_OUT DCDC_OUT VBAT(DCDC) upconverter downconverter 001aac003 Fig 15. Up and down converter topology 7.21.1 Controller The controller consists of an analog and a digital part. The analog part compares the output voltage VOUT[1,2] with a programmable voltage window in eight possible adjust settings. The digital part computes the switching time such that the output voltage stays within this window. In the analog part is one restive divider with a programmable output, see Figure 16. Together with reference voltage Vref the voltage window is defined. The output of the resistive divider is compared to the reference voltage with comparators with added offset. The outputs VTH (voltage too high) and VTL (voltage too low) are based on the comparison. When VTH is asserted means that VIN is higher than the upper limit of the window, indicating to the digital part of the controller that the output voltage must be lowered. When VTL is asserted it indicates that VIN is lower than the lower limit of the window, indicating to the digital part of the controller that the output voltage must be higher. When neither is asserted, VIN is between the lower and upper limit of the window, indicating to the digital part of the controller that the output voltage is in the limits of the window and it does not have to change the output voltage. This is the normal mode of operating and is called continuous mode because the coil continuously carries current. In continuous mode the digital part of the controller generates switching cycles at a fixed frequency. During the first part of such a cycle (t1) switch 1 will be closed and switch 2 will be opened, during the last part of the cycle (t2) switch 2 will be closed and switch 1 will be opened. The length of t1 as a fraction of the cycle time is set such that the required output voltage is generated. When the output voltage runs outside the window this length is updated such that the output voltage falls within the window again. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 VBAT(DCDC) DCDC_SW DCDC_SW DCDC_LX DCDC_LX VSS VSS 47 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband VBAT(DCDC) bias clk VOUT[1,2] DCDC[1,2]_ADJUST[2 comparator VTH[1,2] comparator VTL[1,2] 7x Vss Vref Vss(clean) Fig 16. Analog part of the controller See Figure 17 for a coil current cycle in continuous mode. The average coil current is equal to the average current demanded by the load. The lengths of t1 and t2 are determined by the battery voltage and the output voltage of the DC-to-DC converter. The output voltage is allowed to vary within a certain window. This means that there will be a voltage ripple with a frequency that is largely correlated to the frequency content of the load current. The peak-to-peak amplitude of the ripple will be more or less equal to the window height. There will be ripple at the switching frequency too, this is mainly caused by the fact that the coil current will run through parasitic resistances of the load circuit. IL (A) decoding 001aac004 t (s) t1 t2 t1 t2 t1 001aac005 Fig 17. Coil current cycle in continuous mode SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 48 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband See Figure 18 for a coil current cycle in ramp-up mode. The controller enters this mode when there is an increased demand for energy (voltage falls to below the lower limit). By a one-time increase of t1 the coil current is increased to a higher average. IL (A) t (s) t1 t2 t1 t2 t1 t2 t1 t2 t1 t2 001aac006 Fig 18. Coil current cycle in ramp-up mode See Figure 19 for a coil current cycle in discontinuous mode. In this mode the coil current does not flow continuously. Dependent on energy demand a cycle is generated. So instead of changing the duty cycle as in continuous mode the frequency is changed. This mode is intended for low power operation. During the first phase the battery ramps up the current from zero and during the second phase it is ramped down to zero by the load. The coil current is made to decrease to zero by opening both switches shortly before the current reaches zero. The moment when the switches are to be closed is learned from the behavior of the DC-to-DC converter in continuous mode. IL (A) t (s) t1 t2 t1 t2 001aac007 Fig 19. Coil current cycle in discontinuous mode SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 49 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband The digital part of the controller consists of a state machine that enables the controller to switch modes. A decision to jump to a different state is taken on the basis of the outputs of the analog part. As a result of some of the jumps, the duration of the first phase of the cycle is increased or decreased, see Figure 20. sample VTH DISCONTINUOUS MODE dec. t1 VTH sample VTL CONTINUOUS MODE VTH VTL AND VTH VTL inc. t1 sample RAMP-UP MODE VTL inc. t1 001aac008 The controller will be in discontinuous mode if adjusted DCDC_OUT1V8 VBAT(DCDC). No forward diode from VBAT(DCDC) to DCDC_OUT1V8 allowed. Fig 20. Digital part of the controller 7.21.2 Linear regulators The linear regulators will be implemented as Low Drop voltage Output (LDO) regulators for a fixed output voltage, see Figure 21. One LDO has to handle input signals in the order of 5.0 V so a special construction with thick gate oxide is needed. The other LDO handles an input signal of 3.3 V thus a normal construction with thick gate oxide is sufficient. For the loop stability the choice is made that the dominant pole lies externally. The series resistance of Cext (ESR) gives a zero and degrades the stability and thus limited to a maximum value. For an accurate output voltage a reference voltage is needed. This voltage can be made with a band gap circuit. A fraction of the output voltage is fed back to the operation amplifier. In Stop mode the LDOs should be stable to deliver only small currents. VIN EF self-biased operational amplifier capacitor ON VSS VSS(clean) 001aac009 DCDC_OUT ESR Cext PCB star ground The on terminal is connected to VUSB_PRESENT. Fig 21. Principle of LDO SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 50 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.21.3 Timing specification 7.21.3.1 Play and stop with battery supply A negative edge at pin DCDC_PLAY starts the DC-to-DC converter, see Figure 22. When minimum supply voltages are detected for DCDC_OUT1V8 and DCDC_OUT3V3 by the POR, the signal SUPPLY_OK is made logic 1. After about 1 ms signal RESET_B becomes logic 1. When the supply voltages are correct the voltages to the application control switches rises from VBAT(DCDC) to DCDC_OUT3V3. New negative edges on pin DCDC_PLAY has no influence. When pin DCDC_STOP becomes HIGH the DC-to-DC converter stops and directly the signal SUPPLY_OK becomes a logic 0. VBAT(DCDC), DCDC_OUT3V3 0 DCDC_PLAY DCDC_ON SUPPLY_OK 1 ms RESET_B PLAYDET DCDC_STOP 001aac010 Fig 22. Play and stop with battery supply The reference circuit, ring oscillator and the POR will be fed by VDD(ALWAYS). Signal RESET_B stays at logic 0 for about 1 ms for proper reset. Not shown in Figure 22 is signal CLK_STABLE, showing the moment for the core clock to become available to the DC-to-DC converters. As soon as a stable core clock is detected the DC-to-DC converters will switch to this clock in order to be in-phase with the DAC clock, which will minimize interference into the audio signal. The SAA8200HL is started up when this has happened. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 51 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.21.3.2 Play and stop with USB supply A start-up from the USB supply gives also a RESET_B pulse, see Figure 23. The signal VUSB is shaped by the bonding pad supplies VDDI and VDDE. The disconnection of VUSB(DCDC) generates a stop pulse. 0 VUSB(DCDC) DCDC_O SUPPLY_OK 1 ms RESET_B STOP VUSB_PRESENT USB_DET (internal iwab signal) "VUSB" 001aac011 Fig 23. Play and stop with USB supply SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 52 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 7.21.3.3 Change from battery to USB supply Figure 24 shows the timing diagram with a wireless transceiver changed to USB supply. The USB supply has the priority. When the USB plug is disconnected the device goes to the off state. In Idle mode the supplies DCDC_OUT1V8 and DCDC_OUT3V3 has still to be present, but the LDOs have to deliver only a small current. The total device may not draw more than 500 mA from the USB supply so a quiescent current of the few active circuits has to be less then 100 mA each. VBAT(DCDC) 0 DCDC_ON VUSB(DCDC) supply transients from DCDC to LDO and LDO to off DCDC_OUT3V3 DCDC_OUT1V8 0 SUPPLY_OK RESET_B VUSB_PRESENT USB_DET (internal iwab signal) STOP PLAY PLAYDET "VUSB" DCDC_OUT3V3 and DCDC_OUT1V8 001aac012 Fig 24. Change from battery to USB supply SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 53 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 8. Limiting values Table 23: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDI VDDE VDDA(1V8) VDDA(3V3) VI Parameter core supply voltage (internal) core supply voltage (external) 1.8 V supply voltage 3.3 V supply voltage input voltage normal digital input pins 5 V tolerant digital input pins analog input pins pin XTALH_IN Tamb Tj Tstg Txtal ambient temperature junction temperature storage temperature crystal temperature single battery double battery VUSB(DCDC) USB voltage range Vesd electrostatic discharge voltage [1] [2] Conditions Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -20 -40 -65 0.9 1.8 4.0 Max 2.5 4.6 2.5 4.6 VDDE + 0.5 6.0 VDDA3v3 + 0.5 2.0 +70 +125 +125 150 1.6 3.2 5.5 Unit V V V V V V V V C C C C V V V V V VBAT(DCDC) battery voltage [1] [2] Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor. 9. Thermal characteristics Table 24: Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 54 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 10. Characteristics Table 25: Symbol VDDI VDDE VDDA(1V8_XTALH) VDDA(3V3_SPDIF) VDDA(1V8_ADC) VDDA(3V3_ADC) VDDA(3V3_DAC) VDDA(3V3_HP) VUSB(DCDC) Table 26: Symbol VIH VIL Vhys VOH VOL IOH IOL Isc(H) Isc(L) Supply voltage characteristics Parameter core supply voltage (internal) core supply voltage (external) crystal oscillator supply voltage SPDIF supply voltage audio ADC supply voltage audio ADC supply voltage audio DAC supply voltage headphone supply voltage USB supply voltage 5 V tolerant cells characteristics Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH depends on I/O cell type IOL depends on I/O cell type 10 ns slew rate output; VOH = VDDE - 0.4 V 10 ns slew rate output; VOL = 0.4 V [1] [1] [1] Conditions MPMC pins other Min 1.7 1.7 2.7 1.7 3.0 2.7 1.7 2.7 2.7 2.7 4.0 Typ 1.8 3.3 3.3 1.8 3.3 3.3 1.8 3.3 3.3 3.3 5.0 Max 2.0 3.6 3.6 2.0 3.6 3.6 2.0 3.6 3.6 3.6 5.5 Unit V V V V V V V V V V V VDDA(3V3_ADC10B) control ADC supply voltage Conditions Min 2.0 0.4 VDDE - 0.4 -5 4 - Typ - Max 0.8 0.4 -45 50 Unit V V V V V mA mA mA mA Input circuits Output circuits [1] HIGH-level short circuit current 10 ns slew rate output; VOH = 0 V LOW-level short circuit current 10 ns slew rate output; VOL = VDDE [2] [2] [1] [2] Accounts for 100 mV voltage drop in all supply lines. Allowed for a short time period. Table 27: Symbol VREFN VREFP fsmpl Zi Vi fclk SAA8200HL_2 Control ADC characteristics Parameter negative reference voltage positive reference voltage sampling rate input impedance REFN to REFP input voltage clock frequency Conditions Min VSSA VREFN + 2 400 20 VREFN Typ Max VDDA 1500 39 VREFP 4.5 Unit V kHz k V MHz VREFP - 2 V (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 55 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 27: Symbol N INL DNL EOS EFS tconv Control ADC characteristics ...continued Parameter resolution integral non-linearity differential non-linearity offset error full scale error conversion time Conditions Min 2 -20 -20 Typ (N + 1) cycles Max 10 1 1 +20 +20 Unit bit LSB LSB mV mV Table 28: Symbol Static audio characteristics Parameter negative reference voltage positive reference voltage output voltage output resistance load resistance resistance between VREFP and VREFN reference input voltage common mode output voltage input offset voltage load resistance output current at short circuit left and right center digital silence during power-down [1] [2] [3] Conditions Min 0.7 >75 - Typ VSSA(DAC) VDDA(3V3_DAC) 0.5VDDA(3V3_DAC) 0 1 4 Max 1.3 - Unit V V V V k k k Audio DAC VREFN VREFP VO RO RL RINT Headphone amplifier VHP_COM VO(cm) Voffset RL Isc Audio ADC VADC_REFP positive reference voltage VADC_REFN negative reference voltage VADC_COM RI CI RI Voffset [1] [2] [3] -10 16 80 180 3.5 - 0.5VDDA(3V3_VREFP) VI(ref) 100 200 VDDA(3V3_ADC) 0 0.5VDDA(3V3_ADC) 12 24 5 1 +10 140 240 - V V mV mA mA V V V k pF k mV common mode reference voltage input resistance input capacitance input resistance output offset voltage Low noise amplifier Set headphone amplifier in Power-down mode before setting audio DAC in Power-down mode because the line output is connected to the headphone driver the output of the headphone clips towards its analog supply. Exclusive the input load of the headphone driver which is 10 k. The output of the DAC is already connected with the headphone driver which has an input load of 10 k. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 56 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 29: Dynamic audio characteristics VDDA(3V3) = 3.3 V; fi = 1 kHz at -1 dB; Tamb = 25 C; RL = 100 k; fs = 48 kHz; all voltages measured with respect to ground; unless otherwise specified. Symbol Audio DAC Vo(rms) Vo VO output voltage (RMS value) unbalance between channels output voltage digital silence during power-down (THD+N)/S total harmonic distortion-plus-noise to signal ratio S/N cs Po(rms) signal-to-noise ratio channel separation output power (RMS value) at 0 dBFS digital input; RL = 16 at 0 dB; RL = 16 at 0 dB; RL = 5 k at -60 dB; A-weighted code = 0; A-weighted RL = 16 no decoupling capacitors with decoupling capacitors Audio ADC Vi S/N cs PSRR unbalance between channels signal-to-noise ratio channel separation power supply rejection ratio VDDA(3V3_ADC) VDDA(3V3_REFP) Do digital output level 0 dB setting; Vi(rms) = 1.0 V 3 dB setting; Vi(rms) = 708 mV 6 dB setting; Vi(rms) = 501 mV 9 dB setting; Vi(rms) = 354 mV 12 dB setting; Vi(rms) = 252 mV 15 dB setting; Vi(rms) = 178 mV 18 dB setting; Vi(rms) = 125 mV 21 dB setting; Vi(rms) = 89 mV 24 dB setting; Vi(rms) = 63 mV SAA8200HL_2 Parameter Conditions at 0 dBFS digital input; [1] Min [1] Typ 1 <0.1 Max - Unit V dB V V dB dB dB dB mW dB dB dB dB dB dB dB dB dB 0.5VDDA(3V3_DAC) 0 -80 -40 100 90 35 62 82 35 97 -36 -90 <1 95 110 -52 - - at 0 dB at -60 dB; A-weighted code = 0; A-weighted; bidirectional DWA Headphone amplifier (THD+N)/S total harmonic distortion-plus-noise to signal ratio S/N cs signal-to-noise ratio channel separation Vi = 0 V; A-weighted fripple = 1 kHz; Vripple(p-p) = 30 mV - -2.5 -2.5 -2.5 -2.5 -2.5 -2.5 -2.5 -2.5 -2.5 -55 -65 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 dB dB dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 57 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 29: Dynamic audio characteristics ...continued VDDA(3V3) = 3.3 V; fi = 1 kHz at -1 dB; Tamb = 25 C; RL = 100 k; fs = 48 kHz; all voltages measured with respect to ground; unless otherwise specified. Symbol Parameter Conditions at -1 dBFS 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting at -60 dBFS 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting LNA plus ADC Vi(rms) input voltage (RMS value) at 0 dBFS digital output; RS = 2.2 k Vo = 600 mV at -60 dB; A-weighted Vi = 0 V; A-weighted -75 -25 85 35 mV dB dB dB -35 -34 -32 -30 -28 -26 -23 -20 -20 dB dB dB dB dB dB dB dB dB -85 -87 -88 -88 -87 -85 -83 -80 dB dB dB dB dB dB dB dB Min Typ Max Unit (THD+N)/S total harmonic distortion-plus-noise to signal ratio (THD+N)/S total harmonic distortion-plus-noise to signal ratio S/N [1] [2] [3] signal-to-noise ratio The output voltage of the DAC is proportional to the DAC power supply voltage and the headphone is in Power-down mode. Exclusive the input load of the headphone driver which is 10 k. The output of the DAC is already connected with the headphone driver which has an input load of 10 k. Table 30: Symbol Vbat VUSB VO VO(tol) DC-to-DC converter characteristics Parameter battery voltage USB voltage output voltage output voltage tolerance Conditions single battery double battery Min 0.9 1.8 4.0 3.0 Typ 1.35 2.7 5.0 3.4 Max 1.6 3.2 5.5 3.7 100 Unit V V V V mV DC-to-DC converter for 3.3 V SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 58 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 30: Symbol IO DC-to-DC converter characteristics ...continued Parameter output current Conditions Vbat = 2.4 V; RL = 0.3 Vbat = 2.0 V; RL = 0.3 Min 200 150 Vbat = 2.4 V; IO = 100 mA; RL = 0.3 90 Typ Isu Isw fswitch fclk start-up current switch current switching frequency clock frequency efficiency RP RN ESRC VO VO(tol) IO PMOST switch on resistance NMOST switch on resistance maximum ESRC output voltage output voltage tolerance output current Vbat = 2.4 V; RL = 0.3 Vbat = 2.0 V; RL = 0.3 1.3 100 50 Vbat = 2.4 V; IO = 50 mA; RL = 0.3 92 0.3 0.3 1.85 0.7 2.0 50 200 10 1 12 - V mV mA mA mA mA MHz MHz % DC-to-DC converter for 1.8 V Isu Isw fswitch fclk start-up current switch current switching frequency clock frequency efficiency RP RN ESRC VO VO(tol) IO IIDLE VO VO(tol) IO PMOST switch on resistance NMOST switch on resistance maximum ESRC output voltage output voltage tolerance output current idle current output voltage output voltage tolerance output current VUSB = 5 V unloaded IO = 50 mA VUSB = 5 V unloaded IO = 100 mA 150 50 0.9 0.9 3.5 3.4 1.95 1.85 - 0.7 100 200 100 50 100 V V mV mA A V V mV mA Low-drop-out converter for 3.3 V Low-drop-out converter for 1.8 V SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 59 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 30: Symbol DC-to-DC converter characteristics ...continued Parameter current consumption oscillator output frequency SRI characteristics Parameter Conditions Min Typ Max Unit Conditions Min Typ 12 Max 100 Unit A MHz Ring oscillator IDDA fOSC Table 31: Symbol LVDS buffer Static IDDA IDDA(pd) CL RO VI(det) Dynamic fclk(max) Table 32: Symbol Crystal oscillator Static Ci(XTALH_IN) Ri(XTALH_IN) Pdrive Dynamic fosc cl tsu fBCK Tcy(BCK) oscillator frequency duty cycle start-up time bit clock frequency bit clock cycle time Tcy(s) is sample frequency cycle time 12 50 500 128fs 1 128Tcy(s) supply current power-down supply current load capacitor output voltage as ratio of the digital supply voltage input voltage required for detection maximum clock frequency Timing characteristics Parameter Conditions - 150 0.25 100 - 1 5 1 A A pF mV MHz Min Typ Max Unit parasitic input capacitance pin XTALH_IN parasitic input resistance pin XTALH_IN crystal level of driver power fi = 12 MHz pF W MHz % ms Hz s Serial interface input and output data timing; see Figure 25 tBCKH tBCKL tr tf tsu(WS) th(WS) tsu(I2SIN) th(I2SIN) SAA8200HL_2 bit clock HIGH time bit clock LOW time rise time fall time word select setup time word select hold time data input setup time data input hold time Rev. 02 -- 17 October 2005 30 30 10 10 10 10 - 20 20 - ns ns ns ns ns ns ns ns 60 of 71 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband Table 32: Symbol th(I2SOUT) Timing characteristics ...continued Parameter data output hold time data output to bit clock delay data output to word select delay I2C-bus; SDA and SCL lines 0 4.7 4.0 4.0 4.7 4.0 4.7 5.0 250 0 1.3 0.6 0.6 0.6 0.6 1.3 0 100 20 + 0.1Cb 20 + 0.1Cb 0 100 0.9 1000 300 400 300 300 50 400 kHz s s s s s s s ns ns ns kHz s s s s s s s ns ns ns ns pF Conditions Min 0 Typ Max 30 30 Unit ns ns ns td(I2SOUT_BCK) td(I2SOUT_WS) Standard mode 100 kHz mode fSCL tLOW tHIGH tHD;STA tSU;STA tSU;STO tBUF tHD;DAT tSU;DAT tr tf 400 kHz mode fSCL tLOW tHIGH tHD;STA tSU;STA tSU;STO tBUF tHD;DAT tSU;DAT tr tf tSP Cb SCL clock frequency SCL clock LOW period SCL clock HIGH period hold time start condition setup time start condition setup time stop condition bus free time between a stop and start condition data hold time data setup time rise time SDA and SCL fall time SDA and SCL SCL clock frequency SCL clock LOW period SCL clock HIGH period hold time start condition setup time repeated start setup time stop condition bus free time between a stop and start condition data hold time data setup time rise time SDA and SCL fall time SDA and SCL pulse width of spikes capacitive load for each bus line SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 61 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband WS tr t BCKH tf t h(WS) t su(WS) t d(I2SOUT_BCK) BCK t BCKL Tcy(BCK) I2SIN t d(I2SOUT_WS) t h(I2SOUT) t su(I2SIN) t h(I2SIN) I2SOUT 001aab634 Fig 25. Serial interface input data timing Table 33: Filter characteristics Conditions up to 0.45fs from 0.55fs DC up to 0.45fs at 0.45fs Value 0.02 -60 3 140 -0.18 none 0 at 0.00045fs up to 0.45fs 0.5 > 40 > 110 none 0 at 0.00045fs up to 0.45fs up to 0.4535fs from 0.5465fs pass band up to 0.4535fs 0.031 > 40 > 110 0.02 -72 -1.1 >143 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Description Decimation filter Pass band ripple Stop band Overall gain Dynamic range Droop DC blocking filter 1 Pass band ripple Pass band gain Droop DC attenuation Dynamic range DC blocking filter 2 Pass band ripple Pass band gain Droop DC attenuation Dynamic range Interpolation filter pass band ripple stop band gain dynamic range SAA8200HL_2 Preliminary data sheet Rev. 02 -- 17 October 2005 62 of 71 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Preliminary data sheet Rev. 02 -- 17 October 2005 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. SAA8200HL_2 Philips Semiconductors SDA t BUF t LOW tr tf t HD;STA t SP Ensation Base integrated wireless audio baseband SCL P S t HD;STA t HD;DAT t HIGH t SU;DAT t SU;STA Sr t SU;STO P mbc611 SAA8200HL 63 of 71 Fig 26. Timing of the I2C-bus transfer xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Preliminary data sheet Rev. 02 -- 17 October 2005 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. SAA8200HL_2 11. Application information Philips Semiconductors 3.3 V 1.8 V DCDC_OUT1V8 DCDC_OUT3V3 VBAT (DCDC) VBAT DCDC_LX2 59 XTALH_IN XTALH_OUT TX FILTER SRI_INT IIC_SRI_SCL IIC_SRI_SDA 92 91 8 100 1 99 98 95 94 97 96 29 72 73 74 7 84 87 23 24 27 42 41 40 39 56 62 DCDC_LX1 61 VCCD(1V8) VCCA(3V3) 55 SYSTEM PAR EEPROM IIC_MS_SCL 2 IIC_MS_SDA 3 I2SOUT_WS 76 I2SOUT_BCK 77 I2SOUT_2_DATA 78 I2SOUT_1_DATA 79 DAC_OUTL line out 15 DAC_OUTR APP CODE EEPROM I 2 C-bus main system TEA7000 RX FILTER SRI_DATA_N SRI_DATA_P SRI_FSYNC_N SRI_FSYNC_P SRI_GCHCLK_N SRI_GCHCLK_P SPDIF_IN I2SIN_1_DATA I2SIN_1_WS I2SIN_1_BCK I2SIN_2_BCK I2SIN_2_DATA I2SIN_2_WS ADC_INR ADC_INL ADC_MIC_IN ADC10B_GPA3 ADC10B_GPA2 ADC10B_GPA1 ADC10B_GPA0 I 2 S-bus out2 Ensation Base integrated wireless audio baseband I 2 S-bus out1 SPDIF_in I 2 S-bus1 SAA8200 14 I 2 S-bus2 VBAT line in mic in cmd4 cmd3 cmd2 cmd1 4 channel analog in 3.3 V HP_OUTL 16 HP_OUTC 18 HP_OUTR 20 ADC_MIC_LNA 26 ADC_MIC_PGA 25 UART_TXS 83 UART_RXS 82 UART_NCTS 81 UART_NRTS 80 headphone out SAA8200HL UART 001aab384 64 of 71 Fig 27. Ensation Link application diagram Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 12. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X 75 76 51 50 ZE A e E HE wM bp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0 16.25 16.25 15.75 15.75 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Fig 28. Package outline SOT407-1 (LQFP100) SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 65 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 13. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 14. Soldering 14.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 66 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 14.5 Package related soldering information Table 34: Package [1] BGA, LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], [1] Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave Reflow [2] suitable suitable not suitable not suitable [4] HTSSON..T [3], suitable not WQCCN..L [8] recommended [5] [6] not recommended [7] not suitable suitable suitable suitable not suitable PMFP [9], For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 67 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. [3] [4] [5] [6] [7] [8] [9] 15. Additional soldering information 15.1 Lead-free solder Lead-free solder can be used for soldering the TEA7000. 15.2 MSL level MSL level: 16. Revision history Table 35: Revision history Release date 20051017 Data sheet status Preliminary data sheet Change notice Doc. number Supersedes SAA8200HL_1 Document ID SAA8200HL_2 Modifications: * * * Audio ADC supply voltages added (Table 25). Audio DAC RL value revised; VHP_COM value corrected; VADC_COM value added (Table 28). Dynamic audio characteristics revised (Table 29). Objective data sheet 9397 750 13236 - SAA8200HL_1 20041217 SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 68 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 17. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. Trademarks Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of Koninklijke Philips Electronics N.V. Ensation -- is a trademark of Koninklijke Philips Electronics N.V. 19. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 69 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 10 7.1 EPICS7B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1.1 User registers . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 VPB0 bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.1 VPB0 bridge address definitions . . . . . . . . . . 15 7.3 Clock generation unit . . . . . . . . . . . . . . . . . . . 23 7.3.1 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 24 7.3.2 Audio PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 Serial radio interface. . . . . . . . . . . . . . . . . . . . 25 7.5 SRI I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 System I2C-bus interface . . . . . . . . . . . . . . . . 26 7.7 Control ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 26 7.9 Reed-Solomon codec . . . . . . . . . . . . . . . . . . . 27 7.10 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.11 SPDIF inputs. . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.12 I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.12.1 I2S-bus inputs . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.12.2 I2S-bus outputs . . . . . . . . . . . . . . . . . . . . . . . . 31 7.13 Time stamp counters . . . . . . . . . . . . . . . . . . . 31 7.14 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 32 7.15 I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 32 7.16 VPB1 bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.17 UART configuration. . . . . . . . . . . . . . . . . . . . . 33 7.18 Audio configuration . . . . . . . . . . . . . . . . . . . . . 34 7.19 Audio input . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.19.1 ADC analog front-end . . . . . . . . . . . . . . . . . . . 34 7.19.1.1 Applications and Power-down modes . . . . . . . 34 7.19.1.2 LNA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.19.1.3 PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.19.1.4 Applications with 2 V (RMS) input . . . . . . . . . 35 7.19.1.5 SDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19.2 Decimation filter (ADC) . . . . . . . . . . . . . . . . . . 36 7.19.2.1 Volume control . . . . . . . . . . . . . . . . . . . . . . . . 37 7.19.2.2 DC blocking filter. . . . . . . . . . . . . . . . . . . . . . . 37 7.19.2.3 Soft start-up after reset . . . . . . . . . . . . . . . . . 7.19.2.4 Signal polarity. . . . . . . . . . . . . . . . . . . . . . . . . 7.19.2.5 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.19.2.6 Overflow detection . . . . . . . . . . . . . . . . . . . . . 7.19.2.7 AGC function . . . . . . . . . . . . . . . . . . . . . . . . . 7.20 Audio output . . . . . . . . . . . . . . . . . . . . . . . . . . 7.20.1 SDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.20.1.1 Features of the SDAC . . . . . . . . . . . . . . . . . . 7.20.1.2 Functional description . . . . . . . . . . . . . . . . . . 7.20.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 7.20.1.4 Silence detection . . . . . . . . . . . . . . . . . . . . . . 7.20.1.5 Polarity control . . . . . . . . . . . . . . . . . . . . . . . . 7.20.1.6 Digital upsampling filter . . . . . . . . . . . . . . . . . 7.20.1.7 Noise shaper . . . . . . . . . . . . . . . . . . . . . . . . . 7.20.1.8 SDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.20.1.9 Data weighting averaging. . . . . . . . . . . . . . . . 7.20.2 Headphone. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.20.2.1 Headphone driver. . . . . . . . . . . . . . . . . . . . . . 7.20.2.2 Headphone Limiter. . . . . . . . . . . . . . . . . . . . . 7.21 DC-to-DC converter . . . . . . . . . . . . . . . . . . . . 7.21.1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.21.2 Linear regulators . . . . . . . . . . . . . . . . . . . . . . 7.21.3 Timing specification . . . . . . . . . . . . . . . . . . . . 7.21.3.1 Play and stop with battery supply. . . . . . . . . . 7.21.3.2 Play and stop with USB supply . . . . . . . . . . . 7.21.3.3 Change from battery to USB supply. . . . . . . . 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal characteristics . . . . . . . . . . . . . . . . . 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Handling information . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 14.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 14.5 Package related soldering information . . . . . . 15 Additional soldering information . . . . . . . . . . 15.1 Lead-free solder . . . . . . . . . . . . . . . . . . . . . . . 15.2 MSL level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 39 39 39 40 40 40 41 42 43 43 43 44 44 44 45 45 45 46 47 50 51 51 52 53 54 54 55 64 65 66 66 66 66 66 67 67 68 68 68 68 69 69 69 continued >> SAA8200HL_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 02 -- 17 October 2005 70 of 71 Philips Semiconductors SAA8200HL Ensation Base integrated wireless audio baseband 20 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Contact information . . . . . . . . . . . . . . . . . . . . 69 (c) Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 17 October 2005 Document number: SAA8200HL_2 Published in The Netherlands |
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