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Ordering number : EN4845B
Monolithic Digital IC
LB1825
Three-Phase Brushless Motor Driver
Overview
The LB1825 is a three-phase brushless motor driver IC optimal for LBP polygon mirror and magneto-optical disk spindle motor drive.
Package Dimensions
unit: mm 3147A-DIP28H
[LB1825]
Functions and Features
* * * * * * * * * * * * * * Three-phase full-wave current control drive PLL speed control Internal 24-mode clock divisor switching Phase lock detector output FG/Hall FG selection Current limiter circuit 7 V stabilized power supply output pin Reverse torque braking Crystal oscillator circuit Internal/external reference frequency selection Built-in FG amplifier and FG pulse output Forward/reverse rotation switching Low power supply voltage protection circuit Thermal protection circuit
SANYO: DIP28H
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg t < 0.1 s Independent IC With an arbitrarily large heat sink Conditions Ratings 30 2.0 3 20 -20 to +80 -55 to +150 Unit V A W W C C
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83097HA (OT)/N3095HA (OT)/91494TH (OT) No. 4845-1/9
LB1825 Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage Symbol VCC Conditions Ratings 10 to 28 Unit V
Electrical Characteristics at Ta = 25C, VCC = 24 V
Parameter Symbol ICC1 Current drain ICC2 ICC3 Upper transistor (1) Output saturation voltage Upper transistor (2) Lower transistor (1) Lower transistor (2) Output leakage current [Fixed voltage block] Output voltage Output current Load variation Temperature coefficient [Hall input block] Input bias current Common-mode input range Input sensitivity Input offset voltage [Drive block] Dead zone width Output idling voltage Forward gain Reverse gain Accelerate command voltage Decelerate command voltage Forward limiter voltage Reverse limiter voltage [Phase comparator block] Output high level voltage Output low level voltage Output source current Output sink current [Error amplifier block] Input bias current Input offset voltage Output high level voltage Output low level voltage [Lock detector block] Output saturation voltage [FG amplifier block] Input bias current Input offset voltage Output high level voltage Output low level voltage [FG Schmitt block] Input operating level Input hysteresis (high low) Input hysteresis (low high) Hysteresis Output saturation voltage VIS VSHL VSLH VFGS VFG2 (sat) IFG2 = 10 mA FGOUT1 generation signal External clock, braking stopped mode External clock, braking stopped mode 18 160 0 36 36 60 0.4 mVp-p mV mV mV V IB (FG) VIO (FG) VFGH VFGL No external load No external load -10 5.0 2.0 1 +10 A mV V V VLD (sat) ILD = 10 mA 0.4 V IB (ER) VIO (ER) VERH VERL No external load No external load -10 5.5 1.0 1 +10 A mV V V VPDH VPDL IPD+ IPD- No external load No external load 0.4 2.5 VREG - 0.4 0.4 V V mA mA VDZ VID GDF+ GDF- VSTA VSTO VL+ VL- Rf = 1.8 Rf = 1.8 0.45 0.45 0.4 -0.6 6.0 0.5 -0.5 6.3 0.8 0.53 0.53 1.5 0.61 0.61 50 200 6 0.6 -0.4 V V V V mV mV DVH VIOH IB (HA) 1.5 1 4 VCC - 1.8 20 20 A V mV mV VREG IREG VREG VREG IREG = 0 to 20 mA Design target value -2.0 IREG = 20 mA 6.3 20 0.25 7.0 7.8 V mA V mV/C VO (sat)1 VO (sat)2 VO (sat)1 VO (sat)2 IO LEAK Conditions Braking stopped mode FGOUT1 stopped mode External clock, braking stopped mode IO = 1.0 A IO = 1.5 A IO = 1.0 A IO = 1.5 A min typ 35 35 28 1.0 1.25 0.6 0.9 max 47 47 40 1.6 2.1 1.0 1.6 100 Unit mA mA mA V V V V A
Continued on next page. No. 4845-2/9
LB1825
Continued from preceding page.
Parameter [FG switching setting] Single Hall FG operating level Triple Hall FG operating level [Stop mode setting] FGOUT1 low level voltage FGOUT1 low level current [Current limiter] Reference voltage External supply range Offset voltage [Signal block] Internal oscillator frequency External input frequency Low level pin voltage High level pin current [Divisor switching] Input high level voltage Input middle level voltage Input low level voltage [F/R switching] Input high level voltage Input low level voltage High level input current [S/B switching] Input high level voltage Input low level voltage Hysteresis (high low) [Stop detection] SCT1 Count setting SCT2 SCT3 [Undervoltage protection] Operating voltage Hysteresis [Thermal protection] Operating temperature Recovery temperature [Pin leakage currents] LD pin FGOUT2 pin [GND pin-heat sink] Resistance Design target value. 30 ILD (LEAK) Pin voltage = 30 V 10 10 A A TSD TSDR Design target value Design target value 150 180 140 C C VSD DVSD 8.4 0.2 8.8 0.4 9.2 0.6 V V FG mode Triple Hall FG mode Single Hall FG mode 32 8 2 VSBH VSBL DVSB 0.15 0.25 2.4 VREG 1.5 0.35 V V V VFRH VFRL IFRH F/R pin voltage = VREG 2.4 0 VREG 1.5 0.22 V V mA VN1 to 3H VN1 to 3M VN1 to 3L 4.2 2.1 0 VREG 2.9 0.8 V V V fOSC fREF VOSCL IOSCH Crystal oscillator mode External clock mode 1 30 4.0 0.3 4.5 0.5 12 5000 5.0 0.75 MHz Hz V mA VCS VCS (EX) VCSO R = 47 k, Rf = 1.8 R = 47 k 0.51 0.7 25 50 0.58 0.65 3.0 90 V V mV VFG1L IFG1L FGOUT1 pin voltage = 0 V 0.6 0.4 2.4 V mA VFGIH VFGIL FGIN pin voltage FGIN pin voltage VREG - 0.1 0 VREG 0.1 V V Symbol Conditions min typ max Unit
IFG2 (LEAK) Pin voltage = 30 V
No. 4845-3/9
LB1825 Pin Assignment
Pin Functions
Pin No. 1 2 to 7 8 to 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 to 26 27 28 Symbol FC IN1+ to IN3+, IN1- to IN3- OUT1 to OUT3 Rf VREG LD VCC ERROUT ERRIN PD VCS GND FGIN FGOUT1 FGOUT2 S/B N1 to N3 OSC F/R Function Frequency characteristics correction Hall element inputs Outputs Output current detector Stabilized power supply output Phase lock detector output Power supply Error amplifier output Error amplifier input Phase comparator output Current limiter reference voltage generation Ground FG amplifier input FG amplifier output FG/Hall FG output Brake command input Reference frequency divisor switching Crystal oscillator/external clock input Forward/reverse switching Also functions as the Hall FG switching pin. The LB1825 goes to stop mode when pin 21 is set low. This pin is an open-collector output. Braking is applied when pin 23 is set high. The clock divisor is set by the states of pins 24 to 26. On when the phase is locked. This pin is an open-collector output. A capacitor must be inserted between pin 11 and ground. Notes A capacitor must be inserted between pin 1 and ground. Taken as high when IN+ > IN-, and as low otherwise.
Clock Divisor Switching
Pin N1 L L L M M M H H H Pin N2 L M H L M H L M H Divisor (1)*I *II 128 256 512 1024 2048 4096 8192 16384 Pin N3 L M H Divisor (2)*I 5 4 3
Note: I. Total divisor = (divisor (1) x divisor (2)) PLL servo frequency = (crystal oscillator frequency)/(total divisor) II. External clock mode The PLL servo frequency = external input frequency
No. 4845-4/9
LB1825
Figure 1 Pin Circuit for Internal Clock Mode Table 1: External Component Values (reference values)
Crystal (MHz) 3 to 4 4 to 5 5 to 7 7 to 10 C1 (pF) 39 39 39 39 C2 (pF) 82 82 47 27 R (k) 0.82 1.0 1.5 2.0
Use a crystal that has a ratio of at least 1:5 between the fundamental f0 impedance and the 3f0 impedance.
Figure 2 Pin Circuit for External Clock Mode F/R Switching and Phase Selection
F/R IN1 H H L H L L L H H H H L L L IN2 H L L L H H H L L L H H IN3 L L H H H L L L H H H L OUT1 M H H M L L M L L M H H OUT2 H M L L M H L M H H M L OUT3 L L M H H M H H M L L M
Columns OUT1 to OUT3 H: Source L: Sink
No. 4845-5/9
LB1825 Equivalent Circuit Block Diagram
No. 4845-6/9
LB1825 Sample Application Circuit (Polygon Mirror Motor)
No. 4845-7/9
LB1825 Sample Application Circuit (Optical Disk Spindle Motor)
Usage Notes 1. Position detector circuit (Hall element input circuit) The position detection circuit consists of a differential amplifier, and will operate if a differential input of 40 mVp-p (minimum) is provided. However, an input of 100 mVp-p is desirable from the standpoint of noise and other problems. The input DC level must be within the common mode input voltage range (1.5 to (VCC - 1.8) V). 2. Current limiter circuit The output current limiter operates by holding the sink side output transistor in an unsaturated state. The current limit value can be calculated from the following formula. I = VCS/Rf Where: VCS = 0.58 V typical, Rf = The value of the resistor between pin 11 and ground. 3. FG input The following three methods can be used to input the speed signal FG from the motor. * The signal can be input to FGIN through an amplifier. (FG mode) * The Hall input IN1 can be used as the FG input. (single Hall FG mode) This is set up by connecting FGIN to VREG. * The composite signal from the IN1, IN2 and IN3 Hall inputs can be used as the FG input. (triple Hall FG mode) This is set up by connecting FGIN to ground.
No. 4845-8/9
LB1825 4. Reference signal input circuit * Internal clock mode (crystal oscillator) The values of the external components associated with the crystal oscillator must be set up according to the frequency of the oscillator. (See Table 1.) To avoid trouble with the oscillator circuit, confirm the component values used with the oscillator's manufacturer. * External clock mode Use the external circuit shown in Figure 2 to input the clock signal when controlling the motor speed using a reference signal with the same frequency as FG. 5. Start/stop When driving motors such as polygon mirror motors, the motor is normally stopped by turning off motor drive and putting the motor in the free-running state. For this type of motor, set the S/B pin low and attach an external transistor at FGOUT1 as shown in the Sample Application Circuit (Optical Disk Spindle Motor) figure to start and stop the drive. (Motor drive is turned off when FGOUT1 is low.) 6. Start/brake When driving motors such as optical disk spindle motors, stopping is performed by applying some form of braking. In these applications it is necessary for the motor to decelerate briefly and come to a complete stop. See the Sample Application Circuit (Optical Disk Spindle Motor) figure for a sample circuit for this case. (The difference between this circuit and the circuit shown in the Sample Application Circuit (Optical Disk Spindle Motor) figure is the addition of the capacitor C5 to the S/B pin start/brake circuit.) Braking Operation This braking circuit applies full torque reverse rotation braking (in the current limited state) directly after the S/B pin is set low while the motor is turning. After that, the reverse torque is gradually decreased (according to the time constant determined by R4 and C5) at the points where the speed falls below the values listed below. This operation brings the disk to a full stop. f3H = fFG/32 (FG mode) f3H = fFG/8 (Triple Hall FG mode) f3H = fFG/2 (Single Hall FG mode)
f3H: Triple Hall input composite frequency. fFG: The FG frequency when locked
Depending on the size of the disk and the motor torque the following adjustments may be required to improve the disk stopping characteristics. 1. Increase the time constant if the motor continues to rotate in the forward direction after the braking torque has gone to zero. 2. Decrease the time constant if the motor is observed to rotate in the reverse direction due to the braking operation. 3. A value of about 51 k is recommended for R4. In particular, it should be under 100 k.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 4845-9/9

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