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M29W641DH, M29W641DL M29W641DU
64 Mbit (4Mb x16, Uniform Block) 3V Supply Flash Memory
PRODUCT PREVIEW
FEATURES SUMMARY s SUPPLY VOLTAGE - VCC = 2.7V to 3.6V Core Power Supply - VCCQ = 1.8V to 3.6V for Input/Output - VPP =12 V for Fast Program (optional)
s s
Figure 1. Packages
ACCESS TIME: 70, 90, 100 and 120ns PROGRAMMING TIME - 10 s typical - Double Word Program option
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128 UNIFORM, 32-KWord MEMORY BLOCKS PROGRAM/ERASE CONTROLLER - Embedded Program and Erase algorithms ERASE SUSPEND and RESUME MODES - Read and Program another Block during Erase Suspend
TSOP48 (N) 12 x 20mm
s
s
UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming WRITE PROTECT OPTIONS
FBGA
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- M29W641DH: WP Pin for Write Protection of Highest Address Block - M29W641DL: WP Pin for Write Protection of Lowest Address Block - M29W641DU: No Write Protection s TEMPORARY BLOCK UNPROTECTION MODE
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TFBGA63 (ZA) 7 x 11mm
COMMON FLASH INTERFACE EXTENDED MEMORY BLOCK - Extra block used as security block or to store additional information
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LOW POWER CONSUMPTION - Standby and Automatic Standby ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Device Code M29W641D: 22C7h
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April 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. TFGBA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VPP (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCCQ Supply Voltage (1.8V to 3.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 25 Table 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25 Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view package outline 26 Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . 26 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 17. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 18. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 21. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 22. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 24. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 25. Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 16. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 18. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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SUMMARY DESCRIPTION The M29W641D is a 64 Mbit (4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single, low voltage, 2.7V to 3.6V VCC supply for the circuitry and a 1.8V to 3.6V VCCQ supply for the Input/Output pins. An optional 12 V VPP power supply is provided to speed up customer programming. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The highest address block of the M29W641DH or the lowest address block of the M29W641DL can be protected from accidental programming or erasure using the WP pin (if WP = VIL). The M29W641DU does not feature the WP pin. Each block can be erased independently so it is possible to preserve valid data while old data is erased. The blocks can be protected to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The M29W641D has an extra block, the Extended Block, (of 32 KWords) that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in a 48-pin TSOP package (M29W641DL and M29W641DH) or in a 63-ball TFBGA package (M29W641DU). All devices are delivered with all the bits erased (set to 1).
Figure 2. Logic Diagram
VCC
VCCQ
VPP
22 A0-A21 W E G RB RP WP M29W641D
16 DQ0-DQ15
VSS
AI06697b
Table 1. Signal Names
A0-A21 DQ0-DQ7 DQ8DQ15 E G W RP Address Inputs Data Inputs/Outputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect (M29W641DH and M29W641DL only) Ready/Busy Output (M29W641DU only) Write Protect Supply Voltage Supply Voltage for Input/Output Supply Voltage for Fast Program (optional) Ground
RB WP
VCC VCCQ
VPP
VSS
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Figure 3. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
1
48
12 13
M29W641D
37 36
24
25
AI06698
A16 VCCQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
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Figure 4. TFGBA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
NC(1)
NC(1)
NC(1)
NC(1)
B
NC(1)
NC(1)
NC(1)
C
A3
A7
RB
W
A9
A13
D
A4
A17
VPP
RP
A8
A12
E
A2
A6
A18
A21
A10
A14
F
A1
A5
A20
A19
A11
A15
G
A0
DQ0
DQ2
DQ5
DQ7
A16
H
E
DQ8
DQ10
DQ12
DQ14
VCCQ
J
G
DQ9
DQ11
VCC
DQ13
DQ15
K
VSS
DQ1
DQ3
DQ4
DQ6
VSS
L
NC(1)
NC(1)
NC(1)
NC(1)
M
NC(1)
NC(1)
NC(1)
NC(1)
AI06879
Note: 1. Balls are shorted together via the substrate but not connected to the die.
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M29W641DH, M29W641DL, M29W641DU
SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Write Protect (WP). The Write Protect pin is available in the M29W641DH and M29W641DL only. It provides a hardware method of protecting the highest address block for the M29W641DH and the lowest address block for the M29W641DL. The Write Protect pin must not be left floating or unconnected. When Write Protect is Low, VIL , the memory protects either the highest or lowest address block; Program and Erase operations in this block are ignored while Write Protect is Low. When Write Protect is High, VIH, the memory reverts to the previous protection status for this block. Program and Erase operations can now modify the data in this block unless the block is protected using Block Protection. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, V OL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 13 and Figure 12, Reset/Block Temporary Unprotect AC Characteristics. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if Write Protect (WP) is at V IL, then one of the two outermost blocks will remain protected even if RP is at V ID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Table 13 and Figure 12, Reset/Block Temporary Unprotect AC Characteristics, for more details. Holding RP at V ID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. VPP (VPP). When the VPP pin is raised to VPPH the memory automatically enters the Unlock Bypass mode. When the pin is returned to V IH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to V PP and from V PP to VIH must be slower than tVHVPP, see Figure 13. Never raise the pin to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. VCC Supply Voltage (2.7V to 3.6V). VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. VCCQ Supply Voltage (1.8V to 3.6V). VCCQ provides the power supply to the I/O pins and enables all Outputs to be powered independently of VCC.
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VCCQ can be tied to VCC or can use a separate supply. VSS Ground. VSS is the reference for all voltage measurements. The device features two V SS pins which must be both connected to the system ground. Note: Each device in a system should have VCC, VCCQ and VPP decoupled from VSS with a Table 2. Bus Operations
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code E VIL VIL X VIH VIL VIL G VIL VIH VIH X VIL VIL W VIH VIL VIH X VIH VIH Address Inputs A0-A21 Cell Address Command Address X X A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Data Inputs/Outputs DQ15-DQ0 Data Output Data Input Hi-Z Hi-Z 0020h 22C7h 98h (factory locked, WP protects highest address block) 18h (not factory locked, WP protects highest address block) 88h (factory locked, WP protects lowest block) 08h (not factory locked, WP protects lowest block)
0.1F ceramic capacitor close to the pin for current surge protection (high frequency, inherently low inductance capacitors should be as close as possible to the device). See Figure 8, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required V PP program and erase currents. See Table 9, DC Characteristics.
Extended Memory Block Verify Code
VIL
VIL
VIH
A0 = VIH, A1 = VIH, A6 = VIL, A9 = VID, Others VIL or VIH
Note: X = VIL or VIH.
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BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9, Read Mode AC Waveforms, and Table 10, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 10 and Figure 11, Write AC Waveforms, and Table 11 and Table 12, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should
be held within VCC 0.2V. For the Standby current level see Table 9, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 2, Bus Operations. Block Protect and Chip Unprotect. Groups of blocks can be protected against accidental Program or Erase. The whole chip can be unprotected to allow the data inside the blocks to be changed. Write Protect (WP) can be used to protect one of the outermost blocks. When Write Protect (WP) is at V IL one of the two outermost blocks is protected and remains protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status. For the M29W641DH, it is the highest addressed block that can be protected. For the M29W641DL, it is the lowest. Block Protect and Chip Unprotect operations are described in Appendix D.
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COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. See Table 3 for a summary of the commands. Read/Reset Command The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a Block erase operation then the memory will take up to 10s to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. Auto Select Command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Memory Block Verify Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. In Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either V IL or VIH. The Device Code for the M29W641D is 22C7h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = V IL , A1 = V IH, and A12-A21 specifying the address of the block. The other address bits may be set to either V IL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output. Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the de-
vice is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode. See Appendix B, Table 18 to Table 23 for details on the information contained in the Common Flash Interface (CFI) memory area. Program Command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 4. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Fast Program Commands There is a Fast Program command available to improve the programming throughput, by writing several adjacent words or bytes in parallel: the Double Word Program command. Double Word Program Command. The Double Word Program command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command.
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s s s
The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller.
Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Programming should not be attempted when VPP is not at V PPH. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Fast Program commands cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Typical Program times are given in Table 4, Program, Erase Times and Program, Erase Endurance Cycles. Unlock Bypass Command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory enters Unlock Bypass mode. When in this mode the memory can be read as if in Read mode. When V PPH is applied to the VPP pin the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately. Unlock Bypass Program Command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the ad-
dress and data, and starts the Program/Erase Controller. A Program operation initiated by issuing the Unlock Bypass Program command is identical to a Program operation initiated by issuing the Program command. It cannot be aborted and a Bus Read operation will output the Status Register. See the Program Command paragraph for further details. Unlock Bypass Reset Command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/ Reset command does not exit from Unlock Bypass Mode. Chip Erase Command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 4. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost. Block Erase Command The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50s after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50s of
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the lowest address block. The 50s timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 4. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost. Erase Suspend Command The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/ Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. Erase Resume Command The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. Enter Extended Block Command The device has an extra 32 KWord block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus write cycles are required to issue the Extended Block command. Once the command has been issued the device enters Extended Block mode where all Bus Read or Write operations to the Boot Block addresses access the Extended Block. The Extended Block (with the same address as the Boot Blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are not accessible. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected, however once protected the protection cannot be undone. Exit Extended Block Command The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. Block Protect and Chip Unprotect Commands Groups of blocks can be protected against accidental Program or Erase. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in Appendix D.
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Table 3. Commands
Command Length Bus Write Operations 1st Addr X 555 555 555 555 555 X X 555 555 X X 55 555 555 Data F0 AA AA AA 50 AA A0 90 AA AA B0 30 98 AA AA 2AA 2AA 55 55 555 555 88 90 X 00 2AA 2AA 2AA PA0 2AA PA X 2AA 2AA 55 55 55 PD0 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 X 555 555 PA1 555 F0 90 A0 PD1 20 PA PD 2nd Addr Data 3rd Addr Data 4th Addr Data 5th Addr Data 6th Addr Data
1 Read/Reset 3 Auto Select Program Double Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume Read CFI Query Enter Extended Block Exit Extended Block 3 4 3 3 2 2 6 6+ 1 1 1 3 4
Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Chip Erase Block Erase (32 KWords) Erase Suspend Latency Time Program (Word) Double Word Program Chip Program (Word by Word) Chip Program (Double Word) Program/Erase Cycles (per Block) Data Retention
Note: 1. 2. 3. 4.
Min
Typ (1, 2) 80 0.8
Max(2) 400(3) 6(4) 50(4)
Unit s s s s s s s cycles years
10 10 40 20 100,000 20
200(3) 200(3) 200(3) 100(3)
Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VCC.
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STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 5, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling Bit will change from a '0' to a '1' when the Program/Erase Controller has suspended the Erase operation. Figure 5, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 6, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. Before the Program/Erase Controller starts the Erase Timer Bit is set to '0' and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
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Table 5. Status Register Bits
Operation Program Program During Erase Suspend Program Error Chip Erase Address Any Address Any Address Any Address Any Address Erasing Block Block Erase before timeout Non-Erasing Block Erasing Block Block Erase Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address
Note: 1. Only the M29W641DU device is concerned. 2. Unspecified data bits should be ignored.
DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1
DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle
DQ5 0 0 1 0 0 0 0 0 0
DQ3 - - - 1 0 0 1 1 -
DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle
RB(1) 0 0 0 0 0 0 0 0 1 1
Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Toggle
0 0
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Figure 5. Data Polling Flowchart
START
Figure 6. Data Toggle Flowchart
START READ DQ6
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ5 & DQ6
DQ7 = DATA NO NO YES
DQ6 = TOGGLE YES
NO
DQ5 =1 YES
NO
DQ5 =1 YES READ DQ6 TWICE
READ DQ7 at VALID ADDRESS
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLE
PASS
NO
YES FAIL PASS
AI90195B
AI90194
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at Table 6. Absolute Maximum Ratings
Symbol TBIAS TSTG VCCQ VCC VID VPP(3) Temperature Under Bias Storage Temperature Input/Output Supply Voltage (1,2) Supply Voltage Identification Voltage Program Voltage Parameter Min -50 -65 -0.6 -0.6 -0.6 -0.6 Max 125 150 4 4 13.5 13.5 Unit C C V V V V
these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to V CC +2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 7. Operating and AC Measurement Conditions
M29W641D Parameter Min VCC Supply Voltage VCCQ Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 3.0 3.0 -40 30 10 0 to VCCQ VCCQ/2 70 Max 3.6 3.6 85 Min 2.7 2.7 -40 30 10 0 to VCCQ VCCQ/2 90 Max 3.6 3.6 85 Min 3.0 1.65 -40 30 10 0 to VCCQ VCCQ/2 100 Max 3.6 1.95 85 Min 2.7 1.65 -40 30 10 0 to VCCQ VCCQ/2 120 Max 3.6 1.95 85 V V C pF ns V V Unit
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
VPP VCCQ VCC VCCQ
VCCQ VCCQ/2 0V
AI05557b
25k DEVICE UNDER TEST 25k 0.1F 0.1F 0.1F CL
CL includes JIG capacitance
AI05558b
Table 8. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 9. DC Characteristics
Symbol ILI ILO ICC1 ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Test Condition 0V VIN VCCQ 0V VOUT VCCQ E = VIL, G = VIH, f = 6 MHz E = VCC 0.2V, RP = VCC 0.2V VPP pin = VIL or VIH VPP pin = VPPH -0.5 0.7VCCQ 11.5 Min Max 1 1 10 100 20 20 0.8 VCCQ + 0.3 12.5 15 0.45 0.85VCCQ VCCQ - 0.4 11.5 1.8 12.5 2.3 Unit
A A
mA
A
mA mA V V V mA V V V V V
ICC3
Supply Current (Program/ Erase)
Program/Erase Controller active
VIL VIH VPPH IPP VOL VOH (1) VID VLKO (1)
Input Low Voltage Input High Voltage Voltage for VPP Program Acceleration Current for VPP Program Acceleration Output Low Voltage Output High Voltage
VCCQ VCC VCCQ VCC VCC = 3.0V 10% VCC = 3.0V 10% IOL = 4.0mA, VCC = VCCmin IOH = -2.0mA, VCC = VCCmin IOH = -100A, VCC = VCCmin
Identification Voltage Program/Erase Lockout Supply Voltage
Note: 1. Sampled only, not 100% tested.
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Figure 9. Read Mode AC Waveforms
tAVAV A0-A21 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tGHQX tGHQZ VALID tEHQZ tEHQX VALID tAXQX
AI06699
Table 10. Read AC Characteristics
M29W641D Symbol Alt Parameter Test Condition 70 tAVAV tAVQV tELQX (1) tELQV tGLQX (1) tGLQV tEHQZ (1) tGHQZ (1) tEHQX tGHQX tAXQX tRC tACC tLZ tCE tOLZ tOE tHZ tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Min Max Min Max Max Max Min 70 70 0 70 0 30 25 25 0 90 90 90 0 90 0 35 30 30 0 100 100 100 0 100 0 35 30 30 0 120 120 120 0 120 0 50 30 30 0 ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested.
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Figure 10. Write AC Waveforms, Write Enable Controlled
tAVAV A0-A21 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX tWLWH tWHGL tWHEH
VCC tVCHEL RB tWHRL
Note: 1. RB concerns the M29W461DU only.
AI06800b
Table 11. Write AC Characteristics, Write Enable Controlled
M29W641D Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL(1) tVCHEL tOEH tBUSY tVCS Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 70 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 35 45 0 0 30 0 45 0 0 90 50 90 90 0 35 45 0 0 30 0 45 0 0 90 50 100 100 0 35 45 0 0 30 0 45 0 0 90 50 120 120 0 50 50 0 0 30 0 50 0 0 90 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
Note: 1. This timing concerns the M29W461DU only.
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Figure 11. Write AC Waveforms, Chip Enable Controlled
tAVAV A0-A21 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VCC tVCHWL RB tEHRL
AI06801b
Note: 1. RB concerns the M29W461DU only.
Table 12. Write AC Characteristics, Chip Enable Controlled
M29W641D Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL (1) tVCHWL tOEH tBUSY tVCS Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 70 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low Chip Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 45 45 0 0 30 0 45 0 0 90 50 90 90 0 45 45 0 0 30 0 45 0 0 90 50 100 100 0 45 45 0 0 30 0 45 0 0 90 50 120 120 0 50 50 0 0 30 0 50 0 0 90 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
Note: 1. This timing concerns the M29W461DU only.
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Figure 12. Reset/Block Temporary Unprotect AC Waveforms
W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH
AI06802b
Note: 1. RB concerns the M29W461DU only.
Table 13. Reset/Block Temporary Unprotect AC Characteristics
M29W641D Symbol tPHWL (1) tPHEL tPHGL (1) tRHWL (1, 2) tRHEL (1, 2) tRHGL
(1, 2)
Alt
Parameter 70 RP High to Write Enable Low, Chip Enable Low, Output Enable Low 90 100 120
Unit
tRH
Min
50
50
50
50
ns
tRB
RB High to Write Enable Low, Chip Enable Low, Output Enable Low
Min
0
0
0
0
ns
tPLYH tPLPX tPHPHH (1) tVHVPP (1)
tREADY RP Low to Read Mode tRP tVIDR RP Pulse Width RP Rise Time to VID VPP Rise and Fall Time
Max Min Min Min
50 500 500 250
50 500 500 250
50 500 500 250
50 500 500 250
s ns ns ns
Note: 1. Sampled only, not 100% tested. 2. These timings concern the M29W461DU only.
Figure 13. Accelerated Program Timing Waveforms
VPP VPP Pin VIL or VIH tVHVPP
tVHVPP
AI06806
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PACKAGE MECHANICAL Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 e E L alfa N 48 0.500 19.800 18.300 - 11.900 0.500 0 0.100 1.000 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 0.100 20.200 18.500 - 12.100 0.700 5 48 0.0197 0.7795 0.7205 - 0.4685 0.0197 0 0.0039 0.0394 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.7953 0.7283 - 0.4764 0.0276 5 inches
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Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view package outline
D D1 FD SD
e
E
E1
SE
ddd
BALL "A1"
FE A e b A1 A2
BGA-Z33
Note: Drawing is not to scale.
Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 7.000 5.600 - 11.000 8.800 0.800 0.700 1.100 0.400 0.400 0.350 6.900 - - 10.900 - - - - - - 0.250 0.900 0.450 7.100 - 0.100 11.100 - - - - - - 0.2756 0.2205 - 0.4331 0.3465 0.0315 0.0276 0.0433 0.0157 0.0157 0.0138 0.2717 - - 0.4291 - - - - - - Min Max 1.200 0.0098 0.0354 0.0177 0.2795 - 0.0039 0.4370 - - - - - - Typ Min Max 0.0472 inches
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PART NUMBERING Table 16. Ordering Information Scheme
Example: Device Type M29 Operating Voltage W = VCC = 2.7 to 3.6V Device Function 641DH = 64 Mbit (x16), Uniform Block, Write Protection on highest address Block 641DL = 64 Mbit (x16), Uniform Block, Write Protection on Lowest Address Block 641DU = 64 Mbit (x16), Uniform Block, No Write Protection Speed 70 = 70ns 90 = 90ns 10 = 100ns 12 = 120ns Package N = TSOP48: 12 x 20 mm (M29W641DH and M29W641DL only) ZA = TFBGA63: 7 x 11mm, 0.80mm pitch (M29W641DU only) Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing M29W641DL 70 N 1 T
Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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APPENDIX A. BLOCK ADDRESSES Table 17. Block Addresses
Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 KWords 32 32 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 0F0000h-0F7FFFh 0F8000h-0FFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh Protection Group Protection Block Group Address Range 000000h-007FFFh (1) 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh
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Block 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 KWords 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 210000h-217FFFh 218000h-21FFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh Protection Block Group Address Range 100000h-107FFFh 108000h-10FFFFh
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Block 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 KWords 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 330000h-337FFFh 338000h-33FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh Protection Block Group Address Range 220000h-227FFFh 228000h-22FFFFh
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Block 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 KWords 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 32 32 Protection Group 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh Protection Block Group Address Range 340000h-347FFFh 348000h-34FFFFh
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
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APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Table 18 to Table 23 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 23, Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST.
Table 18. Query Structure Overview
Address 10h 1Bh 27h 40h 61h Sub-section Name CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Description Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 19. CFI Query Identification String
Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h Address for Primary Algorithm extended Query table (see Table 22) 0000h 0000h 0000h 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table NA P = 40h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Query Unique ASCII String "QRY" Description Value "Q" "R" "Y" AMD Compatible
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
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Table 20. CFI Query System Interface Information
Address 1Bh Data 0027h Description VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Typical timeout per single word program = 2n s Typical timeout for minimum size write buffer program = 2n s Typical timeout per individual block erase = 2n ms Typical timeout for full chip erase = 2n ms Maximum timeout for word program = 2n times typical Maximum timeout for write buffer program = 2n times typical Maximum timeout per individual block erase = 2n times typical Maximum timeout for chip erase = 2n times typical Value 2.7V
1Ch
0036h
3.6V
1Dh
00B5h
11.5V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C5h 0004h 0000h 000Ah 0000h 0004h 0000h 0003h 0000h
12.5V 16s NA 1s NA 256 s NA 8s NA
Table 21. Device Geometry Definition
Address 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h Data 0017h 0001h 0000h 0000h 0000h 0001h 007Fh 0000h 0000h 0001h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions. It specifies the number of regions containing contiguous Erase Blocks of the same size. Region 1 Information Number of identical size erase block = 007Fh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Value 8 MByte x16 Async. NA 1 128 64 KByte
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Table 22. Primary Algorithm-Specific Extended Query Table
Address 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0030h 0000h Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write Block Protection 00 = not supported, x = number of blocks per protection group Temporary Block Unprotect 00 = not supported, 01 = supported Block Protect /Unprotect 04 = M29W400B Simultaneous Operations, 00 = not supported Burst Mode, 00 = not supported, 01 = supported Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word VPP Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0" Yes
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
0002h 0004h 0001h 0004h 0000h 0000h 0000h 00B5h
2 4 Yes 4 No No No 11.5V
4Eh
00C5h
12.5V
Table 23. Security Code Area
Address 61h 62h 63h 64h Data XXXX XXXX XXXX XXXX 64 bit: unique device number Description
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APPENDIX C. EXTENDED MEMORY BLOCK The M29W641D has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 32 KWords. It is used as a security block (to provide a permanent security identification number) or to store additional information. The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit DQ7. This bit is permanently set to either `1' or `0' at the factory and cannot be changed. When set to `1', it indicates that the device is factory locked and the Extended Block is protected. When set to `0', it indicates that the device is customer lockable and the Extended Block is unprotected. Bit DQ7 being permanently locked to either `1' or `0' is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure must be followed to read it. See "Extended Memory Block Verify Code" in Table 2, Bus Operations, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Enter Extended Block Command and Exit Extended Block Command paragraphs, and to Table 3, "Commands".
Factory Locked Extended Block In devices where the Extended Block is factory locked, the Security Identification Number is written to the Extended Block address space (see Table 24, Extended Block Address and Data) in the factory. The DQ7 bit is set to `1' and the Extended Block cannot be unprotected. Customer Lockable Extended Block A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to `0' and the Extended Block unprotected. It is up to the customer to program and protect the Extended Block but care must be taken because the protection of the Extended Block is not reversible. There are two ways of protecting the Extended Block: s Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique (refer to Appendix D, In-System Technique and to the corresponding flowcharts, Figures 18 and 19, for a detailed explanation of the technique). s Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique (refer to Appendix D, Programmer Technique and to the corresponding flowcharts, Figures 16 and 17, for a detailed explanation of the technique). Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode.
Table 24. Extended Block Address and Data
Device Address(1) x16 000000h-000007h M29W641D 000008h-007FFFh
Note: 1. See Table 17, Block Addresses.
Data Factory Locked Security Identification Number Determined by Customer Unavailable Customer Lockable
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APPENDIX D. BLOCK PROTECTION Block protection can be used to prevent any operation from modifying the data stored in the memory. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Programmer Technique The Programmer technique uses high (V ID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 16, Programmer Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 17, Programmer Equipment Chip Unprotect Flowchart. Table 25, Programmer Technique Bus Operations, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is Table 25. Programmer Technique Bus Operations
Operation Block (Group) Protect(1) Chip Unprotect Block (Group) Protection Verify Block (Group) Unprotection Verify E VIL VID G VID VID W VIL Pulse VIL Pulse Address Inputs A0-A21 A9 = VID, A12-A21 Block Address Others = X A9 = VID, A12 = VIH, A15 = VIH Others = X A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A21 Block Address Others = X A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A21 Block Address Others = X Data Inputs/Outputs DQ15-DQ0 X X Pass = XX01h Retry = XX00h Retry = XX01h Pass = XX00h
specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. In-System Technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 18, In-System Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 19, In-System Equipment Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
VIL
VIL
VIH
VIL
VIL
VIH
Note: 1. Block Protection Groups are shown in Appendix A, Tables 17.
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Figure 16. Programmer Equipment Group Protect Flowchart
START
ADDRESS = GROUP ADDRESS Set-up W = VIH n=0
G, A9 = VID, E = VIL
Wait 4s Protect W = VIL Wait 100s W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Wait 4s G = VIL Wait 60ns Read DATA
Verify
DATA NO = 01h YES A9 = VIH E, G = VIH End PASS ++n = 25 YES A9 = VIH E, G = VIH FAIL
AI05574
NO
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Figure 17. Programmer Equipment Chip Unprotect Flowchart
START PROTECT ALL GROUPS Set-up n=0 CURRENT GROUP = 0
A6, A12, A15 = VIH(1) E, G, A9 = VID
Wait 4s Unprotect W = VIL Wait 10ms W = VIH E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1, A6 = VIH
E = VIL Wait 4s G = VIL Verify Wait 60ns Read DATA
INCREMENT CURRENT GROUP
NO
DATA = 00h
YES
NO
++n = 1000 YES
LAST GROUP YES A9 = VIH E, G = VIH PASS
NO
End
A9 = VIH E, G = VIH FAIL
AI05575
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Figure 18. In-System Equipment Group Protect Flowchart
START Set-up n=0 RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
Protect
WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
Wait 100s WRITE 40h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Verify
Wait 4s READ DATA ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
DATA NO = 01h YES RP = VIH End ISSUE READ/RESET COMMAND ++n = 25 YES RP = VIH ISSUE READ/RESET COMMAND NO
PASS
FAIL
AI05576
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Figure 19. In-System Equipment Chip Unprotect Flowchart
START PROTECT ALL GROUPS Set-up n=0 CURRENT GROUP = 0
RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH Verify
Wait 4s READ DATA ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH INCREMENT CURRENT GROUP
NO
DATA = 00h
YES
NO
++n = 1000 YES RP = VIH
LAST GROUP YES RP = VIH
NO
End
ISSUE READ/RESET COMMAND
ISSUE READ/RESET COMMAND
FAIL
PASS
AI05577
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M29W641DH, M29W641DL, M29W641DU
REVISION HISTORY Table 26. Document Revision History
Date 30-Apr-2002 Version -01 Document released When in Extended Block mode, the block at the boot block address can be used as OTP. Data Toggle Flow chart corrected. Double Word Program Time (typ) changed to 20s. Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 01 equals 1.0). New Part Numbers added. 100ns and 120ns Speed Classes added. TFBGA63 package added. VIO removed from and VCCQ added to Table 6, Absolute Maximum Ratings. VCCQ added to Table 7, Operating and AC Measurement Conditions. Ready/Busy pin (TFBGA63 package) added to the signals (concerns M29W641DU only). Figure 7, AC Measurement I/O Waveform, and Figure 8, AC Measurement Load Circuit, modified. Unlock Bypass Commands clarified and VCCQ description specified in SIGNAL DESCRIPTIONS section. Test Conditions modified for ILI, ILO, VIL, VIH, VOL and VOH parameters in Table 9, DC Characteristics, and VIL, VIH, VOL and VOH parameters corrected. tWLWH, tDVWH, tWLAX, tWHRL parameters modified for 90ns speed class in Table 11, Write AC Characteristics, Write Enable Controlled. tELEH, tDVEH, tELAX and tEHRL parameters modified for 90ns speed class in Table 12, Write AC Characteristics, Chip Enable Controlled. tPLYH parameter added to Table 13, Reset/Block Temporary Unprotect AC Characteristics. Data and Value modified for address 2Dh, and Data modified for address 30h in Table 21, Device Geometry Definition. Description modified at address offset 4Eh in Table 22. Data Retention and Erase Suspend Latency Time parameters added to Table 6, Program, Erase Times and Program, Erase Endurance Cycles, and Typical after 100k W/E Cycles column removed. IID (Identification) current removed from Table 9, DC Characteristics. Lead-free package options E and F added to Table 16, Ordering Information Scheme. Appendix C, EXTENDED MEMORY BLOCK, added. VSS pin connection to ground clarified. Auto Select Command is used to read the Extended Memory Block. Note added to Table 16, Ordering Information Scheme. Revision Details
05-Sep-2002
1.1
8-Apr-2003
2.0
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M29W641DH, M29W641DL, M29W641DU
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