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DS3006 - 2.1
ZN427E8 / ZN427J8
MICROPROCESSOR COMPATIBLE 8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER
The ZN427 is an 8-bit successive approximation converter with three-state outputs to permit easy interfacing to a common data bus. The IC contains a voltage switching DAC, a fast comparator, successive approximation logic and a 2.56V precision bandgap reference, the use of which is pin optional to retain flexibility. An external fixed or varying reference may therefore be substituted, thus allowing ratiometic operation Only passive external components are required for operation of the converter.
BUSY (END OF CONVERSION) RD (OUTPUT ENABLE) CLOCK WR (START CONVERSION) REXT VIN
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
BIT 8 (LSB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) +VCC (+5V)
FEATURES
s s s s s s s s s Easy Interfacing to Microprocessor, or Operates as a 'Stand-Alone' Converter Fast: 10 microseconds Conversion time Guaranteed No Missing Codes over Operating Temperature Range Data Outputs Three-State TTL Compatible, other Logic Inputs and Output TTL and CMOS Compatible Choice of On-Chip or External Reference Voltage Ratiometric Operation Unipolar or Bipolar Input Ranges Complementary to ZN428 DAC Commercial or Military Temperature Range
VREF IN VREF OUT GROUND
ZN427J8 (DC18) ZN427E8 (DP18)
Fig.1 Pin connection - top view
ORDERING INFORMATION
Device type ZN427E8 ZN427J8 Operating temperature 0C to +70C -55C to +125C Package DP18 DC18
8 VREF OUT D TO A OUTPUT R-2R LADDER COMPARATOR VIN REXT CLOCK INPUT 6 5 4 3 SUCCESSIVE APPROXIMATION REGISTER WR (START CONVERSION) 1 BUSY (END CONVERSION) ANALOGUE VOLTAGE SWITCHES + 9 GROUND 7 VREF IN +2.5V REFERENCE
VCC (+5V)
10
3-STATE BUFFERS
2 RD (OUTPUT ENABLE)
11 MSB
12
13
14
15
16
17
18 LSB
Fig.2 System diagram
ZN427
ABSOLUTE MAXIMUM RATINGS
Supply voltage VCC Max. voltage, logic and VREF input Operating temperature range Storage temperature range +7.0V +VCC 0C to +70C (ZN427E8) -55C to +125C (ZN427J8) -55C to +125C
ELECTRICAL CHARACTERISTICS (at VCC = 5V, Tamb = 25C unless otherwise specified). Parameter
Converter Resolution Linearity error Differential non-linearity Linearity error T.C. Differential non-linearity T.C. Full-scale (gain) T.C. Zero T.C. Zero transition 00000000 to 00000001 F.S. transition 11111110 to 11111111 Conversion time External reference voltage Supply voltage (VCC) Supply current Power consumption Comparator Input current Input resistance Tail current, IEXT Negative supply, V- Input voltage Internal voltagee reference Output voltage Slope resistance VREF temperature coefficient Reference current Logic (over operating temperature range) High level input voltage VIH Low level input voltage VIL High level input current, WR and RD inputs IIH High level input current, Clock input IIH Low level input current IIL High level output current IOH Low level output current IOL High level output voltage VOH Low level output voltage VOL Disable output leakage Input clamp diode voltage Read input to data output Enable/disable delay time tRD Start pulse width tWR WR to BUSY propagation delay tBD Clock pulse width Maximum clock frequency Min. Typ. Max. Units Bits LSB LSB ppm/C ppm/C ppm/C V/C mV mV V s V V mA mW A k A V V Conditions
8 12 10 2.545 1.5 4.5 -
0.5 3 6 2.5 8 15 13 2.550 25 125
0.5 18 16 2.555 10 3.0 5.5 40 -
External Ref. 2.5V DC Package DP Package VREF IN = 2.560V See note 1
25 -3.0 -0.5
1 100 -
15 -30.0 3.5
VIN = +3V, REXT = 82k V - = -5V See comparator (page x-xx)
2.475 4
2.560 0.5 50 -
2.625 2 15
V ppm/C mA
RREF = 390, CREF = 47 See reference (page x-xx)
2.0 2.4 250 500 900
180 160 1000
0.8 50 15 100 30 -5 -100 1.6 0.4 2 -1.5 250 250 250 -
V V A A A A A A mA V V A V ns ns ns ns ns kHz
VIN = 5.5V, VCC = max. VIN = 2.4V, VCC = max. VIN = 5.5V, VCC = max. VIN = 2.4V, VCC = max. VIN = 0.4V, VCC = max. IOH = max., VCC = min. IOL = max., VCC = min. VO = 2.4V See Fig.9 See Fig.9
See note 1
Note 1: A 900kHz clock gives a conversion time of 10s (9 clock periods).
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ZN427
GENERAL CIRCUIT OPERATION
The ZN427 utilises the successive approximation technique. Upon receipt of a negative-going pulse at the WR input the BUSY output goes low, the MSB is set to 1 and all other bits are set to 0, which produces an output voltage of VREF/2 from the DAC. This is compared to the input voltage VIN; a decision is made on the next negative clock edge to reset the MSB to 0 if VREF VREF > VIN or leave it set to 1 if < VIN. 2 2 to 1. This procedure is repeated for all eight bits. On the ninth negative clock edge BUSY goes high indicating that the conversion is complete. During a conversion the RD input will normally be held high to keep the three-state buffers in their high impedance state. Data can be read out by taking RD high, thus enabling the three-state output. Readout is non-destructive. The BUSY output may be tied to the RD input to automatically enable the outputs when the data is valid. For reliable operation of the converter the start pulse applied to the WR input must meet certain timing criteria with respect to the converter clock. These are detailed in the timing diagram of Fig.3.
Bit 2 is set to 1 on the same clock edge, producing an output VREF VREF VREF from the DAC of or + depending on the state 4 2 4 of the MSB. This voltage is compared to VIN and on the next clock edge a decision is made regarding bit 2, whilst bit 3 is set
Fig.3 Timing diagram
NOTES ON TIMING DIAGRAM
1. A conversion sequence is shown for the digital word 01100110. For clarity the three-state outputs are shown as being enabled during the conversion, but normal practice would be to disable them until the conversion was complete. 2. The BUSY output goes low during a conversion. When BUSY goes high at the end of a conversion the output data is valid. In a microprocessor system the BUSY output can be used to generate an interrupt request when the conversion is complete.
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ZN427
3. In the timing diagram cross hatching indicates a 'don't care' condition. 4. The start pulse operates as an asynchronous (independent of clock) reset that sets the MSB output to 1 and sets all other outputs and the end of conversion flag to 0. This resetting occurs on the low-going edge of the start pulse and as long as WR is low the converter is inhibited. Conversion commences on the first active (negative going) clock edge after the WR input has gone high again, when the MSB decision is made. A number of timing constraints thus supply to the start pulse. (a) The minimum duration of the start pulse is 250ns, to allow reliable resetting of the converter logic circuits. (b) There is no limit to the maximum duration of the start pulse. (c) To allow the MSB to settle at least 1.5s must elapse between the negative going edge of the start pulse and the first active clock edge that indicates the MSB desicion. (d) To ensure relaible clocking the positive-going edge of the start pulse should not occur within 200ns of an active (negative-going) clock edge. The ideal place for the positivegoing edge of the start pulse is coincident with a positive-going clock edge. As a special case of the above conditions that start pulse may be synchronous with a negative-going clock pulse.
PRACTICAL CLOCK AND SYNCHRONISING CIRCUITS
The actual method of generating the clock signal and synchronising it to the start conversion system in which the ZN427 is incorporated. When used with a microprocessor the ZN427 can be treated as RAM and can be assigned a memory address using an address decoder. If the P clock is used to drive the ZN427 and the P write pulse meets the ZN427 timing criteria with respect to the P clock then generating the start pulse is simply a matter of gating the decoded address with the microprocessor write pulse. Whilst the conversion is being performed the microprocesor can perform other instructions or No operation (NOP). when the conversion is complete the outputs can be enabled onto the bus by gating the decoded address with the read pulse. A timing diagram for this sequence of operation is given in Fig.4. An advantage of using the microprocessor clock is that the conversion time is known precisely in terms of machine cycles. the data outputs may therefore be read after a fixed delay of at least nine clock cycles after the end of the WR pulse, when the conversion will be complete. Alternatively the read operation may be initiated by using the BUSY output to generate interrupt request.
Fig.4 Typical timing diagram using P clock and write pulse
In some systems, for example single-chip microcomputers such as the 8048, this simple method may not be feasible for one or more of the following reasons:
(a) The MPU clock is not available externally. (b) The clock frequency is too high.
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ZN427
(c) The write pulse timing criteria make it unsuitable for direct use as a start conversion pulse. If any of these conditions apply then the self-synchronising clock circuit of Fig.5a is recommended.
Fig.5a Self-synchronising clock circuit
Fig.5b Timing diagram for circuit of Fig.5a
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ZN427
N1 is connected as an astable multivibrator which, when the BUSY output is high, is inhibited by the output of N2 holding one of its inputs low. The start conversion pulse resets the BUSY flag and N1 begins to oscillate. When the conversion is complete BUSY goes high and the clock is inhibited. Since the start pulse starts the clock it may occur at any time. The only constraints on the start pulse are that it must be longer than 250ns but at least 200ns shorter than the first clock pulse. The first clock pulse is in fact longer than the rest since C1 starts from a fully charged condition whereas on subsequent cycles it changes between the upper and lower threshold (VT+ and VT) of the Schmitt trigger.
LOGIC INPUTS AND OUTPUTS
The logic inputs of the ZN427 utilise the emitter-follower configuration shown in Fig.6. This gives extremely low input currents for CMOS as well as TTL compatibility.
Fig.6 Equivalent circuit of all inputs
The BUSY output, shown in Fig.7, utilises a passive pullup for CMOS/TTL compatibility.
Fig.7
The data outputs have three-state buffers, an equivalent circuit of which is shown in Fig.8. Whilst the RD input is low both output transistors are turned off and the output is in a high
impedance state. When RD is high the data output will assume the appropriate logic state (0 or 1).
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ZN427
VCC 500 20k
BITS 1-8 (PINS 11-18)
10k RD (PIN 2)
GROUND
Fig.8 Equivalent circuit of data outputs
A test circuit and timing diagram for the output enable/disable delays are given in Fig.9.
Fig.9 Output enable/disable waveforms
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ZN427
ANALOG CIRCUITS
D-A converter IThe converter is of the voltage switching type and uses an R2R ladder network as shown in Fig.10. Each element is connected to either 0V or VREF IN by transistor voltage switches specially designed for low offset voltage (<1mV). A binary weighted voltage is produced at the output of the R2R ladder. D to A output = n (VREF IN -VOS) + VOS 256 where n is the digital input to the D-A from successive approximation register. VOS is a small offset voltage that is produced by the device supply current flowing in the package lead resistance. The value of VOS is typically 2mV for the ZN427E8 and 4mV for the ZN427J8. This offset will normally be removed by the setting up procedure and since the offset temperature coefficient is low (8V/C), the effect on accuaracy will be negligible. The D-A output range can be considered to be 0 - VREF IN through an output resistance R (4k).
R(4k)
R
R
R
D TO A OUTPUT
2R VREF IN (PIN 7)
2R
2R
2R
2R
VOLTAGE SWITCHES 0 VOLTS (PIN 9)
VOS
BIT 8
BIT 7
BIT 2
BIT 1 MSB
Fig.10 R-2R ladder network
REFERENCE (a) Internal reference The internal reference is an active bandgap circuit which is equivalent to a 2.5V Zener diode with a very low slope impedance (Fig.11). A Resistor (RREF) should be connected between pins 8 and 10. The recommended value of 390 will supply a nominal reference current of (5.0 - 2.5)/0.39=6.4mA. A stabilising/decoupling capacitor, CREF (47), is required between pins 8 and 9. For internal reference operation VREF OUT (pin 8) is connected to VREF IN (pin 7).
UP to five ZN427's may be driven from one internal reference, there being no need to reduce RREF. This useful feature saves power and gives excellent gain tracking between the converters. Alternatively the internal reference can be used as the reference voltage for other external circuits and can source or sink up to 3mA.
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ZN427
VCC +5V (PIN 10)
RREF (390) VREF OUT (PIN 8) CREF (4.7) GROUND (PIN 9)
Fig.11 Internal voltage reference
(b) External reference If required an external reference in the range +1.5 to +3.0V may be connected to VREF IN. The slope resistance of such a reference source should be less than 2.5, where n is the n number of converters supplied.
same supply. The external reference can vary from +1.5 to +3.0V. The ZN448/9 will operate if VREF IN is less than +1.5V but reduced overdrive to the comparator will increase its delay and so the conversion time will need to be increased.
COMPARATOR RATIOMETRIC OPERATION
If the output from a transducer varies with its supply then an external reference for the ZN427 should be derived from the The ZN427 contains a fast comparator, the equivalent input circuit of which is shown in Fig.12.
+5V PIN 10
6k
6k + TO LOGIC HIGH = 'RETAIN BIT'
AIN
RIN 4k
VIN PIN 6 4k
D TO A OUTPUT (O - VREF IN)
PIN 5 REXT IEXT
V-
Fig.12 Comparator equivalent circuit
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ZN427
The comparator derives the tail current, IEXT, for its first stage from an external resistor, REXT, which is taken to a negative supply V-. This arrangement allows the ZN427 to work with any negative supply in the range -3 to -30 volts. the ZN427 is designed to be insensitive to changes in IEXT from 25A to 150A. The suggested nominal value of IEXT is 65A and a suitable value for REXT is given by REXT = |V_|15k. V - (volts) -3 -5 -10 -12 -15 -20 -25 -30 REXT (10%) 47k 82k 150k 180k 220k 330k 390k 470k The output from the D-A converter is connected through the 4k ladder resistance to one side of the comparator. The analog input to be converted could be connected directly to the other comparator input (VIN, pin 6) but for optimum stability with temperature the analog input should be applied through a source resistance (RIN = 4k) to match the ladder resistance).
ANALOG INPUT RANGES
The basic connection of the ZN427 shown in Fig.13 has an analog input range 0 to VREF IN which, in some applications, may be made available from previous signal conditioning/ scaling circuits. Input voltage ranges greater than this are accommodated by providing an attenuator on the comparator input, whilst for smaller input ranges the signal must be amplified to a suitable level. Bipolar input ranges are accommodated by off-setting the analog input input range so that the comparator always sees a positive input voltage.
DIGITAL OUTPUTS LSB BIT 8 7 6 5 4 3 2 MSB BIT 1 VCC (+5V)
18
17
16
15
14
13
12
11
10
RREF (390)
1
2
3
4
5 VIN REXT (82k) RIN (4k)
6
7
8
9
CREF (47) BUSY RD CK WR V(-5V) AIN VREFINVREFOUT GND (0V)
NOMINAL AIN RANGE = 0 TO VREFIN
Fig.13 External components for basic operation
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ZN427
UNIPOLAR OPERATION
The general connection for unipolar operation is shown in Fig.14. The values of R1 and R2 are chosen so that VIN = VREF IN when the analogue input (AIN) is at full-scale. The resulting full-scale range is given by: AINFS = 1 + R1 R2 , VREF IN = G.VREF IN. To match the ladder resistance R1/R2 (RIN) = 4k. The required nominal values of R1 and R2 are given by R1 = 4Gk, R2 = 4G k G-1
AIN
VREF IN 1M ZERO ADJUST R1
680k VIN 7 6 9 GROUND R2 ZN427
Fig.14 Unipolar operation - general connection
Using these relationships a table of nominal values of R1 and R2 can be constructed for VREF IN = 2.5V. Input range +5V +10V G 2 4 R1 8k 16k R2 8k 5.33k
Zero adjustment Due to offsets in the DAC and comparator the zero (0 to 1) code transition would occur with typically 15mV applied to the comparator input, which correpsonds to 1.5LSB with a 2.56V reference. Zero adjustment must therefore be provided to set the zero transition to its correct value of +0.5LSB or 5mV with a 2.56V reference. This is achieved by applying an adjustable positive offset to the comparator input via P2 and R3. The values shown are suitable for all input ranges greater than 1.5 times VREF IN. Practical circuit values for +5 and +10V input ranges are given in Fig.15, which incorporates both zero and gain adjustments.
Gain adjustment Due to tolerance in R1 and R2, tolerance in VREF and the gain (full-scale) error of the DAC, some adjustment should be incorporated into R1 to calibrate the full-scale of the converter. When used with the internal reference and 2% resistors a preset capable of adjusting R1 by at least 5% of its nominal value is suggested.
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ZN427
AIN
VREF IN
AIN
VREF IN
P1 5k GAIN ADJUST
1M ZERO ADJUST
P2
P1 10k GAIN ADJUST
1M ZERO ADJUST
P2
R1 5k6
680k
R3
R1 11k
680k
R3
TO PIN 6 R2 8k2 2% RESISTORS 20% POTENTIOMETERS R2 5k6
TO PIN 6
+5V FULL-SCALE
+10V FULL-SCALE
Fig.15 Unipolar operation - component values
Unipolar adjustment prodedure
(i) Apply continuous convert pulses at intervals long enough to allow a complete conversion and monitor the digital outputs. (ii) Apply full-scale minus 1.5LSB to AIN and adjust off-set until the 8 bit (LSB) output just flickers between 0 and 1 with all other bits at 0. (iii) Apply 0.5LSB) to AIN and adjust zero until 8 bit just flickers between 0 and 1 with all other bits at 1.
Unipolar setting up points
Input range, +FS +5V +10V 0.5LSB 9.8mV 19.5mV FS - 1.5LSB 4.9707V 9.9414V 1LSB = FS 256
Unipolar logic coding
Analogue input (AIN) (Nominal code centre value) FS - 1LSB FS - 2LSB 0.75FS 0.5FS + 1LSB 0.5FS 0.5FS - 1LSB 0.25FS 1LSB 0 Output code (offset binary) 11111111 11111110 11000000 10000001 10000000 01111111 01000000 00000001 00000000
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ZN427
BIPOLAR OPERATION
For bipolar operation the input to the ZN427 is offset by half full-scale by connecting a resistor R3 between VREF IN and VIN (Fig.16).
AIN
VREF IN
R1
R3
VIN
7 6 9 GROUND ZN427
R2
Fig.16 Bipolar operation - general connection
When AIN = -FS, VIN needs to be equal to zero. When AIN = +FS, VIN needs to be equal to VREF IN. If the full-scale range is G. VREF IN then R1 = (G - 1). R2 and R1 = G. R3 fulfil the required conditions. To match the ladder resistance, R1/R2/R3 (=RIN) = 4k.
Thus the nominal values of R1, R2, R3 are given by R1 = 8 Gk, R2 = 8G/(G - 1)k, R3 = 8k. A bipolar range of VREF IN (which corresponds to the basic unipolar range 0 to +VREF IN) results if R1 = R3 = 8k and R2 = . Assuming the VREF IN = 2.5V the nominal values of resistors for 5 and 10V input ranges are given in the following table.
Input range +5V +10V
G 2 4
R1 16k 32k
R2 16k 10.66k
R3 8k 8k
Minus full-scale (offset) is set by adjusting R1 about its nominal value relative to R3. Plus full-scale (gain) is set by adjusting R2 relative to R1. Practical circuit realisations are given in Fig.17.
Note that in the 5V case R3 has been chosen as 7.5k (instead of 8.2k) to obtain a more symmetrical range of adjustment using standard potentiometers.
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ZN427
AIN
VREF
AIN
VREF
5k OFFSET ADJUST
7k5
10k OFFSET ADJUST
8k2
13k
27k
TO PIN 6 5k GAIN ADJUST 2% RESISTORS 20% POTENTIOMETERS 13 8k2 5k GAIN ADJUST
TO PIN 6
5VOLTS FULL SCALE
10VOLTS FULL SCALE
Fig.17 Bipolar operation - component values
Bipolar adjustment prodedure
(i) Apply continuous SC pulses at intervals long enough to allow a complete conversion and monitor the digital outputs. (ii) Apply -(FS -0.5LSB) to AIN and adjust off-set until the 8 bit (LSB) output just flickers between 0 and 1 with all other bits at 0. (iii) Apply +(FS -1.5LSB) to AIN and adjust gain until the 8 bit just flickers between 0 and 1 with all other bits at 1. (iv) Repeat step (ii).
Bipolar setting up points
Input range, FS +5V +10V -(FS -0.5LSB) -4.9805V -9.9609V +(FS -1.5LSB) +4.9414V +9.8828V 1LSB =2FS 265
Bipolar logic coding
Analogue input (AIN) (Nominal code centre value) +(FS - 1LSB) +(FS - 2LSB) +0.5FS +1LSB 0 -1LSB -0.5FS -(FS - 1LSB) -FS Output code (offset binary) 11111111 11111110 11000000 10000001 10000000 01111111 01000000 00000001 00000000
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ZN427
SINGLE 5 V SUPPLY RAIL OPERATION
The ZN427 takes very little power from the negative rail and so a suitable negative supply can be generated very easily using a 'diode pump' circuit. The circuit shown in Fig.18 works with any clock frequency from 10kHz to 1MHz and can supply up to five ZN427's.
Fig.18 single 5V supply operation
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ZN427
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576
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(c) GEC Plessey Semiconductors 1994 Publication No. DS3006 Issue No. 2.1 May 1994
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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