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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-30326-1E
MEMORY
FLASH MEMORY CARD
PCMCIA Rel.2/JEIDA Ver.4 conformable
MB98A8113x-/8123x-/8133x-/8143x-20
FLASH ERASABLE AND PROGRAMMABLE MEMORY CARD 2 M/4 M/8 M/16 M-BYTE s DESCRIPTION
The Fujitsu MB98A8113x, MB98A8123x, MB98A8133x and MB98A8143x are electrically erasable and programmable (Flash) memory cards capable of storing and retrieving large amounts of data. The memory circuits are housed in a credit-card sized 68-pin package. Internal circuit is protected by two metal panels, one at the top and the other at the bottom of the card, that help to reduce chip damage from electrostatic discharge. A unique feature of the Fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus configuration. All cards are portable and operate on low power at high speed. In accordance with the Personal Computer Memory Card Internal Association (PCMCIA) and Japan Electrical Industry Development Association (JEIDA) industry standard specifications, Flash memory cards offer additional EEPROM memory that is used to store attribute data. The attribute memory is a Flash memory card option. (See page 2 for description of the three available options.) * * * * * * * * * Conformed to PCMCIA and JEIDA industry standards. Credit card size: 85.6 mm (length) x 54.0 mm (width) x 3.3 mm (thickness) PCMCIA/JEIDA conformed two-piece 68-pin connector (with a two-row built-in receptacle) Single +5 V 5% power supply (+12.0 V 5%VPP) Command control for Automated Program/Automated Erase operation Write protect function Erase Suspend Capability Status Resister Capability 128 KB Block Erase (at x16 mode)
s PACKAGE
(CRD-68P-M05)
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MB98A8113x-/8123x-/8133x-/8143x-20
s ATTRIBUTE MEMORY OPTIONS
PCMCIA and JEIDA standard memory cards from Fujitsu provide a separate EEPROM memory address space for recording fundamental card information. It is used by the customers to record basic configuration information such as device type, size, speed, etc. The attribute memory is selected by asserting the REG pin on the card interface. Option descriptions as follows:
OPTION 1: Attribute memory is not supported. REG Pin: Not Contacted
(JEIDA Ver. 3 conformable) Main Memory Part Number Memory Device Attribute Memory Access Memory Device Access Time Time 200 ns 200 ns 200 ns -- -- -- -- -- -- -- -- Memory Organization * 2 M x 8 bits/1 M x 16 bits 4 M x 8 bits/2 M x 16 bits 8 M x 8 bits/4 M x 16 bits 16 M x 8 bits/8 M x 16 bits
MB98A81131 8 M Flash Memory x 2 pcs MB98A81231 8 M Flash Memory x 4 pcs MB98A81331 8 M Flash Memory x 8 pcs
MB98A81431 8 M Flash Memory x 16 pcs 200 ns
OPTION 2: Attribute memory in a separate location is not supported. When REG line is asserted, "FF" is output to the data bus to indicate that attribute data may be stored in main memory.
(PCMCIA Rel. 2/JEIDA Ver. 4 conformable) Main Memory Part Number Memory Device Attribute Memory Access Memory Device Access Time Time 200 ns 200 ns 200 ns -- -- -- -- -- -- -- -- Memory Organization * 2 M x 8 bits/1 M x 16 bits 4 M x 8 bits/2 M x 16 bits 8 M x 8 bits/4 M x 16 bits 16 M x 8 bits/8 M x 16 bits
MB98A81132 8 M Flash Memory x 2 pcs MB98A81232 8 M Flash Memory x 4 pcs MB98A81332 8 M Flash Memory x 8 pcs
MB98A81432 8 M Flash Memory x 16 pcs 200 ns
OPTION 3: Attribute memory is supported. The data is stored in 64 K-bit EEPROM. When the REG line is asserted, data stored in EEPROM is output to the data bus.
(PCMCIA Rel. 2/JEIDA Ver. 4 conformable) Main Memory Part Number Memory Device Access Time 200 ns 200 ns 200 ns Attribute Memory Memory Device EEPROM x 1 pcs EEPROM x 1 pcs EEPROM x 1 pcs EEPROM x 1 pcs Access Time Memory Organization *
MB98A81133 8 M Flash Memory x 2 pcs MB98A81233 8 M Flash Memory x 4 pcs MB98A81333 8 M Flash Memory x 8 pcs
300 ns 2 M x 8 bits/1 M x 16 bits 300 ns 4 M x 8 bits/2 M x 16 bits 300 ns 8 M x 8 bits/4 M x 16 bits 300 ns 16 M x 8 bits/8 M x 16 bits
MB98A81433 8 M Flash Memory x 16 pcs 200 ns * : To be configured by user. 2
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MB98A8113x-/8123x-/8133x-/8143x-20
s PIN ASSIGNMENTS
MB98A8113x MB98A8123x MB98A8133x MB98A8143x Pin No. MB98A8113x MB98A8123x MB98A8133x MB98A8143x GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 62 63 64 65 66 67 68 GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 A20 N.C. VCC VPP2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 A20 A21 VCC VPP2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 A20 A21 VCC VPP2 A22 N.C. N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 A20 A21 VCC VPP2 A22 A23 N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND
61 REG/N.C.* REG/N.C.* REG/N.C.* REG/N.C.*
* : N.C. terminal in MB98A8xx31 series.
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MB98A8113x-/8123x-/8133x-/8143x-20
s PIN DESCRIPTIONS
Symbol A0 to A23 D0 to D15 Pin Name Address Input Data Input/Output Input/Output Input Input/Output Function Address Inputs, A0 to A23. Data Inputs/Outputs. This data bus size (8-bit or 16-bit) is selected with CE1 and CE2. Active Low. - Lower byte (D0 to D7) is selected for read/write/ erase function of flash memory cards. Active Low. - Upper byte (D8 to D15) is selected for read/write / erase function of flash memory cards. Active Low. - Attribute memory is selected for read/write function of identification data of flash memory cards. (N.C. or "FF" data or attribute data.) Active Low. - Output enable for flash memory cards. Active Low. - Write enable for flash memory cards. Programming voltage for lower byte. Programming voltage for upper byte. These pins detect if the card has been correctly inserted. Both pins are tied to GND internally. Write controller for flash memory cards. This pin outputs the Protect/Non Protect status of "WP Switch". Both pins are tied to VCC internally. Power Supply Voltage. (+5.0 V 5%) System Ground.
CE1
Card Enable for Lower Byte
Input
CE2
Card Enable for Upper Byte
Input
REG
Attribute Memory Select
Input
OE WE VPP1 VPP2 CD1, CD2 WP BVD1, BVD2 VCC GND N.C.
Output Enable Write Enable Programming Voltage 1 Programming Voltage 2 Card Detect Write Protect Battery Voltage Detect Power Supply Ground Non Connection
Input Input Input Input Output Output Output -- -- --
s PIN LOCATIONS
Fig. 1 - BOTTOM VIEW (CONNECTOR SIDE)
Front Side
34
1
68 Back Side
35
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MB98A8113x-/8123x-/8133x-/8143x-20
Fig. 2 - MB98A8113x, 8123x, 8133x, and 8143x BLOCK DIAGRAM
R WE OE VPP1 VPP2 C C R R R = 100 K, C = 0.22 F VCC GND
64 K EEPROM *1 CS R CE1 R CE2 R REG *3 A0 A21 *2 A22 *2 A23 *2 A1 * * * A20 CE INPUT DECODER & BUFFER CE0 * * * * * CE15 13 ADD OE I/O WE
WP.SW CE OE WE 8 Mb Flash Memory x1 (MB98A8113x) x2 (MB98A8123x) x4 (MB98A8133x) x8 (MB98A8143x) ADD 20 I/O 8 I/O TRANSCEIVER & BUFFER
VPP
VPP ADD 8 Mb Flash Memory x1 (MB98A8113x) x2 (MB98A8123x) x4 (MB98A8133x) x8 (MB98A8143x) I/O 8
OE WE
VCC R1 = 10 K BVD1 BVD2 WP D0 * * D15 CD1 CD2
Internal circuit
Notes: *1. EEPROM is only available in Option 3 (for attribute memory) Flash Memory cards. *2. See pins 50, 53 and 54 in "PIN ASSIGNMENTS." *3. N.C. terminal in MB98A8xx31 series.
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MB98A8113x-/8123x-/8133x-/8143x-20
s FUNCTION DESCRIPTIONS
MB98A8113x, 8123x, 8133x and 8143x have the common memory and the attribute one, and REG selects the common memory (REG = VIH) or the attribute memory (REG = VIL). MB98A8xx31 has the common memory only and REG pin is non-connected. If the attribute data is necessary, the data is programmed into the common memory. MB98A8xx32 has also the common memory only and "FFH" is output if the attribute data is read. MB98A8xx33 has both common memory and attribute memory.
1. Read Mode
The data in the common and attribute memory can be read with "OE = VIL" and "WE = VIH". The address is selected with A0 to A23. And CE1 and CE2 select output mode (x8/x16 output mode). The following 1) and 2) are the descriptions for Common Memory Read and Attribute Memory Read mode. 1) Common Memory Read - Three modes of Common Memory Read, reading the data in memory array, Intelligent ID and Status Register, are available. The card entered each Read Mode by writing "Read Memory/Reset Command", "Intelligent ID Read Command" or "Status Register Read Command". At writing each command, VPP is "VPPL" or "VPPH". The card automatically resets to the condition of Common Memory Read Mode upon initial power-up. 2) Attribute Memory Read - The data on the attribute memory can be read with "REG = VIL", "OE = VIL" and "WE = VIH". - An address on attribute memory can be selected with A0 to A13 pin. And CE1 and CE2 select output mode.
2. Standby Mode
- CE1 and CE2 at "VIH" place the card in Standby mode. D0 to D15 are placed in a high-Z state independent of the status "OE", "WE" and "REG".
3. Output Disable Mode
- The outputs are disabled with OE and WE at "VIH". D0 to D15 are placed in high-Z state.
4. Write Mode
1) Common Memory Write - The card is in Write mode with "OE = VIH" and "WE and CE = VIL". Commands can be written at the write mode. - VPP must be placed in "VPPH" at programming and erase operations only. And "VPP = VPPL or VPPH" at other write mode. Two types of the write mode, "WE control" and "CE control" are available. 2) Attribute Memory Write - REG at L-level selects Attribute memory and "OE = VIH", "WE and CE = VIL" place it in write mode. Two types of the write mode, "WE control" and "CE control" are available. - Attribute memory is not controlled by writing Commands. And attribute memory has the data polling function, which can detect whether the card status is programming operation. If the read operation is executed at programming cycle, the opposite data ( I7 ) to written data is output from D7 pin at the programming operation, and the same data (O7) as the written data is output from D7 pin at the completion of programming operation.
5. Automated Program Capability
- The card automatically executes the operation from programming to verification by one time of writing "Setup Program/Program command". - Address and data are latched at rising edge of WE or CE. - The card contains a Status Register which is read to check whether a byte (word) programming operation is completed successfully. - If VPP goes "VPPL" at programming operation, VPPS of Status Register does not indicate "1", but a result of the programming is not guaranteed. In this case, there is a possibility that the incorrect data are written and therefore, the written data should be erased to be reprogrammed.
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MB98A8113x-/8123x-/8133x-/8143x-20
6. Automated Erase Capability
- The card automatically executes the operation from erasing to verification by one time of writing "Setup erase/ erase command". - Address and data are latched at rising edge of "WE" or "CE". - Whether or not block erase operation is completed successfully can be checked by reading Status Register. - If VPP goes "VPPL" at erase operation, VPPS of Status Register does not indicate "1", but a result of the erase is not guaranteed. Therefore, erase should be executed once again.
7. Status Register
- The card contains a Status Register for each chip to show the status of the common memory. - Status Register is automatically read after Status Register Read command, Program command, Erase command, Erase Resume command or Erase Suspend command is input. After writing this command, all subsequent read operations output data from the status register until another valid command is written. - The contents of Status Register are latched on the falling edge of OE or CE, whichever occurs last in the cycle. OE or CE must be toggled to VIH before further reads to update the Status Register latch. - The Read Status Register command functions when VPP = VPPL or VPPH.
8. Erase Suspend
- The Erase Suspend Command allows block erase interruption in order to read data from another block of memory. - By writing the Erase Suspend Command (B0H) to chip in erasing state, the Write State Machine (WSM) suspends the erase sequence in the erase algorithm. At this point, a Read Command (FFH) can be written to read the data from block other than that suspended. - Other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H). By writing the Erase Resume Command into the chip with suspended block, the WSM will execute the erase process again. - VPP must remain at VPPH while the card is in Erase Suspend. - The Erase Suspend status can be checked by Status Register Read. When Erase Suspend Status (ESS) bit of Status Register is "1", the card is in the Suspend Status. At erase operation, "0" is output from Write State Machine Status (WSMS) bit. At erase suspend status, "1" is output from WSMS.
9. Intelligent Identifier (ID) Read Mode
- Each common memory can execute an intelligent identifier operation, initiated by writing Intelligent ID command (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code of 89H, and a read cycle from address 01H returns the device code of A2H. To terminate the operation, it is necessary to write another valid command. - The intelligent ID command is functional when VPP = VPPL or VPPH.
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MB98A8113x-/8123x-/8133x-/8143x-20
s FUNCTIONAL TRUTH TABLE
MAIN MEMORY FUNCTION *1
Read Function (REG = VIH) CE2 H H H L L X CE1 H L L H L X A0 X L H X X X OE X L L L L H WE WP *2 X H H H H H X X X X X X VPP2 VPPX VPPX VPPX VPPX VPPX VPPX VPP1 VPPX VPPX VPPX VPPX VPPX VPPX Mode Standby Read (x8 No.1) Read (x8 No.1) Read (x8 No.2) Read (x16) Output Disable High-Z High-Z DOUT (Upper Byte) DOUT High-Z Data Input/Output D8 to D15 D0 to D7 High-Z WP SW P or NP
DOUT P or NP (Lower Byte) DOUT P or NP (Upper Byte) High-Z P or NP P or NP P or NP
Write Command/Erase/Program Function (REG = VIH) CE2 H H H H H L L L L X CE1 H L L L L H H L L X A0 X L H L H X X X X X OE X L L H H L H L H H WE WP *2 X H H L L H L H L H X X X L L X L X L L VPP2 VPP1 Mode Standby Read (x8 No.1) Read (x8 No.1) Write (x8 No.1) Write (x8 No.1) Read (x8 No.2) Write (x8 No.2) Read (x16) Write (x16) Output Disable High-Z High-Z High-Z High-Z DOUT (Upper Byte) DIN (Upper Byte) DOUT DIN High-Z Data Input/Output D8 to D15 D0 to D7 High-Z WP SW P or NP
VPPX *3 VPPX *3 VPPX VPPX *3 VPPX VPPX *3 VPPX *3 VPPX *3 VPPX *3 VPPX VPPX *3 VPPX VPPX VPPX
DOUT P or NP (Lower Byte) DOUT P or NP (Upper Byte) DIN (Lower Byte) DIN (Upper Byte) High-Z High-Z NP NP P or NP NP P or NP NP P or NP
VPPX *3 VPPX *3 VPPX *3 VPPX *3 VPPX *3 VPPX *3
Notes: *1. H = VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect *2. L-level is output when WP SW = NP. H-level is output when WP SW = P. *3. VPP must be VPPH at Program/Erase cycle.
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY FUNCTION *1 (REG = VIL) *2 CE2 H H H H H L L L L X H H H H H L L L L X Notes: *1. *2. *3. *4. CE1 H L L L L H H L L X H L L L L H H L L X A0 X L H L H X X X X X X L H L H X X X X X OE X L L H H L H L H H X L L H H L H L H H WE X H H L L H L H L H X H H L L H L H L H WP L L L L L L L L L L H H H H H H H H H H Mode Standby Read (x8 No.1) Read (x8 No.1) Write (x8 No.1) Write (x8 No.1) Read (x8 No.2) Write (x8 No.2) Read (x16) Write (x16) Output Disable Standby Read (x8 No.1) Read (x8 No.1) Output Disable Output Disable Read (x8 No.2) Output Disable Read (x16) Output Disable Output Disable H H High-Z DOUT *3 (Lower Byte) High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z H High-Z H X Data Input/Output D15 to D8 High-Z DOUT *3 (Lower Byte) H DIN *4 (Lower Byte) X High-Z High-Z DOUT *3 (Lower Byte) DIN *4 (Lower Byte) High-Z High-Z DOUT *3 (Lower Byte) H D7 to D0 WP SW NP NP NP NP NP NP NP NP NP NP P P P P P P P P P P
H = VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect N.C. for MB98A81131, 81231, 81331, and 81431. H-level is output for MB98A81132, 81232, 81332, and 81432. "X" for MB98A81132, 81232, 81332 and 81432.
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MB98A8113x-/8123x-/8133x-/8143x-20
s ADDRESS CONFIGURATIONS *1 (MAIN MEMORY)
8-BIT BUS ORGANIZATION No.1 (CE1 = VIL, CE2 = VIH) Chip Address A23 to A21, A0 0000 0001 0000 0001 1110 1111 1110 1111 Block Address A20 to A17 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 Byte Address A16 to A1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0001 0001 1110 1110 1111 1111 CE2 H H H H H H H H CE1 L L L L L L L L D15 to D8 ----- ----- ----- ----- ----- ----- ----- ----- D7 to D0 0 Add. 1 Add. 2 Add. 3 Add. 16,777,212 Add. 16,777,213 Add. 16,777,214 Add. 16,777,215 Add.
8-BIT BUS ORGANIZATION No.2 (CE1 = VIH, CE2 = VIL) *2 Chip Address A23 to A21, A0 000X 000X 000X 000X 111X 111X 111X 111X Block Address A20 to A17 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 Byte Address A16 to A1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0001 0010 0011 1100 1101 1110 1111 CE2 L L L L L L L L CE1 H H H H H H H H D15 to D8 1 Add. 3 Add. 5 Add. 7 Add. 16,777,209 Add. 16,777,211 Add. 16,777,213 Add. 16,777,215 Add. D7 to D0 ----- ----- ----- ----- ----- ----- ----- -----
16-BIT BUS ORGANIZATION (CE1 = VIL, CE2 = VIL) Chip Address A23 to A21, A0 000X 000X 000X 000X 111X 111X 111X 111X Block Address A20 to A17 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 Byte Address A16 to A1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0001 0010 0011 1100 1101 1110 1111 CE2 L L L L L L L L CE1 L L L L L L L L D15 to D8 1 Add. 3 Add. 5 Add. 7 Add. 16,777,209 Add. 16,777,211 Add. 16,777,213 Add. 16,777,215 Add. D7 to D0 0 Add. 2 Add. 4 Add. 6 Add. 16,777,208 Add. 16,777,210 Add. 16,777,212 Add. 16,777,214 Add.
Notes: *1. H = VIH, L = VIL, X = Either 0 or 1. REG = "H". *2. Even addresses can not be selected.
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MB98A8113x-/8123x-/8133x-/8143x-20
s ADDRESS CONFIGURATIONS *1 (ATTRIBUTE MEMORY)
8-BIT BUS ORGANIZATION No.1 (CE1 = VIL, CE2 = VIH) A23 to A14 XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX A13 to A0 0 --- 0000 0 --- 0001 0 --- 0010 0 --- 0011 1 --- 1100 1 --- 1101 1 --- 1110 1 --- 1111 CE2 H H H H H H H H CE1 L L L L L L L L D15 to D8 ----- ----- ----- ----- ----- ----- ----- ----- D7 to D0 0 Add. ---- 2 Add. ---- 16,380 Add. ---- 16,382 Add. ----
8-BIT BUS ORGANIZATION No.2 (CE1 = VIH, CE2 = VIL) *2 A23 to A14 XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX A13 to A0 0 --- 000X 0 --- 001X 0 --- 010X 0 --- 011X 1 --- 100X 1 --- 101X 1 --- 110X 1 --- 111X CE2 L L L L L L L L CE1 H H H H H H H H D15 to D8 ----- ----- ----- ----- ----- ----- ----- ----- D7 to D0 ----- ----- ----- ----- ----- ----- ----- -----
16-BIT BUS ORGANIZATION (CE1 = VIL, CE2 = VIL) A23 to A14 XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX XX --- XX A13 to A0 0 --- 000X 0 --- 001X 0 --- 010X 0 --- 011X 1 --- 100X 1 --- 101X 1 --- 110X 1 --- 111X CE2 L L L L L L L L CE1 L L L L L L L L D15 to D8 ----- ----- ----- ----- ----- ----- ----- ----- D7 to D0 0 Add. 2 Add. 4 Add. 6 Add. 16,376 Add. 16,378 Add. 16,380 Add. 16,382 Add.
Notes: *1. H = VIH, L = VIL, X = Either 0 or 1. *2. Attribute memory can not be accessed.
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MB98A8113x-/8123x-/8133x-/8143x-20
s PROGRAM/ERASE CHIP DECODING TABLE
Bus Organization CE2 CE1 A23 A22 A21 L L H L L H H H L L L H 8-bit Bus H L H H L L H L H L H H L L H 16-bit Bus L L L H H Note: H = VIH, L = VIL, X = Either VIH or VIL L H L H L H L H L H L H L H L H A0 L H L H L H L H L H L H L H L H Decode Chips Chip 0 Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 Chip 7 Chip 8 Chip 9 Chip 10 Chip 11 Chip 12 Chip 13 Chip 14 Chip 15 Chip 1 Chip 3 Chip 5 Chip 7 Chip 9 Chip 11 Chip 13 Chip 15 Chip 0, Chip 1 Chip 2, Chip 3 Chip 4, Chip 5 Chip 6, Chip 7 Chip 8, Chip 9 Chip 10, Chip 11 Chip 12, Chip 13 Chip 14, Chip 15
X
X
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MB98A8113x-/8123x-/8133x-/8143x-20
s ERASE BLOCK DECODING TABLE
A20 A19 A18 L L H L L H H L L H H L H H Note: H = VIH, L = VIL, X = Either VIH or VIL A17 L H L H L H L H L H L H L H L H Decode Block Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Block 9 Block 10 Block 11 Block 12 Block 13 Block 14 Block 15
s CARD CHIP/BLOCK CONFIGURATION
D15 ODD BYTE Chip 15 Chip 13 Chip 11 Chip 9 Chip 7 Chip 5 Chip 3 Chip 1 D8 D7 D0 x16 bit mode x8 bit mode Chip 1 (8 M Flash Chip) Chip 0 (8 M Flash Chip) Chip 14 Chip 12 Chip 10 Chip 8 Chip 6 Chip 4 Chip 2 Chip 0 Block 15 (64 K x 8 bits) Block 15 (64 K x 8 bits) Block 14 (64 K x 8 bits) Block 14 (64 K x 8 bits) Block 13 (64 K x 8 bits) Block 13 (64 K x 8 bits) * * * * * * * * * * * * UPPER BYTE LOWER BYTE EVEN BYTE
Block 2 (64 K x 8 bits) Block 1 (64 K x 8 bits) Block 0 (64 K x 8 bits)
Block 2 (64 K x 8 bits) Block 1 (64 K x 8 bits) Block 0 (64 K x 8 bits)
Card Chip Configuration for 16 MB Card
Block Configuration for 2 Chips
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MB98A8113x-/8123x-/8133x-/8143x-20
s COMMAND DEFINITION TABLE
Command Table for 8-bit Mode
Command Read Memory/Reset Read Intelligent ID Codes *4 Setup Erase/Erase *5 Erase Suspend *7 /Erase Resume Setup Program/ Program *6 Alternate Setup Program/Program *6 Read Status Register Clear Status Register First Bus Cycle Second Bus Cycle Bus Cycle Required Operation *1 Address *2 Data *3 Operation *1 Address *2 Data *3 1 3 2 2 2 2 2 1 Write Write Write Write Write Write Write Write DA DA ZA DA WA WA DA DA FFH 90H 20H B0H 40H 10H 70H 50H -- Read Write Write Write Write Read -- -- IA ZA DA WA WA DA -- -- ID D0H D0H WD WD SRD --
Command Table for 16-bit Mode
Command Read Memory/Reset Read Intelligent ID Codes *4 Setup Erase/Erase *5 Erase Suspend *7 /Erase Resume Setup Program/ Program *6 Alternate Setup Program/Program *6 Read Status Register Clear Status Register First Bus Cycle Second Bus Cycle Bus Cycle Required Operation *1 Address *2 Data *3 Operation *1 Address *2 Data *3 1 3 2 2 2 2 2 1 Write Write Write Write Write Write Write Write DA DA ZA DA WA WA DA DA FFFFH 9090H 2020H B0B0H 4040H 1010H 7070H 5050H -- Read Write Write Write Write Read -- -- IA ZA DA WA WA DA -- -- ID D0D0H D0D0H WD WD SRD --
Notes: *1. Bus operations are defined in "FUNCTIONAL TRUTH TABLE". *2. DA = Address in selected chip IA = Identifier address: 00H for manufacturer code, 01H for device code. WA = Address of memory location to be programmed. ZA = Address of 128 K-Byte zones involved in erase operation. Addresses are latched on the rising edge of the Write Enable pulse or Card Enable pulse. *3. ID = Data read from location IA during device identification. Manufacturer = 89H for 8-bit, 8989H for 16-bit/Device = A2H for 8-bit, A2A2H for 16-bit SRD = Data of Status Register. WD = Data to be programmed at location WA. Data is latched on the rising edge of Write Enable or Card Enable. *4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes. *5. "ERASE FLOWCHART" in Fig.5 illustrates the Erase Algorithm. *6. "PROGRAM FLOWCHART" in Fig.4 illustrates the Program Algorithm. *7. "ERASE SUSPEND LOOP" in Fig.6 illustrates the Erase Suspend Algorithm. 14
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MB98A8113x-/8123x-/8133x-/8143x-20
s STATUS REGISTER DEFINITIONS
8-BIT BUS ORGANIZATION STATUS REGISTER BIT WSMS 7 ESS 6 ES 5 BPS 4 VPPS 3 R 2 R 1 R 0
16-BIT BUS ORGANIZATION STATUS REGISTER BIT STATUS REGISTER BIT WSMS 7 WSMS 15 ESS 6 ESS 14 ES 5 ES 13 BPS 4 BPS 12 VPPS 3 VPPS 11 R 2 R 10 R 1 R 9 R 0 R 8
WSMS (Write State Machine Status) 1 = Ready 0 = Busy Byte write or block erase completion can be checked with WSMS bit. "1" of Ready status is output at erase suspended condition. ESS (Erase Suspend Status) 1 = Erase Suspended When Erase operation is suspended, "1" is output from ESS bit. 0 = Erase In Process/Completed
ES (Erase Status) 1 = Error in Block Erase 0 = Successful Block Erase ES bit indicates whether the erase operation was successfully performed. BPS (Byte Program Status) 1 = Error in Byte Program 0 = Successful Byte Program BPS bit indicates whether the byte program operation was successfully performed. VPPS (VPPS Status) 1 = VPP Low Detect; Operation Abort 0 = VPP OK VPPS bit indicates VPP status before program/erase operation, and does not detect the status in program/ erase operation. R (Reserve) "0" is output during Status Register output. Clear Status Register Command ES, BPS and VPPS are cleared by input of Clear Status Register Command. These Status Register bits must be cleared before Program/Erase operations are executed.
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MB98A8113x-/8123x-/8133x-/8143x-20
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Supply Voltage Input Voltage Output Voltage Programming Voltage Ambient Temperature Storage Temperature Note: *1. Minimum DC input voltage is -0.5 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. *1 Note Symbol VCC VIN VOUT VPP1, VPP2 TA TSTG Value -0.5 to +6.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -2.0 to +14.0 0 to +60 -30 to +70 Unit V V V V C C
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MB98A8113x-/8123x-/8133x-/8143x-20
s RECOMMENDED OPERATING CONDITIONS
Parameter VCC Supply Voltage Ground Input Low Voltage Input High Voltage VPP during Read-Only Operation VPP during Program/Erase Operation Ambient Temperature *1 Notes Symbol VCC GND VIL VIH VPPL VPPH TA Min. 4.75 -- -0.3 2.4 0 11.4 0 Typ. 5.0 0 -- -- -- 12.0 -- Max. 5.25 -- 0.8 VCC +0.3 6.5 12.6 55 Unit V V V V V V C
Note: *1. Program/Erase are inhibited when VPP = VPPL. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
s CAPACITANCE
(TA = 25C, f = 1 MHz, VIN = VI/O = GND) Parameter Input Capacitance I/O Capacitance Notes *1 *2 Symbol CIN CI/O Min. -- -- Max. 50 50 Unit pF pF
Notes: *1. This value does not apply to CE1, CE2, WE and REG. *2. This value does not apply to CE1, CE2, BVD1 and BVD2. Fig. 3 - AC TEST CONDITIONS
* Input Pulse Levels: VIH = 2.6 V, VIL = 0.6 V
* Output Load
+5 V R1
* Input Pulse Rise and Fall Times: 5 ns (Transient between 0.8 V and 2.4 V) * Timing Reference Levels Input: VIL = 0.8 V, VIH = 2.4 V Output: VOL = 0.8 V, VOH = 2.0 V
DOUT (I/O) CL R2
* Including jig and stray capacitance
R1 Load I Load II 1.8 k 1.8 k
R2 990 990
CL 100 pF 5 pF
Parameter Measured All parameters except tCLZ, tOLZ, tCHZ, tOHZ, tRCLZ, tROLZ, tRCHZ and tROHZ tCLZ, tOLZ, tCHZ, tOHZ, tRCLZ, tROLZ, tRCHZ and tROHZ
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MB98A8113x-/8123x-/8133x-/8143x-20
s DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Notes *1 *2 Symbol ILI ILO ISB1 Standby Current ISB2 Condition VCC = VCC max VIN = 0 V or VCC VCC = VCC max VIN = 0 V or VCC VCC = VCC max CE1 = CE2 = VCC -0.2 V VCC = VCC max CE1 = CE2 = VIH VCC = VCC max CE1 = CE2 = VIL Cycle = 200 ns IOUT = 0 mA Program in progress Erase in progress Erase Suspend CE1 = CE2 = VIH VPP > VCC VPP VCC VPP = VPPH Program in progress VPP = VPPH Erase in progress IOL = 3.2 mA VCC = VCC min IOH = -2.0 mA VCC = VCC min Value Min. -- -- -- -- Typ. 1.0 1.0 0.5 4.0 Max. 20 20 1.7 8.0 Unit A A mA mA
Active Read Current Program Current Erase Current Erase Suspend Current VPP Read Current or Standby Current VPP Program Current VPP Erase Current Output Low Voltage Output High Voltage Notes: *1. *2. *3. *4. *5. *3 *4 *5 *5 *5
ICC1 ICC2 ICC3 ICCES IPP1 IPP2 IPP3 VOL VOH
-- -- -- -- -- -- -- -- -- 3.8
110 20 20 10 0.9 -- 10 10 -- --
150 60 60 20 1.8 175 30 30 0.4 --
mA mA mA mA mA A mA mA V V
This value does not apply to CE1, CE2, WE and REG. This value does not apply to BVD1, BVD2, CD1 and CD2. This value does not apply to BVD1 and BVD2. The read current during erase-suspend operation = ICCES + ICC1. These values for VPP1 and VPP2.
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MB98A8113x-/8123x-/8133x-/8143x-20
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) MAIN MEMORY PROGRAM/ERASE PERFORMANCE
Parameter Block Erase Time Block Program Time Program/Erase Cycle Min. -- -- 10,000 Typ. 1.6 * 0.6 * 100,000 Max. 10 2.1 -- Unit Sec. Sec. Cycle
* : The conditions of typical values are TA = 25C, VPP = 12 V, 10,000 cycles by algorithm).
ATTRIBUTE MEMORY PROGRAM PERFORMANCE
Parameter Byte Program Time Number of Program per Byte Min. -- 10,000 Typ. -- -- Max. 10 -- Unit mS Times
MAIN MEMORY READ CYCLE *1
Parameter Read Cycle Time Card Enable Access Time Address Access Time Output Enable Access Time Card Enable to Output in Low-Z Card Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address, CE, or OE Change *2 *2 *2 *2 *3 Notes Symbol tRC tCE tACC tOE tCLZ tCHZ tOLZ tOHZ tOH Min. 200 -- -- -- 5 -- 5 -- 5 Max. -- 200 200 100 -- 60 -- 60 -- Unit ns ns ns ns ns ns ns ns ns
ATTRIBUTE MEMORY READ CYCLE *1*4
Parameter Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Hold from Address Change Card Enable to Output Low-Z Output Enable to Output Low-Z Card Enable to Output High-Z Output Enable to Output High-Z *2 *2 *2 *3 Notes Symbol tRRC tRAA tRCE tROE tROH tRCLZ tROLZ tRCHZ tROHZ Min. 300 -- -- -- 5 5 5 -- -- Max. -- 300 300 150 -- -- -- 60 60 Unit ns ns ns ns ns ns ns ns ns
Notes: *1. Rise/Fall time < 5 ns. *2. Transition is measured at the point of 500 mV from steady state voltage. This parameter is specified using Load II in Fig.3. *3. This parameter is specified from the rising edge of OE, CE1 and CE2, whichever occurs first. *4. This parameter is for MB98A81133, 81233, 81333, and 81433. 19
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 1: CE1 = OE = VIL, CE2 = VIH: x 8-bit No.1 Bus Organization
tRC Address (A0 to A23) VIH VIL tACC tOH VOH D0 to D7 VOL PREVIOUS DATA VALID DATA VALID
READ CYCLE 2: CE1 = VIH, CE2 = OE = VIL: x 8-bit No.2 Bus Organization CE1 = CE2 = OE = VIL: x 16-bit Bus Organization
tRC Address *1 (A1 to A23) VIH VIL tACC tOH D8 to D15 or D0 to D15 VOH PREVIOUS DATA VALID VOL DATA VALID
: Undefined
Note: *1. A0 = Either VIH or VIL.
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 3: CE2 = VIH: x 8-bit No.1 Bus Organization
tRC Address (A0 to A23) VIH VIL tACC VIH CE1 VIL tCE tCLZ VIH OE VIL tOE tOH VOH D0 to D7 VOL tOLZ High-Z DATA VALID tOHZ tCHZ
: Undefined
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 4: CE1 = VIH: x 8-bit No.2 Bus Organization tRC Address *1 (A1 to A23) VIH VIL tACC CE2 VIH VIL tCE tCLZ OE VIH VIL tOLZ VOH D8 to D15 VOL High-Z DATA VALID tOE tOH tOHZ tCHZ
READ CYCLE 5: CE1 = CE2 = VIL: x 16-bit Bus Organization tRC Address *1 (A1 to A23) VIH VIL tACC VIH CE1 = CE2 VIL tCE tCLZ OE VIH VIL tOLZ VOH D0 to D15 VOL High-Z tOE tOH DATA VALID tOHZ tCHZ
: Undefined
Note: *1. A0 = Either VIL or VIH.
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIL) *1
READ CYCLE 1: CE1 = OE = VIL, CE2 = VIH: x 8-bit No.1 Bus Organization CE1 = CE2 = OE = VIL: x 16-bit Bus Organization tRRC Address *2 (A0 to A13) VIH VIL tRAA tROH D0 to D7 or D0 to D15 VOH PREVIOUS DATA VALID VOL DATA VALID
READ CYCLE 2: CE2 = VIH: x 8-bit No.1 Bus Organization
tRRC Address (A0 to A13) VIH VIL tRAA VIH CE1 VIL tRCE tRCLZ OE VIH VIL tROLZ VOH D0 to D7 VOL High-Z DATA VALID tROE tROH tROHZ tRCHZ
: Undefined
Notes: *1. This timing diagram is for MB98A81133, 81233, 81333, and 81433. "FF" data is available on MB98A81132, 81232, 81332, and 81432 only. *2. A0 = VIL or VIH at x16-bit bus organization.
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIL) *1
READ CYCLE 3: CE1 = VIH: x 8-bit No.2 Bus Organization
tRRC Address *2 (A1 to A13) VIH VIL tRAA VIH CE2 VIL tRCE tRCLZ OE VIH VIL tROLZ D8 to D15 VOH VOL High-Z "FFH" DATA VALID tROE tROH tROHZ tRCHZ
READ CYCLE 4: CE1 = CE2: x 16-bit Bus Organization tRRC
Address *2 (A1 to A13)
VIH VIL tRAA VIH
CE1 = CE2
VIL tRCE tRCLZ tRCHZ VIH VIL tROE VOH tROLZ High-Z DATA VALID tROHZ tROH
OE
D0 to D7 *3
VOL
: Undefined
Notes: *1. This timing diagram is for MB98A81133, 81233, 81333, and 81433. "FF" data is available on MB98A81132, 81232, 81332, and 81432 only. *2. A0 = Either VIH or VIL. *3. H-level is output from D8 to D15. 24
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY PROGRAM/ERASE CYCLE *1 *2
Parameter Write Cycle Time Address Set Up Time Address Hold Time Data Setup Time Data Hold Time Write Recovery Time before Read (WE control) Write Recovery Time before Read (CE control) Read Recover Time Card Enable Setup Time before Write Card Enable Hold Time Write Enable Pulse Width Write Enable Pulse Width High Write Enable Setup Time Write Enable Hold Time Card Enable Pulse Width Card Enable Pulse Width High Duration of Byte Program Operation (WE Control) Duration of Block Erase Operation (WE Control) Duration of Byte Program Operation (CE Control) Duration of Block Erase Operation (CE Control) VPP Setup Time to Write Enable Low VPP Setup Time to Chip Enable Low VPP Hold Time *3 *3 *3 *3 Notes Symbol tWC tAS tAH tDS tDH tWHGL tEHGL tGHWL tCS tCH tWP tWPH tWS tWH tCP tCPH tWHQV1 tWHQV2 tEHQV1 tEHQV2 tVPWH tVPEH tQVVL Min. 200 100 30 80 25 10 10 0 0 0 100 60 0 0 100 60 6 0.3 6 0.3 100 100 0 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s s s s ns ns ns
Notes: *1. Read timing parameters during Program/Erase operations are the same as those during read only operations. Refer to AC characteristics for Main Memory Read Cycle. *2. Rise/Fall time 5 ns. *3. The integrated stop timer terminates the Program/Erase operations, thereby eliminating the necessary for a maximum specification.
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY PROGRAM CYCLE *1
Parameter Address Setup Time Card Enable Setup Time Output Enable Setup Time Write Pulse Width Address Hold Time Data Setup Time Data Hold Time Card Enable Hold Time Output Enable Hold Time Program Time Program Recovery Time End of Program to Output Time Write Enable Hold Time Symbol tRAS tRCS tROES tRWP tRAH tRDS tRDH tRCH tROEH tRWR tRRE tRRBO tRWEH Min. 20 0 20 100 50 50 20 0 20 -- 50 -- 10 Max. -- -- -- -- -- -- -- -- -- 10 -- 100 -- Unit ns ns ns ns ns s ns ns ns ms ns ns ns
Note: *1. This parameter is for MB98A81133, 81233, 81333, and 81433.
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY PROGRAM & ERASE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH) *1
WRITE CYCLE 1: CE2 = VIH: x 8-bit Bus Organization No.1 Write (Alternate) Setup Program/Erase Command Address VIH (A1 to A20) VIL tWC tAS Address VIH (A0, A21, A22, A23) VIL VIH CE1 VIL tCS tCH tCH tWC tAH tRC tWC Write Program *2 /Erase Command
Programming/
Erasing
Read Status Data
Write Read Command
tCS
VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH/OH D0 to D7 VIL/OL tVPWH VPP1 VPPH or VPP2 VPPL : Undefined High-Z DATA IN DATA IN tDS tWP tDH tOE VALID SRD(=80H) tQVVL tDS DATA IN = FFH tWHQV1,2 tWP tDH tWHGL tCS tCH
Notes: *1. A0, A21, A22 and A23 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the PROGRAM/ERASE CHIP DECODING INFORMATION. *2. Latch address and data.
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY PROGRAM & ERASE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH) *1
WRITE CYCLE 1: CE1 = VIH: x 8-bit Bus Organization No.2 Write (Alternate) Setup Program/Erase Command Address (A1 to A20) VIH VIL tWC tAS Address VIH (A21, A22, A23) VIL VIH CE2 VIL tCS VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH/OH D8 to D15 VIL/OL High-Z DATA IN tVPWH VPPH VPP2 VPPL : Undefined DATA IN tDS tWP tDH tOE VALID SRD(=80H) tQVVL tDS DATA IN =FFH tWHQV1, 2 tWP tDH tWHGL tCS tCH tCH tCS tCH tWC tAH tRC tWC Write Program *2 /Erase Command
Programming
/Erasing
Read Status Data
Write Read Command
Notes: *1. A21, A22 and A23 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the PROGRAM/ERASE CHIP DECODING INFORMATION. A0 = Either VIL or VIH. *2. Latch address and data. 28
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY PROGRAM & ERASE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH) *1
WRITE CYCLE 1: CE1 = CE2: x 16-bit Bus Organization Write (Alternate) Setup Program/Erase Command Address VIH (A1 to A20) VIL tWC tAS Address VIH (A21, A22, A23) VIL VIH VIL tCS tCH tCH tWC tAH tRC tWC Write Program *2 /Erase Command
Programming
/Erasing
Read Status Data
Write Read Command
CE1 CE2
tCS
VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH/OH D0 to D15 VIL/OL tVPWH VPP1 & VPP2 VPPH VPPL : Undefined tQVVL High-Z DATA IN DATA IN tDS tWP tDH tOE VALID SRD (= 8080H) tDS DATA IN = FFFFH tWHQV1,2 tWP tDH tWHGL tCS tCH
Notes: *1. A21, A22 and A23 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the PROGRAM/ERASE CHIP DECODING INFORMATION. A0 = Either VIL or VIH. *2. Latch address and data. 29
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY PROGRAM & ERASE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH) *1
WRITE CYCLE 1: CE2 = VIH: x 8-bit Bus Organization No.1 Write (Alternate) Setup Program/Erase Command Address VIH (A1 to A20) VIL tWC tAS Address VIH (A0, A21, A22, A23) VIL VIH WE VIL tCS tWH tWS tWH tWS tWC tAH tRC tWC Write Program *2 /Erase Command
Programming
/Erasing
Read Status Data
Write Read Command
VIH OE VIL tGHWL tCPH VIH CE1 VIL tCP tDH tDS VIH/OH D0 to D7 VIL/OL tVPEH VPP1 VPPH or VPP2 VPPL : Undefined tQVVL High-Z DATA IN DATA IN tDS tCP tDH tOE VALID SRD(=80H) tDS DATA IN = FFH tEHQV1,2 tCP tDH tEHGL tWS tWH
Notes: *1. A0, A21, A22 and A23 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the PROGRAM/ERASE CHIP DECODING INFORMATION. *2. Latch address and data.
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY PROGRAM & ERASE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH) *1
WRITE CYCLE 1: CE1 = VIH: x 8-bit Bus Organization No.2 Write (Alternate) Setup Program/Erase Command Address VIH (A1 to A20) VIL tWC tAS Address VIH (A21, A22, A23) VIL VIH WE VIL tCS tWH tWH tWS tWC tAH tRC tWC Write Program *2 /Erase Command
Programming
/Erasing
Read Status Data
Write Read Command
tWS
VIH OE VIL tGHWL tCPH VIH CE2 VIL tCP tDH tDS VIH/OH D8 to D15 VIL/OL tVPEH VPPH VPP2 VPPL : Undefined tQVVL High-Z DATA IN DATA IN tDS tCP tDH tOE VALID SRD(=80H) tDS DATA IN = FFH tEHQV1,2 tCP tDH tEHGL tWS tWH
Notes: *1. A21, A22 and A23 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the PROGRAM/ERASE CHIP DECODING INFORMATION. A0 = VIL or VIH. *2. Latch address and data. 31
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MB98A8113x-/8123x-/8133x-/8143x-20
MAIN MEMORY PROGRAM & ERASE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH) *1
WRITE CYCLE 1: CE1 = CE2: x 16-bit Bus Organization Write (Alternate) Setup Program/Erase Command Address VIH (A1 to A20) VIL tWC tAS Address VIH (A21, A22, A23) VIL VIH WE VIL tCS VIH OE VIL tGHWL tCPH CE1 CE2 VIH VIL tCP tDH tDS VIH/OH D0 to D15 VIL/OL tVPEH VPP1 & VPP2 VPPH VPPL : Undefined tQVVL High-Z DATA IN DATA IN tDS tCP tDH tOE VALID SRD (=8080H) tDS DATA IN = FFFFH tEHQV1,2 tEHGL tWS tWH tWH tWS tWH tWS tWC tAH tRC tWC Write Program *2 /Erase Command
Programming
/Erasing
Read Status Data
Write Read Command
tCP
tDH
Notes: *1. A21, A22 and A23 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the PROGRAM/ERASE CHIP DECODING INFORMATION. A0 = VIL or VIH. *2. Latch address and data. 32
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 1: CE2 = VIH: x 8-bit No.1 Bus Organization
Address (A1 to A13)
VIH VIL tRAS tRCS VIH tRAH tRCH
CE1 VIL tROES VIH OE VIL tRWEH VIH WE VIL tRDS VIH D0 to D7 VIL tRWR VOH D7 *2 VOL High-Z tRRBO High-Z tRDH tRRE High-Z tRWP tROEH
DATA VALID
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A81133, 81233, 81333, and 81433. "FF" data is available on MB98A81132, 81232, 81332, and 81432 only. A0 = VIL. *2. Data polling operation.
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 2: CE1 = CE2: x 16-bit Bus Organization
Address (A1 to A13)
VIH VIL tRAS tRCS VIH tRAH tRCH
CE1 = CE2 VIL tROES VIH OE VIL tRWEH tRWP VIH WE VIL tRDS VIH D0 to D7 *2 VIL tRWR VOH D7 *3 VOL High-Z tRRBO High-Z tRDH tRRE High-Z tROEH
DATA VALID
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A81133, 81233, 81333, and 81433. "FF" data is available on MB98A81132, 81232, 81332, and 81432 only. A0 = VIH or VIL. *2. Inputs from D8 to D15 are not defined. *3. Data polling operation.
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 3: CE2 = VIH: x 8-bit No.1 Bus Organization
Address (A1 to A13)
VIH VIL tRAS tRAH tRWP tRWEH
VIH CE1 VIL tROES VIH OE VIL tRCS VIH WE VIL
tROEH
tRCH
tRDS VIH D0 to D7 VIL High-Z
tRDH
tRRE High-Z
DATA VALID tRWR tRRBO
VOH D7 *2 VOL
High-Z
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A81133, 81233, 81333 and 81433. A0 = VIL. *2. Data polling operation.
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MB98A8113x-/8123x-/8133x-/8143x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 4: CE1 = CE2: x 16-bit Bus Organization
Address (A1 to A13)
VIH VIL tRAS tRAH tRWP VIH tRWEH
CE1 = CE2 VIL tROES VIH OE VIL tRCS VIH WE VIL tRDS VIH D0 to D7 *2 VIL High-Z DATA VALID tRWR VOH D7 *3 VOL High-Z tRDH tRRE High-Z tRCH tROEH
tRRBO
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A81133, 81233, 81333, and 81433. A0 = VIL or VIH. *2. Inputs from D8 to D15 are not defined. *3. Data polling operation.
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MB98A8113x-/8123x-/8133x-/8143x-20
s PROGRAM/ERASE INFORMATION
Fig. 4 - PROGRAM FLOWCHART
START
COMMAND/STATUS Setup Program Command Alternate Setup Program Command Clear Status Register Command Read Command Full Status Check WSMS checked Bit
x8 bit mode 40H 10H 50H FFH 80H bit 7
x16 bit mode 4040H 1010H 5050H FFFFH 8080H bit 7, 15
Set WA VCC = 5.0 V VPP1 = VPP2 = VPPH
WRITE (ALTERNATE) SETUP PROGRAM COMMAND LATCH WA/WD SET TIMER 0S AND START READ DEVICE STATUS *1
VPPH = 12.0 V 0.6 V VPPL 6.5 V WA: PROGRAMMING ADDRESS WD: PROGRAMMING DATA WSMS: WRITE STATE MACHINE STATUS NO NO *1: Toggle OE or CE to update Status Register. *2: Read programmed data if necessary. If unnecessary, the read operation can be omitted.
STATUS CHECK WSMS = 1 ?
TIMER = 32 s ? YES ERROR
YES
READ DEVICE STATUS *1
FULL STATUS CHECK OK ?
NO
YES WRITE READ COMMAND *2 WRITE STATUS REGISTER CLEAR COMMAND
1 byte (word) Program Completed
ERROR
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MB98A8113x-/8123x-/8133x-/8143x-20
Fig. 5 - ERASE FLOWCHART
COMMAND/STATUS START VCC = 5.0 V, VPP1 = VPP2 = VPPH SET ZA WRITE SETUP ERASE COMMAND WRITE ERASE COMMAND SET TIMER 0S AND START READ DEVICE STATUS *1 Setup Erase Command Erase Command Clear Status Register Command Read Command Full Status Check WSMS checked Bit
x8 bit mode 20H D0H 50H FFH 80H bit 7
x16 bit mode 2020H D0D0H 5050H FFFFH 8080H bit 7, 15
NO
STATUS CHECK WSMS=1 ?
ERASE SUSPEND LOOP *4
NO
YES READ DEVICE STATUS *1
TIMER = 10S ? *3 YES ERROR
NO
ERASE SUSPEND ?
YES
FULL STATUS CHECK OK ?
NO
YES WRITE READ COMMAND *2 WRITE STATUS REGISTER CLEAR COMMAND ERROR
VPPH = 12.0 V 0.6 V VPPL 6.5 V ZA: ERASE ADDRESS WSMS: WRITE STATE MACHINE STATUS *1: Toggle OE or CE to update Status Register. *2: Read erased data if necessary. If unnecessary, the read operation can be omitted. *3: Time of "Erase suspend" is not included in "10s" *4: Please see "Erase Suspend Loop" in next page. Note: Erase both even and odd Address blocks at x8 bit mode.
1 BLOCK ERASE COMPLETED
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MB98A8113x-/8123x-/8133x-/8143x-20
Fig. 6 - ERASE SUSPEND LOOP
NO
STATUS CHECK WSMS = 0 ?
COMMAND/STATUS Erase Suspend Command Erase Resume Command Read Command Full Status Check
x8 bit mode B0H D0H FFH C0H bit 7 bit 6
x16 bit mode B0B0H D0D0H FFFFH C0C0H bit 7, 15 bit 6, 14
YES WRITE ERASE SUSPEND COMMAND
READ DEVICE STATUS *1 WSMS checked Bit ESS checked Bit
FULL STATUS CHECK OK ?
NO
YES SET RCA
WRITE READ COMMAND
SET RA READ COMMON MEMORY
FINISH THE READ OPERATION ?
NO ZA: ERASE ADDRESS WSMS: WRITE STATE MACHINE STATUS ESS: ERASE SUSPEND STATUS RCA: ADDRESS IN READ CHIP RA: READ ADDRESS *1: Toggle OE or CE to update Status Register.
YES SET ZA WRITE ERASE RESUME COMMAND READ DEVICE STATUS *1
STATUS CHECK WSMS = 0 and ESS = 0 ?
NO
YES RETURN
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MB98A8113x-/8123x-/8133x-/8143x-20
s UNIQUE FEATURES FOR FLASH MEMORY CARD
1. SPECIAL MONITORING PINS
VCC CD1
1.1 CD1, CD2: Card Detection Pins CD1 and CD2 are to detect whether or not the card has been correctly inserted. (See Fig. 7.) When the memory card has been correctly inserted, CD1 and CD2 are detected by the system. CD1, CD2 are tied to ground on the card side as shown in Fig. 7.
(A)
VCC CD2 (B) system side card side
- Fig. 7 -
1.2 WP: Write Protect Pins This pin monitors the position of the Write Protect switch. As shown in Fig. 8, the Flash memory card has a Write Protect switch at the top of the card. To write to the card, the switch must be turned to the "Non Protect" position and the WE pin low. And at that time, L-level is output on the WP pin. To prevent writing to the card, the switch must be turned to the "Protect" position. At that time, H-level is output on the WP pin.
Non Protect Protect Flash Memory Card Write Protect Switch
WP Switch Protect Non Protect
WP (output) H L
- Fig. 8 -
s DEVICE HANDLING PRECAUTIONS
This device in composed of fine electronic parts, so take care in handling or keeping it as below. * The card is made fine,so do not keep it in the high temperature nor high humiditly, place like in the direct sunshine nor near the heater. * The card shoud not be bent, scratched, dropped nor be shocked violently. * This device shoud never be taken a part. It could destroy the card or your personal computer hardware. * To help you handle this device safely, request us the device specifications when purchasing this device.
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MB98A8113x-/8123x-/8133x-/8143x-20
s PACKAGE DIMENSIONS
68-PIN MEMORY CARD (CRD-68P-M05)
2-R1.00(.039) 1.600.05 (.063.002) 1.000.05 (.039.002) 14.50(.571) 41.91 (1.650) REF 1.000.05 (.039.002) "A" 1.000.05 (.039.002) 10.50(.413) 54.000.10 (2.126.004)
Note: Dimensions conform with "PC Card Standard 95"
85.600.20(3.370.008) 10.50(.413)
3.300.10(.130.004) Connector portion
3.300.20(.130.008) Card body
Details of "A" part 1.270.10(.050.004)TYP.
1PIN 1.270.10 (.050.004)
C
1997 FUJITSU LIMITED K68005SC-5-2
Dimensions in mm (inches)
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MB98A8113x-/8123x-/8133x-/8143x-20
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9706 (c) FUJITSU LIMITED Printed in Japan
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