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HAT2165H Silicon N Channel Power MOS FET Power Switching REJ03G0004-0500Z (Previous ADE-208-1632C (Z)) Rev.5.00 Apr.09.2003 Features * * * * * High speed switching Capable of 4.5 V gate drive Low drive current High density mounting Low on-resistance RDS(on) = 2.5 m typ. (at VGS = 10 V) Outline LFPAK 5 5 D 3 12 4 4 G 1, 2, 3 Source 4 Gate 5 Drain SSS 123 Rev.5.00, Apr.09.2003, page 1 of 10 HAT2165H Absolute Maximum Ratings (Ta = 25C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel to Case Thermal Resistance Channel temperature Storage temperature Symbol VDSS VGSS ID ID(pulse)Note1 IDR IAP Note 2 Ratings 30 20 55 220 55 30 90 30 4.17 150 -55 to +150 Unit V V A A A A mJ W C/W C C EAR Note 2 Pch Note3 ch-C Tch Tstg Notes: 1. PW 10 s, duty cycle 1% 2. Value at Tch = 25C, Rg 50 3. Tc = 25C Rev.5.00, Apr.09.2003, page 2 of 10 HAT2165H Electrical Characteristics (Ta = 25C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Gate Resistance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time Notes: 4. Pulse test Symbol Min V(BR)DSS 30 Typ -- -- -- -- -- 2.5 3.4 100 5180 1200 380 0.5 33 15 7.1 13 65 60 9.5 0.81 40 Max -- -- 10 1 2.5 3.3 5.3 -- -- -- -- -- -- -- -- -- -- -- -- 1.06 -- Unit V V A A V m m S pF pF pF nc nc nc ns ns ns ns V ns VDD = 10 V VGS = 4.5 V ID = 55 A VGS = 10 V, ID = 27.5 A VDD 10 V RL = 0.36 Rg = 4.7 IF = 55 A, VGS = 0 Note4 IF = 55 A, VGS = 0 diF/ dt = 100 A/ s Test Conditions ID = 10 mA, VGS = 0 IG = 100 A, VDS = 0 VGS = 16 V, VDS = 0 VDS = 30 V, VGS = 0 VDS = 10 V, I D = 1 mA ID = 27.5 A, VGS = 10 V Note4 ID = 27.5 A, VGS = 4.5 V VDS = 10 V VGS = 0 f = 1 MHz Note4 V(BR)GSS 20 IGSS IDSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss Rg Qg Qgs Qgd td(on) tr td(off) tf VDF trr -- -- 1.0 -- -- 60 -- -- -- -- -- -- -- -- -- -- -- -- -- ID = 27.5 A, VDS = 10 V Note4 Rev.5.00, Apr.09.2003, page 3 of 10 HAT2165H Main Characteristics Power vs. Temperature Derating 40 Pch (W) I D (A) Maximum Safe Operation Area 500 100 DC 10 30 PW Op 10 =1 era 1m 10 0 s s s 0m n Channel Dissipation 20 Drain Current tio s 10 1 Operation in this area is limited by R DS(on) 0.1 Tc = 25C 1 shot Pulse 0.01 0.1 0.3 1 3 10 30 100 Drain to Source Voltage V DS (V) 0 50 100 150 Tc (C) 200 Case Temperature Typical Output Characteristics 100 10 V 4.5 V Pulse Test 100 3.0 V (A) Typical Transfer Characteristics V DS = 10 V Pulse Test 80 I D (A) 80 2.8 V 60 2.6 V 40 2.4 V ID Drain Current 60 25C Tc = 75C -25C Drain Current 40 20 20 VGS = 2.2 V 0 2 4 6 Drain to Source Voltage 8 10 V DS (V) 0 1 2 3 Gate to Source Voltage 5 4 V GS (V) Rev.5.00, Apr.09.2003, page 4 of 10 HAT2165H Drain to Source Saturation Voltage vs. Gate to Source Voltage Pulse Test Static Drain to Source on State Resistance vs. Drain Current 10 Pulse Test V DS(on) (mV) 200 Drain to Source On State Resistance R DS(on) (m ) 250 5 VGS = 4.5 V 10 V 2 Drain to Source Voltage 150 I D = 50 A 100 20 A 10 A 0 4 8 12 Gate to Source Voltage 16 20 V GS (V) 50 1 1 3 10 100 300 30 Drain Current I D (A) 1000 Static Drain to Source on State Resistance R DS(on) (m ) Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance vs. Temperature 8 Pulse Test 6 I D = 10 A, 20 A 50 A 4 V GS = 4.5 V Forward Transfer Admittance vs. Drain Current 1000 300 100 30 10 3 1 0.3 0.1 0.1 0.3 1 3 V DS = 10 V Pulse Test 10 30 100 25C 75C Tc = -25C 2 10 V 0 -25 10 A, 20 A, 50 A 0 25 50 75 100 125 150 Case Temperature Tc (C) Drain Current I D (A) Rev.5.00, Apr.09.2003, page 5 of 10 HAT2165H Body-Drain Diode Reverse Recovery Time 100 Reverse Recovery Time trr (ns) Typical Capacitance vs. Drain to Source Voltage 10000 Ciss Capacitance C (pF) 3000 1000 300 100 30 10 0 5 10 15 20 VGS = 0 f = 1 MHz 25 30 Coss Crss 50 20 di / dt = 100 A / s V GS = 0, Ta = 25C 0.3 1 3 10 30 100 Reverse Drain Current I DR (A) 10 0.1 Drain to Source Voltage V DS (V) Dynamic Input Characteristics V DS (V) Switching Characteristics 16 V GS (V) 40 I D = 55 A VDD = 5 V 10 V 25 V V GS 12 1000 300 100 30 t d(on) 10 tr 3 V GS = 10 V , VDS = 10 V Rg = 4.7 , duty < 1 % tf t d(off) 30 V DD = 25 V 20 V DS 10 10 V 5V Drain to Source Voltage 8 4 0 20 40 60 80 Gate Charge Qg (nc) 0 100 Gate to Source Voltage Switching Time t (ns) 0.1 0.2 0.5 1 2 5 10 20 50 100 Drain Current I D (A) Rev.5.00, Apr.09.2003, page 6 of 10 HAT2165H Reverse Drain Current vs. Source to Drain Voltage Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating 100 I AP = 30 A V DD = 15 V duty < 0.1 % Rg > 50 100 (A) 80 Reverse Drain Current IDR 10 V 5V V GS = 0 80 60 60 40 40 20 Pulse Test 0 0.4 0.8 1.2 1.6 V SD (V) 2.0 20 0 25 Source to Drain Voltage 50 75 100 125 150 Channel Temperature Tch (C) Avalanche Test Circuit EAR = Avalanche Waveform 1 2 L * IAP2 * VDSS VDSS - V DD V DS Monitor L I AP Monitor V (BR)DSS I AP VDD ID V DS Rg Vin 15 V D. U. T 50 0 VDD Rev.5.00, Apr.09.2003, page 7 of 10 HAT2165H Normalized Transient Thermal Impedance vs. Pulse Width 3 Normalized Transient Thermal Impedance s (t) Tc = 25C 1 D=1 0.5 0.2 0.3 0.1 0.1 0.05 ch - c(t) = s (t) * ch - c ch - c = 4.17C/ W, Tc = 25C PDM 0.03 0.02 1 0.0 1s h D= PW T PW T p ot uls e 0.01 10 100 1m 10 m 100 m 1 10 Pulse Width PW (s) Switching Time Test Circuit Vin Monitor Rg D.U.T. RL Vin Vin 10 V V DS = 10 V Vout Monitor Switching Time Waveform 90% 10% 10% 90% td(on) tr 90% td(off) tf 10% Vout Rev.5.00, Apr.09.2003, page 8 of 10 HAT2165H Package Dimensions As of January, 2003 Unit: mm 4.9 5.3 Max 4.0 0.2 5 0.25 -0.03 +0.05 3.3 1.0 3.95 1 4 6.1 -0.3 +0.1 0 - 8 1.1 Max +0.03 0.07 -0.04 0.75 Max 1.27 0.10 *0.40 0.06 0.25 M 0.6 -0.20 1.3 Max +0.25 *0.20 -0.03 +0.05 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) LFPAK -- -- 0.080 g Rev.5.00, Apr.09.2003, page 9 of 10 4.2 HAT2165H Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.5.00, Apr.09.2003, page 10 of 10 |
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