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T DUC MENT E PRO ETE REPLAC enter at OL OBS ENDED pport C m/tsc Su MM l.co tersi ECO nical T Sheet NO R Data ech r www.in ur December 1995, Rev. G IL o act o cont -INTERS 1-888
EL2018
FN7024
Fast, High Voltage Comparator with Transparent Latch
The EL2018 represents a quantum leap forward in comparator speed, accuracy and functionality. Manufactured with Elantec's proprietary Complementary Bipolar process, this device uses fast PNP and NPN transistors in the signal path. A unique circuit design gives the inputs the ability to handle large common mode and differential mode signals, yet retain high speed and excellent accuracy. Careful design of the front end insures the part maintains speed and accuracy when operating with a mix of small and large signals. The three-state output stage is designed to be TTL compatible for any power supply combination, yet it draws a constant current and does not generate glitches. When the output is disabled, the supply current consumption drops by 50%, but the input stage and latch remain active. Elantec facilities comply with MIL-I-45208A and other applicable quality specifications. For information on Elantec's processing, see QRA1: Elantec's Processing-Monolithic Products.
Features
* Fast response time--20ns * Wide input differential voltage range--24V to 15V supplies * Precision input stage--VOS = 1mV * Low input bias current--IB = 100nA * Low input offset current--IOS = 30nA * 4.5V to 18V supplies * Three-State TTL and CMOS compatible output * No supply current glitch during switching * High voltage gain--40V/mV * 50% power reduction in shutdown mode * Input and latch remain active in shutdown mode * P/N compatible with industry standard comparators
Applications
* Analog to digital converters * ATE pin receiver
Ordering Information
PART NUMBER EL2018CN TEMP. RANGE -40C to +85C PACKAGE 8-Pin PDIP PKG. NO. MDP0031
* Precision crystal oscillators * Zero crossing detector * Window detector * Pulse width modulation generator * "Go/no-go" detector
Pinout
EL2018 (8-PIN PDIP) TOP VIEW
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL2018
Absolute Maximum Ratings (TA = 25C)
VS VIN VIN IIN IINS PD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS to -VS Differential Input Voltage . . . . Limited only by Power Supplies Input Current (Pins 1, 2 or 3) . . . . . . . . . . . . . . . . . . . . 10mA Input Current (Pins 5 or 6) . . . . . . . . . . . . . . . . . . . . . . . 5mA Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . .1.25W IOP IO TA TJ TST Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . 25mA Operating Temperature Range . . . . . . . . . . . .-40C to +85C Operating Junction Temperature Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . .-65C to +150C
The maximum power dissipation depends on package type, ambient temperature and heat sinking. See the Typical Performance curves for more details. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VOS
VS = 15V unless otherwise specified DESCRIPTION TEMP 25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN, TMAX 85 80 85 77 12 12 15 10 -0.05 -0.1 3.5 3.5 2.4 2.4 2.4 4.65 4.65 3.5 -0.3 2.0 2.2 -1 4.0 0.15 0.4 0.4 4.65 4.65 40 13 100 105 30 100 MIN TYP 1.0 MAX 5 7 400 600 150 250 UNITS mV mV nA nA nA nA dB dB dB dB V V V/mV V/mV V V V V V V V V V V V V V
Input Offset Voltage (Note 1) VCM = 0V, VO = 1.4V Input Bias Current VCM = 0V, Pin 2 or 3 Input Offset Current VCM = 0V Common Mode Rejection Ratio (Note 2)
IB
IOS
CMRR
PSRR
Power Supply Rejection Ratio (Note 3)
25C TMIN, TMAX
VCM
Common Mode Input Range
25C TMIN, TMAX
AV
Voltage Gain VOUT = 0.8V to 2.0V Output Voltage Logic Low IOL = 0mA to 8mA Output Voltage Logic High VS = 15V VS = 15V VS = 5V VS = 5V VS = 5V
25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN TMAX 25C TMIN, TMAX 25C ALL 25C TMIN, TMAX
VOL
VOH
VODIS1
VOUT Range, Disabled, IOL = -1mA
VS = 15V VS = 15V VS = 5V
VODIS2 VINH
VOUT Range, Disabled, IOL = 1 mA, VS = 5V to 15V LE or CS Inputs Logic High Input Voltage
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EL2018
DC Electrical Specifications
PARAMETER VINL VS = 15V unless otherwise specified (Continued) DESCRIPTION LE or CS Inputs Logic Low Input Voltage LE or CS Inputs Logic Input Current, VIN = 0V to 5V Positive Supply Current Enabled Positive Supply Current Disabled Negative Supply Current Enabled Negative Supply Current Disabled TEMP 25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN, TMAX 25C TMIN, TMAX 5.0 13.0 4.7 8.4 MIN TYP MAX 0.8 0.8 200 300 12 13 6 7 17 18 6.5 6.5 UNITS V V A A mA mA mA mA mA mA mA mA
IIN
IS+EN
IS+DIS
IS-EN
IS-DIS
NOTES: 1. VOUT = 1.4V. 2. VCM = 12V to -12V. 3. VS = 5V to 15V.
AC Electrical Specifications
PARAMETER TPD TS TH TUN TMPW TEN TDIS
VS = 15V, TA = 25C DESCRIPTION MIN TYP 20 6 -2 23 12 40 150 70 300 MAX 40 12 0 40 UNITS ns ns ns ns ns ns ns
Propagation Delay, 5mV Overdrive Setup Time Hold Time Unlatch Time Minimum Clock Pulse Width Output Three-State Enable Delay Output Three-State Disable Delay
3
EL2018 Typical AC Performance Curves
Propagation Delay (-) 5mV Overdrive Propagation Delay vs Overdrive
Propagation Delay vs Load Capacitance
Propagation Delay vs Temperature
Propagation Delay vs Input Step
Enabled/Disabled Time vs Temperature
4
EL2018 Typical AC Performance Curves
(Continued)
Input Bias Current vs Differential Input Voltage
Input Bias Current vs Temperature
Open-Loop Gain vs Frequency
CMRR vs Frequency
VO/VI Transfer Characteristic
VOUT vs Temperature
5
EL2018 Typical AC Performance Curve
VOH vs Positive Supply Voltage
(Continued)
VOL vs Positive Supply Voltage
Supply Current vs Temperature
Supply Current vs Supply Voltage
8-Pin Plastic DIP Maximum Power Dissipation vs Ambient Temperature
6
EL2018 Block Diagram
Function Table
INPUTS (TIME N-1) +IN + + X X -IN + + X X CS L L H H L H LE L L L L H H INTERNAL Q H L H L Qn-1 Qn-1
NOTES Normal Comparator Operation Internal Normal Comparator Operation Output Power Down Mode Data Retained in Latch Data Retained in Latch Power Down Mode
OUTPUT H L High Z High Z Qn-1 High Z
Application Hints
Device Overview
The EL2018 is the first comparator of its kind. It is capable of 24V differential signals, yet has excellent accuracy, linearity and voltage gain. It even has a three-state output feature that reduces the power supply currents 50% when the output is disabled, yet the input stage and latch remain active. This extremely fast and accurate device is built with the proprietary Elantec Complementary Bipolar Dielectric Isolation Process, which is immune to power sequencing and latch up problems.
The large common mode range (12V minimum) and differental voltage handling ability (24V min.) of the device make it useful in ATE applications without the need for an input attenuator with its associated delay.
Recovery from Large Overdrives
Timing accuracy is excellent for all signals within the common mode range of the device (12V with 15V supply). When the common mode range is exceeded the input stage will saturate, input bias currents increase and it may take as much as 200ns for the device to recover to normal operation after the inputs are returned to the common mode range. If signals greater than the common mode range of the device are anticipated, the inputs should be diode clamped to remain within the common mode range of the device.
Power Supplies
The EL2018 will work with 5V to 18V supplies or any combination between (Example +12V and -5V). The supplies should be well bypassed with good high frequency capacitors (0.1F monolithic ceramic recommended) close to the power supply leads. Good ground plane construction techniques enhance stability, and the lead from pin 1 to ground should be short.
Input Slew Rate
All comparators have input slew rate limitations. The EL2018 operates normally with any input slew rate up to 300V/s. Input signal slew rates over 300V/s induce offset voltages of 5mV to 20mV. This induced offset voltage settles out in about 20ns, 20 times faster than previous high voltage comparators.
Front End
The EL2018 uses schottky diodes to make a "bullet proof" front end with very low input bias currents, even if the two inputs are tied to very large differential voltages (24V). The transfer function of the EL2018 is linear, and the output is stable when in the linear region.
Latch
The EL2018 contains a "transparent" latch. A "transparent" latch acts as an amplifier when the LE input is low and it "latches" and holds the value it had just before the LE transition from low to high.
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EL2018
It is possible to make an oscillation resistant design by putting a short duration "0" on the LE input whenever you wish to make a comparison. This gates the comparator on only for a brief instant, long enough to compare, but not long enough to oscillate. The minimum duration of this pulse is specified by the minimum clock width parameter in the AC electrical tables. The CS input may be left floating and still produce a guaranteed logic "0" input (active). Floating the LE input will normally produce a logic "0" input also, but operation is not guaranteed. Proper RF technique suggests that these inputs be grounded or pulled to ground if they are not used. Due to the power saving feature and linear output stage, the EL2018 does not have a standard TTL three-state output stage. As such one must be careful when using the threestate feature with devices other than other EL2018s or EL2019s. When operating from 15V supplies the threestate feature is compatible with all TTL families, however CMOS families may conflict on high outputs. Since the output stage of the EL2018 turns on faster than it turns off, a 50 to 100 resistor in series with the output will limit fault currents between devices with minimum impact on logic drive capability.
System Design Considerations
The most common problem users have with high speed comparators is oscillations due to output to input feedback. This can be avoided by using a ground plane, proper supply bypassing, and routing the inputs and outputs away from each other. Since the EL2018 has a gain bandwidth product of about 40GHz, layout and bypassing are important to a successful system design. A unique alternative to the EL2018 is the EL2019, with its edge triggered master/slave flip flop.
Output Stage
The output stage of the EL2018 is a pair of complementary emitter followers operating as a linear amplifier. This makes the output stage of the EL2018 glitch free, and improves accuracy and stability when operating with small signals.
Three-State Output, Power Saving Feature
The EL2018 has an output stage which can be put into a high impedance "three-state" mode. When it is in this mode, the input stage and latch remain active, yet the device dissipates only 50% of the power used when the output is active. This has advantages in a large ATE system where there may be 1000 comparators, but only 10% are in use at any one time.
Device Functions
The various operating states of the EL2018 are described in the function table on page 7.
8
EL2018 Typical Applications
USING THE POWER DOWN/ THREE-STATE FEATURE POWER DISSIPATION VS AMBIENT TEMPERATURE
SERIES RESONANT CRYSTAL OSCILLATOR
A WIDE INPUT RANGE WINDOW COMPARATOR
USING THE EL2018 IN THE TRANSPARENT MODE (LATCH NOT USED)
VIN range +12V to -12V with VS = 15V
9
EL2018 Equivalent Schematic
Burn-In Circuit
PIN NUMBERS ARE FOR DIP PACKAGES. ALL PACKAGES USE THE SAME SCHEMATIC.
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EL2018 EL2018 Macromodel
* Connections: +input * | -input * | | +V * | | | -V * | | | | LE * | | | | | CS * | | | | || output * | | | | || | .subckt M2018 2384657 * * Input Stage * i1 8 10 700A r1 13 4 1K r2 14 4 1K q1 8 3 11 qn q2 8 2 12 qn q3 13 11 10 qp q4 14 12 10 qp i2 11 4 200A i3 12 4 200A * * 2nd Stage & Flip Flop * *i4 8 24 700A i4 8 24 1mA q9 22 6 24 qp q10 18 17 24 qp v1 17 0 2.5V q5 15 14 22 qp q6 16 13 22 qp r3 15 4 1K r4 16 4 1K q7 16 15 18 qp q8 15 16 18 qp * * Output Stage * i7 8 35 2mA s1 35 20 5 0 sw d2 35 8 ds i6 26 34 5mA s2 34 4 5 0 sw d3 34 26 ds q19 8 20 21 qn 2 q20 4 19 7 qp 2 r8 21 7 60 r7 20 19 4K q17 19 16 26 qn 5 q18 0 15 26 qn 5 q22 20 20 30 qn 5 EL2018 Macromodel * Connections:IN+IN+IN+IN+IN+IN+IN+IN+INININININ q23 19 19 30 qn 8 d1 0 19 ds q21 0 17 19 qp * * Power Supply Current *
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EL2018
ips 8 4 4mA * * Models * .model qn npn (is=2e-15 bf=400 tf=0.05nS cje=0.3pF cjc=0.2pF ccs=0.2pF) .model qp pnp (is=0.6e-15 bf=60 tf=0.3nS cje=0.5pF cjc=0.5pF ccs=0.4pF) .model ds d(is=2e-12 tt=0.05nS eg=0.62V vj=0.58) .model sw vswitch (von=0.4V voff=2.5V) .ends
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12

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