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SM9103M
NIPPON PRECISION CIRCUITS INC.
DVDRAM Head Amplifier LSI
OVERVIEW
The SM9103M is a photodiode photoelectric current-to-voltage conversion head amplifier LSI for optical disk pickups in DVDRAM/DVDROM equipment. It sums the photodiode current data signals and then converts the signals to a differential signal for output. The output tracking servo and focusing servo signals are derived from built-in sum and difference circuits, and the gain for these servo signals can be adjusted using serial interface controls. Each of the signals from the photodiodes, used to generate DPD (Differential Phase Detection) tracking servo signal, is current-to-voltage converted and then also output. It operates from a single 5 V supply, and is available in 36-pin plastic SSOP packages.
PINOUT
36-pin SSOP
(Top view)
MODE WRITE DGND DVCC TEMPO TEMPI T1 T2 T3 T4
1 2 3 4 5
36 35 34 33 32
SCLK SDATA SENB CALREQ TADD TADDB CAPAP CAPAN TSUB TSUBB DATAP DATAN DPDA DPDB DPDC DPDD AVCC AGND
SM9103M NPC
6 7 8 9 10 11 12 13 14 15 16 17 18
31 30 29 28 27 26 25 24 23 22 21 20 19
FEATURES
s
F1 F2
s s
s s s s s s s
s s s
RAM/ROM gain switching, low-noise RF signal generator (differential output) ROM tracking DPD signal output Variable-gain RAM tracking push-pull signal output Address signal, high-speed push-pull signal output Variable-gain focus error signal output Tracking PD sum signal output Focus PD sum signal output Offset correction timing output (logic) Temperature monitor function Serial interface to control internal parameter settings Sleep-mode function Single 5 V supply 36-pin plastic SSOP
AGND VREF FSUBB FSUB FADDB FADD
TYPICAL APPLICATIONS
s s
Double-speed DVDROM equipment Double-speed DVDRAM equipment
ORDERING INFORMATION
Device SM9103M Package 36-pin SSOP
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SM9103M
PACKAGE DIMENSIONS
(Unit: mm)
15.20 to 15.40 0.85 0.63 0.10
0 to 8
7
7.40 to 7.60
R0.63 to 0.89
0.51 0.20 45
0.51 to 1.01 DATAP DATAN TADDB TADD CAPAP CAPAN TSUBB TSUB DPDA DPDB DPDC DPDD CALREQ FSUB FSUBB FADDB FADD
0.23 to 0.32
0.29 to 0.39
0.80 0.10 to 0.30 2.44 to 2.64
BLOCK DIAGRAM
WRITE SDATA DGND MODE AGND
+5V
Serial interface to each block
T1 T2 T3 T4
Gain switching amplifier (RAM read/write, ROM read)
A+B+C+D (A+B)-(C+D)
Differential output buffer Amplifier
Analog Signal processor
A B C D
Differential output buffer Gain switch (2dB step)
Offset canceller
TEMPI TEMPO +5V
Thermal sensor Offset canceller Canceller control
Buffer Buffer Buffer Buffer
F1 F2
Gain switching amplifier
Analog Signal processor
Gain switch (2dB step) Amplifier
NIPPON PRECISION CIRCUITS--2
10.11 to 10.51
7 DVCC AVCC VREF
SENB
SCLK
SM9103M
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name MODE WRITE DGND DVCC TEMPO TEMPI T1 T2 T3 T4 F1 F2 AGND VREF FSUBB FSUB FADDB FADD AGND AVCC DPDD DPDC DPDB DPDA DATAN DATAP TSUBB TSUB CAPAN CAPAP TADDB TADD CALREQ SENB SDATA SCLK I/O1 Ipd Ipd - - O I I I I I I I - I I O I O - - O O O O O O I O O O I O O I I/O I Function Mode switching/offset correction control input 1 Mode switching/offset correction control input 2 Logic circuit ground. Connect to the analog ground if there is no dedicated pickup or logic ground. Logic circuit supply. Connect to the analog supply if there is no dedicated pickup or logic supply. Thermal sensor test output. Leave open for normal operation Thermal sensor test input. Leave open for normal operation Tracking PD input A Tracking PD input B Tracking PD input C Tracking PD input D Focus PD input E Focus PD input F Analog circuit ground 2.0 V reference voltage input Focus error signal feedback input Focus error signal output Focus sum signal feedback input Focus sum signal output Analog circuit ground Analog circuit supply Buffered tracking signal output D for DPD servo Buffered tracking signal output C for DPD servo Buffered tracking signal output B for DPD servo Buffered tracking signal output A for DPD servo Phase-modulated data signal differential inverting output Phase-modulated data signal differential non-inverting output Tracking push-pull signal feedback input Tracking push-pull signal output ID data signal differential inverting output ID data signal differential non-inverting output Tracking PD sum signal feedback input Tracking PD sum signal output Offset correction status/request output Serial interface enable input Serial interface data input/acknowledge output Serial interface clock input
1. I = input, Ipd = Input with built-in pull-down resistor, I/O = input/output, O = output
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SM9103M
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0 V
Parameter Supply voltage range Input voltage range Input current range Operating temperature range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol V CC V IN IIN Topr Tstg PD Tsld tsld Condition Rating -0.5 to 7.0 - 0.5 to V CC + 0.5 - 3.0 to +3.0 0 to 70 -40 to 125 250 260 10 Unit V V mA C C mW C s
Recommended Operating Conditions
GND = 0 V
Parameter Specs-guaranteed supply voltage range Operating supply voltage range Reference voltage input Operating temperature range Symbol V CC V CC V REF Topr Condition Rating 4.75 to 5.25 4.5 to 5.5 1.89 to 2.11 0 to 70 Unit V V V C
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SM9103M
DC Electrical Characteristics
VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter Symbol ICC1 ICC2 MODE, WRITE, SENB, SDATA, SCLK HIGH-level input voltage MODE, WRITE, SENB, SDATA, SCLK LOW-level input voltage MODE, WRITE HIGH-level input current SENB, SDATA, SCLK HIGH-level input current MODE, WRITE, SENB, SDATA, SCLK LOW-level input current CALREQ HIGH-level output voltage CALREQ LOW-level output voltage SDATA LOW-level output voltage VREF input current V IH V IL IIH1 IIH2 IIL VOH VOL1 VOL2 IREF V IN = V CC V IN = V CC V IN = 0 V IOH = -0.2 mA IOL = 0.8 mA IOL = 7 mA V REF = 2.0 V Condition min Current consumption1 Operating mode Sleep mode - - 0.8VCC - 50 - -3 V CC - 0.2 - - - typ 24 - - - 100 - - - - - - max 30 mA 1 - 0.2VCC 200 3 - - 0.4 1.0 250 V V A A A V V V A Unit
1. 18 k resistor connected between TSUB and TSUBB 47 k resistor connected between TADD and TADDB 22 k resistor connected between FSUB and FSUBB 27 k resistor connected between FADD and FADDB SENB, SDATA, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit.
Tracking PD Input Characteristics (T1, T2, T3, T4)
VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter Input impedance Input conversion noise current Pin voltage No signal RAM 100 kHz to 10 MHz ROM No signal read1 read1 Condition min - - - - typ - 0.035 0.27 - max 250 - - 1.5 A rms V Unit
1. DATAP - DATAN output difference operation when 10 pF capacitors are connected to T1, T2, T3, T4
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SM9103M
Data Signal Processor Characteristics
VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter DATAP -DATAN current-to-voltage converter coefficient1 CAPAP -CAPAN current-to-voltage converter coefficient2 DATAP, DATAN, CAPAP, CAPAN output impedance DATAP, DATAN, CAPAP, CAPAN output center voltage3 CAPAP, CAPAN output center voltage difference3 DATAP, DATAN, CAPAP, CAPAN output operating output voltage Variable coefficient switching time Saturation output reset time4 DATAP, DATAN signal bandwidth5 CAPAP, CAPAN signal bandwidth5 DATAP -DATAN, CAPAP -CAPAN gain peaking5 DATAP -DATAN, CAPAP -CAPAN group delay time5 1. 2. 3. 4. 5. No signal No signal 10 k load, output center voltage reference RAM ROM read RAM write RAM read f = 100 kHz -3 dB frequency f = 100 kHz -3 dB frequency f = 100 kHz -3 dB frequency f = 1 to 10 MHz RAM read ROM read RAM read Condition min 10.0 2.50 11.3 - 0.9VREF - -0.7 - - 19 20 -3 - typ 12.5 3.12 14.1 - - - - - - - - - - max 15.0 3.74 16.9 100 1.1VREF 50 +0.7 10 500 - - +0.5 1.0 k k V mV V ms ns MHz MHz dB ns Unit
[DATAP - DATAN] = K x [IT1 + IT2 + IT3 + IT4] [CAPAP - CAPAN] = K x {[IT1 + IT2] - [IT3 + IT4]} 5 k load connected to ground to prevent abnormal operation Converging to within final value 10% 10 pF input load capacitors connected to T1, T2, T3, T4. DATAP, DATAN, CAPAP, CAPAN output load conditions shown below.
0.01F DATAP 5pF 5pF CAPAP
0.01F 10pF 5pF
10k
10k
0.01F DATAN 5pF 5pF CAPAN
0.01F 10pF 5pF
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SM9103M
Tracking Signal Processor Characteristics
VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter RAM read TSUB current-to-voltage converter coefficient1 ROM read RAM write RAM read TADD current-to-voltage converter coefficient2 ROM read RAM write DPDA, DPDB, DPDC, DPDD current-to-voltage converter coefficient3 T1, T2, T3, T4 converter coefficient relative error TSUB, TADD, DPDA, DPDB, DPDC, DPDD output impedance TSUB operating output voltage TADD, DPDA, DPDB, DPDC, DPDD operating output voltage Converter coefficient switching time TSUB, TADD signal bandwidth4 DPDA, DPDB, DPDC, DPDD signal bandwidth4 TSUB, TADD gain peaking4 DPDA, DPDB, DPDC, DPDD gain peaking4 TSUB phase response4 DPDA, DPDB, DPDC, DPDD group delay4 10 k load connected to VREF 10 k load connected to VREF RAM read ROM read RAM write RAM read DC to -3 dB frequency f = 100 kHz to -3 dB frequency f = 10 kHz to -3 dB frequency f = 100 kHz to -3 dB frequency @ f = 100 kHz f = 1 to 5 MHz group delay differential absolute value Relative error between 4 pins RAM read/write max gain No input signal, V REF reference, post-correction, Ta = 25C, R f = 18 k RAM read, min to max gain RAM read/write differential gain max. ROM read, gain min/max TADD offset voltage DPDA, DPDB, DPDC, DPDD offset voltage TSUB offset voltage temperature coefficient TSUB variable gain range TSUB variable gain step width No input signal, V REF reference No input signal, V REF reference R f = 18 k RAM read ROM read RAM/ROM read RAM read ROM read TSUB output, RAM/ROM read R f = 47 k R f = 18 k, VOUT = V REF 0.8 V Condition min 10.64 2.67 1.78 27.82 6.95 4.63 40.0 10.0 - - 1 V REF - - 1 5 -3 -3 - - - - - - - - - -550 - -16 - typ 11.95 2.99 1.99 31.25 7.80 5.20 50.0 12.5 - - - - - - - - - - - - - - - - - - - - - - 2 max 13.26 9.92 2.20 34.68 8.65 5.77 60.0 k 15.0 2 100 3 3 10 3 - - +0.5 +4.0 10 5 ns 1.0 10.0 26 mV 4 100 30 mV 300 +50 0.4 +14 - mV mV/C dB dB % V V ms s MHz MHz dB dB k k Unit
TSUB offset voltage
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SM9103M
Rating Parameter VOUT = V REF 0.8 V Condition min TSUB gain switching absolute accuracy 1. 2. 3. 4. -16 to +8 dB +10 to +14 dB - - typ - - max 0.5 dB 1.0 Unit
TSUB = K x {[IT1 + IT2] - [IT3 + IT4]}, gain = 0 dB TADD = K x [IT1 + IT2 + IT3 + IT4] DPDA = K x IT1, DPDB = K x IT2, DPDC = K x IT3, DPDD = K x IT4 T1, T2, T3, T4: 10 pF input load capacitance TSUB, TADD, DPDA, DPDB, DPDC, DPDD: 10 pF output load capacitance TSUB, TADD: 10 k load resistance DPDA, DPDB, DPDC, DPDD: 100 k load resistance
Focus PD Input Characteristics (F1, F2) VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter Input impedance No signal RAM Input conversion noise current DC to 10 kHz ROM RAM Pin voltage No signal, V REF reference read1 read1 write1 Condition min - - - - - typ - - - - - max 250 24 96 150 50 mV nArms Unit
1. Conversion from FSUB output noise value when 14 pF capacitors connected to F1 and F2
Focus Signal Processor Characteristics VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter RAM read FSUB current-to-voltage converter coefficient1 ROM read RAM write RAM read FADD current-to-voltage converter coefficient2 F1, F2 converter coefficient relative error FSUB, FADD output impedance FSUB operating output voltage FADD operating output voltage Converter coefficient switching time FSUB, FADD signal bandwidth3 FSUB, FADD gain peaking3 response3 10 k load connected to VREF 10 k load connected to VREF RAM read ROM read RAM write RAM read DC to -3 dB frequency f = 10 kHz to -3 dB frequency @ f = 10 kHz ROM read RAM write FSUB output, RAM/ROM read R f = 27 k R f = 22 k, VOUT = V REF 0.35 V Condition min 370 94 58 223 56.1 35.6 - - 1 V REF - - 200 -3 - typ 415 105 65 250 63 40 - - - - - - - - - max 460 116 72 277 69.9 44.1 2 100 3 3 10 3 - +0.5 5 % V V ms s kHz dB k k Unit
FSUB, FADD phase
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SM9103M
Rating Parameter Condition min RAM read/write, ROM read max gain RAM read, min to max gain RAM read/write differential gain max. - - - - - -16 - VOUT = V REF 0.35 V -16 to +8 dB +10 to +14 dB - - typ - - - - - - 2 - - max 7.0 21 4 50 0.22 +14 - 0.5 dB 1.0 mV mV/C dB dB mV Unit
FSUB offset voltage
No input signal, V REF reference, post-correction, Ta = 25C
FADD offset voltage FSUB offset voltage temperature coefficient FSUB variable gain range FSUB variable gain step width FSUB gain switching absolute accuracy
No input signal, VREF reference
1. FSUB = K x [IF1 - IF2], gain = 0 dB 2. FADD = K x [IF1 + IF2] 3. F1, F2: 14 pF input load capacitance FSUB, FADD: 10 pF output load capacitance, 10 k load resistance
Mode Control Logic
Control input Operating mode WRITE LOW or open LOW or open HIGH HIGH MODE LOW or open HIGH LOW or open RAM write HIGH Inactive RAM read ROM read Active Offset correction
Offset Correction Characteristics
VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter TSUB offset residual FSUB offset residual Supply voltage droop detect level Correction circuit startup supply voltage V 1 and V 2 difference Correction thermal sensor detect temperature Offset correction time V1 V2 V2 - V1 Symbol Condition min V REF reference, Ta = 25 C V REF reference, Ta = 25 C - - 1.9 3.2 0.7 15 - typ - - 2.8 3.8 1.0 20 - max 8.5 5.5 3.7 4.4 1.3 25 150 mV mV V V V C ms Unit
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SM9103M
Serial Interface Characteristics
VCC = 5 V 5%, GND = 0 V, Ta = 0 to 70 C
Rating Parameter SCLK pulse cycle SCLK HIGH-level pulsewidth SCLK LOW-level pulsewidth SENB setup time SENB hold time SDATA setup time SDATA hold time ACK setup time1 ACK hold time1 SENB interval Symbol tcySCK twhSCK twlSCK tsSEN thSEN tsSDA thSDA tsACK thACK tinSEN Condition min 100 40 40 20 40 15 15 0 - 100 typ - - - - - - - - - - max - - - - - - - 20 50 - ns ns ns ns ns ns ns ns ns ns Unit
1. ACK is the acknowledge output (n-channel open-drain). LOW-level output when the data received is valid. SDATA load capacitance is 15 pF.
tinSEN SENB tsSEN twhSCK twlSCK tcySCK SCLOCK tsSDA thSDA SDATA bit 0 LSB bit 1 bit 15 MSB ACK High Impedance tsACK thSEN
thACK
Controller SDATA Port
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SM9103M
FUNCTIONAL DESCRIPTION
Serial Interface
The SM9103M uses a serial interface comprising 2 ports to control and set TSUB/FSUB output gain switching, sleep mode to reduce current consumpTable 1. Port address and bit configuration1
Bit number 15 14 13 12 Data MSB TG3 SL1 TG2 CS1 TG1 - TG0 - FG3 - FG2 - FG1 - FG0 - x x LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH x x 11 10 9 8 7 6 5 4 3 2 1 0
tion, and TSUB/FSUB offset correction. The address and bit configuration of each port is shown in table 1.
Address LSB x x
1. x = don't care, - = unassigned TG3 to TG0: TSUB gain set bits. Default = 0111 (0 dB) FG3 to FG0: FSUB gain set bits. Default = 0111 (0 dB) SL1: sleep mode set bit. Sleep mode when 1, normal operation when 0. Default = 0. CS1: offset correction control. Offset correction when 1, normal operation when 0. Default = 0.
Serial data is input on SDATA with the LSB first in sync with the falling edge of the SCLK clock. After the 16th SCLK falling edge and 16 bits of valid data has been input, the SDATA n-channel open-drain output goes LOW to perform the function of an acknowledge signal. If the number of SCLK cycles which occur when SENB (serial interface enable) is HIGH is less than
16, the received data is ignored and the internal port is not updated. If the number of SCLK cycles is greater than 16, the data is still considered value up to the 16th SCLK falling edge, the data is latched into the internal port, and the acknowledge signal is output. The acknowledge signal is held until SENB goes LOW again.
Data Signal Processor
This stage creates the data signal and ID signal for output. The weak current from the tracking PD cells (T1, T2, T3, T4) are input to the front-end amplifier where the signals are current-to-voltage converted at fixed gain. The gain setting is controlled by pins WRITE and MODE. WRITE switches between read/write, and MODE switches the gain between values corresponding to high-reflectivity and low-reflectivity discs. These signals control the settings for RAM (low-reflectivity disc) read/write and ROM (high-reflectivity disc) read. The front-end amplifier outputs are processed by the signal processor block to generate intermediate signals. The data signal, (A + B + C + D), is converted to a difference signal by a differential output buffer and output on DATAP and DATAN. The ID signal, generated from the difference between 2 signals, (A + B) and (C + D), is converted to a difference signal by a differential output buffer and output on CAPAP and CAPAN. The data signal (DATAP, DATAN) and ID signal (CAPAP, CAPAN) DC components are removed using output stage capacitive networks. T1, T2, T3 and T4 have a hold function to provide the appropriate reverse bias required by the tracking PD to ensure the data read bandwidth.
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SM9103M
Tracking Signal Processor
The tracking stage generates the push-pull tracking error signal and output signal for DPD servo, as well as a push-pull sum signal used as an auxiliary signal. The [(A + B) - (C + D)] signal from the common-data front-end amplifier and signal processor block is sent to the gain switching block. The gain switching block amplifies the difference signal using one of 16 preset gain settings in 2 dB steps to form a push-pull signal output on TSUB. A feedback resistor connected to TSUBB is used to ensure gain setting stability. The gain of the gain switching block is controlled by serial interface control bits as shown in table 2. Each signal from T1, T2, T3, T4 is buffered and then output on DPDA, DPDB, DPDC, DPDD, respectively, for DPD servos. The auxiliary signal is generated from the push-pull sum signal (A + B + C + D). This signal is buffered (TAB) and output on TADD. A feedback resistor connected to TADDB is used to ensure gain setting stability.
Table 2. TSUB gain setting
TG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1. Default is 0 dB TG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB)1 +14 +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 -14 -16
Focus Signal Processor
The focus stage generates the focus error signal from the focus PD, and a sum signal. The weak focus PD current signals (F1, F2) are input to the front-end amplifier and then current-to-voltage converted at fixed gain. The front-end amplifier output is sent to the signal processor block where the focus error signal (F1 - F2) and the sum signal (F1 + F2) are generated. The focus error signal is sent to the gain switching block. The gain switching block amplifies the difference signal using one of 16 preset gain settings in 2 dB steps with output on FSUB. A feedback resistor connected to FSUBB is used to ensure gain setting stability. The gain of the gain switching block is controlled by serial interface control bits as shown in table 3. The sum is buffered and output on FADD. A feedback resistor connected to FADDB is used to ensure gain setting stability.
Table 3. FSUB gain setting
FG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1. Default is 0 dB FG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB)1 +14 +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 -14 -16
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SM9103M
Offset Correction
The SM9103M has built-in offset correction circuits for tracking and focus. During offset correction, the internal the device operates in RAM read mode, and FSUB and TSUB operate at maximum gain (+14 dB). The outputs on FSUB, FADD and TSUB are indeterminate. Also, inputs T1, T2, T3, T4 and F1, F2 may be ignored. After correction is complete, the FSUB and TSUB gain settings return to their default values (0 dB). Offset correction is performed under the following conditions:
s s
If the voltage falls below 2.8 0.9 V during offset correction, then correction stops and does not restart until the supply recovers to above 3.8 0.6 V. During offset correction, the CALREQ output is held HIGH. CALREQ goes LOW after correction stops. The SM9103M also incorporates a temperature detect function which detects temperature changes of 20 5 C from the time the initial correction is performed. If a temperature change is detected, CALREQ goes HIGH and the device waits for an offset correction instruction. Note that when both WRITE and MODE are HIGH, offset correction is inactive and the output appears uncorrected. However, if a correction start condition occurs when correction is inactive, such as the correction flag CS1 set to 1, then correction operation is initiated internally but does not appear at the output unless correction is activated prior to correction operation finishing. Once correction has been made inactive, the output remains uncorrected even if correction is subsequently reactivated. In this case, the output remains uncorrected until a valid correction start condition is detected.
s s
When power is applied. When the supply drops below 2.8 0.9 V and then rises to above 3.8 0.6 V. When sleep mode operation is cancelled. When the serial interface bit CS1 is 1. Note that if SL1 is also 1, then SL1 has priority.
Table 4. Offset correction setting
CS1 0 1 1. Default is No correction Offset correction1 No correction Correction
Sleep Mode
The SM9103M features a sleep mode which can be used when the device is not operating to significantly reduce current consumption. The sleep mode is controlled by serial interface bit SL1.
Table 5. Sleep mode settings
SL1 LOW HIGH 1. Default is OFF Sleep mode1 OFF ON Mode description Normal operation Sleep condition
Preset Function
When power is applied or after offset correction, all serial interface flags are reset to their default values. Flags TG3 to TG0 and FG3 to FG0 are also set to their default values in sleep mode.
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SM9103M
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9806AE 1998.12
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS--14

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