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SI5010
OC-12/3, STM-4/1 SONET/SDH CLOCK
Features
Complete CDR solution includes the following:
! ! ! ! !
AND
DATA RECOVERY IC
Supports OC-12/3, STM-4/1 Low Power, 293 mW (TYP OC-12) Small Footprint: 4 mm x 4 mm DSPLLTM Eliminates External Loop Filter Components 3.3 V Tolerant Control Inputs
! ! ! ! !
Exceeds All SONET/SDH Jitter Specifications Jitter Generation 1.6 mUIRMS (TYP) Device Power Down Loss-of-Lock Indicator Single 2.5 V Supply
Ordering Information: See page 14.
Applications
! ! ! !
CLKOUT+
17
Description
The SI5010 is a fully integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data rates. DSPLLTM technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance in the application. The SI5010 represents an industry-leading combination of low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (-40C to 85C).
RE XT VD D GND RE FCLK+ RE FCLK- 1 2 3 4 5
20
19
18
16 15 14 PW R DN/CA L VD D DO UT+ DO UT- VD D
G ND Pad
CLKOUT-
13 12 11 10
RATESEL
7
6
GND
8
SONET/SDH/ATM Routers Add/Drop Multiplexers Digital Cross Connects Board Level Serial Links
! ! !
SONET/SDH Test Equipment Optical Transceiver Modules SONET/SDH Regenerators
Pin Assignments SI5010
NC
S
9
LO L
GND
VDD
DIN+
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Top View
Functional Block Diagram
LO L
D IN + D IN -
2
BUF
DSPLL TM Phase-Locked Loop
Retim er
BUF
2
D O U T+ D O U T- P W R D N /C A L
Bias
2
BUF
2
C LK O U T+ C LK O U T-
REXT
RATESEL
REFC LK+ REFC LK-
Preliminary Rev. 0.31 4/01
Copyright (c) 2001 by Silicon Laboratories
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
DIN-
SI5010-DS031
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2
Preliminary Rev. 0.31
SI5010 TA B L E O F CON T E N T S
Section Page
4 5 9 9 9 9 9 9 10 10 10 11 11 12 14 15 16
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLLTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.31
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Detailed Block Diagram
R e tim e
DOUT+ DOUT-
c
D IN + D IN -
Phase D e te c to r
A /D
DSP n
VCO
CLK D ivid e r
CLKOUT+
c
CLKOUT-
REFCLK+ REFCLK- Lock D e te c to r
LOL
RATES EL REXT
B ias G en e ra tio n C a lib ratio n
P W R D N /C A L
Figure 1. Detailed Block Diagram
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Preliminary Rev. 0.31
SI5010
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature SI5010 Supply Voltage2 Symbol TA VDD Test Condition Min1 -40 2.375 Typ 25 2.5 Max1 85 2.625 Unit C V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. 2. The SI5010 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 8.
V SIGNAL + Differential V ICM , V O CM SIGNAL - I/Os V IS
(SIGNAL +) - (SIGNAL -) Differential Voltage Swing V ID ,V O D Differential Peak-to-Peak Voltage t
Figure 2. Differential Voltage Measurement
tC-D DOUT
CLKOUT
Figure 3. Clock to Data Timing
DOUT, CLKOUT tF tR
80% 20%
Figure 4. DOUT and CLKOUT Rise/Fall Times
Preliminary Rev. 0.31
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Table 2. DC Characteristics
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter Supply Current OC-12 OC-3 Power Dissipation OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK) Input Voltage Range* (DIN+, DIN-, REFCLK+, REFCLK-) Differential Input Voltage Swing* (DIN, REFCLK) Input Impedance (DIN, REFCLK) Differential Output Voltage Swing (DOUT) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (DOUT,CLKOUT) Output Impedance (DOUT,CLKOUT) Output Short to GND (DOUT,CLKOUT) Output Short to VDD (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Leakage Current
Symbol IDD
Test Condition
Min -- --
Typ 117 124 293 310 .80 VDD
"
Max 127 134 333 352 -- 750 1500 116 TBD TBD -- 116 TBD -- .8 -- 10 10 0.4 -- -- TBD
Unit mA
PD -- -- VICM VIS VID RIN VOD VOD VOCM ROUT ISC(-) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN VPWRDN 0.8 V IO = 2 mA IO = 2 mA varies with VDD See Figure 2 See Figure 2 Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line Single-ended -- -- 200 84 TBD TBD -- 84 -- TBD -- 2.0 -- -- -- 2.0 10 TBD mW V mV mV (pk-pk) mV (pk-pk) mV (pk-pk) V mA mA V V A A V V k A
-- -- 100 940 900 VDD - 0.7 100 25 -15 -- -- -- -- -- -- -- 25
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min) and the unused input must be tied to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (DIN+, DIN-, REFCLK+, or REFCLK-) must not exceed the specified maximum Input Voltage Range (VIS max).
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Preliminary Rev. 0.31
SI5010
Table 3. AC Characteristics (Clock & Data)
(VA 2.5 V 5%, TA = -40C to 85C)
Parameter Output Clock Rate Output Rise Time Output Fall Time Clock to Data Delay OC-12 OC-3 Input Return Loss
Symbol fCLK tR tF t(c-d)
Test Condition Figure 4 Figure 4 Figure 3
Min .15 -- -- -- --
Typ -- 100 100 890 4100 --
Max 666 TBD TBD TBD TBD --
Unit MHz ps ps ps ps dB
100 kHz-622 MHz
18.7
Table 4. AC Characteristics (PLL Characteristics)
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter Jitter Tolerance (OC-12 Mode)
*
Symbol JTOL(PP)
Test Condition f = 30 Hz f = 300 Hz f = 25 kHz f = 250 kHz
Min 40 4 4 0.4 40 4 4 0.4 -- -- -- -- -- 1.45 40 40 19.44 -100 TBD
Typ TBD TBD TBD TBD TBD TBD TBD TBD 1.6 25 -- -- .03 1.5 60 50 -- 600
Max -- -- -- -- -- -- -- -- 3.0 55 500 130 0.1 1.7 150 60 155.52 100 TBD
Unit UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP mUI mUI kHz kHz dB ms s % MHz ppm ppm
Jitter Tolerance (OC-3 Mode)
*
JTOL(PP)
f = 30 Hz f = 300 Hz f = 6.5 kHz f = 65 kHz
RMS Jitter Generation* Peak-to-Peak Jitter Generation Jitter Transfer Bandwidth Jitter Transfer Peaking Acquisition Time
* *
JGEN(RMS) with no jitter on serial data JGEN(PP) JBW JP TAQ with no jitter on serial data OC-12 Mode OC-3 Mode f < 2 MHz After falling edge of PWRDN/CAL From the return of valid data
Input Reference Clock Duty Cycle Reference Clock Range Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock)
CDUTY CTOL LOL
LOCK
TBD
300
TBD
ppm
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 -1 data pattern.
Preliminary Rev. 0.31
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Table 5. Absolute Maximum Ratings
Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k) TJCT TSTG Symbol VDD VDIG VDIF Value -0.5 to 2.8 -0.3 to 3.6 -0.3 to (VDD+ 0.3) 50 -55 to 150 -55 to 150 300 1 Unit V V V mA C C C kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Thermal Resistance Junction to Ambient Symbol JA Test Condition Still Air Value 38 Unit C/W
LVTTL Control Inputs
Loss-of-Lock Indicator
PWRDN/CAL
RATESEL
High Speed Serial Input
DIN+ DIN-
LOL
DOUT+ DOUT-
Recovered Data
SI5010
System Reference Clock REFCLK+ REFCLK- CLKOUT+ CLKOUT- Recovered Clock
REXT
10 k (1%)
VDD
0.1 F 2200pF 20pF
Figure 5. SI5010 Typical Application Circuit
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Preliminary Rev. 0.31
GND
VDD
SI5010
Functional Description
The SI5010 utilizes a phase-locked loop (PLL) to recover a clock synchronous to the input data stream. This clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (CML) drivers. Optimal jitter performance is obtained by using Silicon Laboratories' DSPLLTM technology to eliminate the noise entry points caused by external PLL loop filter components.
Table 7. Data-Rate Configuration
RATESEL 0 1 SONET/SDH 622.08 Mbps 155.52 Mbps
Reference Clock Detect
The Si5020 uses the reference clock to center the VCO operating frequency so that clock and data can be recovered from the input data stream. The VCO operates at an integer multiple of the REFCLK frequency. (See "Lock Detect" section.) The device will self configure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The REFCLK frequency should be 19.44 MHz, 77.76 MHz, or 155.52 MHz with a frequency accuracy of 100 ppm.
DSPLLTM
The phase-locked loop structure (shown in Figure 1 on page 4) utilizes Silicon Laboratories' DSPLL technology to eliminate the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated thus making the DSPLL less susceptible to board-level noise sources that make SONET/SDH jitter compliance difficult to attain.
Lock Detect
The SI5010 provides lock-detect circuitry that indicates whether the DSPLL has frequency locked with the incoming data signal (DIN). The circuit compares the frequency of a divided down version of the CLKOUT output with the frequency of the supplied reference clock. If the divided CLKOUT frequency deviates from that of the reference clock by the amount specified in Table 4 on page 7, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. While out of lock, the DSPLL will try to reacquire lock with the input data. During reacquisition, the clock output (CLKOUT) will drift over a range of approximately 1% relative to the supplied reference clock. The LOL output will remain asserted until the divided clock output frequency differs from the REFCLK frequency by less than the amount specified in Table 4.
Note: LOL is not asserted during PWRDN/CAL.
PLL Self-Calibration
The Si5020 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 V when calibration occurs. For best performance, the user should force a self-calibration once the supply has stabilized on power-up. A self-calibration can be initiated by forcing a high-to-low transition on the power-down control input, PWRDN/CAL, while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL input should be held high at least 1 S before transitioning low to guarantee a self-calibration. Several application circuits that could be used to initiate a power-on self-calibration are provided in Silicon Laboratories application note AN42.
PLL Performance
The PLL implementation used in the SI5010 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. Jitter Tolerance The SI5010's tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 6. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device.
Multi-Rate Operation
The SI5010 supports clock and data recovery for OC-12/3 and STM-4/1 data streams. Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the desired data rate. The RATESEL configuration and associated data rates are given in Table 7.
Preliminary Rev. 0.31
9
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Sinusoidal Input Jitter (UI p-p)
Jitter Transfer
S lo p e = 2 0 d B /D e c a d e
15 1.5 0.15
0.1 dB Acceptable Range
20 dB/Decade Slope
f0
f1
f2
Frequency
f3
ft Fc Frequency F3 (kHz) 25 6.5 Ft (kHz) 250 65
SONET Data Rate OC-12 OC-3
F0 (Hz) 10 10
F1 (Hz) 30 30
F2 (Hz) 300 300
SONET D ata R ate
Fc (kH z)
OC-12 OC-3
500 130
Figure 6. Jitter Tolerance Specification
Jitter Transfer The SI5010 is fully compliant with the relevant Bellcore/ ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency (see Figure 7). These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 6. Jitter Generation The SI5010 meets all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The SI5010 typically generates less than 1.6 mUIRMS of jitter when presented with jitter-free input data.
Figure 7. Jitter Transfer Specification
Power Down
The SI5010 provides a power down pin, PWRDN/CAL, that disables the device. When the PWRDN/CAL pin is driven "high", the positive and negative terminals of CLKOUT and DOUT are each tied to VDD through 100 on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant serial channels. When PWRDN/CAL is released (set to "low") the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the data stream.
Note: LOL is not asserted when the device is in the power down state.
Device Grounding
The SI5010 uses the GND pad on the bottom of the 20-pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location.
Bias Generation Circuitry
The SI5010 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k (1%) resistor connected between REXT and GND.
10
Preliminary Rev. 0.31
SI5010
Differential Input Circuitry
The SI5010 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 8. In applications where direct DC coupling is possible, the 0.1 F capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6.
Differential Output Circuitry
The SI5010 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with AC coupling is shown in Figure 9. In applications in which direct DC coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6.
Differential Driver
SI5010 VDD
2.5 k 0.1 F Zo = 50 D IN +, REFC LK+
10 k 0.1 F Zo = 50 D IN -, REFC LK-
2.5 k
102
10 k
GND
Figure 8. Input Termination for DIN and REFCLK (AC Coupled)
SI5010 VDD
100
VDD
50
DOUT+, CLKOUT+
0.1 F
Zo = 50
DOUT-, CLKOUT-
0.1 F
Zo = 50
100
VDD
50
VDD
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
Preliminary Rev. 0.31
11
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Pin Descriptions: SI5010
CLKO UT+ 17
20 REXT VDD G ND REFCLK+ REFCLK- 1 2 3 4 5 6 LO L
19
18
16 15 14 PW RDN/CAL VDD DO UT+ DO UT- VDD
GND Pad
CLKO UT- 13 12 11 10 DIN-
RATESEL 7 VDD
G ND 8 G ND
NC
9 DIN+
Top View
Figure 10. SI5010 Pin Configuration
Table 8. SI5010 Pin Descriptions
Pin # 1 Pin Name REXT I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 k (1%) resistor. 2, 7, 11, 14 3, 8, 18, and GND Pad VDD GND 2.5 V GND Supply Voltage. Nominally 2.5 V. Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 11) must be connected directly to supply ground. REFCLK+, REFCLK- I See Table 2 Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. Additionally, the reference clock is used to derive the clock output when no data is present. O LVTTL Loss of Lock. This output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 7. 9, 10 DIN+, DIN- I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins.
4, 5
6
LOL
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Preliminary Rev. 0.31
SI5010
Table 8. SI5010 Pin Descriptions (Continued)
Pin # 12, 13 Pin Name DOUT-, DOUT+ I/O O Signal Level CML Description Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT. I LVTTL Power Down. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a high-to-low transition on this pin. (See "PLL Self-Calibration" on page 9.)
Note: This input has a weak internal pulldown.
15
PWRDN/CAL
16, 17
CLKOUT-, CLKOUT+
O
CML
Differential Clock Output. The output clock is recovered from the data signal present on DIN. In the absence of data, the output clock is derived from REFCLK.
19
RATESEL
I
LVTTL
Data Rate Select. This pin configures the onboard PLL for clock and data recovery at one of two user selectable data rates. See Table 7 for configuration settings.
Note: This input has a weak internal pulldown.
20
NC
No Connect. This pin should be tied to ground.
Preliminary Rev. 0.31
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Ordering Guide
Table 9. Ordering Guide Part Number SI5010-BM Package 20-pin MLP Temperature -40C to 85C
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Preliminary Rev. 0.31
SI5010
Package Outline
Figure 11 illustrates the package details for the SI5010. Table 10 lists the values for the dimensions shown in the illustration.
TO P VIEW
A D D /2 10 0 .0 5 D1 A A1 D 1 /2 2X N 0 .2 5 C B 4X P 5 6 1 0 .5 0 D IA . 2 3 E1 E 4X Q E 1 /2 E /2 1 2 3 (N e-1 )X e E2 REF. A2 A3 N R D2 D 2 /2 8. C 4X P b 4 0 .1 0
M
2X 0 .2 5 C A
BO TTO M VIEW
CA B
E 2 /2 L 0 .2 0 2X C B B 0 .2 0 2X b 4 C C L C C L A1 11 C A 0 e S E A T IN G PLANE (N d -1 )X e REF.
C
NO TES: 1. 2. DIE THICKNESS ALLO W ABLE IS 0.305mm MA XIMUM(.012 INCHES MAXIMUM ) DIMENSIO NING & TO LERANCES CO NFO RM T O ASME Y14.5M. - 1994. N IS THE NUMB ER O F TERMINALS. Nd IS THE NUM BER O F TERMINALS IN X-DIR ECTIO N & Ne IS THE NUM BER O F TERMINALS IN Y-DIR ECTIO N. DIMENSIO N b A PPLIES TO PLATED TERMINA L AND IS MEASURED BETW EEN 0.20 AND 0.25mm FRO M TERMINA L TIP.
SEC TIO N "C -C "
SCALE: NONE
3.
e
e
4.
T E R M IN A L T IP
5.
FO R EVEN TER M IN AL/SID E
THE PIN #1 IDE NTIFIER MUST BE EXISTED O N THE TO P SURFACE O F THE PACKAG E BY U SING INDENTATIO N MARK O R O THER FEATURE O F PACKA G E BO DY.
FO R O D D TER M IN AL/SID E
6. 7. 8. 9. 10.
EXACT SHAPE AND SIZE O F THIS FEATURE IS O PTIO NAL. ALL DIMENSIO N S ARE IN MILLIMETERS. THE SHAPE SH O W N O N FO UR CO RNERS AR E NO T ACTUAL I/O . PACKAG E W AR PAG E MAX 0.05mm. APPLIED FO R E XPO SED PAD AND TERMINAL S. EXCLUDE EMB EDDING PART O F EXPO SED PAD FRO M MEA SURING .
11.
APPLIED O NLY FO R TERMINALS.
Figure 11. 20-pin Micro Leaded Package (MLP) Table 10. Package Diagram Dimensions Symbol A A1 A2 A3 b D D1 D2 e E Min -- 0.00 -- 0.23 Millimeters Nom 0.85 0.01 0.65 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 0.50 BSC 4.00 BSC Max 1.00 0.05 0.80 0.35 Symbol Min E1 E2 N Nd Ne L P Q R 1.95 Millimeters Nom 3.75 BSC 2.10 20 5 5 0.60 0.42 0.40 0.17 -- Max 2.25
1.95
2.25
0.50 0.24 0.30 0.13 --
0.75 0.60 0.65 0.23 12
Preliminary Rev. 0.31
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Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.31

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