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LH5496/96H
FEATURES * Fast Access Times: 15 */20/25/35/50/65/80 ns * Full CMOS Dual Port Memory Array * Fully Asynchronous Read and Write * Expandable-in Width and Depth * Full, Half-Full, and Empty Status Flags * Read Retransmit Capability * TTL Compatible I/O * Packages: 28-Pin, 300-mil PDIP 28-Pin, 600-mil PDIP 32-Pin PLCC * Pin and Functionally Compatible with IDT7201 FUNCTIONAL DESCRIPTION
The LH5496/96H are dual port memories with internal addressing to implement a First-In, First-Out algorithm. Through an advanced dual port architecture, they provide fully asynchronous read/write operation. Empty, Full, and Half-Full status flags are provided to prevent data overflow and underflow. In addition, internal logic provides for unlimited expansion in both word size and depth. Read and write operations automatically access sequential locations in memory in that data is read out in the same order that it was written, that is on a First-In, First-Out basis. Since the address sequence is internally predefined, no external address information is required for the operation of this device. A ninth data bit is provided for parity or control information often needed in communication applications. Empty, Full, and Half-Full status flags monitor the extent to which data has been written into the FIFO, and prevent improper operations (i.e., Read if the FIFO is empty, or Write if the FIFO is full). A retransmit feature resets the Read address pointer to its initial position, thereby allowing repetitive readout of the same data. Expansion In and Expansion Out pins implement an expansion scheme that allows individual FIFOs to be cascaded to greater depth without incurring additional latency (bubblethrough) delays.
* LH5496 only.
NC
CMOS 512 x 9 FIFO
PIN CONNECTIONS
28-PIN PDIP W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
5496-1D
TOP VIEW
Figure 1. Pin Connections for PDIP Packages
VCC
32-PIN PLCC
TOP VIEW
D3
D8
4 D2 D1 D0 XI FF Q0 Q1 NC Q2 5 6 7 8 9 10 11 12 13
3
2
1
32 31 30 29 28 27 26 25 24 23 22 21 D6 D7 NC FL/RT RS EF XO/HF Q7 Q6
14 15 16 17 18 19 20
Q4
D4
VSS
NC
Q3
Q8
Q5
R
D5
W
5496-2D
Figure 2. Pin Connections for PLCC Package
1
LH5496/96H
CMOS 512 x 9 FIFO
RS
RESET LOGIC INPUT PORT CONTROL WRITE POINTER
DATA INPUTS D0 - D8 OUTPUT PORT CONTROL READ POINTER
W
R
DUAL-PORT RAM ARRAY 512 x 9
...
DATA OUTPUTS Q0 - Q8
FLAG LOGIC
EF FF
FL/RT XI
EXPANSION LOGIC
XO/HF
5496-3
Figure 3. LH5496/96H Block Diagram
PIN DESCRIPTIONS
PIN PIN TYPE * DESCRIPTION PIN PIN TYPE * DESCRIPTION
D0 - D8 Q0 - Q8 W R EF FF
I O/Z I I O O
Input Data Bus Output Data Bus Write Request Read Request Empty Flag Full Flag
XO/HF XI FL/RT RS VCC VSS
O I I I V V
Expansion Out/Half-Full Flag Expansion In First Load/Retransmit Reset Positive Power Supply Ground
* I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
2
CMOS 512 x 9 FIFO
LH5496/96H
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER RATING
Supply Voltage to VSS Potential Signal Pin Voltage to VSS Potential DC Output Current 2 Storage Temperature Range Power Dissipation (Package Limit) DC Voltage Applied To Outputs In High-Z State
3
-0.5 V to 7 V -0.5 V to VCC + 0.5 V (not to exceed 7 V) 50 mA -65oC to 150oC 1.0 W -0.5 V to Vcc + 0.5 V (not to exceed 7 V)
NOTES: 1. Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a device stress rating for transient conditions only. Functional operation at these or any other conditions above those indicated in the `Operating Range' of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 3. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
OPERATING RANGE
SYMBOL PARAMETER MIN MAX UNIT oC oC
TA TA VCC VSS VIL VIH
Temperature, Ambient, LH5496 Temperature, Ambient, LH5496H Supply Voltage Supply Voltage Logic `0' Input Voltage Logic `1' Input Voltage
1
0 -40 4.5 0 -0.5 2.0
70 85 5.5 0 0.8 VCC + 0.5
V V V V
NOTE: 1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT
ILI ILO VOH VOL ICC ICC2 ICC3
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Supply Current
1 1 1
VCC = 5.5 V, VIN = 0 V to VCC R V IH, 0 V VOUT VCC IOH = -2.0 mA IOL = 8.0 mA Measured at f = 40 MHz All Inputs = VIH All Inputs = VCC - 0.2 V
-10 -10 2.4
10 10
A A V
0.4 100 15 5
V mA mA mA
Average Standby Current Power Down Current
NOTE: 1. ICC, ICC2, and ICC3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open.
3
LH5496/96H
CMOS 512 x 9 FIFO
AC TEST CONDITIONS
PARAMETER RATING
+5 V 1.1 k DEVICE UNDER TEST 680
Input Pulse Levels Input Rise and Fall Times (10% to 90%) Input Timing Reference Levels Output Reference Levels Output Load, Timing Tests
VSS to 3 V 5 ns 1.5 V 1.5 V Figure 4
30 pF *
CAPACITANCE 1,2
PARAMETER RATING
*
5 pF 7 pF
INCLUDES JIG & SCOPE CAPACITANCES
5496-4
CIN (Input Capacitance) COUT (Output Capacitance)
Figure 4. Output Load Circuit
NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25oC measured at 1.0 MHz with VIN = 0 V.
4
CMOS 512 x 9 FIFO
LH5496/96H
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)
tA = 15 ns 2 tA = 20 ns tA = 25 ns tA = 35 ns tA = 50 ns tA = 65 ns SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tA = 80 ns MIN MAX UNIT
READ CYCLE TIMING
tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ Read Cycle Time Access Time Read Recover Time Read Pulse Width 3 Data Bus Active from Read LOW 4 Data Bus Active from Write HIGH 4,5 Data Valid from Read Pulse HIGH Data Bus High-Z from Read 4 HIGH Write Cycle Time Write Pulse Width Data Setup Time Data Hold Time Reset Cycle Time Reset Pulse Width
3 3
25 - 10 15 5 10 5 -
- 15 - - - - - 15
30 - 10 20 5 10 5 -
- 20 - - - - - 15
35 - 10 25 5 10 5 -
- 25 - - - - - 15
45 - 10 35 5 10 5 -
- 35 - - - - - 15
65 - 15 50 5 10 5 -
- 50 - - - - - 20
80 - 15 65 5 10 5 -
- 65 - - - - - 30
100 - 15 80 10 20 5 -
- 80 - - - - - 30
ns ns ns ns ns ns ns ns
WRITE CYCLE TIMING
tWC tWPW tWR tDS tDH tRSC tRS tRSR tRRSS tWRSS tRTC tRT tRTR tEFL tHFH,FFH tREF tRFF tWEF tWFF tWHF tRHF tXOL tXOH tXI tXIR tXIS 25 15 10 10 0 25 15 10 15 15 25 15 10 - - - - - - - - - - 15 10 7 - - - - - - - - - - - - - 25 25 20 20 20 20 25 25 18 18 - - - 30 20 10 10 0 30 20 10 20 20 30 20 10 - - - - - - - - - - 20 10 10 - - - - - - - - - - - - - 30 30 25 25 25 25 30 30 20 20 - - - 35 25 10 10 0 35 25 10 25 25 35 25 10 - - - - - - - - - - 25 10 10 - - - - - - - - - - - - - 35 35 25 25 25 25 35 35 25 25 - - - 45 35 10 15 0 45 35 10 35 35 45 35 10 - - - - - - - - - - 35 10 15 - - - - - - - - - - - - - 45 45 35 35 35 35 45 45 35 35 - - - 65 50 15 20 0 65 50 15 50 50 65 50 15 - - - - - - - - - - 50 10 15 - - - - - - - - - - - - - 65 65 45 45 45 45 65 65 50 50 - - - 80 65 15 20 5 80 65 15 65 65 80 65 15 - - - - - - - - - - 65 10 15 - - - - - - - - - - - - - 80 80 60 60 60 60 80 80 65 65 - - - 100 80 15 20 5 100 80 15 80 80 100 80 15 - - - - - - - - - - 80 10 15 - - - - - - - - - - - - - 100 100 60 60 60 60 100 100 80 80 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Recovery Time
RESET TIMING
Reset Recovery Time Read HIGH to RS HIGH Write HIGH to RS HIGH Retransmit Cycle Time Retransmit Pulse Width 3 Retransmit Recovery Time Reset LOW to Empty Flag LOW Reset LOW to Half-Full and Full Flags HIGH Read LOW to Empty Flag LOW Read HIGH to Full Flag HIGH Write HIGH to Empty Flag HIGH Write LOW to Full Flag LOW Write LOW to Half-Full Flag LOW Read HIGH to Half-Full Flag HIGH Expansion Out LOW Expansion Out HIGH Expansion In Pulse Width Expansion In Recovery Time Expansion in Setup Time
RETRANSMIT TIMING
FLAG TIMING
EXPANSION TIMING
NOTES: 1. LH5496 only. 2. All timing measurements performed at `AC Test Condition' levels.
5
LH5496/96H
CMOS 512 x 9 FIFO The internal read and write address pointers are maintained by the device such that consecutive read operations will access data in the same order as it was written. The Empty flag is asserted (EF = LOW) after the falling edge of R which accesses the last available data in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another word of valid data. Data Flow-Through Read flow-through mode occurs when the Read (R) pin is brought LOW while the FIFO is empty, and held LOW in anticipation of a write cycle. At the end of the next write cycle, the Empty flag will be momentarily deasserted, and the data just written will become available on the data out pins after a maximum time of tWEF + tA. Additional writes may occur while the R pin remains LOW, but only data from the first write flows through to the outputs. Additional data, if any, can only be accessed by toggling R. Write flow-through mode occurs when the Write (W) pin is brought LOW while the FIFO is full, and held LOW in anticipation of a read cycle. At the end of the read cycle, the Full flag will be momentarily deasserted, but then immediately reasserted in response to W held LOW. Data is written into the FIFO on the rising edge of W which may occur tRFF + tWPW after the read. Retransmit The FIFO can be made to reread previously read data through the retransmit function. Retransmit is initiated by pulsing RT LOW. This resets the internal read address pointer to the first physical location in the memory while leaving the internal write address pointer unchanged. Data between the read and write pointers may be reaccessed by subsequent reads. Both R and W must be inactive (HIGH) during the retransmit pulse. Retransmit is useful if no more than 512 writes are performed between resets. Retransmit may affect the status of EF, HF, and FF flags, depending on the relocation of the read pointer. This function is not available in depth expansion mode.
OPERATIONAL DESCRIPTION
Reset The device is reset whenever the Reset pin (RS) is taken to a LOW state. The reset operation initializes both the read and write address pointers to the first memory location. The XI and FL pins are also sampled at this time to determine whether the device is in Single mode or Depth Expansion mode. A reset pulse is required when the device is first powered up. The Read (R) and Write (W) pins may be in any state when reset is initiated, but must be brought to a HIGH state tRPW and tWPW before the rising edge of RS. The reset operation forces the Empty Flag EF to be asserted (EF = LOW), and the Half-Full Flag HF and the Full FLag FF to be deasserted (HF = FF = HIGH); the Data Out pins (D0 - D8) are forced into a high-impedance state. Write A write cycle is initiated on the falling edge of the Write (W) pin. Data setup and hold times must be observed on the data in (D0 - D8) pins. A write operation is only possible if the FIFO is not full, (i.e. the Full flag pin is HIGH). Writes may occur independently of any ongoing read opertations. At the falling edge of the first write after the memory is half filled, the Half-Full flag will be asserted (HF = LOW) and will remain asserted until the difference between the write pointer and read pointer indicates that the remaining data in the device is less than or equal to one half the total capacity of the FIFO. The Half-Full flag is deasserted (HF = HIGH) by the appropriate rising edge of R. The Full flag is asserted (FF = LOW) at the falling edge of the write operation which fills the last available location in the FIFO memory array. The Full flag will inhibit further writes until cleared by a valid read. The Full flag is deasserted (FF = HIGH) after the next rising edge of R releases another memory location. Read A read cycle is initiated on the falling edge of the Read (R) pin. Read data becomes valid on the data out (Q0-Q8) pins after a time tA from the falling edge of R. After R goes HIGH, the data out pins return to a high-impedance state. Reads may occur independent of any ongoing write operations. A read is only possible if the FIFO is not empty (EF = HIGH).
6
CMOS 512 x 9 FIFO
LH5496/96H
TIMING DIAGRAMS
t RSC t RS
RS
R,W t RRSS t WRSS tEFL t RSR
EF t FFH , t HFH
FF,HF NOTES: 1. tRSC = tRS + tRSR. 2. W and R VIH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
5496-14
Figure 5. Reset Timing
t RC tA t RR tA
t RPW
R t RLZ t DV t RHZ
Q0 - Q8
VALID DATA OUT t WC t WPW t WR
VALID DATA OUT
W t DS t DH
D0 - D 8
VALID DATA IN
VALID DATA IN
5496-5
Figure 6. Asynchronous Write and Read Operation
7
LH5496/96H
CMOS 512 x 9 FIFO
TIMING DIAGRAMS (cont'd)
LAST WRITE R
FIRST READ
W t WFF t RFF
FF
5496-6
Figure 7. Full Flag from Last Write to First Read
LAST READ W
FIRST WRITE
R t REF t WEF
EF
NOTE: The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
5496-7
Figure 8. Empty Flag from Last Read to First Write
8
CMOS 512 x 9 FIFO
LH5496/96H
TIMING DIAGRAMS (cont'd)
D0 - D 8
VALID DATA IN
W
tRPE
R
EF t WEF t WLZ tA t REF
Q0 - Q 8 NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
VALID DATA OUT
5496-8
Figure 9. Read Data Flow-Through
R
tWPF
W t RFF
FF t WFF t DS t DH
D0 - D 8 tA
VALID DATA IN
Q0 - Q8
VALID DATA OUT
NOTES: 1. tWPF = tWPW 2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
5496-9
Figure 10. Write Data Flow-Through
9
LH5496/96H
CMOS 512 x 9 FIFO
TIMING DIAGRAMS (cont'd)
W t WEF
EF t RPE
R NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
5496-10
Figure 11. Empty Flag Timing
R t RFF
FF t WPF
W NOTES: 1. tWPF = tWPW 2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
5496-11
Figure 12. Full Flag Timing
HALF-FULL OR LESS W
MORE THAN HALF-FULL
HALF-FULL OR LESS
R t WHF tRHF
HF
5496-12
10
CMOS 512 x 9 FIFO
LH5496/96H
TIMING DIAGRAMS (cont'd)
t RT
RT t RTR
R,W NOTES: 1. tRTC = tRT + tRTR 2. EF, HF and FF may change state during retransmit, but flags will be valid at tRTC.
5496-13
Figure 14. Retransmit Timing
W
WRITE TO LAST AVAILABLE LOCATION READ FROM LAST VALID LOCATION t XOL t XOH t XOL t XOH
R
XO
5496-15
Figure 15. Expansion Out Timing
t XI
t XIR
XI t XIS WRITE TO FIRST AVAILABLE LOCATION
W
t XIS READ FROM FIRST VALID LOCATION
5496-16
R
Figure 16. Expansion In Timing
11
LH5496/96H
CMOS 512 x 9 FIFO Width Expansion Word-width expansion is implemented by placing multiple LH5496/96H devices in parallel. Each LH5496/96H should be configured for standalone mode. In this arrangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive `composite' flag values using external logic, since there may be minor speed variations between different actual devices. (See Figures 17 and 18.)
OPERATIONAL MODES
Single Device Configuration When depth expansion is not required for the given application, the device is placed in Single mode by tying the Expansion In pin (XI) to ground. This pin is internally sampled during reset.
HF WRITE W R READ
DATA IN D0 - D8
9 LH5496/96H
9
DATA OUT Q0 - Q8
FULL FLAG
FF
EF
EMPTY FLAG
RESET
RS
RT
RETRANSMIT
XI
5496-17
Figure 17. Single FIFO (512 x 9)
DATA IN
18 9 WRITE FULL FLAG RESET W FF RS
HF 9 W LH5496/96H R RS RT 9 XI
HF
LH5496/96H
R READ EF RT 9 EMPTY FLAG RETRANSMIT
XI
18
DATA OUT
5496-18
Figure 18. FIFO Width Expansion (512 x 18)
12
CMOS 512 x 9 FIFO
LH5496/96H are shared by all devices, while internal logic controls the steering of data. Only one FIFO will be enabled for any given read cycle, so the common Data Out pins of all devices are wire-ORed together. Likewise, the common Data In pins of all devices are tied together. In Expansion mode, external logic is required to generate a composite Full or Empty flag. This is achieved by ORing the FF pins of all devices and ORing the EF pins of all devices respectively. The Half-Full flag and Retransmit functions are not available in Depth Expansion mode.
OPERATIONAL MODES (cont'd)
Depth Expansion Depth expansion is implemented by configuring the required number of FIFOs in Expansion mode. In this arrangement, the FIFOs are connected in a circular fashion with the Expansion Out pin (XO) of each device tied to the Expansion In pin (XI) of the next device. One FIFO in this group must be designated as the first load device. This is accomplished by tying the First Load pin (FL) of this device to ground. All other devices must have their FL pin tied to a high level. In this mode, W and R signals
XO W DATA IN D 0 - D8 9 9 LH5496/96H FF RS XI XO 9 FULL FF RS XI XO 9 FF RS XI LH5496/96H EF FL 9 LH5496/96H EF FL Vcc 9 EMPTY EF FL Vcc 9 9 R DATA OUT Q 0 - Q8
RS
5496-19
Figure 19. FIFO Depth Expansion (1536 x 9)
13
LH5496/96H
CMOS 512 x 9 FIFO LH5496/96H devices in parallel but opposite directions. The Data In pins of a device may be tied to the corresponding Data Out pins of another device operating in the opposite direction to form a single bidirectional bus interface. Care must be taken to assure that the appropriate read, write, and flag signals are routed to each system. Both depth and width expansion may be used in this configuration.
OPERATIONAL MODES (cont'd)
Compound Expansion A combination of width and depth expansion can be easily implemented by operating groups of depth expanded FIFOs in parallel. Bidirectional Operation Applications which require bidirectional data buffering between two systems can be realized by operating
Q0 - Q 8
Q0 - Q17
Q0 - QN-10
Q0 - QN-1
DATA OUT
R W RS
LH5496/96H DEPTH EXPANSION BLOCK
LH5496/96H DEPTH EXPANSION BLOCK
LH5496/96H DEPTH EXPANSION BLOCK
DATA IN
D0 - DN-1
D9 - DN-1
D18 - DN-1
DN-9 - DN-1
5496-20
Figure 20. Compound FIFO Expansion
Wa FFa LH5496/96H RS Da0 - 8 XI SYSTEM A Qb0 - 8
Rb EFb HFb RTb
SYSTEM B
Qa0 - 8 Ra EFa HFa RTa XI LH5496/96H
Db0 - 8 Wb FFb
RS
5496-21
Figure 21. Bidirectional FIFO Buffer
14
CMOS 512 x 9 FIFO
LH5496/96H
PACKAGE DIAGRAMS
28SK-DIP (DIP028-P-0300)
28 15 7.05 [0.278] 6.65 [0.262] 1 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 14 0.35 [0.014] 0.15 [0.006] 7.62 [0.300] TYP. 0 TO 15
DETAIL
DIMENSIONS IN MM [INCHES]
28DIP-1
28-pin, 300-mil PDIP
28DIP (DIP028-P-0600)
28 15
DETAIL
13.45 [0.530] 12.95 [0.510]
1 36.30 [1.429] 35.70 [1.406]
14
0 TO 15 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP.
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN.
DIMENSIONS IN MM [INCHES]
28DIP-2
28-pin, 600-mil PDIP
15
LH5496/96H
CMOS 512 x 9 FIFO
32PLCC (PLCC32-P-R450)
1.27 [0.050] 4 SIDES BSC
15.11 [0.595] 14.86 [0.585] 14.05 [0.553] 13.89 [0.547] 13.46 [0.530] 12.45 [0.490]
11.51 [0.453] 11.35 [0.447] 12.57 [0.495] 12.32 [0.485]
DETAIL
0.81 [0.032] 0.66 [0.026]
0.10 [0.004]
3.56 [0.140] 3.12 [0.123]
2.41 [0.095] 1.52 [0.060] 10.92 [0.430] 9.91 [0.390]
0.38 [0.015] MIN 0.53 [0.021] 0.33 [0.013]
MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT
32PLCC
32-pin, 450-mil PLCC
ORDERING INFORMATION
LH5496/96H Device Type X Temperature Range X Package - ## Speed 15 * 20 25 35 Access Time (ns) 50 65 80 Blank 28-pin, 600-mil Plastic DIP (DIP28-P-600) D 28-pin, 300-mil Plastic DIP (DIP28-P-300) U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450) Blank Commercial (0 C to 70 C) H Industrial (-40 C to 85 C) CMOS 1K x 9 FIFO
* LH5496 only
Example: LH5496U-25 (CMOS 512 x 9 FIFO, 32-pin PLCC, 25 ns)
5496MD
16

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