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DSP56858/D Rev. 1.0, 1/2002
DSP56858
Preliminary Technical Data
DSP56858 16-bit Digital Signal Processor
* 120 MIPS at 120MHz * 40K x 16-bit Program SRAM * 24K x 16-bit Data SRAM * 1K x 16-bit Boot ROM * Access up to 2M words of program memory or 8M data memory * Chip Select Logic for glue-less interface to ROM and SRAM * Six (6) independent channels of DMA * Two (2) Enhanced Synchronous Serial Interfaces (ESSI)
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* Two (2) Serial Communication Interfaces (SCI) * Serial Port Interface (SPI) * 8-bit Parallel Host Interface * General Purpose 16-bit Quad Timer * JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging * Computer Operating Properly (COP)/Watchdog Timer * Time-of -Day (TOD) * 144 LQFP and 144 MAPBGA packages * Up to 47 GPIO
VDDIO 12 VDD 8 VSSIO 14 VSS VDDA 8 VSSA 2
JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Address Generation Unit
16-Bit DSP56800E Core
Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit
PAB PDB CDBR CDBW
Memory
XDB2
Program Memory 40,960 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 24,576 x 16 SRAM
XAB1 XAB2 PAB PDB CDBR CDBW
IPBus Bridge (IPBB)
IPWDB IPRDB IPAB
Decoding Peripherals
A0-20 [20:0] D0-D15 [15:0] RD Enable WR Enable CS0-CS3[3:0] or GPIOA0-A3 4 6 6 Bus Control External Address Bus Switch External Data Bus Switch External Bus Interface Unit
DMA Requests
Core CLK
System Bus Control
DMA
6 channel
IPBus CLK
POR
3
CLKO
MODE A-C or GPIOH0-H2
System COP/TOD CLK Integration Module
RSTO RESET EXTAL XTAL
2 SCI ESSI0 or or GPIOE GPIOC
ESSI1 or GPIOD
Quad Timer or GPIOG 4
SPI Host Interrupt or Interface Controller GPIOF or GPIOB 4 16 IRQA IRQB
COP/ Watchdog
Time of Day
Clock Generator OSC PLL
Figure 1. DSP56858 Block Diagram
(c) Motorola, Inc., 2002. All rights reserved.
Part 1 Overview
1.1 DSP56858 Features
1.1.1
* * * * * * * * * * * * * * * *
Digital Signal Processing Core
Efficient 16-bit DSP engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three (3) internal address buses and one (1) external address bus Four (4) internal data buses and one (1) external data bus Instruction set supports both DSP and controller functions Four (4) hardware interrupt levels Five (5) software interrupt levels Controller-style addressing modes and instructions for compact code Efficient C-Compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced OnCE debug programming interface
1.1.2
* *
Memory
Harvard architecture permits up to three (3) simultaneous accesses to program and data memory On-Chip Memory -- 40K x 16-bit Program RAM -- 24K x 16-bit Data RAM -- 1K x 16-bit Boot ROM
*
Off-Chip Memory Expansion (EMI) -- Access up to 2M words of program or 8M data memory (using chip selects) -- Chip Select Logic for glue-less interface to ROM and SRAM
1.1.3
* * * * *
DSP56858 Peripheral Circuit Features
General Purpose 16-bit Quad Timer* Two Serial Communication Interfaces (SCI)* Serial Peripheral Interface (SPI) Port* Two (2) Enhanced Synchronous Serial Interface (ESSI) modules* Computer Operating Properly (COP)/Watchdog Timer
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DSP56858 Preliminary Technical Data
MOTOROLA
DSP56858 Description
* * * * *
JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging Six (6) independent channels of DMA 8-bit Parallel Host Interface* Time-of-Day (TOD) Up to 47 GPIO
* Each peripheral I/O can be used alternately as a GPIO if not needed
1.1.4
* *
Energy Information
Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs Wait and Stop modes available
1.2 DSP56858 Description
The DSP56858 is a member of the DSP56800E core-based family of Digital Signal Processors (DSPs). This device combines the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals on a single chip to create an extremely cost-effective solution. The low cost, flexibility, and compact program code make this device well-suited for many applications. The DSP56858 includes peripherals that are especially useful for teledatacom devices; Internet appliances; portable devices; TAD; voice recognition; hands-free devices; and general purpose applications. The DSP56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C Compilers, enabling rapid development of optimized control applications. The DSP56858 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The DSP56858 also provides two external dedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The DSP56858 DSP controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of Boot RAM. It also supports program execution from external memory. This DSP controller also provides a full set of standard programmable peripherals that include an 8-bit Parallel Host Interface, two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI), two Serial Communications Interfaces (SCI), and one Quad Timer. The Host Interface, Quad Timer, SSI, SPI, SCI I/O and four chip selects can be used as General Purpose Input/Outputs when its primary function is not required.
1.3 "Best in Class" Development Environment
The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces that allow a programmer to create his own unique C application code independent of component architecture. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast and efficient development.
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DSP56858 Preliminary Technical Data
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1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description of and proper design with the DSP56858. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/.
Table 1. DSP56858 Chip Documentation
Topic
DSP56800E Reference Manual DSP56858 User's Manual DSP56858 Technical Data Sheet DSP56858 Product Brief
Description
Detailed description of the DSP56800E architecture, 16-bit DSP core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the DSP56858 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Summary description and block diagram of the DSP56858 core, memory, peripherals and interfaces.
Order Number
DSP56800ERM/D
DSP5685xUM/D
DSP56858/D
DSP56858PB/D
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN 1. Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
"asserted" "deasserted" Examples:
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
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DSP56858 Preliminary Technical Data
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Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56858 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 each table row describes the package pin and the signal or signals present.
Table 2. DSP56858 Functional Group Pin Allocations
Functional Group Power (VDD, VDDIO, or VDDA) Ground (VSS, VSSIO,or VSSA) PLL and Clock External Bus Signals External Chip Select* Interrupt and Program Control Host Interface (HI)* Enhanced Synchronous Serial Interface (ESSI0) Port* Enhanced Synchronous Serial Interface (ESSI1) Port* Serial Communications Interface (SCI0) Ports* Serial Communications Interface (SCI1) Ports* Serial Peripheral Interface (SPI) Port* Quad Timer Module Port* JTAG/On-Chip Emulation (OnCE) *Alternately, GPIO pins Number of Pins (8, 12, 1)1 (8, 14, 2)1 3 39 4 72 163 6 6 2 2 4 4 6
1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA
2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed. 3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.
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Logic Power
VDD VSS
1 8 8 1
RXDO (GPIOE0) TXDO (GPIOE1) SCI 0
1 I/O Power Analog Power1 VDDIO VSSIO VDDA VSSA 12 14 1 1 2 1 1 1 1 A0 - A20 D0 - D15 Address Bus RD WR 1
RXD1 (GPIOE2) TXD1 (GPIOE3) SCI 2
STD0 (GPIOC0) SRD0 (GPIOC1) SCK0 (GPIOC2) SC00 (GPIOC3) SC01 (GPIOC4) SC02 (GPIOC5) ESSI 0
DSP56858
21 16 1 1
1
1 1 1 1
STD1 (GPIOD0) SRD1 (GPIOD1) SCK1 (GPIOD2) SC10 (GPIOD3) SC11 (GPIOD4) SC12 (GPIOD5) ESSI 1
Chip Select
CS0 - CS3 (GPIOA0 - A3)
4
1 1
HD0 - HD7 (GPIOB0 - B7) HA0 - HA2 (GPIOB8 - B10) HRWB (HRD) (GPIOB11) Host Interface HDS (HWR) (GPIOB12) HCS (GPIOB13) HREQ (HTRQ) (GPIOB14) HACK (HRRQ) (GPIOB15)
8 3 1 1 1 1 1 1 1 4 1 1 1 1 1
MISO (GPIOF0) MOSI (GPIOF1) SCK (GPIOF2) SS (GPIOF3) SPI
XTAL EXTAL CLKO PLL/Clock
Timer Module
TIO0 - TIO3 (GPIOG0 - G3)
IRQA IRQB Interrupt/ Program Control MODA, MODB, MODC (GPIOH0 - H2) RESET RSTO
1 1 3 1 1
1 1 1 1 1 1
TCK TDI TDO TMS TRST DE JTAG / Enhanced OnCE
Figure 2. DSP56858 Signals Identified by Functional Group2
1. Specifically for PLL, OSC, and POR. 2. Alternate pin functions are shown in parentheses. Pin direction/type is represented as the preferred functionality. GPIO may provide bidirectional use of
any pin.
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Introduction
Part 3 Signals and Package Information
All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions:
1. When a pin has GPIO functionality, the pull-up may be disabled under software control. 2. MODE A, MODE B and MODE C pins have no pull-up. 3. TCK has a weak pull-down circuit always active. 4. Bidirectional I/O pullups automatically disable when the output is enabled.
This table is presented consistently with the Signals Identified by Functional Group figure.
1. BOLD entries in the Type column represents the state of the pin just out of reset. 2. Ouput(Z) means an output in a High-Z condition.
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS
BGA Pin No.
E1 M6 F12 A9 M2 J12 E12 A12 G1 L6 D12 A7 F1 M7 K12 A8
LQFP Pin No.
14 36 52 72 87 88 109 125 15 16 53 54 71 89 126 127
Type
VDD
Description
Logic Power (VDD)--These pins provide power to the internal structures of the chip, and should all be attached to VDD.
VSS
Logic Power-Ground (VSS)--These pins provide grounding for the internal structures of the chip and should all be attached to VSS.
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Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VDDA VSSA VSSA
BGA Pin No.
B1 H1 M3 M8 M11 H12 C12 A11 A5 A3 C1 M10 D1 J1 M5 M9 L12 G12 B12 A10 A4 A1 A2 M4 M12 A6 K1 M1 L1
LQFP Pin No.
5 6 20 45 61 67 68 80 105 113 129 139 7 21 46 47 62 69 70 82 106 115 128 130 140 141 24 25 26
Type
VDDIO
Description
I/O Power (VDDIO)--These pins provide power for all I/O and ESD structures of the chip and should all be attached to VDDIO (3.3V).
VSSIO
I/O Power-Ground (VSSIO)--These pins provide grounding for all I/O and ESD structures of the chip and should all be attached to VSS.
VDDA
Analog Power (VDDA)--These pins supply an analog power source. Analog Ground (VSSA)--This pin supplies an analog ground.
VSSA
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DSP56858 Preliminary Technical Data
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Introduction
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
BGA Pin No.
E5 E4 E3 E2 J2 H3 G4 H4 G5 L5 J6 K6 J8 K8 L9 K9 K10 K11 J9 J10 J11
LQFP Pin No.
10 11 12 13 29 30 31 32 48 49 50 51 63 64 65 66 75 76 77 78 79
Type
Output(Z)
Description
Address Bus (A0-A20)--These signals specify a word address for external program or data memory access.
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Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RD
BGA Pin No.
H7 G7 F9 F10 F11 E10 D7 B7 E7 F8 F7 D5 B4 C4 F6 B3 D3
LQFP Pin No.
81 94 95 96 97 98 120 121 122 123 124 137 138 142 143 144 8
Type
Input/ Output(Z)
Description
Data Bus (D0-D15)--These pins provide the bidirectional data for external program or data memory accesses.
Output
Read Enable (RD) -- is asserted during external memory read cycles. This signal is pulled high during reset.
WR
D4
9
Output
Write Enable (WR) --is asserted during external memory write cycles. This signal is pulled high during reset.
CS0
H8
83
Output
External Chip Select (CS0)--This pin is used as a dedicated GPIO. Port A GPIO (0) --This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. External Chip Select (CS1)--This pin is used as a dedicated GPIO. Port A GPIO (1) --This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. External Chip Select (CS2)--This pin is used as a dedicated GPIO. Port A GPIO (2) --This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.
GPIOA0 CS1 H9 84
Input/Output Output
GPIOA1 CS2 H11 85
Input/Output Output
GPIOA2
Input/Output
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DSP56858 Preliminary Technical Data
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Introduction
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
CS3
BGA Pin No.
H10
LQFP Pin No.
86
Type
Output
Description
External Chip Select (CS3)--This pin is used as a dedicated GPIO. Port A GPIO (3)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD0)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOA3 HD0 J3 33
Input/Output Input
GPIOB0 HD1 K2 34
Input/Output Input
Port B GPIO (0)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD1)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOB1 HD2 L2 35
Input/Output Input
Port B GPIO (1)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD2)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOB2 HD3 J4 40
Input/Output Input
Port B GPIO (2)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD3)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOB3 HD4 L4 41
Input/Output Input
Port B GPIO (3)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD4)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOB4 HD5 J5 42
Input/Output Input
Port B GPIO (4)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD5)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOB5
Input/Output
Port B GPIO (5)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.
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Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
HD6
BGA Pin No.
K5
LQFP Pin No.
43
Type
Input
Description
Host Address (HD6)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOB6 HD7 H5 44
Input/Output Input
Port B GPIO (6)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD7)--This input provides data selection for HI registers. This pin is disconnected internally during reset.
GPIOB7 HA0 G10 90
Input/Output Input
Port B GPIO (7)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HA0)--These inputs provide the address selection for HI registers. These pins are disconnected internally during reset.
GPIOB8 HA1 G11 91
Input/Output Input
Port B GPIO (8)--These pins are General Purpose I/O (GPIO) pins when not configured for host port usage. Host Address (HA0)--These inputs provide the address selection for HI registers. These pins are disconnected internally during reset.
GPIOB9 HA2 G9 92
Input/Output Input
Port B GPIO (9)--These pins are General Purpose I/O (GPIO) pins when not configured for host port usage. Host Address (HA0)--These inputs provide the address selection for HI registers. These pins are disconnected internally during reset.
GPIOB10 HRWB G8 93
Input/Output Input
Port B GPIO (10)--These pins are General Purpose I/O (GPIO) pins when not configured for host port usage. Host Read/Write (HRWB)--When the HI08 is programmed to interface to a single-data-strobe host bus and the HI function is selected, this signal is the Read/Write input . These pins are disconnected internally during reset.
HRD
Input
Host Read Data (HRD)--This signal is the Read Data input when the HI08 is programmed to interface to a double-datastrobe host bus and the HI function is selected. Port B GPIO (11) --This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.
GPIOB11
Input/Output
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DSP56858 Preliminary Technical Data
MOTOROLA
Introduction
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
HDS
BGA Pin No.
C8
LQFP Pin No.
116
Type
Input
Description
Host Data Strobe (HDS)--When the HI08 is programmed to interface to a single-data-strobe host bus and the HI function is selected, this input enables a data transfer on the HI when HCS is asserted. These pins are disconnected internally during reset.
HWR
Input
Host Write Enable (HWR)--This signal is the Write Data input when the HI08 is programmed to interface to a doubledata-strobe host bus and the HI function is selected. Port B GPIO (12)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Chip Select (HCS)--This input is the chip select input for the Host Interface. These pins are disconnected internally during reset.
GPIOB12 HCS D8 117
Input/Output Input
GPIOB13 HREQ B8 118
Input/Output Open Drain Output
Port B GPIO (13)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Request (HREQ)--When the HI08 is programmed for HRMS=0 functionality (typically used on a single-data-strobe bus), this open drain output is used by the HI to request service from the host processor. The HREQ may be connected to an interrupt request pin of a host processor, a transfer request of a DMA controller, or a control input of external circuitry. These pins are disconnected internally during reset.
HTRQ
Open Drain Output
Transmit Host Request (HTRQ)--This signal is the Transmit Host Request output when the HI08 is programmed for HRMS=1 functionality and is typically used on a double-datastrobe bus. Port B GPIO (14) --This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.
GPIOB14
Input/Output
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Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
HACK
BGA Pin No.
C7
LQFP Pin No.
119
Type
Input
Description
Host Acknowledge (HACK)--When the HI08 is programmed for HRMS=0 functionality (typically used on a single-datastrobe bus), this input has two functions: (1) provide a Host Acknowledge signal for DMA transfers or (2) to control handshaking and provide a Host Interrupt Acknowledge compatible with the MC68000 family processors. These pins are disconnected internally during reset. Receive Host Request (HRRQ)--This signal is the Receive Host Request output when the HI08 is programmed for HRMS=1 functionality and is typically used on a double-datastrobe bus. Port B GPIO (15)--This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Timer Input/Outputs (TIO0)--This pin can be independently configured to be either a timer input source or an output flag. Port G GPIOG0--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. Timer Input/Outputs (TIO1)--This pin can be independently configured to be either a timer input source or an output flag. Port G GPIO (1)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. Timer Input/Outputs (TIO2)--This pin can be independently configured to be either a timer input source or an output flag. Port G GPIO (2)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. Timer Input/Outputs (TIO3)--This pin can be independently configured to be either a timer input source or an output flag. Port G GPIO (3)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. External Interrupt Request A and B--The IRQA and IRQB inputs are asynchronous external interrupt requests that indicate that an external device is requesting service. A Schmitt trigger input is used for noise immunity. They can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for Wired-OR operation.
HRRQ
Open Drain Output
GPIOB15 TIO0 B9 114
Input/Output Input/Output
GPIOG0
Input/Output
TIO1
C9
112
Input/Output
GPIOG1
Input/Output
TIO2
D9
111
Input/Output
GPIOG2
Input/Output
TIO3
B10
110
Input/Output
GPIOG3
Input/Output
IRQA IRQB
G2 F5
22 23
Input
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DSP56858 Preliminary Technical Data
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Introduction
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
MODE A
BGA Pin No.
F4
LQFP Pin No.
17
Type
Input
Description
Mode Select (MODE A)--During the bootstrap process MODE A selects one of the eight bootstrap modes. Port H GPIO (0)--This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Mode Select (MODE B)--During the bootstrap process MODE A selects one of the eight bootstrap modes. Port H GPIO (1)--This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Mode Select (MODE C)--During the bootstrap process MODE A selects one of the eight bootstrap modes. Port H GPIO (2)--This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Reset (RESET)--This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the MODE A, MODE B, and MODE C pins. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but do not assert TRST.
GPIOH0 MODE B F3 18
Input/Output Input
GPIOH1 MODE C F2 19
Input/Output Input
GPIOH2 RESET K4 39
Input/Output Input
RSTO RXD0
K3 L10
38 73
Output Input
Reset Output (RSTO)--This output is asserted on any reset condition (external reset, low voltage, software, or COP). Serial Receive Data 0 (RXD0)--This input receives byteoriented serial data and transfers it to the SCI 0 receive shift register. Port E GPIO (0)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Serial Transmit Data 0 (TXD0)--This signal transmits data from the SCI 0 transmit data register. Port E GPIO (1)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Serial Receive Data 1 (RXD1)--This input receives byteoriented serial data and transfers it to the SCI 1 receive shift register. Port E GPIO (2)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin.
GPIOE0 TXD0 L11 74
Input/Output Output(Z)
GPIOE1 RXD1 B11 107
Input/Output Input
GPIOE2
Input/Output
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Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
TXD1
BGA Pin No.
C10
LQFP Pin No.
108
Type
Output(Z)
Description
Serial Transmit Data 1 (TXD1)--This signal transmits data from the SCI 1 transmit data register. Port E GPIO (3)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. ESSI Transmit Data (STD0)--This output pin transmits serial data from the ESSI Transmitter Shift Register. Port C GPIO (0)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Receive Data (SRD0)--This input pin receives serial data and transfers the data to the ESSI Receive Shift Register. Port C GPIO (1)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Clock (SCK0)--This bidirectional pin provides the serial bit rate clock for the transmit section of the ESSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. Port C GPIO (2)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 0 (SC00)--The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0. Port C GPIO (3)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 1 (SC01)--The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1. Port C GPIO (4)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 2 (SC02)--This pin is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation).
GPIOE3 STD0 B6 131
Input/Output Output
GPIOC0 SRD0 C6 132
Input/Output Input
GPIOC1 SCK0 C5 133
Input/Output Input/Output
GPIOC2 SC00 D6 134
Input/Output Input/Output
GPIOC3 SC01 B5 135
Input/Output Input/Output
GPIOC4 SC02 E6 136
Input/Output Input/Output
GPIOC5
Input or Output Port C GPIO (5)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use.
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DSP56858 Preliminary Technical Data
MOTOROLA
Introduction
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
STD1
BGA Pin No.
E8
LQFP Pin No.
99
Type
Output
Description
ESSI Transmit Data (STD1)--This output pin transmits serial data from the ESSI Transmitter Shift Register. Port D GPIO (0)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Receive Data (SRD1)--This input pin receives serial data and transfers the data to the ESSI Receive Shift Register. Port D GPIO (1)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Clock (SCK1)--This bidirectional pin provides the serial bit rate clock for the transmit section of the ESSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. Port D GPIO (2)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 0 (SC10)--The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0. Port D GPIO (3)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 1 (SC11)--The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1. Port D GPIO (4)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 2 (SC12)--This pin is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port D GPIO (5)--This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use.
GPIOD0 SRD1 E11 100
Input/Output Input
GPIOD1 SCK1 E9 101
Input/Output Input/Output
GPIOD2 SC10 D10 102
Input/Output Input/Output
GPIOD3 SC11 D11 103
Input/Output Input/Output
GPIOD4 SC12 C11 104
Input/Output Input/Output
GPIOC5
Input/Output
MOTOROLA
DSP56858 Preliminary Technical Data
17
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
MISO
BGA Pin No.
B2
LQFP Pin No.
1
Type
Input/Output
Description
SPI Master In/Slave Out (MISO)--This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the highimpedance state if the slave device is not selected. The driver on this pin can be configured as an open-drain driver by the SPI's Wired-OR mode (WOM) bit when this pin is configured for SPI operation. Port F GPIO (0)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. The driver on this pin can be configured as an opendrain driver by the SPI's WOM bit when this pin is configured for SPI operation. Port F GPIO (1)--This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin. SPI Serial Clock (SCK)--This bidirectional pin provides a serial bit rate clock for the SPI. This gated clock signal is an input to a slave device and is generated as an output by a master device. Slave devices ignore the SCK signal unless the SS pin is active low. In both master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. The driver on this pin can be configured as an open-drain driver by the SPI's WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pullup device. Port F GPIO (2)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. SPI Slave Select (SS)--This input pin selects a slave device before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. The SS line of the master must be held high. Port F GPIO (3)--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Crystal Oscillator Output (XTAL)--This output connects the internal crystal oscillator output to an external crystal. If an external clock source other than a crystal oscillator is used, XTAL must be used as the input.
GPIOF0 MOSI C3 2
Input/Output Input/ Output (Z)
GPIOF1
Input/Output
SCK
C2
3
Input/Output
GPIOF2 SS D2 4
Input/Output Input
GPIOF3 XTAL H2 27
Input/Output Input/Output
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DSP56858 Preliminary Technical Data
MOTOROLA
Introduction
Table 3. DSP56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal Name
EXTAL
BGA Pin No.
G3
LQFP Pin No.
28
Type
Input
Description
External Crystal Oscillator Input (EXTAL)--This input should be connected to an external crystal. If an external clock source other than a crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2 Clock Output (CLKO)--This pin outputs a buffered clock signal. When enabled, this signal is the system clock divided by four. Test Clock Input (TCK)--This input pin provides a gated clock to synchronize the test logic and to shift serial data to the JTAG/OnCE port. The pin is connected internally to a pulldown resistor. Test Data Input (TDI)--This input pin provides a serial input data stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Test Data Output (TDO)--This tri-statable output pin provides a serial output data stream from the JTAG/Enhanced OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. Test Mode Select Input (TMS)--This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Test Reset (TRST)--As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment, since the Enhanced OnCE/JTAG module is under the control of the debugger. In this case it is not necessary to assert TRST when asserting RESET . Outside of a debugging environment RESET should be permanently asserted by grounding the signal, thus disabling the Enhanced OnCE/JTAG module on the DSP. Debug Event (DE)--This is an open-drain, bidirectional, active low signal. As an input, it is a means of entering debug mode of operation from an external command controller. As an output, it is a means of acknowledging that the chip has entered debug mode. This pin is connected internally to a weak pull-up resistor.
CLKO
L3
37
Output
TCK
L8
60
Input
TDI
K7
58
Input
TDO
G6
57
Output (Z)
TMS
J7
59
Input
TRST
L7
56
Input
DE
H6
55
Input/Output
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DSP56858 Preliminary Technical Data
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Part 4 Specifications
4.1 General Characteristics
The DSP56858 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5Vcompatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 4 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The DSP56858 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed.
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Table 4. Absolute Maximum Ratings
Characteristic
Supply voltage, core Supply voltage, IO Supply voltage, analog Digital input voltages Analog input voltages (XTAL, EXTAL) Current drain per pin excluding VDD, GND Junction temperature Storage temperature range
1. 2. VDD must not exceed VDDIO VDDIO and VDDA must not differ by more that 0.5V
Symbol
VDD1 VDDIO2 VDDIO VIN VINA I TJ TSTG
2
Min
VSS - 0.3 VSSIO - 0.3 VSSA - 0.3 VSSIO - 0.3 VSSA - 0.3 -- -40 -55
Max
VSS + 2.0 VSSIO + 4.0 VDDA + 4.0 VSSIO + 5.5 VDDA + 0.3 8 120 150
Unit
V V
V
mA C C
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DSP56858 Preliminary Technical Data
MOTOROLA
General Characteristics
Table 5. Recommended Operating Conditions
Characteristic
Supply voltage for Logic Power Supply voltage for I/O Power Supply voltage for Analog Power Ambient operating temperature PLL clock frequency1 Operating Frequency2 Frequency of peripheral bus Frequency of external clock Frequency of oscillator Frequency of clock via XTAL Frequency of clock via EXTAL
Symbol
VDD VDDIO VDDA TA fpll fop fipb fclk fosc fxtal fextal
Min
1.62 3.0 3.0 -40 -- -- -- -- 2 -- 2
Max
1.98 3.6 3.6 85 240 120 60 240 4 240 4
Unit
V V V C MHz MHz MHz MHz MHz MHz MHz
1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and selected. The actual frequency depends on the source clock frequency and programming of the CGM module. 2. Master clock is derived from on of the following four sources: fclk = fxtal when the source clock is the direct clock to EXTAL fclk = fpll when PLL is selected fclk = fosc when the source clock is the crystal oscillator and PLL is not selected fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected
Table 6. Thermal Characteristics1
Symbol Characteristic 144-pin LQFP Thermal resistance junction-to-ambient (estimated) I/O pin power dissipation Power dissipation Maximum allowed PD
1. See Section 6.1 for more detail.
Value 144 MAPBGA 36.1 User Determined PD = (IDD x VDD) + PI/O (TJ - TA) / JA
Unit
JA PI/O PD PDMAX
42.9
C/W W W C
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DSP56858 Preliminary Technical Data
21
4.2 DC Electrical Characteristics
Table 7. DC Electrical Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage Input low voltage Input current low (pullups disabled) Input current high (pullups disabled) Output tri-state current low Output tri-state current high Output High Voltage Output Low Voltage Output High Current Output Low Current Input capacitance Output capacitance VDD supply current @ nominal voltage and 25 C Run Deep Stop2 Light Stop3 VDDIO supply current @ nominal voltage and 25 C Run5 VDDA supply current @ nominal voltage and 25 C Deep Stop
2 1
Symbol
VIHC VILC VIH VIL IIL IIH IOZL IOZH VOH VOL IOH IOL CIN COUT IDD4
Min
VDDA - 0.8 -0.3 2.0 -0.3 -1 -1 -10 -10 VDD - 0.7 -- 8 8 -- --
Typ
VDDA -- -- -- -- -- -- -- -- -- -- -- 8 12
Max
VDDA + 0.3 0.5 5.5 0.8 1 1 10 10 -- 0.4 16 16 -- --
Unit
V V V V A A A A V V mA mA pF pF
-- -- -- IDDIO -- IDDA -- VEI VEIH POR -- -- --
70 100 2.6
-- -- --
mA A mA
40
--
mA
60 2.5 50 1.5
-- 2.85 -- 2.0
A V mV V
Low Voltage Interrupt6 Low Voltage Interrupt Recovery Hysteresis Power on Reset7
1. Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
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DSP56858 Preliminary Technical Data
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Supply Voltage Sequencing and Separation Cautions
2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating. 3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating. 4. 5. 6. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry. Running core and performing external memory access. Clock at 120 MHz. When VDD drops below VEI max value, an interrupt is generated.
7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.
4.3 Supply Voltage Sequencing and Separation Cautions
Figure 3 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.
3.3V DC Power Supply Voltage
VDDIO, VDDA
2 1.8V
Supplies Stable VDD
1
0
Notes: 1. VDD rising before VDDIO, VDDA 2. VDDIO, VDDA rising much faster than VDD
Time
Figure 3. Supply Voltage Sequencing and Separation Cautions
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4. This keeps VDD from rising faster than VDDIO. VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 4. The series diodes forward bias when the difference between VDDIO and VDD reaches approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper operation, the difference between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: VDDIO > VDD > (VDDIO - 2.1V)
MOTOROLA
DSP56858 Preliminary Technical Data
23
In practice, VDDA is typically connected directly to VDDIO with some filtering.
3.3V Regulator VDDIO, VDDA
Supply
1.8V Regulator
VDD
Figure 4. Example Circuit to Control Supply Sequencing
4.4 AC Electrical Characteristics
Timing waveforms in Section 4.3 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 5 the levels of VIH and VIL for an input signal are shown.
VIH Input Signal Midpoint1 Fall Time
Note: The midpoint is VIL + (VIH - VIL)/2.
Low
High
90% 50% 10%
VIL
Rise Time
Figure 5. Input Signal Measurement References
Figure 6 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid Data1 Data Invalid State Data Active
Data2 Valid Data2 Data Tri-stated
Data3 Valid Data3
Data Active
Figure 6. Signal States
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DSP56858 Preliminary Technical Data
MOTOROLA
External Clock Operation
4.5 External Clock Operation
The DSP56858 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins.
4.5.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 9. In Figure 7 a typical crystal oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 2-4MHz (optimized for 4MHz)
EXTAL XTAL Rz
Sample External Crystal Parameters: Rz = 10M TOD_SEL bit in CGM must be set to 0 fc = 4MHz
fC
Figure 7. Crystal Oscillator
4.5.2
High Speed External Clock Source (> 4MHz)
The recommended method of connecting an external clock is given in Figure 8. The external clock source is connected to XTAL and the EXTAL pin is held at ground, VDDA, or VDDA/2. The TOD_SEL bit in CGM must be set to 0.
DSP56858 XTAL EXTAL GND,VDDA, External Clock or VDDA/2 (up to 240MHz)
Figure 8. Connecting a High Speed External Clock Signal using XTAL
4.5.3
Low Speed External Clock Source (2-4MHz)
The recommended method of connecting an external clock is given in Figure 9. The external clock source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM must be set to 0.
MOTOROLA
DSP56858 Preliminary Technical Data
25
DSP56858 XTAL EXTAL External Clock (2-4MHz)
VDDA/2
Figure 9. Connecting a Low Speed External Clock Signal using XTAL Table 8. External Clock Operation Timing Requirements4
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
Frequency of operation (external clock driver)1 Clock Pulse Width4 External clock input rise time2, 4 External clock input fall time3, 4
1. 2. 3. 4.
Symbol
fosc tPW trise tfall
Min
0 6.25 -- --
Typ
-- -- -- --
Max
240 -- TBD TBD
Unit
MHz ns ns ns
See Figure 8 for details on using the recommended connection of an external clock driver. External clock input rise time is measured from 10% to 90%. External clock input fall time is measured from 90% to 10%. Parameters listed are guaranteed by design.
VIH
External Clock
90% 50% 10%
tPW
tPW tfall trise
90% 50% 10% VIL
Note: The midpoint is VIL + (VIH - VIL)/2.
Figure 10. External Clock Timing Table 9. PLL Timing
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
External reference crystal frequency for the PLL1 PLL output frequency PLL stabilization time 2
Symbol
fosc fclk tplls
Min
2 40 --
Typ
4 -- 1
Max
4 240 10
Unit
MHz MHz ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 4MHz input crystal. 2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
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DSP56858 Preliminary Technical Data
MOTOROLA
External Memory Interface Timing
4.6 External Memory Interface Timing
Table 10. External Memory Interface Timing 1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz, TOP = 8.3, FIPB = 60MHz, TIPB = 16.6
Characteristic
Address Valid to WR Asserted WR Width Asserted Wait states > 1 D0-D15 Out Valid to WR Asserted Data Out Hold Time from WR Deasserted Data Out Set Up Time to WR Deasserted Wait states > 1 RD Deasserted to Address Not Valid Address Valid to RD Deasserted Wait states > 1 Input Data Hold to RD Deasserted RD Assertion Width Wait states > 1 Address Valid to Input Data Valid Wait states > 1 Address Valid to RD Asserted RD Asserted to Input Data Valid Wait states > 1 WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted
Symbol
tAWR tWR
Typical Min
4.36
Typical Max
--
Unit
ns
(TIPB*WS) - .81 tWRD tDOH tDOS (TIPB*WS) + 4.76 tRDA tARDD (TIPB*WS) - 2.28 tDRD tRD (TIPB*WS) - 1.58 tAD -- tARDA tRDD -- tWRRD4 tRDRD4 tWRWR4 tRDWR4 TOP TOP x 2 TOP x 2 TOP x 3 -1.70 0 12.65 4.57 5.37
-- -- --
ns ns ns
-- --
ns ns
-- --
ns ns
--
ns
(TIPB*WS) - 21.76 --
ns ns
(TIPB*WS) - 21.06 -- -- -- --
ns ns ns ns ns
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states (min. 1) and Top = System Clock Period. 2. 3. Parameters listed are guaranteed by design. EMI operates at fipb rate. Wait states are in terms of fipb periods.
4. Shows separation of R/W enables in system cycles (Top) in data space using consecutive one-word assembly language instructions.
MOTOROLA
DSP56858 Preliminary Technical Data
27
A0-A20, CS (See Note)
tARDA
tARDD tRDA tRD tWR tWRRD tRDRD
RD
tAWR tWRWR
tRDWR tRDD tDRD Data In
WR
tWRD tDOS tAD tDOH Data Out
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 11. External Memory Interface Timing
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 11. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration3 RESET Deassertion to First External Address Output Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State4 IRQA Width Assertion to Recover from Stop State5 Fast6 Normal7, 8
Symbol
Typical Min
-- 30 -- 1T + 3 --
Typical Max
11 -- 120T -- 18T
Unit
See Figure
Figure 12 Figure 12 Figure 12 Figure 13 Figure 14
tRAZ tRA tRDA tIRW tIDM
ns ns ns ns ns
tIG
--
18T
ns
Figure 14
tIRI
--
13T
ns
Figure 15
tIW 4T 8ET -- -- ns ns Figure 16
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DSP56858 Preliminary Technical Data
MOTOROLA
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 11. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) Fast5 Normal6,7 RSTO pulse width7 normal operation internal reset mode
1. 2.
Symbol
tIF
Typical Min
Typical Max
Unit
See Figure
Figure 16
-- -- tRSTO 128ET 8ET
13T 25ET
ns ns Figure 17
-- --
-- --
In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock, txtal, textal or tosc. 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Wait state. This is not the minimum required so that the IRQA interrupt is accepted. 5. 6. This interrupt instruction fetch is visible on the pins only in Mode 3. Fast stop mode:
Fast stop recovery applies when fast stop mode recovery is requested (OMR bit 6 is set to 1). The PLL and the master clock are unaffected by stop mode entry. Recovery takes one less cycle and tclk will continue with the same value it had before stop mode was entered. 7. Normal stop mode: As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate. 8. ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.
RESET tRA tRAZ tRDA
A0-A20, D0-D15 CS, RD, WR
First Fetch
First Fetch
Figure 12. Asynchronous Reset Timing
IRQA IRQB
tIRW
Figure 13. External Interrupt Timing (Negative-Edge-Sensitive)
MOTOROLA
DSP56858 Preliminary Technical Data
29
A0-A20, CS,
RD, WR tIDM
First Interrupt Instruction Execution
IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin IRQA, IRQB b) General Purpose I/O
tIG
Figure 14. External Level-Sensitive Interrupt Timing
IRQA, IRQB
tIRI
A0-A20, CS, RD, WR
First Interrupt Vector Instruction Fetch
Figure 15. Interrupt from Wait State Timing
tIW
IRQA
tIF
A0-A20, CS, RD, WR
First Instruction Fetch Not IRQA Interrupt Vector
Figure 16. Recovery from Stop State Using Asynchronous Interrupt Timing
RESET
tRSTO
Figure 17. Reset Output Timing
30 DSP56858 Preliminary Technical Data MOTOROLA
Host Interface Port
4.8 Host Interface Port
Table 12. Host Interface Port Timing1
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
Access time Disable time Time to disassert Lead time Access time Disable time Disable time Setup time Hold time Setup time Hold time Pulse width Time to re-assert 1. After second write in 16-bit mode 2. After first write in 16-bit mode or after write in 8-bit mode
1.
Symbol
TACKDV TACKDZ TACKREQH
Min
-- 3 3.5 0 -- 5 3 3 1 3 1 5
Max
13 -- 9 -- 13 -- -- -- -- -- -- --
Unit See Figure
ns ns ns ns ns ns ns ns ns ns ns ns Figure 18 Figure 18 Figure 18 Figure 21 Figure 18 Figure 21 Figure 19 Figure 20 Figure 19 Figure 20 Figure 19 Figure 20 Figure 21 Figure 21 Figure 22 Figure 23 Figure 22 Figure 23 Figure 22 Figure 23 Figure 18, Figure 21
TREQACKL
TRADV
TRADX
TRADZ TDACKS TACKDH TADSS
TDSAH
TWDS
TACKREQL
4T + 5 5
5T + 9 13
ns ns
The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.
HACK
TACKDZ TACKDV
HD
TREQACKL TACKREQH TACKREQL
HREQ
Figure 18. DSP-to-Host DMA Read Mode
MOTOROLA
DSP56858 Preliminary Technical Data
31
HA
TRADX
HCS
HDS
HRW
TRADV TRADZ
HD
Figure 19. Single Strobe Read Mode
HA
TRADX
HCS
HWR
HRD
TRADZ TRADV
HD
Figure 20. Dual Strobe Read Mode
HACK
TDACKS TACKDH
HD
TREQACKL TACKREQH TACKREQL
HREQ
Figure 21. Host-to-DSP DMA Write Mode
32
DSP56858 Preliminary Technical Data
MOTOROLA
Host Interface Port
HA
TDSAH
HCS
TWDS
HDS
TDSAH
HRW
TADSS TADSS TDSAH
HD
Figure 22. Single Strobe Write Mode
HA
HCS
TWDS
HWR
TADSS TDSAH
HRD
TADSS
HD
Figure 23. Dual Strobe Write Mode
MOTOROLA
DSP56858 Preliminary Technical Data
33
4.9 Serial Peripheral Interface (SPI) Timing
Table 13. SPI Timing 1
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave
1. Parameters listed are guaranteed by design.
Symbol tC
Min
Max
Unit
See Figure Figures 24, 25, 26, 27
25 25 tELD -- 12.5 tELG -- 12.5 tCH 9 12.5 tCL 12 12.5 tDS 10 2 tDH 0 2 tA 5 tD 2 tDV -- -- tDI 0 0 tR -- -- tF -- --
-- --
ns ns
Figure 27 -- -- ns ns Figure 27 -- -- ns ns ns ns Figures 24, 25, 26, 27
-- --
Figure 27 -- -- ns ns Figures 24, 25, 26, 27
-- --
ns ns
-- --
ns ns ns ns ns ns
Figures 24, 25, 26, 27
Figure 27
15
Figure 27
9
2 14
ns ns
Figures 24, 25, 26, 27
-- --
ns ns
Figures 24, 25, 26, 27
11.5 10.0
ns ns
Figures 24, 25, 26, 27
9.7 9.0
ns ns
Figures 24, 25, 26, 27
34
DSP56858 Preliminary Technical Data
MOTOROLA
Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tC tR tF
SCLK (CPOL = 0) (Output)
tCL tCH tF tR tCL
SCLK (CPOL = 1) (Output)
tDH tDS tCH tCH
MISO (Input)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14-1
Master LSB out
tR
Figure 24. SPI Master Timing (CPHA = 0)
SS
(Input)
tC
SS is held High on master
tF tCL tR
SCLK (CPOL = 0) (Output)
tCH tF tCL
SCLK (CPOL = 1) (Output)
tCH tDS tR tDH
MISO (Input)
tDV(ref)
MSB in
tDI
Bits 14-1
tDV
LSB in
MOSI (Output)
Master MSB out
tF
Bits 14- 1
Master LSB out
tR
Figure 25. SPI Master Timing (CPHA = 1)
MOTOROLA DSP56858 Preliminary Technical Data 35
SS
(Input)
tC tCL tCH tELD tCL tR tF tELG
SCLK (CPOL = 0) (Input)
SCLK (CPOL = 1) (Input)
tA tCH tR tF tD
MISO (Output)
tDS
Slave MSB out
tDH
Bits 14-1
tDV
Slave LSB out
tDI tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 26. SPI Slave Timing (CPHA = 0)
SS
(Input)
tF tC tR tCL tCH tELD tELG tCL tDV tA tCH tF tR tD
SCLK (CPOL = 0) (Input)
SCLK (CPOL = 1) (Input)
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 27. SPI Slave Timing (CPHA = 1)
36
DSP56858 Preliminary Technical Data
MOTOROLA
Quad Timer Timing
4.10 Quad Timer Timing
Table 14. Quad Timer Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
Timer input period Timer input high/low period Timer output period Timer output high/low period
1. 2.
Symbol
PIN PINHL POUT POUTHL
Min
2T + 3 1T + 3 2T - 3 1T - 3
Max
-- -- -- --
Unit
ns ns ns ns
In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns. Parameters listed are guaranteed by design.
Timer Inputs
PIN PINHL PINHL
Timer Outputs
POUT POUTHL POUTHL
Figure 28. Timer Timing
Enhanced Synchronous Serial Interface (ESSI) Timing
Table 15. ESSI Master Mode1 Switching Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Parameter
SCK frequency SCK period3 SCK high time SCK low time Output clock rise/fall time Delay from SCK high to SC2 (bl) high - Master5 Delay from SCK high to SC2 (wl) high - Master5 Delay from SC0 high to SC1 (bl) high - Master5 Delay from SC0 high to SC1 (wl) high - Master5 Delay from SCK high to SC2 (bl) low - Master5
Symbol
fs tSCKW tSCKH tSCKL -- tTFSBHM tTFSWHM tRFSBHM tRFSWHM tTFSBLM
Min
-- 66.7 33.44 33.44 -- -1.0 -1.0 -1.0 -1.0 -1.0
Typ
-- -- -- -- 4 -- -- -- -- --
Max
152 -- -- -- -- 1.0 1.0 1.0 1.0 1.0
Units
MHz ns ns ns ns ns ns ns ns ns
MOTOROLA
DSP56858 Preliminary Technical Data
37
Table 15. ESSI Master Mode1 Switching Characteristics(Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Parameter
Delay from SCK high to SC2 (wl) low - Master5 Delay from SC0 high to SC1 (bl) low - Master5 Delay from SC0 high to SC1 (wl) low - Master5 SCK high to STD enable from high impedance - Master SCK high to STD valid - Master SCK high to STD not valid - Master SCK high to STD high impedance - Master SRD Setup time before SC0 low - Master SRD Hold time after SC0 low - Master
Symbol
tTFSWLM tRFSBLM tRFSWLM tTXEM tTXVM tTXNVM tTXHIM tSM tHM
Min
-1.0 -1.0 -1.0 -0.1 -0.1 -0.1 -4 4 4
Typ
-- -- -- -- -- -- -- -- --
Max
1.0 1.0 1.0 2 2 -- 0 -- --
Units
ns ns ns ns ns ns ns ns ns
Synchronous Operation (in addition to standard internal clock parameters) SRD Setup time before SCK low - Master SRD Hold time after SCK low - Master tTSM tTHM 4 4 -- -- -- -- ns ns
1. Master mode is internally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part. 3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length
38
DSP56858 Preliminary Technical Data
MOTOROLA
Quad Timer Timing
tSCKW tSCKH tSCKL SCK output tTFSBHM SC2 (bl) output tTFSWHM SC2 (wl) output tTXVM tTXEM STD SC0 output tRFSBHM SC1 (bl) output tRFSWHM SC1 (wl) output tTSM tSM SRD tHM tTHM tRFSWLM tRFBLM First Bit tTFSWLM tTFSBLM
tTXNVM Last Bit
tTXHIM
Figure 29. Master Mode Timing Diagram
Table 16: ESSI Slave Mode1 Switching Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Parameter
SCK frequency SCK period3 SCK high time SCK low time Output clock rise/fall time Delay from SCK high to SC2 (bl) high - Slave5 Delay from SCK high to SC2 (wl) high - Slave5 Delay from SC0 high to SC1 (bl) high - Slave5
Symbol
fs tSCKW tSCKH tSCKL -- tTFSBHS tTFSWHS tRFSBHS
Min
-- 66.7 33.44 33.44 -- -1 -1 -1
Typ
-- -- -- -- 4 -- -- --
Max
152 -- -- -- -- 29 29 29
Units
MHz ns ns ns ns ns ns ns
MOTOROLA
DSP56858 Preliminary Technical Data
39
Table 16: ESSI Slave Mode1 Switching Characteristics(Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Parameter
Delay from SC0 high to SC1 (wl) high - Slave5 Delay from SCK high to SC2 (bl) low - Slave5 Delay from SCK high to SC2 (wl) low - Slave5 Delay from SC0 high to SC1 (bl) low - Slave5 Delay from SC0 high to SC1 (wl) low - Slave5 SCK high to STD enable from high impedance - Slave SCK high to STD valid - Slave SC2 high to STD enable from high impedance (first bit) - Slave SC2 high to STD valid (first bit) - Slave SCK high to STD not valid - Slave SCK high to STD high impedance - Slave SRD Setup time before SC0 low - Slave SRD Hold time after SC0 low - Slave
Symbol
tRFSWHS tTFSBLS tTFSWLS tRFSBLS tRFSWLS tTXES tTXVS tFTXES tFTXVS tTXNVS tTXHIS tSS tHS
Min
-1 -29 -29 -29 -29 -- 4 4 4 4 4 4 4
Typ
-- -- -- -- -- -- -- -- -- -- -- -- --
Max
29 29 29 29 29 15 15 15 15 15 15 -- --
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns
Synchronous Operation (in addition to standard external clock parameters) SRD Setup time before SCK low - Slave SRD Hold time after SCK low - Slave tTSS tTHS 4 4 -- -- -- -- ns ns
1. Slave mode is externally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. 3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length
40
DSP56858 Preliminary Technical Data
MOTOROLA
Serial Communication Interface (SCI) Timing
tSCKW tSCKH SCK input tTFSBLS tTFSBHS SC2 (bl) input tTFSWHS SC2 (wl) input tFTXES tTXES STD SC0 input tRFSBHS SC1 (bl) input tRFSWHS SC1 (wl) input tTSS tRFSWLS tRFBLS tTXVS First Bit tFTXVS tTXNVS tTXHIS Last Bit tTFSWLS tSCKL
tSS SRD
tHS
tTHS
Figure 30. Slave Mode Clock Timing
4.11 Serial Communication Interface (SCI) Timing
Table 17. SCI Timing4
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width
1. 2. 3. 4.
Symbol
BR RXDPW TXDPW
Min
-- 0.965/BR 0.965/BR
Max
(fMAX)/(32) 1.04/BR 1.04/BR
Unit
Mbps ns ns
fMAX is the frequency of operation of the system clock in MHz. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. Parameters listed are guaranteed by design.
MOTOROLA
DSP56858 Preliminary Technical Data
41
RXD SCI receive data pin (Input)
RXDPW
Figure 31. RXD Pulse Width
TXD SCI receive data pin (Input)
TXDPW
Figure 32. TXD Pulse Width
4.12 JTAG Timing
Table 18. JTAG Timing1, 3
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
TCK frequency of operation2 TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time
Symbol
fOP tCY tPW tDS tDH tDV tTS tTRST tDE
Min
DC 33.3 16.6 3 3 -- -- 35 4T
Max
30 -- -- -- -- 12 10 -- --
Unit
MHz ns ns ns ns ns ns ns ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation, T = 8.33ns. 2. 3. TCK frequency of operation must be less than 1/4 the processor rate. Parameters listed are guaranteed by design.
42
DSP56858 Preliminary Technical Data
MOTOROLA
JTAG Timing
tCY tPW
VIH
tPW
VM
TCK (Input) VM = VIL + (VIH - VIL)/2
VM VIL
Figure 33. Test Clock Input Timing Diagram
TCK (Input)
tDS tDH
TDI TMS (Input) TDO (Output)
Input Data Valid
tDV
Output Data Valid
tTS
TDO (Output)
Figure 34. Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 35. TRST Timing Diagram
DE tDE
Figure 36. Enhanced OnCE--Debug Event
MOTOROLA
DSP56858 Preliminary Technical Data
43
4.13 GPIO Timing
Table 19. GPIO Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, fop = 120MHz
Characteristic
GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period
1.
Symbol
PIN PINHL POUT POUTHL
Min
2T + 3 1T + 3 2T - 3 1T - 3
Max
-- -- -- --
Unit
ns ns ns ns
In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns Parameters listed are guaranteed by design.
2.
GPIO Inputs PIN PINHL PINHL
GPIO Outputs POUT POUTHL POUTHL
Figure 37. GPIO Timing
44
DSP56858 Preliminary Technical Data
MOTOROLA
Package and Pin-Out Information DSP56853
Part 5 Packaging
5.1 Package and Pin-Out Information DSP56853
This section contains package and pin-out information for the 144-pin LQFP configuration of the DSP56858.
MISO MOSI SCK SS VDDIO VDDIO VSSIO RD WR A0 A1 A2 A3 VDD VSS VSS MODA MODB MODC VDDIO VSSIO IRQA IRQB VDDA VSSA VSSA XTAL EXTAL A4 A5 A6 A7 HD0 HD1 HD2 VDD
D15 D14 D13 VSSIO VSSIO VDDIO D12 D11 SC02 SC01 SC00 SCK0 SRD0 STD0 VSSIO VDDIO VSSIO VSS VSS VDD D10 D9 D8 D7 D6 HACK HREQ HCS HDS VSSIO TIO0 VDDIO TIO1 TIO2 TIO3 VDD
Orientation Mark PIN 1 PIN 109
Motorola DSP56858
PIN 37
PIN 73
TXD1 RXD1 VSSIO VDDIO SC12 SC11 SC10 SCK1 SRD1 STD1 D5 D4 D3 D2 D1 HRWB HA2 HA1 HA0 VSS VDD VDD CS3 CS2 CS1 CS0 VSSIO D0 VDDIO A20 A19 A18 A17 A16 TXD0 RXD0
MOTOROLA
CLKO RSTO RESET HD3 HD4 HD5 HD6 HD7 VDDIO VSSIO VSSIO A8 A9 A10 A11 VDD VSS VSS DE TRST TDO TDI TMS TCK VDDIO VSSIO A12 A13 A14 A15 VDDIO VDDIO VSSIO VSSIO VSS VDD
Figure 38. Top View, DSP56858 144-pin LQFP Package
DSP56858 Preliminary Technical Data
45
Table 20. DSP56858 Pin Identification by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name MISO MOSI SCK SS VDDIO VDDIO VSSIO RD WR A0 A1 A2 A3 VDD VSS VSS MODA MODB MODC VDDIO VSSIO IRQA IRQB VDDA VSSA Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Signal Name CLKO RSTO RESET HD3 HD4 HD5 HD6 HD7 VDDIO VSSIO VSSIO A8 A9 A10 A11 VDD VSS VSS DE TRST TDO TDI TMS TCK VDDIO Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Signal Name RXD0 TXD0 A16 A17 A18 A19 A20 VDDIO D0 VSSIO CS0 CS1 CS2 CS3 VDD VDD VSS HA0 HA1 HA2 HRWB D1 D2 D3 D4 Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 Signal Name VDD TIO3 TIO2 TIO1 VDDIO TIO0 VSSIO HDS HCS HREQ HACK D6 D7 D8 D9 D10 VDD VSS VSS VSSIO VDDIO VSSIO STD0 SRD0 SCK0
46
DSP56858 Preliminary Technical Data
MOTOROLA
Package and Pin-Out Information DSP56853
Table 20. DSP56858 Pin Identification by Pin Number
Pin No. 26 27 28 29 30 31 32 33 34 35 36 Signal Name VSSA XTAL EXTAL A4 A5 A6 A7 HD0 HD1 HD2 VDD Pin No. 62 63 64 65 66 67 68 69 70 71 72 Signal Name VSSIO A12 A13 A14 A15 VDDIO VDDIO VSSIO VSSIO VSS VDD Pin No. 98 99 100 101 102 103 104 105 106 107 108 Signal Name D5 STD1 SRD1 SCK1 SC10 SC11 SC12 VDDIO VSSIO RXD1 TXD1 Pin No. 134 135 136 137 138 139 140 141 142 143 144 Signal Name SC00 SC01 SC02 D11 D12 VDDIO VSSIO VSSIO D13 D14 D15
MOTOROLA
DSP56858 Preliminary Technical Data
47
Figure 39. 144-pin LQFP Mechanical Information
48
DSP56858 Preliminary Technical Data
MOTOROLA
Package and Pin-Out Information DSP56853
This section contains package and pin-out information for the 144-pin MAPBGA configuration of the DSP56858.
METALLIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
12
11
10
9
8
7
6
5
4
3
2
1 A
VDD
VDDIO
VSSIO
VDD
VSS
VSS
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
B
VSSIO RXD1 TIO3 TIO0 HREQ D7 STD0 SC01 D12 D15 MISO VDDIO
C
VDDIO SC12 TXD1 TIO1 HDS HACK SRD0 SCK0 D13 MOSI SCK VDDIO
D
VSS SC11 SC10 TIO2 HCS D6 SC00 D11 WR RD SS VSSIO
E
VDD SRD1 D5 SCK1 STD1 D8 SC02 A0 A1 A2 A3 VDD
F
VDD D4 D3 D2 D9 D10 D14 IRQB MODA MODB MODC VSS
G
VSSIO HA1 HA0 HA2 HRWB D1 TDO A8 A6 EXTAL IRQA VSS
H
VDDIO CS2 CS3 CS1 CS0 D0 DE HD7 A7 A5 XTAL VDDIO
J
VDD A20 A19 A18 A12 TMS A10 HD5 HD3 HD0 A4 VSSIO
K
VSS A17 A16 A15 A13 TDI A11 HD6 RESET RSTO HD1 VDDA
L
VSSIO TXD0 RXD0 A14 TCK TRST VSS A9 HD4 CLKO HD2 VSSA
M
VSS10 VDDIO VDDIO VSSIO VDDIO VSS VDD VSSIO VSSIO VDDIO VDD VSSA
Figure 40. Bottom-View, DSP56858 144-pin MAPBGA Package
MOTOROLA
DSP56858 Preliminary Technical Data
49
Table 21. DSP56858 Pin Identification by Pin Number
Pin No. E5 E4 E3 E2 J2 H3 G4 H4 G5 L5 J6 K6 J8 K8 L9 K9 K10 K11 J9 J10 J11 L3 H8 H9 H11 H10 Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CLKO CS0 CS1 CS2 CS3 Pin No. F7 D5 B4 C4 F6 B3 H6 G3 M1 L1 G1 L6 D12 A7 F1 M7 K12 A8 D1 J1 M5 M9 L12 G12 B12 A10 Signal Name D10 D11 D12 D13 D14 D15 DE EXTAL VSSA VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO Pin No. D8 J3 K2 L2 J4 L4 J5 K5 H5 C8 B8 G8 G2 F5 B2 F4 F3 F2 C3 K1 E1 M6 F12 A9 M2 J12 Signal Name HCS HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HDS HREQ HRWB IRQA IRQB MISO MODA MODB MODC MOSI VDDA VDD VDD VDD VDD VDD VDD Pin No. A5 A3 C1 M10 D3 K4 K3 L10 B11 D6 B5 E6 D10 D11 C11 C5 E9 C2 C6 E11 D2 B6 E8 L8 K7 G6 Signal Name VDDIO VDDIO VDDIO VDDIO RD RESET RSTO RXD0 RXD1 SC00 SC01 SC02 SC10 SC11 SC12 SCK0 SCK1 SCK SRD0 SRD1 SS STD0 STD1 TCK TDI TDO
50
DSP56858 Preliminary Technical Data
MOTOROLA
Package and Pin-Out Information DSP56853
Table 21. DSP56858 Pin Identification by Pin Number
Pin No. H7 G7 F9 F10 F11 E10 D7 B7 E7 F8 Signal Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Pin No. A4 A1 A2 M4 M12 A6 G10 G11 G9 C7 Signal Name VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO HA0 HA1 HA2 HACK Pin No. E12 A12 B1 H1 M3 M8 M11 H12 C12 A11 Signal Name VDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO Pin No. B9 C9 D9 B10 J7 L7 L11 C10 D4 H2 Signal Name TIO0 TIO1 TIO2 TIO3 TMS TRST TXD0 TXD1 WR XTAL
MOTOROLA
DSP56858 Preliminary Technical Data
51
X Y
D
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
Detail K
M
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
0.20
S 11X
12 11 10 9
e
8 5 4 3 2 1 METALIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA A B C
MILLIMETERS DIM MIN MAX A --1.60 A1 0.27 0.47 A2 1.16 REF b 0.40 0.60 D 13.00 BSC E 13.00 BSC e 1.00 BSC S 0.50 BSC
11X
e
D E F G
5 A A2 0.20 Z
S
H J K L
A1
Z
4
0.12 Z
3
144X
M
ROTATED 90 CLOCKWISE
DETAIL K
b 0.25 ZX Y Z
VIEW M-M
0.10
CASE 1242A-03
Figure 41. 144-pin MAPBGA Mechanical Information
52
DSP56858 Preliminary Technical Data
MOTOROLA
Thermal Design Considerations
Part 6 Design Considerations
6.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple. RJA = RJC + RCA TJ = TA + (PD x RJA)
* *
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading
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on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
6.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct DSP operation: * * Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place six 0.01-0.1 F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND. Bypass the VDD and GND layers of the PCB with approximately 100 F, preferably with a highgrade capacitor such as a tantalum capacitor. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Take special care to minimize noise levels on the VDDA and VSSA pins. When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pullup device.
* * * * *
* * *
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DSP56858 Preliminary Technical Data
MOTOROLA
Electrical Design Considerations
*
Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but requires that TRST be asserted at power on.
*
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Part 7 Ordering Information
Table 22 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts.
Table 22. DSP56858 Ordering Information
Part
DSP56858 DSP56858
Supply Voltage
1.8V, 3.3V 1.8V, 3.3V
Package Type
Low-Profile Quad Flat Pack (LQFP) MAP Ball Grid Array (MAPBGA)
Pin Count
144 144
Frequency (MHz)
120 120
Order Number
DSP56858FV120 DSP56858VF120
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MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2002. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
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