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DS1249Y/AB 2048k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation Read and write access times as fast as 70 ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full =10% VCC operating range (DS1249Y) Optional =5% VCC operating range (DS1249AB) Optional industrial temperature range of -40C to +85C, designated IND JEDEC standard 32-pin DIP package PIN ASSIGNMENT NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 32-Pin ENCAPSULATED PACKAGE 740-mil EXTENDED PIN DESCRIPTION A0 - A17 DQ0 - DQ7 CE WE OE VCC GND NC - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+5V) - Ground - No Connect DESCRIPTION The DS1249 2048k Nonvolatile SRAMs are 2,097,152-bit, fully static, nonvolatile SRAMs organized as 262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles which can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 033004 DS1249Y/AB READ MODE The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs (A0 - A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than tACC. WRITE MODE The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1249AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1249Y provides full-functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protects themselves, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1249AB and 4.5 volts for the DS1249Y. FRESHNESS SEAL Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation. 2 of 8 DS1249Y/AB ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -0.3V to +6.0V 0C to 70C, -40C to +85C for IND parts -40C to +70C, -40C to +85C for IND parts 260C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER DS1249AB Power Supply Voltage DS1249Y Power Supply Voltage Logic 1 Logic 0 SYMBOL VCC VCC VIH VIL MIN 4.75 4.5 2.2 0.0 TYP 5.0 5.0 MAX 5.25 5.5 VCC 0.8 (tA: See Note 10) UNITS V V V V NOTES DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current CE VIH VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE =2.2V Standby Current CE =VCC-0.5V Operating Current Write Protection Voltage (DS1249AB) Write Protection Voltage (DS1249Y) (VCC=5V =5% for DS1249AB) (tA: See Note 10) (VCC=5V =10% for DS1249Y) SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VTP VTP 4.50 4.25 4.62 4.37 MIN -2.0 -2.0 -1.0 2.0 1.0 100 1.5 150 85 4.75 4.5 TYP MAX +2.0 +2.0 UNITS A A mA mA mA A mA V V NOTES CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 10 10 MAX 20 20 pF pF (tA=25C) UNITS NOTES 3 of 8 DS1249Y/AB AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Access Time OE CE OE (VCC=5V =5% for DS1249AB) (tA: See Note 10) (VCC=5V =10% for DS1249Y) DS1249AB-70 DS1249Y-70 DS1249AB-100 DS1249Y-100 SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 MIN 70 MAX 70 35 70 MIN 100 MAX 100 50 100 UNITS ns ns ns ns ns NOTES to Output Valid to Output Valid or CE to Output Active 5 25 5 70 55 0 5 15 25 5 30 0 10 5 35 5 100 75 0 5 15 35 5 40 0 10 5 5 Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time ns ns ns ns ns ns ns ns ns ns ns ns 3 12 13 5 5 4 12 13 4 of 8 DS1249Y/AB READ CYCLE SEE NOTE 1 WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12 5 of 8 DS1249Y/AB WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8, and 13 POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 6 of 8 DS1249Y/AB POWER-DOWN/POWER-UP TIMING PARAMETER VCC Fail Detect to CE and WE Inactive VCC slew from VTP to 0V VCC slew from 0V to VTP VCC Valid to CE and WE Inactive VCC Valid to End of Write Protection SYMBOL tPD tF tR tPU tREC 150 150 2 125 MIN TYP MAX 1.5 (tA: See Note 10) UNITS s s s ms ms NOTES 11 (tA=25C) PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a Read Cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition in Write Cycle 1, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1249 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to 70C. For industrial products (IND), this range is -40C to +85C. 11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. DS1249 modules are recognized by Underwriters Laboratory (U.L.) under file E99151. 7 of 8 DS1249Y/AB DC TEST CONDITIONS Outputs Open Cycle = 200 ns for operating current All voltages are referenced to ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns ORDERING INFORMATION DS1249 TTP - SSS - III Operating Temperature Range blank: 0 to 70 IND: -40 to +85C Access Speed 70: 70 ns 100: 100 ns Package Type blank: 32-pin, 600-mil DIP VCC Tolerance Y: 10% AB: 5% DS1249Y/AB NONVOLATILE SRAM, 32-PIN, 740-MIL EXTENDED MODULE PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 32-PIN MIN 2.080 52.83 0.715 18.16 0.395 10.03 0.280 7.11 0.015 0.38 0.120 3.05 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.43 MAX 2.100 53.34 0.740 18.80 0.405 10.29 0.310 7.49 0.030 0.76 0.160 4.06 0.110 2.79 0.630 16.00 0.012 0.30 0.025 0.58 8 of 8 |
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