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| MIC8030 Micrel MIC8030 High-Voltage Display Driver General Description The MIC8030 is a CMOS high voltage liquid crystal display driver. Up to 38 segments can be driven from four CMOS level inputs (CLOCK, DATA IN, LOAD and CHIP SELECT). The MIC8030 is rated at 50V. Data is loaded serially into a shift register, and transferred to latches which hold the data until new data is received. The backplane can be driven from external source, or the internal oscillator can be used. If the internal oscillator is used, the frequency of the backplane will be determined by an external resistor and capacitor. The oscillator need not be used if a DC output is desired. Features * High Voltage Outputs capable of a driving up to 100 volt outputs from 5 to 15 volt logic * Drives 30, 32, or 38 segments * Cascadable * On chip Oscillator or External Backplane Input * CMOS construction for wide supply range and low power consumption * Schmitt Triggers on all inputs * CMOS, PMOS, and NMOS compatible Applications * * * * Dichroic and Standard Liquid Crystal Displays Flat Panel Displays Print Head Drives Vacuum Fluorescent Displays Functional Diagram Data S Data Out 38 Data Out 32 CS S Data Out 30 Ordering Information Part Number MIC8030-01CV 38 Bit Static Shift Register Temperature Range Package 0C to +70C 44-pin PLCC Clock S Load S 38 Bit Latch LCD0 LCD0 Opt Oscillator Voltage Translators Voltage Translator HV Output Driver HV Output Drivers Segments Back Plane MIC8030 8-16 October 1998 MIC8030 Micrel Pin Configuration Data Out 32 Back Plate Seg 25 Seg 24 Seg 23 Seg 22 Seg 21 Seg 20 Seg 19 Seg 18 40 39 Seg 17 38 Seg 16 37 Seg 15 36 VBB 35 Seg 14 MIC8030-01 34 Seg 13 33 Seg 12 32 Seg 11 31 Seg 10 30 Seg 9 29 Seg 8 19 21 23 Seg 4 25 LCD Opt. 20 Seg 6 27 18 22 24 Seg 5 26 Seg 7 28 43 44 Seg 26 Seg 27 Seg 28 Seg 29 Seg 30 Seg 31 Seg 32 VSS Chip Select Clock Load 7 8 9 10 11 12 13 14 15 16 17 Data In Seg 1 Seg 2 44-Pin PLCC (-V) Functional Description With CHIP SELECT tied low, serial data is clocked into the shift register at each falling edge of the CLOCK input. Pulling LOAD high will cause a parallel loading of the shift register contents into the latches. If load is left high, the latches are transparent. A logic "1" clocked into the shift register corresponds to that segment being on, and that segment is out of phase with the backplane. The backplane may be externally driven or the internal oscillator can be used. If LCD is externally driven, the backplane will be in phase with the input; LCD OPT is not connected. The internal oscillator is used by shorting LCD OPT to LCD, connecting a capacitor to ground, and a resistor to VCC. The frequency of the backplane will be 1/256 of the input frequency, and is given as: f = 10/[R(C + .0002)] at VDD = 5V, R in k, C in F. Example: R = 150 k, C = 420 pF: f = 108 Hz For displays with more than 38 segments, two or more MIC8030 may be cascaded by connecting DATA OUT of the previous stage with DATA IN of the next stage; CLOCK, LOAD and CHIP SELECT of all following stages should be tied to the control lines of the first MIC8030. The backplane output of the first stage should be tied to LCD of all following stages, the LCD OPT must be left unconnected on those stages. If the internal oscillator is used, and VBB > 50V then an external 330 k resistor must be used between the BACKPLANE of the first stage and LCD of all following stages. Packaging options available include DATA OUT 30, 32 or 38 with the corresponding number of segments, and the availability of LCD OPT. Types of packages include plastic and ceramic DIPs, surface mount packages, plastic and ceramic Leadless Chip Carriers and custom packaging. Seg 3 LCD VCC 42 41 6 4 5 3 2 1 N/C 8 October 1998 8-17 MIC8030 MIC8030 Micrel Internal Oscillator Circuit V CC 200k - + 200k - + 200k - + 200k 1k Divide by 256 Counter Reset Clock Q Q O LCD0 VZ 65V 30 k VZ 35V LCD0 Opt Typical Application External Oscillator Chip Select Clock Load Load Clock CS Data Data In Data Out Load Clock CS Data In Data Out Load Clock CS Data In Data Out MIC8030 LCD0 BP MIC8030 LCD0 BP MIC8030 LCD0 BP Segments 1-32 Segments 33-64 Back Plane Segments 65-96 Internal Oscillator Chip Select Clock Load Load Clock CS Data 150k Data In Data Out Load Clock CS Data In Data Out Load Clock CS Data In Data Out MIC8030 *330k LCD0 BP MIC8030 LCD0 BP MIC8030 LCD0 BP 470pF LCD0 Opt Segments 1-32 *Required if using MIC8031 with V BB > 50V. Segments 33-64 Back Plane Segments 65-96 MIC8030 8-18 October 1998 MIC8030 Micrel Absolute Maximum Ratings VCC VBB (MIC8030) Inputs (CLK, DATA IN, LOAD, CS) Inputs (LCD0) Storage Temperature Operating Temperature Maximum Current into and out of any segment Maximum Power Dissipation, any segment Maximum Total power dissipation 18V 75V -0.5V to 18V -0.5V to 50V -65C to +150C -55C to +125C 20 mA 50 mW 600 mW VCC = 5V, VSS = 0V, VBB = 50V, -55C TA +125C, unless otherwise noted. Condition Min Typ Max Units DC Electrical Characteristics: Symbol Power Supply VCC VBB ICC IBB VIH VIL IL CI Input LCD0 VIH VIL ILCD0 ILCD0 ILCD0 CLSEG CLBP VOAVG RSEG RBP RDATA OUT LCD0 Input High Level LCD0 Input Low Level LCD0 Leakage Current LCD0 Leakage Current LCD0 Leakage Current Logic Supply Voltage Display Supply Voltage Parameter 4.5 20 Note 1 Note 1 fBP = 100Hz, no loads 5 35 35 35 7 5.5 50 250 250 100 V V A A A Supply Current (external oscillator) Supply Current (internal oscillator) Display Driver Current Inputs (CLK, DATA IN, LOAD, CS) Input High Level Input Low Level Input Leakage Current Input Capacitance Note 2 VCC-1.5 VCC-1.8 0 2.5 <1 5 VCC 2.0 5 10 V V A pF Externally driven Externally driven VLCD0 = 15V VLCD0 = 35V VLCD0 = 50V fBP < 100Hz fBP < 100Hz fBP < 100Hz, Note 2 IL = 100A IL = 100A IL = 100A 0.9VCC -0.5V VCC 0 2 6 50 0.1VCC 10 100 1 V V A A mA 8 Capacitance Loads (typical) Segment Output Backplane Output DC Bias (Average) Any Segment 100 4000 +25 pF pF mV Output to Backplane Segment Output Impedance Backplane Output Impedance Data Out Output Impedance 1.4 170 1.8 10 312 3 k k Note 1: CMOS input levels. No loads. Note 2: Guaranteed by design but not tested on a production basis. October 1998 8-19 MIC8030 MIC8030 Micrel VCC = 5V, VSS = 0V, VBB = 50V, -55C TA +125C AC Electrical Characteristics: Symbol tCYC tOL, tOH tr, tf tDS tCSC tDH tCCS tCL tLCS tLW tLC tCDO tCSL FBP Parameter Cycle Time Min 500 250 Typ Max Units ns ns Clock Pulse Width low/high Clock rise/fall Data In Setup CS Setup to Clock Data Hold CS Hold Load Pulse Setup CS Hold (rising load to rising CS) Load Pulse Width Load Pulse Delay (falling load to falling clock) Data Out Valid from Clock CS Setup to LOAD Backplane Frequency 1 100 100 10 220 250 200 300 0 220 0 50 100 2000 s ns ns ns ns ns ns ns ns ns ns Hz Timing Diagram tCYC tOH tf Clock tDS Data In tCSC CS tCCS tLCS tDH tOL tr 3.5V 1.5V Logic Truth Table Data Chip In Clock Select Load Q1(SR) QN(SR) QN(DRIVER) X 0 0 0 0 X 1 0 0 0 0 0 0 0 0 X 0 1 0 1 0 1 0 1 NC NC NC 0 0 NC NC 1 1 NC NC NC QN - 1QN QN - 1QN NC NC QN - 1QN QN - 1QN QN(L) QN(L) QN(L) QN(L) QN(SR) QN(L) QN(L) QN(L) QN(SR) * * tCSL tCL tLC tLW 1 1 1 1 Load tCDO Data Out * The CS high-to-low transition will generate a clock pulse. = Rising Edge, = Falling Edge MIC8030 8-20 October 1998 |
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