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| MCVVQ111AFB Product Preview VirtuoVue Monochrome Video Display Driver The MCVVQ111AFB VirtuoVue Monochrome Video Display is designed to accept a standard monochrome video signal (525 or 625 lines), and convert it for display on the CyberDisplay320 LCD Display Panel. The MCVVQ111AFB provides all necessary power supply voltages to the display panel by means of a voltage regulator. The input video signal is converted to appropriate differential video signals required by the LCD display panel. A separate OSD input is provided. An on-board sync separator, PLL, and logic control section generate the appropriate horizontal and vertical timing signals for the LCD panel. Horizontal and vertical sync outputs are provided. The MCVVQ111AFB is designed to operate under two input voltages: one is from 2.7 to 5.5 volts ,and the other is 11 volts, A Sleep mode can be set to reduce power consumption. *Support 525 and 625 line monochrome systems *Separate input pin for OSD signals (OSD overlay). *Integrated Voltage regulator provides all necessary voltages for the LCD display panel *Internal sync separator, PLL, and logic provide all necessary timing signals to the LCD display panel. *Control pins to adjust video black level, gain. *Gamma Bias pin to adjust the video output characteristics *Supplies required: 2.7 to 5.5 volts DC, 11 volts DC *Sleep mode for power conservation. *Operating ambient temperature range: -20 to 70oC. *Surface mount package. VirtuoVue Monochrome Video Display FB SUFFIX PLASTIC PACKAGE CASE 932-02 (LQFP-48) Package RjA =88 oC/W (typ) ORDERING INFORMATION Operating Temperature Range -20 o C - 70o C Device MCVVQ111AFB Package LQFP-48 SIMPLIFIED SYSTEM DIAGRAM MCVVQ111AFB Virtue Video Driver BAND-GAP REFERENCE PLL SYNC SEPARATOR TIMING LOGIC VIDEO AMPLIFIER CYBERDISPLAY 320 LCD DISPLAY PANEL 11 Volt +2.7-5.5 Volt VIDEO LUMA SOURCE OSD SOURCE This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. MOTOROLA REV 0 Jan. 2002 Page 1 MCVVQ111AFB Figure 1 Block Diagram 2.7 to 5.5 V ANALOG VBAT 33uH 11V HODL_INV_FREQ VBAT VDDH 10uF 0.1uF SEL_PDR 100n 10u VDD Cap 0.1u 44 43 42 39 37 32 40 38 Ref Gnd 48 SLEEP 100n VBG AGND 1 33 BAND GAP REFERNCE PDR VOLTAGE REGULATOR 20 19 18 22 VDD VEE VCOM VREF VSS RENO CyberDisplay320 LCD Panel 4 525/625 OK PLL FILTER 10 21 26 35 PLL 7 0.47uF 384Fh TIMING GENERATOR Column Inversion Pixel Inversion 25 RENE 24 23 HCK HPL 10 nF 2.0K H 46 45 47 V VSync HSync VHIO Sel SYFltr 17 16 15 13 HODL VPL VCK PDR DGND SYNC SEPARATOR 9 1uF VIDEO IN 0.1u 75 6 CLAMP 100n OSD Level Detect Blkg DC RESTORE 11 5 Q D 2 HODL SEL VIDEO AMPS 27 VIDL VIDLC OSD In 3 White BLK LEVEL & GAIN ADJ. 28 29 14 1nF VIDHC VIDH 12 AGND Test Mode 41 30 36 31 34 8 GAIN BLK LVL. GAMMA BIAS MOTOROLA REV 0 Jan. 2002 Page 2 MCVVQ111AFB MAXIMUM RATINGS Parameter Power Supply Voltage 1 Power Supply Voltage 2 Maximum Junction Temperature Storage Temperature Package Thermal Conductivity Symbol VBat VDDH Tj Tstg RjA Value -0.5,+6.0 13 +150 -65,+150 88(typ) Unit Vdc Vdc oC o C oC/W Devices should not be operated at these limits. The "Recommended Operating Conditions" provides for actual device operation. RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Video Signal Input Level (composite video - Luma) OSD Input Levels Logic Input Levels (Pins 1, 2, 10,47,37,42) Gain Control (Pin 8) Black Level Control(Pin 30) Gamma Bias (Pin 36) External VDDH Supply Operating Ambient Temperature Symbol Vbat Vvid Vosd Vin VGC VBL VGA VDDH Ta Min 2.7 0 0 1.25 2.0 0.5 10.7 -20 Typ 1.0 11 Max 5.5 VBat VBat 2.5 3.0 1.5 11.3 70 Unit Vdc Vp-p Volt Volt Volt Volt Volt Volt o C All limits are not necessarily functional concurrently. ELECTRICAL CHARACTERISTICS (All parameters are specified at Ta=25oC, Pin 1 = High unless noted) Fh stand for line frequency. Fh = 15750Hz in 525/60 system and Fh = 15625Hz in 625/50 system Parameter Min Typ Max Unit POWER SUPPLIES (TO BE UPDATED) Supply Current into VBat(Pin 43 and Pin 44) Pins 13-27 open, Pin 1 = High, VBat=5 Volt Supply Current into VBat(Pin 43 and Pin 44), Sleep Mode Pins 13-27 open, Pin 1 = Low, VBat=3.3Volts Supply Current into VDDH Power Consumption, VBat=5.0v VDDH= 11.0v 10 100 9 149 15.5 18 275.5 mA uA mA mW DISPLAY OUTPUT VOLTAGES (voltages referenced to VSS) VDD (source 1.4mA) VEE (sink 1mA) VCOM (source 2mA) 8.5 1.9 5.55 +9.0 +2.0 +5.8 9.5 2.1 6.15 Volt Volt Volt MOTOROLA REV 0 Jan. 2002 Page 3 MCVVQ111AFB ELECTRICAL CHARACTERISTICS (All parameters are specified at Ta=25oC, Pin 1 = High unless noted) Fh stand for line frequency. Fh = 15750Hz in 525/60 system and Fh = 15625Hz in 625/50 system Parameter VREF (source 10uA) VBG Bandgap voltage(Pin 33) Min 1.185 Typ VBat/2 1.25 Max 1.3 Unit Volt Volt PLL / SYNC SEPARATOR Pixel Clock Oscillator center frequency(Pin 5 = Open) PLL Lock Range (Horizontal Frequency) 14.175 6.0 17.1875 MHz KHz OSD INPUT Black Threshold White Threshold LOGIC INPUT (Pin: 1, 2, 10, 47) Maximum logic LOW input level Minimum logic HIGH input level Input Impedance HSYNC, VSYNC INPUT/OUTPUT Input Impedance (Pin 47 connect to VBat) Input Threshold (Pin 47 connect to VBat, -ve sync input) Equivalent Output Impedance (Pin 47 connect to GND) TIMING LOGIC OUTPUT (Pin: 13, 15, 16, 17, 23, 24, 25, 26) Equivalent Output Impedance External Capacitive Loading for Logic Timing Signals Logic Output Level High Logic Output Level Low ANALOG VIDEO DRIVER (VIDL, VIDH) External Capacitive Loading for VIDL & VIDH VIDEO AMPLIFIER CHARACTERISTIC Video Output Amplitude (pin36 open, pin30 connect to pin19 AGND - 0.75 2.25 1.00 2.70 Volt Volt 0.33xVbat - Volt Volt Ohm dB - 0.4 Volt 1.3 - 1.7 Volt 1.9 - 2.1 Volt MOTOROLA REV 0 Jan. 2002 Page 4 MCVVQ111AFB ELECTRICAL CHARACTERISTICS (All parameters are specified at Ta=25oC, Pin 1 = High unless noted) Fh stand for line frequency. Fh = 15750Hz in 525/60 system and Fh = 15625Hz in 625/50 system Parameter Black Level Control Range (pin30 Min 2.9 Typ - Max 3.1 Unit Volt Note: Gain, GAMMA-BIAS & BLACK LEVEL are interrelated control, control range may be different at different combination of those setting. TIMING CHARACTERISTICS (Ta=+25oC) Note: MCVVQ111AFB is design to work in conjunction with CyberDisplay 320 Monochrome Display, all timing output are expected to fulfill the minimum timing requirement stated at CyberDisplay 320 Monochrome specification table 2-5, revision "2/13, 1998 " when operate under standard video mode NTSC/PAL. DISPLAY PANEL TIMING (Fh=15750Hz, 525/60 system, Figure 8-9) Parameter VPL start at VPL setup time (VPL start to VCK start) HPL setup time VCK low time HPL low time HCK Cycle time HPL end to RENE start time RENE low time HPL end to RENO start time RENO low time t3 t4 t5 t6 t7 t8 t9 Symbol t1 t2 Min 140 40 Typ line 19 496.5 496.5 165.5 165.5 827.5 54.95 827.5 54.95 Max Unit nS nS nS nS nS nS uS nS uS DISPLAY PANEL TIMING (Fh=15625Hz, 625/50 system, Figure 8-9) Parameter VPL starts at VPL setup time (VPL start to VCK start) HPL setup time VCK low time HPL low time HCK Cycle time HPL end to RENE start time RENE low time HPL end to RENO start time RENO low time t3 t4 t5 t6 t7 t8 t9 Symbol t1 t2 Min 140 40 Typ line 23 500 500 166.67 166.67 833.35 55.33 833.35 55.33 Max Unit nS nS nS nS nS nS uS nS uS SYSTEM TIMING Parameter PDR rising edge after SLEEP rising edge Min Typ 333(NTSC) 400(PAL) Max Unit mS MOTOROLA REV 0 Jan. 2002 Page 5 MCVVQ111AFB SYSTEM TIMING Parameter PDR falling edge after SLEEP falling edge Min Typ 10 Max Unit nS PIN DESCRIPTION Pin No 1 2 Pin Name SLEEP HODL Select Description Logic level input. A logic low sets the IC into the sleep mode. Internal 500K pulldown provided. Used for HODL selection. Logic 1: column inversion output on HODL for ABNORMAL video (such as cue/review/pause mode) Logic 0: pixel inversion output on HODL for NORMAL video Also refer the description of pin 37 Input for the OSD signals. See text for required signal levels. Ground for the PLL section. Input for standard level monochrome video,525 or 625 lines. Source impedance must be less than 500. Clamp capacitor, to ground, for the video black level clamp. Filter pin for the internal horizontal PLL. DC control for the gain of the video signal path. Adjustment range is +/- 3.5dB. Filter pin for the sync separator. Capacitor to ground is required. Set low if the input video is a 525 line system (NTSC). Set high for 625 line systems. Internal 500K pull-down provided. Ground for the digital sections and signals. Power Down reset output to the LCD panel. Active low. Upper video drive signal to the LCD panel. Vck control signal to the LCD panel. Vertical start pulse output to the LCD panel. Inversion control output to the LCD panel. Internally generated supply for the LCD panel. Nominally +5.8 volts. Internally generated supply for the LCD panel. Nominally +2.0 volts. Internally generated supply for the LCD panel. Nominally +9.0 volts. Reference ground for the LCD panel. Internally generated supply for the LCD panel. Nominally VBat/2. Horizontal start pulse output to the LCD panel. Horizontal clock output to the LCD panel. Even Row Enable output to the LCD panel. Odd Row Enable output to the LCD panel. Lower video drive signal to the LCD panel. Connect to VIDHC through a compensation capacitor. Connect to VIDLC through a compensation capacitor, DC Control to adjust the video output black level for normal video and OSD signals. Not connected 3 4,12 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OSD In AGND Video Input Clamp PLL Filter Gain SYFltr 525/625 DGND PDR VIDH VCK VPL HODL VCOM VEE VDD VSS VREF HPL HCK RENE RENO VIDL VIDLC VIDHC Black Level N/C MOTOROLA REV 0 Jan. 2002 Page 6 MCVVQ111AFB PIN DESCRIPTION Pin No 32 33 34 35 36 37 Pin Name VDD Cap VBG N/C OK Gamma-bias HODL_INV_FREQ Description Connect the decoupling capacitor (0.1uF) for VDD Output of the bandgap reference. External capacitor may be required. Not connected For test only. Output indicating the video horizontal freq is within the PLL pull-in range. If PLL is not locked, OK will be set to HIGH. Adjust the characteristics of the video output. Select the switching frequency of HODL polarity to either VF/4 (when the pin is set to high) or VF/2(when the pin is set to low. It is the default state). VF is the vertical frequency. This setting applies to both pixel inversion mode and column inversion mode. Refer the description of HODL section for the switching frequencies under NTSC and PAL modes. Not connected Not connected Power supply input. Voltage range is from 10.7V to 11.3V Used in test mode. It must be connected to ground during normal operation. During normal operation, select either scheme 1 or scheme 2. Logic high: scheme 1 is selected. When PDR is asserted during VBlanking, no RENE/ RENO pulses will be generated. Logic low: scheme 2 is selected. When PDR is asserted during VBlanking, 3 RENE/ RENO pulses will be generated. The default state is logic low. Power Supply Input. Voltage range is +2.7 to +5.5 volts, and must be within 0.5 volt of pin 44. Power Supply Input. Voltage range is +2.7 to +5.5 volts, and must be within 0.5 volt of pin 43. This pin powers the PLL,and other noise sensitive sections. H Sync output of the Sync Separator, or an H Sync input from an external source. Internal 50K pull-up provided. V Sync output of the Sync Separator, or a V Sync input from an external source. Internal 50K pull-up provided. Input. When low, pins 45 & 46 are outputs. When high, pins 45 & 46 are inputs. Ground for the analog sections and signals except for PLL section 38 39 40 41 42 N/C N/C VDDH Test Mode SEL_PDR 43 44 45 46 47 48 VBat Analog VBat HSync VSync VH IO Sel Ref Gnd. MOTOROLA REV 0 Jan. 2002 Page 7 MCVVQ111AFB Figure 2-Black Level Adjustment 10.0 Black Level @VIDL, VIDH (Volts DC) 8.0 VIDH 6.0 4.0 2.0 0 0 2.0 VIDL 3.0 Black Level Set Voltage @Pin 30(Volts DC) Figure 3 - Gain Adjustment (For 1 Volt video input, Gamma bias was adjusted for a linear characteristic) Gain, Video Output at VIDL & VIDH Vp-p Gain Control Voltage at Pin 8 (Volt DC) MOTOROLA REV 0 Jan. 2002 Page 8 MCVVQ111AFB Figure 4 - Horizontal Sync Timing CL VIDEO INPUT @PIN 5 HSYNC OUT @PIN 45 850ns 1/2 Fh BLACK LVL CLAMP (Internal) 4us 2us Figure 5 - VSync Output Line 1 VIDEO INPUT @PIN 5 VSYNC OUT @PIN 46 49 Lines 3.1 mSec Field 2 Field 1 VIDEO INPUT @PIN 5 VSYNC OUT @Pin 46 49 Lines 3.1 mSec Field 1 Field 2 MOTOROLA REV 0 Jan. 2002 Page 9 MCVVQ111AFB Figure 6 - LCD Panel Supply Voltages 40 R VDDH(11V) VDD(9V) 20 9.0V R VDDH + 0.3V VDDH BANDGAP SOURCE + 2.0V 43 R VREF 22 R 21 VSS (VBAT/2) VEE(2V) 19 VBAT (2.7~5.5) To LCD Display Panel VCOM(5.8V) 18 R Figure 7 - Video Display vs. Video Input VIDEO INPUT Video Content ta VIDEO OUTPUT Video Display tb VIDEO INPUT 525/60 625/50 tc 1/Fh 63.5uS 64uS HCK 6.05 MHz 6 MHz ta 0.367uS 0.364uS tb 53.27uS 52.73uS tc 0.367uS 0.364uS % of video Displayed 101.4% 101.4% MOTOROLA REV 0 Jan. 2002 Page 10 MCVVQ111AFB Figure 8 - LCD Panel Vertical & Horizontal Timing VSync Pin 46 t1 VPL Pin 16 Cycle time = 1 Field t2 t3 Cycle time = 2/Fh CL VCK Pin 15 HPL Pin 23 HODL Pin 17 HCK Pin 24 t4 Cycle time = 1/Fh t5 Figure 9 - LCD Panel Active Video Timing VCK Pin 15 HPL Pin 23 t6 RENE Pin 25 t7 t8 RENO Pin 26 t9 MOTOROLA REV 0 Jan. 2002 Page 11 MCVVQ111AFB Figure 10 - LCD Timing Signals vs. Fields (NTSC) Field 1 Line 19 Line 258 Field 2 Line 282 Video Input @Pin 5 VPL VCK HPL RENE RENO Figure 11 - OSD Input Signal Waveform White Level OSD Input Signal White Threshold Black Level OSD Threshold GND Figure 12 - OSD Display Example Row 1 Row 2 Row 3 OSD INPUT For Row 1 GND OSD INPUT For Row 2 GND OSD INPUT For Row 3 GND MOTOROLA REV 0 Jan. 2002 Page 12 MCVVQ111AFB FUNCTIONAL DESCRIPTION (Refer to Figure 1) The MCVVQ111AFB is designed to receive a standard monochrome video signal (525 or 625 lines) at Pin 5, and drive the CyberDisplay320 LCD display panel. The IC contains the following sections: PLL - The PLL will normally lock to the horizontal frequency of the incoming video (via the sync separator) so as to synchronize the timing generator with the video amplifiers. The component values shown at pin 7 are suitable for both 525/60 and 625/50 signals. The PLL output frequency is 384xFh, or 6.05MHz for a standard 525 line/60Hz signal (NTSC), and 6MHz for a standard 625 line/50 Hz signal (PAL/SECAM). The timing generator provides all the timing signals to the LCD panel. Pins 45 and 46 (HSync and VSync) can be configured as inputs or outputs, controlled by pin 47(VHIO Sel). When Pin 47 is low, pins 45 and 46 are outputs. HSync out is a square wave at the horizontal frequency as shown in Figure 4. VSync out is an active high pulse as shown in Figure 5. When pin 47 is high, pins 45 and 46 are inputs, require negative sync input pulses. This permits synchronizing the MCVVQ111AFB to an external signal. When there is no video present, the PLL will continue to provide horizontal and vertical timing signals to the timing generator so as to keep the LCD display active. The PLL frequency will decrease slightly in the absence of video, but will lock up once a valid video signal is applied. Voltage Regulator- The section will provide all the necessary regulated supply voltages to the LCD display panel from an external 11V supply(VDDH). Figure 6 shows the various voltages required by the CyberDisplay320 LCD panel. Video Processor - The video input is a standard 1.0 volt p-p composite monochrome video signal, either 525 or 625 lines. If only color composite video is available, it is recommended that the chroma frequencies be filtered out prior to this IC. The DC Restore section provides black level clamping. For this portion to function correctly, the source impedance of the video signal must be <500. The clamp timing is shown in Figure 4 . The sync separator will separate the horizontal and vertical timing signals from the incoming video, and provide them to the timing generator, and to the PLL. The remaining luma information passes to the two output video amplifiers, via the OSD switch, and the video adjust block. The Black Level Adjust (pin 30) is a DC input, with an input range of 2.0 to 3.0 volts, setting the black level at VIDH and VIDL according to Figure 2. The black level does not change if the voltage at pin 30 is increased past 3.0 volts, and it is not affected by the Gain adjust(Pin 8). The Gain Adjust(pin 8) input is a DC input, with a range of 1.25 to +2.5 volts, resulting in a 7 dB change at VIDL and VIDH, as shown in Figure 3 . The gain of Figure 3 is from the Video Input(Pin 5) to VIDL & VIDH, measured from black level to white level, excluding sync. Since VIDL' upper limit (and VIDH' lower limit) are clamped at 5.5 volts, the gain curve is valid as s s long as the signals are not clamped. Timing Generator - This section provides the horizontal and vertical scaling, and the eight timing signals required by the CyberDisplay320 LCD display panel. All fields of the incoming interlaced signal are provided to the display panel sequentially. This section is synchronized by signals from the sync separator and PLL. The HCK frequency is same as PLL output frequency (6.05 MHz or 6.0 MHz). The vertical scaling algorithm depends on the setting of the 525/625 pin (pin 10). When set low (for 525/60 signals) no vertical scaling occurs. When set high (for 625/50 signals) lines are skipped according to the following algorithms: *Odd field, line number 22+(12N+6) and 22+(12N+12) where N=0,1,2,3.... were skipped, or, the first skipped line is line 28, *Even field, line number 334+(12N+3) and 334+(12N+9) where N=0,1,2,3.... were skipped, or, the first skipped line is line 337, Horizontally, a small portion of the left and right edges of the video content line is expanded. Figure 7 indicates the horizontal timing. All timing values are multiples of the HCK period. The eight timing signals to the CyberDisplay320 LCD display panel are (refer Figures 8-10): *PDR (pin 13) - Power Down Reset is high for normal operation. It is set low when the MCVVQ111AFB is set to the Sleep mode. *VCK (pin 15) - Vertical Clock. The active low output appears every other line, indicating the beginning of an even numbered row. It is present for video lines 22 through 260 only. *VPL (pin 16) - Vertical Start Pulse. This active low output appears once per field at line 22, to indicate the start of a field. *HODL (pin 17) - This output changes polarity to satisfy the HODL inversion requirement of the CyberDisplay320 LCD display panel. The changes occur during the back porch time of video lines 22 through 261 of each field, with an addition change at line 4 of either Field 1 or 2, depending on the initial lock-up condition. *HPL (pin 23) - Horizontal Start Pulse. This active output indicates the beginning of each line. It is present for video lines 22 through 261 only. MOTOROLA REV 0 Jan. 2002 Page 13 MCVVQ111AFB *HCK (pin 24) - Horizontal Clock. This square wave output has a frequency of 384x the video horizontal frequency. This output is present continuously in both fields. *RENE (pin 25) - Row Enable (Even) - This active low output occurs during the active video time of each even numbered line. It is present for video lines 22 through 260. *RENO (pin 26) - Row Enable (Odd) - This active low output occurs during the active video time of each odd numbered line. It is present for video lines 23 through 261. HODL Selection - During cue/review/pause mode of the camcorder operation or under noisy environment, which defined as Abnormal Video Mode, the HODL should be under Column Inversion Output. HODL Selection(pin 2) is set to HIGH (Column Inversion) for abnormal video mode and LOW (Pixel Inversion) for normal mode. The switching frequency of HODL polarity can be either VF/2 Hz or VF/4 Hz depending on the setting of the HODL_INV_FREQ(pin 37). VF is defined as vertical frequency. The minimum voltage level for logic HIGH of HODL SEL is 0.66xVBAT volts and the maximum voltage level for logic LOW is 0.33xVBAT volts. Switching frequency of HODL polarity: HODL_INV_FREQ 0 1 PAL 25 Hz 12.5 Hz NTSC 30 Hz 15 Hz OSD Input - If the OSD display information is not contained in the composite video signal, then OSD information can be applied to pin 3. The signal levels at this pin must conform to that shown in Figure 11, and must be externally generated and synchronized with the video. The sync outputs at pins 45 and 46 can be used for synchronization. Normally, pin 3 is to be at ground to display the video applied at pin 5. When the OSD input signal at pin 3 exceeds the OSD threshold (0.75 volt), the internal switch transfers the video amplifiers' outputs to the black level, causing a black display at the LCD panel. This black time can be, e.g., a border. The OSD Black level is the same as that set for the normal video black level, and is set by the voltage at pin 30 (see Figure 2). When the OSD input signal is increased past the White threshold (2.25 volts), the video amplifiers'outputs go to the White Level. Formation of the on-screen characters is accomplished by appropriate timing of the signal at pin 3, as shown in the example in Figure 12. The OSD input signal must be returned to ground to resume displaying the video signal at pin 5. If the OSD input pin is not used, it must be connected to ground. The default OSD contrast is 92.5%(1.475V). Sleep Mode - The Sleep mode, activated by setting SLEEP pin low, will shut off the entire IC by removing all power supply voltages and the driving signals from the LCD display panel. This mode results in power consumption by the IC of less than 1 mW. PDR - The PDR section prevents invalid video display during the power up or when VDDH drops below 10 volts. The PDR will be released if following two conditions are met: . 333 - 400 ms elapses after power up . VDDH is no less than 10 volts. Only if both of the above conditions meet, the display panel will be enabled. The PDR scheme can be either scheme 1 or scheme 2 depending on the setting of SEL_PDR(pin 42). The difference between these two schemes is: When PDR is asserted during VBlanking, 3 RENE/RENO pulses will be generated under scheme 2 but no RENE/RENO pulse will be generated under scheme 1. MOTOROLA REV 0 Jan. 2002 Page 14 MCVVQ111AFB Figure 13 Application Circuit 2.7 to 5.5 V ANALOG VBAT 33uH 11V HODL_INV_FREQ SEL_PDR VBAT VDDH 10uF 0.1uF 100n 10u VDD Cap 0.1u 38 Ref Gnd 48 44 43 42 39 37 SLEEP 100n VBG AGND 1 33 BAND GAP REFERNCE PDR VOLTAGE CONVERTER 40 32 20 19 18 22 VDD VEE VCOM VREF CyberDisplay320 LCD Panel 4 525/625 OK PLL FILTER 10 21 VSS 26 RENO 35 PLL 7 0.47uF 384Fh TIMING GENERATOR Column Inversion Pixel Inversion 25 RENE 24 23 HCK HPL 10 nF VSync HSync 2.0K H 46 45 V 17 16 15 13 HODL INIT VPL 1K VCK PDR DGND VHIO Sel SYFltr SYNC SEPARATOR 47 HILTOR 9 1uF VIDEO IN 5 0.1u 75 6 CLAMP 100n Blkg OSD Level Detect DC RESTORE 11 Q D 2 HODL SEL VBat or GND VIDEO AMPS 27 VIDL VIDLC OSD Generator 3 White BLK LEVEL & GAIN ADJ. 28 29 14 1nF VIDHC VIDH 12 AGND 41 31 36 GAIN 30 8 BLK LVL. GAMMA BIAS VCOM PIN 18 13K 36K 20K 10K 27K 10K PIN 19 VEE 10K 5K 34 Test Mode MOTOROLA REV 0 Jan. 2002 Page 15 MCVVQ111AFB APPLICATION INFORMATION Figure 13 shows the basic application circuit using MCVVQ111AFB along with CyberDisplay320 LCD Panel. Applicable points are: *The components at pins 6, 7, and 9 must be in a neat, tight arrangement connected directly to the ground at pin 4. *It is recommended that a socket NOT be used for the MCVVQ111AFB. *Pins10 can be hard wired to VBat or to Ground, or controlled by a logic circuit (microprocessor), depending on the application. *The connections to the CyberDisplay320 LCD panel (pins 13 - 27) should be short and direct. The pinout sequence on the MCVVQ111AFB matches that of the LCD panel. *A ground plane is recommended. *The components of the loop filter on Pin 7 may be depending on the customer PCB layout. Gamma Correction The gamma bias pin and the gain pin control the shape and amplitude of the video output so as to match the panel non-linear transmittance characteristics. The Gain parameter controls the slope from black to white region, whereas the Gamma parameter sets the turning point of the black region. Figure 14, Figure 15 and Figure 16 show how different gamma and gain settings can affect the characteristic of video output. (The detailed plots of characteristic of video output under different gain and gamma settings will be provided in another document: Application note.) Figure 14 Gain = 1.5V, Gamma=1.25V of this curve Gain set the slope Gamma set this turning point MOTOROLA REV 0 Jan. 2002 Page 16 MCVVQ111AFB Figure 15 Gain = 1.5V, Gamma=1V With a smaller gain, the slope in Figure 15 is less steeper than the one in Figure 14 Figure 16 Gain = 1.5V, Gamma = 0.75V With a smaller gamma, the black region turning point in Figure 16 is lower than the one in Figure 14 MOTOROLA REV 0 Jan. 2002 Page 17 |
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