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HV506
Preliminary
275V 40-Channel Row Driver with SCR Outputs Ordering Information
Package Options Device 80-Lead Ceramic Gullwing HV506DG 64-Lead 3-Sided Plastic Gullwing HV506PG
Die HV506X
HV506
Features
Processed with HVDI technology
General Description
The HV506 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suitable for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. When the data reset pin (DRIO) is at logic high, it will reset all the outputs of the internal shift register to zero. At the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. The DRIO can be triggered at any time. The DIR pin controls the direction of data through the device. When DIR is at logic high, DRIOA is the input and DRIOB is the output. When DIR is grounded, DRIOB is the input and the DRIOA is the output. See the Output Sequence Operation Table for output sequence. The POL and OE pins perform the polarity select and output enable function respectively. Data is clocked through the shift register loaded on the low to high transition of the clock. A logic high in the shift register will cause the other corresponding output to swing to VDD if POL is high, or to VSS if POL is low. All other outputs will be in the High-Z state. If OE is at logic high all outputs will be in the High-Z state. An output in the High-Z state may block up to 275V above VSS or 275V below VDD. The DP/DN pins are for the positive/negative discharge of the high voltage output HVOUT. Data output buffers are provided for cascading devices. LVDD requires low current for the HV506 logic section. VDD requires high current for the output section . Typically these two pins are at the same potential. The same current and potential conditions apply to the LVSS, logic, and VSS, output pins. Vsub must always be equal or greater than the most positive supply.
Symmetric row drive Output voltage up to 275V Source/Sink current 300mA (min.) Shift Register Speed 3MHz Pin-programmable shift direction (DIR) Hi-Rel processing available
Absolute Maximum Ratings
Logic supply voltage, LVDD1 Output supply voltage, VDD Output voltage, HVOUT Logic input levels Continuous total power dissipation2 Ceramic Plastic
1
-0.5V to +15V -0.5V to +15V See Note 3 300V -0.5V to VDD +0.5V 1900mW 1200mW
Substrate bias voltage, Vsub
Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds
Notes:
Plastic -40C to +85C Ceramic -55C to +125C -65C to +150C 260C
1. All voltages are referenced to VSS. 2. For operation above 25C ambient derate linearly to maximum operating temperture at 20mW/C for plasitc and at 19mW/C for ceramic. 3. Vsub must be the most positive with respect to VSS.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to 1 workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Electrical Characteristics
(over recommended operating conditions of VDD = 12V, LVDD = 12V, and TA = 25C unless noted)
DC Characteristics
Symbol IDD IDDQ VOH VOL IIH IIL IOFF Parameter VDD supply current Quiescent VDD supply current High-level output HVOUT Data out Low-level output HVOUT Data out High-level logic input current Low-level logic input current Output OFF leakage current (High-Z) VDD-10 10.8 VSS+10 1.2 1 -1 10 10
Notes: 1. Only one output can be turned on at a time.
Min
Max 10 100
Units mA A V V V V A A A A
Conditions fCLK = 3MHz All VIN = VSS or VDD IO= -300mA IO= -100A IO= 300mA IO= 100A VIH = VDD VIL = VSS HVOUT - VSS = 275V, Vsub = HVOUT VDD - HVOUT = 275V, Vsub = VDD
SCR Characteristics
Symbol VOH VOL IL VL IH VH IOFF Parameter High-level output Low-level output Latching Current Latching Voltage Holding Current Holding Voltage Output OFF leakage current (High-Z) 10 10 10 10 Min VDD-10 VSS+10 15 100 Max Units V V mA V mA V A A HVOUT - VSS = 275V, Vsub = HVOUT VDD - HVOUT = 275V, Vsub = VDD Conditions IO= -300mA IO= 300mA
2
HV506
AC Characteristics
Symbol fCLK tW (H/L) tSUD tHD tSUC tSUE tHC tHE tDHL tDLH
* *
Parameter Clock frequency Pulse width - clock high or low Data set-up time before clock rises Data hold time after clock rises HVOUT delay from clock rises (Hi-Z to H or L) HVOUT delay from Output Enable rises HVOUT delay from clock rises (H or L to Hi-Z) HVOUT delay from Output Enable rises Delay time clock to data output falls Delay time clock to data output rises Turn off time of output SCR Turn off time of output diode POL pulse width Output Enable pulse width Slew rate of HVOUT
Min
Max 3
Units MHz ns ns ns
Conditions
150 50 50 1 600 2 600 250 250 4 2 3 3 200
s ns s ns ns ns s s s s V/s
CL = 10nF CL = 10nF CL = 10nF CL = 10nF CL = 15pF CL = 15pF Time after IOUT 2mA, CL = 10nF Time after IOUT 2mA, CL = 10nF
tOFF(SCR) tOFF(D) tPOW tOEW SR
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is equal to tWH. Therefore the delay is measured from the trailing edge of the clock.
3
HV506
Recommended Operating Conditions
Symbol LVDD VDD VIH VIL fCLK IO TA IOD Logic supply voltage Output supply voltage High-level input voltage Low-level input voltage Clock frequency High voltage output current Operating free-air temperature Plastic Ceramic Allowable pulse current through diodes -40 -55 Parameter Min 10.8 10.8 0.8LVDD 0 Max 13.2 13.2 LVDD 0.2LVDD 3 300 +85 +125 500 Units V V V V MHz mA C C mA
Notes: The substrate pin Vsub (pin 39) must be biased for proper output breakdown voltage. Vsub VDD or HVOUT whichever is higher. LVDD/VDD are measured with respect to LVSS/VSS.
Input and Output Equivalent Circuits
LVDD LVDD VDD
Input
Data Out
HVOUT
DN DP LVSS Logic Inputs LVSS Logic Data Output VSS High Voltage Outputs
SCR Characteristics
I
IH
IL
VH
VL
V
4
HV506
Switching Waveforms
1/fCLK t WH CLK t SUD Data Reset Input (DRIOA/DRIOB) 50% 50% t HD Data Valid VIH 50% VIL t DLH Data Reset Output (DRIOA/DRIOB) t SUC HVOUT (POL = H) High Impedance 90% HVOUT (POL = L) 10% t SUC t HC VOL 10% High Impedance 50% t DHL VOH 50% VOL 50% t WL VIH 50% 50% VIL
t HC 90%
VOH
POL
50%
t POW
VIH 50% VIL
t OEW
VIH OE 50% 50% VIL
t SUE HVOUT 10% High Impedance 90% HVOUT t SUE
t HE 90% High Impedance 10% t HE
VOH
VOL
5
HV506
Functional Block Diagram
VDD OE POL LVDD Output DRIOA HVOUT1
CLK
S/R
DIR
Output
HVOUT2
DRIOB
Output
HVOUT40
LVSS
VSS
DP DN
Function Table
I/O Relations CLK O/P HIGH O/P OFF O/P LOW O/P OFF X X X X DIR X X X X Inputs S/R Data H L H X POL H X L X OE L L L H HV Outputs H HIGH-Z L All O/P HIGH-Z
Note: H = logic high level, L = logic low level, X = irrelevant
Output Sequence Operation Table
DIR L H Data Reset In Data Reset Out DRIOB DRIOA DRIOA1 DRIOB
2
HVOUT # Sequence 40 1 1 40
Direction3
Notes: 1. DRIOA is DRIOBdelayed by 40 clock pulses. 2. DRIOB is DRIOA delayed by 40 clock pulses. 3. Reference to chip layout drawing.
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HV506
Typical Output Circuit Connections
+HV
LVDD
VDD Source SCR D3
HV506
12V
+ -
HVOUT D4 D1 D2 DN
Sink SCR LVSS VSS
DP
GND
-HV
Note: The voltage potential between LVDD/VDD and LVSS/VSS must not exceed recommended operating conditions of 10.8V - 13.2V (12V typical)
Substrate Bias Operation
In order to achieve the desired output breakdown voltage, the substrate must be biased to the most positive potential of any circuit node. For this condition, Vsub VDD or HVOUT whichever is higher. Refer to Typical Output Circuit Connections for wiring. A typical Vsub signal is shown below.
+ HV Vcolumns 0V
Vsub VSS
-HV
Note: In general, when driving the outputs positive, VSUB = +HV. And when driving outputs negative, VSUB equals most positive voltage; e.g. GND or >0V.
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HV506
HV Switching Waveforms and Operation
To drive a TFEL row with a negative pulse: The desired sink SCR is enabled and VSS is connected to -HV via a current limited switch. After holding the output at the -HV level, the switch is opened in order to set the sink SCR current to zero. The row is then discharged through a discharge diode when D2 is switched to GND. The application of a positive pulse to a row operates in a similar manner using the selected source SCR and D1.
+ HV - (VDD - VSS)
VSS
0V
Drive Current Disabled - HV Drive Current Disabled High Impedance Output n Sink* SCR D2* tOFF (D2) tOFF (Sink SCR) tOFF (Source SCR) tOFF (D1) Output n+1 High Impedance Source* SCR D1*
High Impedance
*
Notes internal device handling current flow. Refer to Typical Output Circuit Connections for schematic.
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HV506
Pin Configurations
HV506 Option A: Pin Function 1 HVOUT1 2 HVOUT 2 3 HVOUT 3 4 HVOUT 4 5 HVOUT 5 6 HVOUT 6 7 HVOUT 7 8 HVOUT 8 9 HVOUT 9 10 HVOUT 10 11 HVOUT 11 12 HVOUT 12 13 HVOUT 13 14 HVOUT 14 15 HVOUT 15 16 HVOUT 16 17 HVOUT 17 18 HVOUT 18 19 HVOUT 19 20 HVOUT 20 21 N/C 22 DP 23 DN 24 N/C 25 N/C 26 LVSS 27 VDD 28 DIR 29 VSS 30 CLOCK 31 DRIOA 32 DRIOB
Note: Pins 65-80 are NC.
Package Outline
1
Index
Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Function OE POL LVDD VSS VDD LVSS Vsub N/C N/C DN DP N/C HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 HVOUT 33 HVOUT 34 HVOUT 35 HVOUT 36 HVOUT 37 HVOUT 38 HVOUT 39 HVOUT 40
64
24 25 top view 40
41
3-sided Plastic 64-pin Gullwing Package
12/13/010
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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