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K9K1208U0A-YCB0, K9K1208U0A-YIB0
Document Title 64M x 8 Bit NAND Flash Memory Revision History
Revision No
0.0
FLASH MEMORY
History
1. Initial issue - Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection). So, /SE pin is don' t-cared regardless of external logic input level and is fixed as low internally.
Draft Date
Dec. 6th 2000
Remark
Preliminary
0.1
1. Changed plane address in Copy-Back Program Dec. 28th 2000 - A14, the plane address, of source and destination page address must be the same. => A14 and A25, the plane address, of source and destination page address must be the same. 1. In addition, explain WE function in pin description - The WE must be held high when outputs are activated. Jan. 17th 2001 Final
0.2
Note : For more detailed features and specifications including FAQ, please refer to Samsung' Flash web site. s http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
64M x 8 Bit NAND Flash Memory
FEATURES
* Voltage Supply : 2.7V~3.6V * Organization - Memory Cell Array : (64M + 2,048K)bit x 8bit - Data Register : (512 + 16)bit x8bit * Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte * 528-Byte Page Read Operation - Random Access : 10s(Max.) - Serial Page Access : 60ns(Min.) * Fast Write Cycle Time - Program time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years * Command Register Operation * Package : - K9K1208U0A-YCB0/YIB0 : 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
The K9K1208U0A are a 64M(67,108,864)x8bit NAND Flash Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528byte page in typically 200s and an erase operation can be performed in typically 2ms on a 16K-byte block. Data in the page can be read out at 60ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9K1208U0As extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K1208U0A-YCB0/YIB0 is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
PIN CONFIGURATION
PIN DESCRIPTION
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-pin TSOP1 Standard Type 12mm x 20mm
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP R/B VCC VSS N.C
Pin Function Data Input/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ready/Busy output Power Ground No Connection
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC VSS A9 - A25 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
FLASH MEMORY
512M + 16M Bit NAND Flash ARRAY
A0 - A7
(512 + 16)Byte x 131072 Page Register & S/A
A8
Command Command Register
Y-Gating
I/O Buffers & Latches
VCC VSS I/0 0 I/0 7
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
Output Driver
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block = 32 Pages = (16K + 512) Byte
128K Pages (=4,096 Blocks)
1st half Page Register (=256 Bytes)
2nd half Page Register (=256 Bytes)
1 Page = 528 Byte 1 Block = 528 Bytes x 32 Pages = (16K + 512) Byte 1 Device = 528Bytes x 32Pages x 4,096 Blocks = 528 Mbits 8 bit 16 Byte
512B Byte
Page Register
512 Byte 16 Byte
I/O 0 ~ I/O 7
I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25
I/O 1 A1 A10 A18 *L
I/O 2 A2 A11 A19 *L
I/O 3 A3 A12 A20 *L
I/O 4 A4 A13 A21 *L
I/O 5 A5 A14 A22 *L
I/O 6 A6 A15 A23 *L
I/O 7 A7 A16 A24 *L
Column Address Row Address (Page Address)
NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low".
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
PRODUCT INTRODUCTION
FLASH MEMORY
The K9K1208U0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K1208U0A. The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K1208U0A.
Table 1. COMMAND SETS
Function Read 1 Read 2 Read ID Reset Page Program Block Erase Read Status 1st. Cycle 00h/01h 50h 90h FFh 80h 60h 70h
(1)
2nd. Cycle 10h D0h -
Acceptable Command during Busy
O
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
PIN DESCRIPTION
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS K9K1208U0A-YCB0 K9K1208U0A-YIB0 Storage Temperature TSTG Symbol VIN VCC Temperature Under Bias TBIAS Rating
FLASH MEMORY
Unit V C C
-0.6 to + 4.6 -0.6 to + 4.6 -10 to +125 -40 to +125 -65 to +150
NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9K1208U0A-YCB0 :TA=0 to 70C, K9K1208U0A-YIB0:TA=-40 to 85C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7 0 Typ. 3.3 0 Max 3.6 0 Unit V V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Operating Current Sequential Read Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL(R/B) IOH=-400A IOL=2.1mA VOL=0.4V Test Conditions tRC=60ns, CE=VIL, IOUT=0mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to 3.6V VOUT=0 to 3.6V Min 2.0 -0.3 2.4 8 Typ 10 15 15 10 10 Max 20 25 25 1 50 10 10 VCC+0.3 0.8 0.4 mA V A mA Unit
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
VALID BLOCK
Parameter Valid Block Number Symbol NVB Min 4,026 Typ. -
FLASH MEMORY
Max 4,096 Unit Blocks
NOTE : 1. The K9K1208U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(K9K1208U0A-YCB0 :TA=0 to 70C, K9K1208U0A-YIB0:TA=-40 to 85C, VCC=2.7V~3.6V unless otherwise) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (3.0V +/-10%) Output Load (3.3V +/-10%) Value 0.4V to 2.4V 5ns 1.5V 1 TTL GATE and CL=50pF 1 TTL GATE and CL=100pF
CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 30 30 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L L X X X X ALE L H L H L L L X X X
(1)
CE L L L L L L L X X X H
WE
RE H H H H H
WP X X H H H X Data Input Write Mode Read Mode
Mode Command Input Address Input(4clock) Command Input Address Input(4clock)
H H X X X X H X X X X
sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect
(2)
X H H L 0V/VCC
X
Stand-by
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG Nop tBERS Min Typ 200 2 Max 500 2 3 3 Unit s cycles cycles ms
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25(1) 0 10 20 15 60 25
FLASH MEMORY
Max Unit ns ns ns ns ns ns ns ns ns ns ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay( ID read ) ALE to RE Delay(Read cycle) CE to RE Delay( ID read) Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low Last RE High to Busy(at sequential read) CE High to Ready(in case of interception by CE at read) CE High Hold Time(at the last serial read) (2) RE Low to Status Output CE Low to Status Output WE High to RE Low RE access time(Read ID) Device Resetting Time(Read/Program/Erase) Symbol tR tAR1 tAR2 tCR tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tRB tCRY tCEH tRSTO tCSTO tWHR tREADID tRST Min 100 50 100 20 30 60 15 25 0 100 60 Max 10 100 35 30 20 100 50 +tr(R/B)(1) 35 45 35 5/10/500 (3) Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 2. To break the sequential read cycle, CE must be held high for longer time than tCEH. 3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
NAND Flash Technical Notes
Invalid Block(s)
FLASH MEMORY
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update) Invalid Block(s) Table
No
*
Check "FFh" ? Yes
Check "FFh" at the column address 517 of the 1st and 2nd page in the block
No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
NAND Flash Technical Notes (Continued)
Error in write or read operation
FLASH MEMORY
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Erase Failure Write Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement or ECC Correction Verify ECC -> ECC Correction
Read
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification operation is not needed. Start Write 00h
Write 80h
Write Address
Write Address
Write Data
Wait for tR Time
Write 10h
Verify Data
No
*
Program Error
Read Status Register
Yes Program Completed
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
*
*
Program Error
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
Yes
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
FLASH MEMORY
Read Flow Chart
Start Write 00h Write Address Read Data ECC Generation
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed
No
Reclaim the Error
No
Verify ECC Yes Page Read Completed
*
Erase Error
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
Buffer memory
error occurs Page a Block A When the error happens with page "a" of Block "A", try to write the data into another Block "B" from an external buffer. Then, prevent further system access to Block "A" (by creating a "invalid block" table or other appropriate scheme.)
Block B
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
Pointer Operation of K9K1208U0A
FLASH MEMORY
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ' 00h' command sets the pointer to ' area(0~255byte), ' A' 01h'command sets the pointer to ' area(256~511byte), and ' B' 50h'command sets the pointer to ' area(512~527byte). With these commands, the starting column address can be set to any of a whole C' page(0~527byte). ' 00h' or ' 50h' is sustained until another address pointer command is inputted. ' 01h' command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ' 01h' command, the address pointer returns to ' area by itself. To program data starting from ' or ' area, ' A' A' C' 00h'or ' 50h'command must be inputted before ' 80h'command is written. A complete read operation prior to ' 80h' command is not necessary. To program data starting from ' area, ' B' 01h'command must be inputted right before ' 80h'command is written.
"A" area (00h plane)
"B" area (01h plane) 256 Byte
"C" area (50h plane) 16 Byte
Table 1. Destination of the pointer Command 00h 01h 50h Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C)
256 Byte
"A"
"B"
"C" Internal Page Register
Pointer select commnad (00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
(1) Command input sequence for programming ' area A'
The address pointer is set to ' area(0~255), and sustained A' Address / Data input 00h 80h 10h 00h 80h Address / Data input 10h
' ,' ,' area can be programmed. A' B' C' It depends on how many data are inputted.
' 00h'command can be omitted.
(2) Command input sequence for programming ' area B'
The address pointer is set to ' area(256~512), and will be reset to B' ' area after every program operation is executed. A' Address / Data input 01h 80h 10h 01h 80h Address / Data input 10h
' , ' area can be programmed. B' C' It depends on how many data are inputted.
' 01h'command must be rewritten before every program operation
(3) Command input sequence for programming ' area C'
The address pointer is set to ' area(512~527), and sustained C' Address / Data input 50h 80h 10h 50h 80h Address / Data input 10h
Only ' area can be programmed. C'
' 50h'command can be omitted.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
System Interface Using CE don' t-care.
FLASH MEMORY
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 3. Program Operation with CE don' t-care. CLE
CE don' t-care
CE
WE ALE
I/O0~7
80h
Start Add.(4Cycle)
Data Input
Data Input
10h
(Min. 10ns)
tCS CE
(Max. 45ns)
tCH CE
tCEA
tREA tWP WE I/O0~7
Timing requirements : If CE is is exerted high during data-loading, tCS must be minimum 10ns and tWC must be increased accordingly.
RE
out
Timing requirements : If CE is exerted high during sequential data-reading, the falling edge of CE to valid data(tCEA) must be kept greater than 45ns.
Figure 4. Read Operation with CE don' t-care.
CLE
CE don' t-care Must be held low during tR.
CE
RE ALE R/B tR
WE
I/O0~7
00h
Start Add.(4Cycle)
Data Output(sequential)
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
* Command Latch Cycle
FLASH MEMORY
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/O0~7
tALH
tDH
Command
* Address Latch Cycle
tCLS CLE
tCS CE
tWC
tWC
tWC
tWP WE tALS ALE tDS I/O0~7 tDH tWH tALH tALS
tWP tWH tALH tALS
tWP tWH tALH tALS
tWP tALH
tDS
tDH
tDS
tDH
tDS
tDH
A0~A7
A9~A16
A17~A24
A25
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
* Input Data Latch Cycle
tCLH CLE
FLASH MEMORY
tCH CE
tALS ALE
tWC
tWP WE tDS I/O0~7 tWH tDH
tWP
tDH
tWP tDH
tDS
tDS
DIN 0 DIN 1 DIN 511
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tREH RE tRHZ
CE
tRC tCHZ*
tREA
tREA
tREA
tRHZ* I/O0~7 tRR R/B Dout Dout
Dout
NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
* Status Read Cycle
tCLS CLE tCLS tCS CE tCH tWP WE tWHR RE tDS I/O0~7 70h tDH tIR tRSTO tCSTO tCLH
FLASH MEMORY
tCHZ*
tRHZ* Status Output
READ1 OPERATION(READ ONE PAGE)
CLE tCEH CE tWC WE tWB tAR2 ALE tR RE tRR I/O0~7
00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 Dout N Dout N+1 Dout N+2
tCHZ*
tCRY
tRC
tRHZ*
Dout 527
Column Address
Page(Row) Address Busy
tRB
R/B
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
READ1 OPERATION(INTERCEPTED BY CE)
FLASH MEMORY
CLE
CE
WE tWB tAR2 ALE tR RE tRR I/O0~7
00h or 01h
tCHZ
tRC
A0 ~ A7
A9 ~ A16
A17 ~ A24
A25
Dout N
Dout N+1
Dout N+2
Column Address
Page(Row) Address Busy
R/B
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE tWB ALE
tR tAR2 tRR
RE
I/O0~7
50h
A0 ~ A7
A9 ~ A16 A17 ~ A24
A25
Dout 511+M
Dout 527
R/B M Address
A0~A3 : Valid Address A4~A7 : Dont care
Selected Row
512
16 Start address M
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
SEQUENTIAL ROW READ OPERATION (WITHIN A BLOCK)
CLE
FLASH MEMORY
CE
WE
ALE
RE
I/O0~7
00h
A0 ~ A7 A9 ~ A16 A17 ~ A24
A25
Dout N
Dout N+1
Dout 527
Dout 0
Dout 1

Dout 527
Ready R/B
M
Busy
Busy
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
WE tWB ALE tPROG
RE
Din Din 10h N 527 1 up to 528 Byte Data Program Command Serial Input
I/O0~7
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24 Page(Row) Address
A25
tWC
tWC
tWC
70h Read Status Command
I/O0
Sequential Data Column Input Command Address
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
18
K9K1208U0A-YCB0, K9K1208U0A-YIB0
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS
RE
I/O0~7
60h
A9 ~ A16 A17 ~ A24 Page(Row) Address
A25
DOh
70h
I/O 0
R/B
Auto Block Erase Setup Command Erase Command
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
RE tREADID I/O 0 ~ 7
90h Read ID Command 00h Address. 1cycle ECh Maker Code 76h Device Code
19
K9K1208U0A-YCB0, K9K1208U0A-YIB0
DEVICE OPERATION
PAGE READ
FLASH MEMORY
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 60ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each read operation.
Figure 3. Read1 Operation CLE CE WE ALE tR R/B RE I/O0~7
00h Start Add.(4Cycle) A0 ~ A7 & A9 ~ A25 Data Output(Sequential)
(00h Command) 1st half array 2st half array
(01h Command)* 1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
20
K9K1208U0A-YCB0, K9K1208U0A-YIB0
Figure 4. Read2 Operation CLE CE WE ALE R/B RE I/O0~7
50h Start Add.(4Cycle) A0 ~ A3 & A9 ~ A25 (A4 ~ A7 : Dont Care)
1st half array 2nd half array
FLASH MEMORY
tR
Data Output(Sequential) Spare Field
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation tR tR
R/B I/O0 ~ 7
Start Add.(4Cycle) A0 ~ A7 & A9 ~ A25 (00h Command)
1st half array
tR
00h 01h
Data Output 1st
Data Output 2nd (528 Byte) (01h Command)
1st half array 2nd half array
Data Output Nth (528 Byte)
2nd half array
1st 2nd Nth
Block
1st 2nd Nth
Data Field
Spare Field
Data Field
Spare Field
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given.
21
K9K1208U0A-YCB0, K9K1208U0A-YIB0
Figure 6. Sequential Row Read2 Operation tR tR
FLASH MEMORY
R/B I/O0~7
tR
50h
Start Add.(4Cycle) A0 ~ A3 & A9 ~ A25 (A4 ~ A7 : Dont Care)
Data Output 1st
Data Output 2nd (16Byte)
Data Output Nth (16Byte)
1st Block Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation tPROG R/B I/O0~7
80h
Address & Data Input A0 ~ A7 & A9 ~ A25 528 Byte Data
10h
70h
I/O0
Pass
Fail
22
K9K1208U0A-YCB0, K9K1208U0A-YIB0
COPY-BACK PROGRAM
FLASH MEMORY
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command with the address of the source page moves the whole 528byte data into the internal buffer. As soon as the Flash returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed. The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory array is internally partitioned into four different planes, copy-back program is allowed only within the same memory plane. Thus, A14 and A25, the plane address, of source and destination page address must be the same.
Figure 8. Copy-Back Program Operation tR R/B I/O0~7 tPROG
00h
Add.(4Cycles) A0 ~ A7 & A9 ~ A25 Source Address
8Ah
Add.(4Cycles) A0 ~ A7 & A9 ~ A25 Destination Address
70h
I/O0
Pass
Fail
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence.
Figure 9. Block Erase Operation tBERS
R/B I/O0~7
60h
Address Input(3Cycle) Block Add. : A9 ~ A25
D0h
70h
I/O0
Pass
Fail
23
K9K1208U0A-YCB0, K9K1208U0A-YIB0
READ STATUS
FLASH MEMORY
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Staus Register Definition
I/O # I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Device Operation Write Protect Reserved for Future Use Status Program / Erase Definition "0" : Successful Program / Erase "1" : Error in Program / Erase "0" "0" "0" "0" "0" "0" : Busy "0" : Protected "1" : Ready "1" : Not Protected
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECH), and the device code (76H) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE tCR CE WE tAR1 ALE RE I/O0~7 tREADID
90h 00h Address. 1cycle ECh Maker code 76h Device code
24
K9K1208U0A-YCB0, K9K1208U0A-YIB0
RESET
FLASH MEMORY
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation tRST R/B I/O0~7
FFh
Table3. Device Status
After Power-up Operation Mode Read 1 After Reset Waiting for next command
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation.
Rp VCC VCC(Max.) - VOL(Max.) Rp = R/B open drain output IOL + IL = 3.2V 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin.
GND Device
25
K9K1208U0A-YCB0, K9K1208U0A-YIB0
DATA PROTECTION
FLASH MEMORY
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional software protection.
Figure 11. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
26
High
Package Dimensions
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F
FLASH MEMORY
Unit :mm/Inch
20.000.20 0.7870.008
0.008-0.001
+0.07
+0.003
0.20 -0.03
#1
#48 ( 0.25 ) 0.010 12.40 0.488 MAX
0.50 0.0197
#24
#25 1.000.05 0.0390.002 1.20 0.047 MAX 0.05 MIN 0.002
0.25 0.010 TYP
0.125 0.035
0~8AE
0.45~0.75 0.018~0.030
( 0.50 ) 0.020
27
+0.003 0.005-0.001
18.400.10 0.7240.004
+0.075
12.00 0.472
0.10 MAX 0.004

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