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| User's Manual V850ES 32-Bit Microprocessor Core Architecture Document No. U15943EJ2V0UM00 (2nd edition) Date Published September 2002 N CP(K) 2002 (c) Printed in Japan [MEMO] 2 User's Manual U15943EJ2V0UM NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. V850 Series, V850ES/KF1, V850ES/KG1, V850ES/KJ1, V850ES/SA2, and V850ES/SA3 are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. User's Manual U15943EJ2V0UM 3 Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. 2 2 2 2 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 4 User's Manual U15943EJ2V0UM Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 * Branch Sweden Taeby, Sweden Tel: 08-63 80 820 NEC Electronics (Europe) GmbH Fax: 08-63 80 388 Duesseldorf, Germany * United Kingdom Branch Tel: 0211-65 03 01 Milton Keynes, UK Fax: 0211-65 03 327 Tel: 01908-691-133 Fax: 01908-670-290 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 J02.4 User's Manual U15943EJ2V0UM 5 Major Revisions in This Edition Page p.16 p.83 p.86 p.190 Description Modification of description of V850ES CPU core in Figure 1-1 V850 Series CPU Development Addition of description of Caution in 5.3 Instruction Set MUL Addition of description of Caution in 5.3 Instruction Set MULU Modification of description of pipeline in APPENDIX C DIFFERENCES IN ARCHITECTURE OF V850 CPU AND V850E1 CPU Addition of APPENDIX F REVISION HISTORY p.196 The mark shows major revised points. 6 User's Manual U15943EJ2V0UM PREFACE Target Readers This manual is intended for users who wish to understand the functions of the V850ES CPU core for designing application systems using the V850ES CPU core. * Products incorporating V850ES CPU core * V850ES/SA2TM: PD703201, 703201Y, 70F3201, 70F3201Y * V850ES/SA3TM: PD703204, 703204Y, 70F3204, 70F3204Y * V850ES/KF1TM: PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y, 70F3210, 70F3210Y * V850ES/KG1TM: PD703212, 703212Y, 703213, 703213Y, 703214, 703214Y, 70F3214, 70F3214Y * V850ES/KJ1TM: PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y Purpose This manual is intended to give users an understanding of the architecture of the V850ES CPU core described in the Organization below. Organization This manual contains the following information: * Register set * * * * How to Use this Manual Data type Instruction format and instruction set Interrupt and exception Pipeline It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To learn about the hardware functions, Read Hardware User's Manual of each product. To learn about the functions of a specific instruction in detail, Read CHAPTER 5 INSTRUCTION. Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Higher digits on the left and lower digits on the right xxxB (B is appended to pin or signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating the power of 2 (address space, memory capacity): K (Kilo): 210 = 1,024 M (Mega): 220 = 1,0242 G (Giga): 230 = 1,0243 User's Manual U15943EJ2V0UM 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. * Documents related to devices Document Name V850ES/SA2, V850ES/SA3 Hardware User's Manual V850ES/KF1, V850ES/KG1, V850ES/KJ1 Hardware User's Manual Document No. U15905E U15862E * Documents related to development tools Document Name IE-V850ES-G1 (In-Circuit Emulator) IE-703204-G1-EM1 (In-Circuit Emulator Option Board for V850ES/SA2, V850ES/SA3) IE-703217-G1-EM1 (In-Circuit Emulator Option Board for V850ES/KF1, V850ES/KG1, V850ES/KJ1) CA850 (Ver. 2.40 or Later) (C Compiler Package) Operation C Language Project Manager Assembly Language ID850 (Ver. 2.40) (Integrated Debugger) RX850 (Ver. 3.13 or Later) (Real-Time OS) Operation WindowsTM Based Fundamental Installation Technical RX850 Pro (Ver. 3.13) (Real-Time OS) Fundamental Installation Technical RD850 (Ver. 3.01) (Task Debugger) RD850 Pro (Ver. 3.01) (Task Debugger) AZ850 (Ver. 3.0) (System Performance Analyzer) PG-FP3 (Flash Memory Programmer) PG-FP4 (Flash Memory Programmer) Document No. To be prepared To be prepared To be prepared U15024E U15025E U15026E U15027E U15181E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U13502E U15260E 8 User's Manual U15943EJ2V0UM CONTENTS CHAPTER 1 GENERAL............................................................................................................................15 1.1 1.2 Features..........................................................................................................................................16 Internal Configuration ...................................................................................................................17 CHAPTER 2 REGISTER SET..................................................................................................................18 2.1 2.2 Program Registers.........................................................................................................................19 System Registers...........................................................................................................................20 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 Interrupt status saving registers (EIPC, EIPSW) ..............................................................................21 NMI status saving registers (FEPC, FEPSW)...................................................................................22 Exception cause register (ECR) .......................................................................................................22 Program status word (PSW) .............................................................................................................23 CALLT caller status saving registers (CTPC, CTPSW) ....................................................................24 Exception/debug trap status saving registers (DBPC, DBPSW) ......................................................25 CALLT base pointer (CTBP).............................................................................................................25 CHAPTER 3 DATA TYPE........................................................................................................................26 3.1 3.2 Data Format....................................................................................................................................26 Data Representation......................................................................................................................28 3.2.1 3.2.2 3.2.3 Integer ..............................................................................................................................................28 Unsigned integer ..............................................................................................................................28 Bit .....................................................................................................................................................28 3.3 Data Alignment ..............................................................................................................................28 CHAPTER 4 ADDRESS SPACE .............................................................................................................29 4.1 4.2 Memory Map...................................................................................................................................30 Addressing Mode...........................................................................................................................31 4.2.1 4.2.2 Instruction address ...........................................................................................................................31 Operand address ..............................................................................................................................33 CHAPTER 5 INSTRUCTION.....................................................................................................................35 5.1 5.2 5.3 Instruction Format .........................................................................................................................35 Outline of Instructions ..................................................................................................................39 Instruction Set................................................................................................................................43 ADD ................................................................................................................................................................45 ADDI ...............................................................................................................................................................46 AND ................................................................................................................................................................47 ANDI ...............................................................................................................................................................48 Bcond .............................................................................................................................................................49 BSH ................................................................................................................................................................51 BSW ...............................................................................................................................................................52 CALLT ............................................................................................................................................................53 CLR1 ..............................................................................................................................................................54 CMOV.............................................................................................................................................................55 User's Manual U15943EJ2V0UM 9 CMP............................................................................................................................................................... 56 CTRET........................................................................................................................................................... 57 DBRET........................................................................................................................................................... 58 DBTRAP ........................................................................................................................................................ 59 DI ................................................................................................................................................................... 60 DISPOSE....................................................................................................................................................... 61 DIV................................................................................................................................................................. 63 DIVH .............................................................................................................................................................. 64 DIVHU............................................................................................................................................................ 66 DIVU .............................................................................................................................................................. 67 EI ................................................................................................................................................................... 68 HALT.............................................................................................................................................................. 69 HSW .............................................................................................................................................................. 70 JARL .............................................................................................................................................................. 71 JMP................................................................................................................................................................ 72 JR .................................................................................................................................................................. 73 LD.B............................................................................................................................................................... 74 LD.BU ............................................................................................................................................................ 75 LD.H............................................................................................................................................................... 76 LD.HU ............................................................................................................................................................ 77 LD.W.............................................................................................................................................................. 78 LDSR ............................................................................................................................................................. 79 MOV............................................................................................................................................................... 80 MOVEA.......................................................................................................................................................... 81 MOVHI ........................................................................................................................................................... 82 MUL ............................................................................................................................................................... 83 MULH............................................................................................................................................................. 84 MULHI............................................................................................................................................................ 85 MULU............................................................................................................................................................. 86 NOP ............................................................................................................................................................... 87 NOT ............................................................................................................................................................... 88 NOT1 ............................................................................................................................................................. 89 OR ................................................................................................................................................................. 90 ORI ................................................................................................................................................................ 91 PREPARE...................................................................................................................................................... 92 RETI............................................................................................................................................................... 94 SAR ............................................................................................................................................................... 96 SASF ............................................................................................................................................................. 97 SATADD ........................................................................................................................................................ 98 SATSUB ........................................................................................................................................................ 99 SATSUBI ..................................................................................................................................................... 100 SATSUBR.................................................................................................................................................... 101 SET1............................................................................................................................................................ 102 SETF............................................................................................................................................................ 103 SHL.............................................................................................................................................................. 105 SHR ............................................................................................................................................................. 106 SLD.B .......................................................................................................................................................... 107 SLD.BU........................................................................................................................................................ 108 10 User's Manual U15943EJ2V0UM SLD.H ...........................................................................................................................................................109 SLD.HU ........................................................................................................................................................110 SLD.W ..........................................................................................................................................................111 SST.B ...........................................................................................................................................................112 SST.H ...........................................................................................................................................................113 SST.W ..........................................................................................................................................................114 ST.B..............................................................................................................................................................115 ST.H .............................................................................................................................................................116 ST.W.............................................................................................................................................................117 STSR ............................................................................................................................................................118 SUB ..............................................................................................................................................................119 SUBR............................................................................................................................................................120 SWITCH .......................................................................................................................................................121 SXB ..............................................................................................................................................................122 SXH ..............................................................................................................................................................123 TRAP ............................................................................................................................................................124 TST...............................................................................................................................................................125 TST1.............................................................................................................................................................126 XOR..............................................................................................................................................................127 XORI.............................................................................................................................................................128 ZXB...............................................................................................................................................................129 ZXH ..............................................................................................................................................................130 5.4 Number of Instruction Execution Clock Cycles .......................................................................131 CHAPTER 6 INTERRUPTS AND EXCEPTIONS .................................................................................135 6.1 Interrupt Servicing.......................................................................................................................136 6.1.1 6.1.2 Maskable interrupt ..........................................................................................................................136 Non-maskable interrupt ..................................................................................................................138 Software exception .........................................................................................................................139 Exception trap.................................................................................................................................140 Debug trap......................................................................................................................................141 Restoring from interrupt and software exception ............................................................................142 Restoring from exception trap and debug trap ...............................................................................143 6.2 Exception Processing .................................................................................................................139 6.2.1 6.2.2 6.2.3 6.3 Restoring from Interrupt/Exception Processing ......................................................................142 6.3.1 6.3.2 CHAPTER 7 RESET ...............................................................................................................................144 7.1 7.2 Register Status After Reset ........................................................................................................144 Starting Up ...................................................................................................................................144 CHAPTER 8 PIPELINE...........................................................................................................................145 8.1 Features........................................................................................................................................146 8.1.1 8.1.2 8.1.3 Non-blocking load/store..................................................................................................................147 2-clock branch ................................................................................................................................148 Efficient pipeline processing ...........................................................................................................149 Load instructions ............................................................................................................................150 User's Manual U15943EJ2V0UM 8.2 Pipeline Flow During Execution of Instructions.......................................................................150 8.2.1 11 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 Store instructions ........................................................................................................................... 151 Multiply instructions ....................................................................................................................... 151 Arithmetic operation instructions.................................................................................................... 153 Saturated operation instructions .................................................................................................... 154 Logical operation instructions ........................................................................................................ 154 Branch instructions ........................................................................................................................ 154 Bit manipulation instructions .......................................................................................................... 156 Special instructions........................................................................................................................ 156 Debug function instructions ........................................................................................................... 161 Alignment hazard ........................................................................................................................... 162 Referencing execution result of load instruction ............................................................................ 163 Referencing execution result of multiply instruction....................................................................... 164 Referencing execution result of LDSR instruction for EIPC and FEPC ......................................... 165 Cautions when creating programs ................................................................................................. 165 Harvard architecture ...................................................................................................................... 166 Short path ...................................................................................................................................... 167 8.3 Pipeline Disorder ........................................................................................................................ 162 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4 Additional Items Related to Pipeline......................................................................................... 166 8.4.1 8.4.2 APPENDIX A INSTRUCTION LIST ...................................................................................................... 169 APPENDIX B INSTRUCTION OPCODE MAP..................................................................................... 183 APPENDIX C DIFFERENCES IN ARCHITECTURE OF V850 CPU AND V850E1 CPU .............. 188 APPENDIX D INSTRUCTIONS ADDED FOR V850ES CPU COMPARED WITH V850 CPU ...... 191 APPENDIX E INDEX .............................................................................................................................. 193 APPENDIX F REVISION HISTORY ...................................................................................................... 196 12 User's Manual U15943EJ2V0UM LIST OF FIGURES Figure No. 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 4-1 4-2 4-3 4-4 4-5 4-6 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 Title Page V850 Series CPU Development ....................................................................................................................... 16 Internal Block Diagram of V850ES CPU........................................................................................................... 17 Registers .......................................................................................................................................................... 18 Program Counter (PC)...................................................................................................................................... 19 Interrupt Status Saving Registers (EIPC, EIPSW)............................................................................................ 21 NMI Status Saving Registers (FEPC, FEPSW) ................................................................................................ 22 Exception Cause Register (ECR) ..................................................................................................................... 22 Program Status Word (PSW)............................................................................................................................ 23 CALLT Caller Status Saving Registers (CTPC, CTPSW)................................................................................. 24 Exception/Debug Trap Status Saving Registers (DBPC, DBPSW) .................................................................. 25 CALLT Base Pointer (CTBP) ............................................................................................................................ 25 Memory Map..................................................................................................................................................... 30 Relative Addressing.......................................................................................................................................... 31 Register Addressing (JMP [reg1] Instruction)................................................................................................... 32 Based Addressing (Type 1) .............................................................................................................................. 33 Based Addressing (Type 2) .............................................................................................................................. 34 Bit Addressing .................................................................................................................................................. 34 Maskable Interrupt Servicing Format.............................................................................................................. 137 Non-Maskable Interrupt Servicing Format...................................................................................................... 138 Software Exception Processing Format ......................................................................................................... 139 Illegal Instruction Code ................................................................................................................................... 140 Exception Trap Processing Format ................................................................................................................ 140 Debug Trap Processing Format ..................................................................................................................... 141 Restoration from Interrupt/Software Exception Processing Format................................................................ 142 Restoration from Exception Trap/Debug Trap Processing Format................................................................. 143 Example of Executing Nine Standard Instructions ......................................................................................... 145 Pipeline Configuration .................................................................................................................................... 146 Non-Blocking Load/Store................................................................................................................................ 147 Pipeline Operations with Branch Instructions ................................................................................................. 148 Parallel Execution of Branch Instructions ....................................................................................................... 149 Align Hazard Example .................................................................................................................................... 162 Example of Execution Result of Load Instruction ........................................................................................... 163 Example of Execution Result of Multiply Instruction....................................................................................... 164 Example of Referencing Execution Result of LDSR Instruction for EIPC and FEPC ..................................... 165 User's Manual U15943EJ2V0UM 13 LIST OF TABLES Table No. 2-1 2-2 5-1 5-2 5-3 5-4 5-5 5-6 6-1 7-1 A-1 A-2 D-1 Title Page Program Registers ............................................................................................................................................19 System Register Numbers ................................................................................................................................20 Conventions of Instruction Format....................................................................................................................43 Conventions of Operation .................................................................................................................................43 Conventions of Opcode ....................................................................................................................................44 Bcond Instructions ............................................................................................................................................50 Condition Codes .............................................................................................................................................104 List of Number of Instruction Execution Clock Cycles ....................................................................................131 Interrupt/Exception Codes ..............................................................................................................................135 Register Status After Reset ............................................................................................................................144 Instruction Function List (in Alphabetical Order).............................................................................................169 Instruction List (in Format Order)....................................................................................................................180 Instructions Added to V850ES CPU and V850 CPU Instructions with Same Instruction Code ......................191 14 User's Manual U15943EJ2V0UM CHAPTER 1 GENERAL Real-time control systems are used in a wide range of applications, including: * office equipment such as HDDs (Hard Disk Drives), PPCs (Plain Paper Copiers), printers, and facsimiles, * automobile electronics such as engine control systems and ABSs (Antilock Braking Systems), and * factory automation equipment such as NC (Numerical Control) machine tools and various controllers. The great majority of these systems conventionally employ 8-bit or 16-bit microcontrollers. However, the performance level of these microcontrollers has become inadequate in recent years as control operations have risen in complexity, leading to the development of increasingly complicated instruction sets and hardware design. As a result, the need has arisen for a new generation of microcontrollers operable at much higher frequencies to achieve an acceptable level of performance under today's more demanding requirements. The V850 SeriesTM of microcontrollers was developed to satisfy this need. This family uses RISC architecture that can provide maximum performance with simpler hardware, allowing users to obtain a performance approximately 15 times higher than that of the existing 78K/III Series and 78K/IV Series of CISC single-chip microcontrollers at a lower total cost. In addition to the basic instructions of conventional RISC CPUs, the V850 Series is provided with special instructions such as saturate, bit manipulate, and multiply/divide (executed by a hardware multiplier) instructions, which are especially suited for digital servo control systems. Moreover, instruction formats are designed for maximum compiler coding efficiency, allowing the reduction of object code sizes. Furthermore, to improve the performance of the V850 Series, new CPU cores, the V850E1 and V850E2 (under development), are being introduced. These CPU cores are based on the conventional V850 CPU and maintain upward instruction compatibility, but feature enhanced operating frequencies and pipeline efficiency. Another new CPU core, the V850ES, was developed for use in applications that primarily employ 16-bit microcontrollers, and offers the kind of high performance at a low cost demanded in this field. The V850ES is a high-performance, compact CPU core that provides a set of functions (operating frequency, multiplier, DMA) optimized for the 16-bit microcontroller market, while maintaining compatibility with the V850E1 CPU with a proven record in 50 MHz class products. User's Manual U15943EJ2V0UM 15 CHAPTER 1 GENERAL Figure 1-1. V850 Series CPU Development V850E2 CPU core V850E2 CPU core V850E2 CPU core V850E1 CPU core 124MIPS@100 MHz High-end product development 82MIPS@66 MHz V850 CPU core 38MIPS@33 MHz General-purpose product development 19MIPS@17 MHz V850ES CPU core Low-power product development 24MIPS@20 MHz : In planning : Under development 1.1 Features (1) High-performance 32-bit architecture for embedded control * Number of instructions: 83 * 32-bit general-purpose registers: 32 * Load/store instructions in long/short format * 3-operand instruction * 5-stage pipeline of 1 clock cycle per stage * Hardware interlock on register/flag hazards * Memory space Program space: 64 MB linear (Usable area: 16 MB linear space + internal RAM area 60 KB) Data space: (2) Special instructions * Saturation operation instructions * Bit manipulation instructions * Multiply instructions (On-chip hardware multiplier executing multiplication in 1 or 4 clocks) 16 bits x 16 bits 32 bits 32 bits x 32 bits 32 bits or 64 bits 4 GB linear 16 User's Manual U15943EJ2V0UM CHAPTER 1 GENERAL 1.2 Internal Configuration The V850ES CPU executes almost all instructions such as address calculation, arithmetic and logical operation, and data transfer in one clock by using a 5-stage pipeline. It contains dedicated hardware such as a multiplier (16 x 16 bits) and a barrel shifter (32 bits/clock) to execute complicated instructions at high speeds. Figure 1-2 shows the internal block diagram. Figure 1-2. Internal Block Diagram of V850ES CPU Instruction queue Multiplier (16 x 16 32) Program counter ROM General-purpose register Barrel shifter Instruction cache System register ALU Data cache User's Manual U15943EJ2V0UM 17 CHAPTER 2 REGISTER SET The registers can be classified into two types: program registers that can be used for general programming, and system registers that can control the execution environment. All the registers are 32 bits wide. Figure 2-1. Registers (a) Program registers 31 r0 (Zero register) r1 (Assembler-reserved register) r2 r3 (Stack pointer (SP)) r4 (Global pointer (GP)) r5 (Text pointer (TP)) r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (Element pointer (EP)) r31 (Link pointer (LP)) 0 31 (b) System registers 0 EIPC (Interrupt status saving register) EIPSW (Interrupt status saving register) FEPC (NMI status saving register) FEPSW (NMI status saving register) ECR (Exception cause register) PSW (Program status word) CTPC (CALLT caller status saving register) CTPSW (CALLT caller status saving register) DBPC (Exception/debug trap status saving register) DBPSW (Exception/debug trap status saving register) CTBP (CALLT base pointer) PC (Program counter) 18 User's Manual U15943EJ2V0UM CHAPTER 2 REGISTER SET 2.1 Program Registers There are general-purpose registers (r0 to r31) and program counter (PC) in the program registers. Table 2-1. Program Registers Program Register General-purpose register r0 r1 r2 r3 r4 r5 Name Function Zero register Assembler-reserved register Always holds 0. Used as working register for address generation. Description Address/data variable register (when the real-time OS to be used is not using r2) Stack pointer (SP) Global pointer (GP) Text pointer (TP) Used for stack frame generation when function is called. Used to access global variable in data area. Used as register for pointing start address of text area (area where program code is placed) r6 to r29 r30 Address/data variable registers Element pointer (EP) Used as base pointer for address generation when memory is accessed. Used when compiler calls function. r31 Program counter PC Link pointer (LP) Holds instruction address during program execution. Remark For detailed descriptions of r1, r3 to r5, and r31 used by assembler and C compiler, refer to the CA850 (C Compiler Package) Assembly Language User's Manual. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are provided. All these registers can be used for data variable or address variable. However, r0 and r30 are implicitly used by instructions, and care must be exercised in using these registers. r0 is a register that always holds 0, and is used for operations and offset 0 addressing. r30 is used as a base pointer when accessing memory using the SLD and SST instructions. r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Before using these registers, therefore, their contents must be saved so that they are not lost. The contents must be restored to the registers after the registers have been used. r2 is sometimes used by the real-time OS. When the real-time OS to be used is not using r2, r2 can be used as a variable register. (2) Program counter (PC) This register holds an instruction address during program execution. The lower 26 bits of this register are valid, and bits 31 to 26 are reserved for future function expansion (fixed to 0). If a carry occurs from bit 25 to bit 26, it is ignored. Bit 0 is always fixed to 0, and execution cannot branch to an odd address. Figure 2-2. Program Counter (PC) 31 26 25 (Instruction address during execution) 10 0 Initial value 00000000H PC 0 0 0 0 0 0 User's Manual U15943EJ2V0UM 19 CHAPTER 2 REGISTER SET 2.2 System Registers The system registers control the status and holds information on interrupts. System registers can be read or written by specifying the relevant system register number from the following list using the LDSR and STSR instructions. Table 2-2. System Register Numbers Register No. Register Name Operand Specifiability LDSR Instruction Interrupt status saving register (EIPC) Interrupt status saving register (EIPSW) NMI status saving register (FEPC) NMI status saving register (FEPSW) Exception cause register (ECR) Program status word (PSW) (Numbers reserved for future function expansion (operation cannot be guaranteed if accessed)) CALLT caller status saving register (CTPC) CALLT caller status saving register (CTPSW) Exception/debug trap status saving register (DBPC) Exception/debug trap status saving register (DBPSW) CALLT base pointer (CTBP) (Numbers reserved for future function expansion (operation cannot be guaranteed if accessed)) x x x x x STSR Instruction 0 1 2 3 4 5 6 to 15 16 17 18 19 20 21 to 31 Caution When returning from interrupt servicing using the RETI instruction after setting bit 0 of EIPC, FEPC, or CTPC to 1 using the LDSR instruction, the value of bit 0 is ignored (because bit 0 of the PC is fixed to 0). Therefore, be sure to set an even number (bit 0 = 0) when setting a value in EIPC, FEPC, or CTPC. Remark O: Accessible x: Inaccessible 20 User's Manual U15943EJ2V0UM CHAPTER 2 REGISTER SET 2.2.1 Interrupt status saving registers (EIPC, EIPSW) Two interrupt status saving registers are provided: EIPC and EIPSW. If a software exception or maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (if a non-maskable interrupt (NMI) occurs, the contents are saved to NMI status saving registers (FEPC, FEPSW)). Except for part of instructions, the address of the instruction next to the one executed when the software exception or maskable interrupt has occurred is saved to the EIPC (see Table 6-1 Interrupt/Exception Codes). The current value of the PSW is saved to the EIPSW. Because only one pair of interrupt status saving registers is provided, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of the EIPC and bits 31 to 8 of the EIPSW are reserved for future function expansion (fixed to 0). Figure 2-3. Interrupt Status Saving Registers (EIPC, EIPSW) 31 26 25 (Contents of PC) 8 (Contents of PSW) 0 Initial value 0xxxxxxxH (x: Undefined) EIPC 0 0 0 0 0 0 31 0 Initial value 000000xxH (x: Undefined) EIPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 User's Manual U15943EJ2V0UM 21 CHAPTER 2 REGISTER SET 2.2.2 NMI status saving registers (FEPC, FEPSW) Two NMI status saving registers are provided: FEPC and FEPSW. If a non-maskable interrupt (NMI) occurs, the contents of the program counter (PC) are saved to FEPC, and the contents of the program status word (PSW) are saved to FEPSW. Except for part of instructions, the address of the instruction next to the one executed when the NMI has occurred is saved to the FEPC (see Table 6-1 Interrupt/Exception Codes). The current value of the PSW is saved to the FEPSW. Because only one pair of NMI status saving registers is provided, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of the FEPC and bits 31 to 8 of the FEPSW are reserved for future function expansion (fixed to 0). Figure 2-4. NMI Status Saving Registers (FEPC, FEPSW) 31 26 25 (Contents of PC) 8 (Contents of PSW) 0 Initial value 0xxxxxxxH (x: Undefined) FEPC 0 0 0 0 0 0 31 0 Initial value 000000xxH (x: Undefined) FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.2.3 Exception cause register (ECR) The exception cause register (ECR) holds the cause information when an exception or interrupt occurs. The ECR holds an exception code which identifies each interrupt source (see Table 6-1 Interrupt/Exception Codes). This is a read-only register, and therefore, no data can be written to it by using the LDSR instruction. Figure 2-5. Exception Cause Register (ECR) 31 ECR FECC 16 15 EICC 0 Initial value 00000000H Bit Position 31 to 16 15 to 0 Bit Name FECC EICC Function Exception code of non-maskable interrupt (NMI) Exception code of exception or maskable interrupt 22 User's Manual U15943EJ2V0UM CHAPTER 2 REGISTER SET 2.2.4 Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of the bits in this register are modified by the LDSR instruction, the PSW will assume the new value immediately after the LDSR instruction has been executed. In setting the ID flag to 1, however, interrupt requests are already disabled even while the LDSR instruction is executing. Bits 31 to 8 are reserved for future function expansion (fixed to 0). Figure 2-6. Program Status Word (PSW) (1/2) 31 PSW 876543210 NE I SCO S Z Initial value PPDAYV 00000020H T 000000000000000000000000 Bit Position 7 Flag Name NP Function Indicates that non-maskable interrupt (NMI) processing is in progress. This flag is set to 1 when NMI request is acknowledged, and multiple interrupts are disabled. 0: NMI processing is not in progress 1: NMI processing is in progress Indicates that exception processing is in progress. This flag is set to 1 when an exception occurs. Even when this bit is set, interrupt requests can be acknowledged. 0: Exception processing is not in progress 1: Exception processing is in progress Indicates whether maskable interrupt request can be acknowledged. 0: Interrupt can be acknowledged 1: Interrupt cannot be acknowledged Indicates that an overflow has occurred in a saturate operation and the result is saturated. This is a cumulative flag. When the result is saturated, the flag is set to 1 and is not cleared to 0 even if the next result does not saturate. To clear this flag to 0, use the LDSR instruction. This flag is neither set to 1 nor cleared to 0 by execution of arithmetic operation instruction. 0: Not saturated 1: Saturated Indicates whether carry or borrow occurred as a result of the operation. 0: Carry or borrow did not occur 1: Carry or borrow occurred Indicates whether overflow occurred as a result of the operation. 0: Overflow did not occur 1: Overflow occurred Indicates whether the result of the operation is negative. 0: Result is positive or zero 1: Result is negative 6 EP 5 ID 4 SATNote 3 CY 2 OVNote 1 SNote Remark See the following page for an explanation of the Note. User's Manual U15943EJ2V0UM 23 CHAPTER 2 REGISTER SET Figure 2-6. Program Status Word (PSW) (2/2) Bit Position 0 Flag Name Z Function Indicates whether the result of the operation is zero. 0: Result is not zero 1: Result is zero Note In the case of saturate instructions, the SAT, S, and OV flags will be set according to the result of the operation as shown in the table below. Note that the SAT flag is set to 1 only when the OV flag has been set to 1 during saturate operation. Status of Operation Result Maximum positive value is exceeded Maximum negative value is exceeded Positive (Not exceeding maximum value) 1 1 Holds the value before Status of Flag SAT 1 1 0 OV 0 1 0 1 S Operation Result of Saturation Processing 7FFFFFFFH 80000000H Operation result Negative (Not exceeding operation maximum value) 2.2.5 CALLT caller status saving registers (CTPC, CTPSW) Two CALLT caller status saving registers are provided: CTPC and CTPSW. If a CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the contents of the program status word (PSW) are saved to CTPSW. The contents saved to the CTPC are the address of the instruction next to the CALLT instruction. The current value of the PSW is saved to the CTPSW. Bits 31 to 26 of the CTPC and bits 31 to 8 of the CTPSW are reserved for future function expansion (fixed to 0). Figure 2-7. CALLT Caller Status Saving Registers (CTPC, CTPSW) 31 26 25 (Contents of PC) 8 (Contents of PSW) 0 Initial value 0xxxxxxxH (x: Undefined) 0 Initial value 000000xxH (x: Undefined) CTPC 0 0 0 0 0 0 31 CTPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 User's Manual U15943EJ2V0UM CHAPTER 2 REGISTER SET 2.2.6 Exception/debug trap status saving registers (DBPC, DBPSW) Two exception/debug trap status saving registers are provided: DBPC and DBPSW. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and the contents of the program status word (PSW) are saved to DBPSW. The contents saved to the DBPC are the address of the instruction next to the one executed when the exception trap or debug trap has occurred. The current value of the PSW is saved to the DBPSW. Bits 31 to 26 of the DBPC and bits 31 to 8 of the DBPSW are reserved for future function expansion (fixed to 0). Figure 2-8. Exception/Debug Trap Status Saving Registers (DBPC, DBPSW) 31 26 25 (Contents of PC) 8 (Contents of PSW) 0 Initial value 0xxxxxxxH (x: Undefined) 0 Initial value 000000xxH (x: Undefined) DBPC 0 0 0 0 0 0 31 DBPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.2.7 CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify a table address and to generate a target address (bit 0 is fixed to 0). Bits 31 to 26 are reserved for future function expansion (fixed to 0). Figure 2-9. CALLT Base Pointer (CTBP) 31 26 25 (Base address) 0 0 Initial value 0xxxxxxxH (x: Undefined) CTBP 0 0 0 0 0 0 User's Manual U15943EJ2V0UM 25 CHAPTER 3 DATA TYPE 3.1 Data Format The following data types are supported (see 3.2 Data Representation). * Integer (32, 16, 8 bits) * Unsigned integer (32, 16, 8 bits) * Bit Three types of data lengths: word (32 bits), halfword (16 bits), and byte (8 bits) are supported. Byte 0 of any data is always the least significant byte (this is called little endian) and shown at the rightmost position in figures throughout this manual. The following paragraphs describe the data format where data of fixed length is in memory. (1) Word A word is 4-byte (32-bit) contiguous data that starts from any word boundary Note . Each bit is assigned a number Note from 0 to 31. The LSB (Least Significant Bit) is bit 0 and the MSB (Most Significant Bit) is bit 31. A word is specified by its address A (with the 2 lowest bits fixed to 0 when misalign access is disabled bytes, A, A+1, A+2, and A+3. Note When misalign access is enabled, any byte boundary can be accessed whether access is in halfword or word units. See 3.3 Data Alignment. ), and occupies 4 31 M S B A+3 24 23 16 15 87 0 L S Data B A Address A+2 A+1 26 User's Manual U15943EJ2V0UM CHAPTER 3 DATA TYPE (2) Halfword A halfword is 2-byte (16-bit) contiguous data that starts from any halfword boundary lowest bit fixed to 0 Note Note . Each bit is assigned a number from 0 to 15. The LSB is bit 0 and the MSB is bit 15. A halfword is specified by its address A (with the ), and occupies 2 bytes, A and A+1. Note When misalign access is enabled, any byte boundary can be accessed whether access is in halfword or word units. See 3.3 Data Alignment. 15 M S B A+1 87 0 L S Data B A Address (3) Byte A byte is 8-bit contiguous data that starts from any byte boundary Note . Each bit is assigned a number from 0 to 7. The LSB is bit 0 and the MSB is bit 7. A byte is specified by its address A. Note When misalign access is enabled, any byte boundary can be accessed whether access is in halfword or word units. See 3.3 Data Alignment. 7 M S B A 0 L S Data B Address (4) Bit A bit is 1-bit data at the nth bit position in 8-bit data that starts from any byte boundary address A and bit number n. Note When misalign access is enabled, any byte boundary can be accessed whether access is in halfword or word units. See 3.3 Data Alignment. Note . A bit is specified by its 7 Byte of address A ... n 0 Bit number Data A Address User's Manual U15943EJ2V0UM 27 CHAPTER 3 DATA TYPE 3.2 Data Representation 3.2.1 Integer An integer is expressed as a binary number of 2's complement and is 32, 16, or 8 bits long. Regardless of its length, the bit 0 of an integer is the least significant bit. The higher the bit number, the more significant the bit. Because 2's complement is used, the most significant bit is used as a sign bit. The integer range of each data length is as follows. * Word (32 bits): * Halfword (16 bits): * Byte (8 bits): 3.2.2 Unsigned integer While an integer is data that can take either a positive or a negative value, an unsigned integer is an integer that is not negative. Like an integer, an unsigned integer is also expressed as 2's complement and is 32, 16, or 8 bits long. Regardless of its length, bit 0 of an unsigned integer is the least significant bit, and the higher the bit number, the more significant the bit. However, no sign bit is used. The unsigned integer range of each data length is as follows. * Word (32 bits): * Halfword (16 bits): * Byte (8 bits): 3.2.3 Bit 1-bit data that can take a value of 0 (cleared) or 1 (set) can be handled as a bit data. Bit manipulation can be performed only to 1-byte data in the memory space in the following four ways: * SET1 * CLR1 * NOT1 * TST1 0 to 4,294,967,295 0 to 65,535 0 to 255 -2,147,483,648 to +2,147,483,647 -32,768 to +32,767 -128 to +127 3.3 Data Alignment Due to the incorporation of a misalign function, data that is allocated to the memory can be placed at any address regardless of the data format (word data, halfword data). However, if word data is not aligned at a word boundary (the lower 2 bits of the address are 0), or halfword data is not aligned at a halfword boundary (the lowest bit of the address is 0), one or more surplus bus cycles are generated, which lowers the bus efficiency. 28 User's Manual U15943EJ2V0UM CHAPTER 4 ADDRESS SPACE The V850ES CPU supports a 4 GB linear address space. Both memory and I/O are mapped to this address space (memory-mapped I/O). The V850ES CPU outputs 32-bit addresses to the memory and I/O. The maximum address is 232-1. Byte data allocated at each address is defined with bit 0 as LSB and bit 7 as MSB. In regards to multiple-byte data, the byte with the lowest address value is defined to have the LSB and the byte with the highest address value is defined to have the MSB (little endian). Data consisting of 2 bytes is called a halfword, and 4-byte data is called a word. In this User's Manual, data consisting of 2 or more bytes is illustrated as shown below, with the lower address shown on the right and the higher address on the left. 31 24 23 16 15 87 0 Word at address A ....... A+3 A+2 15 A+1 87 A 0 Data Address Halfword at address A ............................................................................................ A+1 7 A 0 Data Address Byte at address A ...................................................................................................................................... A Data Address User's Manual U15943EJ2V0UM 29 CHAPTER 4 ADDRESS SPACE 4.1 Memory Map The V850ES CPU employs a 32-bit architecture and supports a linear address space (data area) of up to 4 GB for operand addressing (data access). It supports a linear address space (program area) of up to 64 MB for instruction addressing. However, areas usable as program area are a linear address space of up to 16 MB and the internal RAM area (60 KB max.). Figure 4-1 shows the memory map. Figure 4-1. Memory Map (a) Address space (b) Program area FFFFFFFFH 3FFFFFFH 3FFF000H 3FFEFFFH Peripheral I/O area (4 KB) Internal RAM area 60 KB 3FF0000H 3FEFFFFH Data area (4 GB linear) 1000000H 0FFFFFFH External memory area 04000000H 03FFFFFFH Program area (64 MB linear) 00000000H 0000000H Internal ROM area 16 MB Reserved 64 MB Remark : Use as program area is prohibited 30 User's Manual U15943EJ2V0UM CHAPTER 4 ADDRESS SPACE 4.2 Addressing Mode The CPU generates two types of addresses: instruction addresses used for instruction fetch and branch operations; and operand addresses used for data access. 4.2.1 Instruction address An instruction address is determined by the contents of the program counter (PC), and is automatically incremented (+2) according to the number of bytes of an instruction to be fetched each time an instruction has been executed. When a branch instruction is executed, the branch destination address is loaded into the PC using one of the following two addressing modes: (1) Relative addressing (PC relative) The signed 9- or 22-bit data of an instruction code (displacement: dispx) is added to the value of the program counter (PC). At this time, the displacement is treated as 2's complement data with bits 8 and 21 serving as sign bits (S). This addressing is used for JARL disp22, reg2, JR disp22, and Bcond disp9 instructions. Figure 4-2. Relative Addressing (1/2) (a) JARL disp22, reg2 instruction, JR disp22 instruction 31 26 25 PC 0 0 000000 31 Sign extension 22 21 S + disp22 0 0 31 26 25 PC 0 0 Memory to be manipulated 000000 User's Manual U15943EJ2V0UM 31 CHAPTER 4 ADDRESS SPACE Figure 4-2. Relative Addressing (2/2) (b) Bcond disp9 instruction 31 26 25 PC 0 0 000000 31 Sign extension + 98 S disp9 0 0 31 26 25 PC 0 0 Memory to be manipulated 000000 (2) Register addressing (register indirect) The contents of a general-purpose register (reg1) specified by an instruction are transferred to the program counter (PC). This addressing is applied to the JMP [reg1] instruction. Figure 4-3. Register Addressing (JMP [reg1] Instruction) 31 reg1 0 31 26 25 PC 0 0 Memory to be manipulated 000000 32 User's Manual U15943EJ2V0UM CHAPTER 4 ADDRESS SPACE 4.2.2 Operand address When an instruction is executed, the register or memory area to be accessed is specified in one of the following four addressing modes: (1) Register addressing The general-purpose register or system register specified in the general-purpose register specification field is accessed as operand. This addressing mode applies to instructions using the operand format reg1, reg2, reg3, or regID. (2) Immediate addressing The 5-bit or 16-bit data for manipulation is contained in the instruction code. This addressing mode applies to instructions using the operand format imm5, imm16, vector, or cccc. Remark vector: cccc: Operand that is 5-bit immediate data to specify trap vector (00H to 1FH), and is used in TRAP instruction. Operand consisting of 4-bit data used in CMOV, SASF, and SETF instructions to specify condition code. Assigned as part of instruction code as 5-bit immediate data by appending 1-bit 0 above highest bit. (3) Based addressing The following two types of based addressing are supported: (a) Type 1 The address of the data memory location to be accessed is determined by adding the value in the specified general-purpose register (reg1) to the 16-bit displacement value (disp16) contained in the instruction code. This addressing mode applies to instructions using the operand format disp16 [reg1]. Figure 4-4. Based Addressing (Type 1) 31 reg1 0 31 Sign extension 16 15 disp16 + 0 Memory to be manipulated User's Manual U15943EJ2V0UM 33 CHAPTER 4 ADDRESS SPACE (b) Type 2 The address of the data memory location to be accessed is determined by adding the value in the element pointer (r30) to the 7- or 8-bit displacement value (disp7, disp8). This addressing mode applies to SLD and SST instructions. Figure 4-5. Based Addressing (Type 2) 31 r30 (element pointer) 0 31 0 (Zero extension) + 87 disp8 or disp7 0 Memory to be manipulated Remark Byte access: disp7 Halfword access and word access: disp8 (4) Bit addressing This addressing is used to access 1 bit (specified with bit#3 of 3-bit data) among 1 byte of the memory space to be manipulated by using an operand address which is the sum of the contents of a general-purpose register (reg1) and a 16-bit displacement (disp16) sign-extended to a word length. This addressing mode applies only to bit manipulate instructions. Figure 4-6. Bit Addressing 31 reg1 0 31 Sign extension 16 15 disp16 + 0 Memory to be manipulated n Remark n: Bit position specified with 3-bit data (bit#3) (n = 0 to 7) 34 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION 5.1 Instruction Format There are two types of instruction formats: 16-bit and 32-bit. and instructions that handle 16-bit immediate data. An instruction is actually stored in memory as follows: * Lower bytes of instruction (including bit 0) lower address The 16-bit format instructions include binary operation, control, and conditional branch instructions, and the 32-bit format instructions include load/store, jump, * Higher bytes of instruction (including bit 15 or bit 31) higher address Caution Some instructions have an unused field (RFU). This field is reserved for future expansion and must be fixed to 0. (1) reg-reg instruction (Format I) A 16-bit instruction format having a 6-bit opcode field and two general-purpose register specification fields. 15 reg2 11 10 opcode 5 4 reg1 0 (2) imm-reg instruction (Format II) A 16-bit instruction format having a 6-bit opcode field, 5-bit immediate field, and a general-purpose register specification field. 15 reg2 11 10 opcode 5 4 imm 0 User's Manual U15943EJ2V0UM 35 CHAPTER 5 INSTRUCTION (3) Conditional branch instruction (Format III) A 16-bit instruction format having a 4-bit opcode field, 4-bit condition code field, and an 8-bit displacement field. 15 disp 11 10 opcode 7 6 disp 4 3 cond 0 (4) 16-bit load/store instruction (Format IV) A 16-bit instruction format having a 4-bit opcode field, a general-purpose register specification field, and a 7-bit displacement field (or 6-bit displacement field + 1-bit sub-opcode field). 15 reg2 11 10 opcode 7 6 disp 1 0 disp/sub-opcode A 16-bit instruction format having a 7-bit opcode field, a general-purpose register specification field, and a 4-bit displacement field. 15 reg2 11 10 opcode 4 3 disp 0 (5) Jump instruction (Format V) A 32-bit instruction format having a 5-bit opcode field, a general-purpose register specification field, and a 22-bit displacement field. 15 reg2 11 10 opcode 65 0 31 disp 17 16 0 36 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION (6) 3-operand instruction (Format VI) A 32-bit instruction format having a 6-bit opcode field, two general-purpose register specification fields, and a 16bit immediate field. 15 reg2 11 10 opcode 54 reg1 0 31 imm 16 (7) 32-bit load/store instruction (Format VII) A 32-bit instruction format having a 6-bit opcode field, two general-purpose register specification fields, and a 16bit displacement field (or 15-bit displacement field + 1-bit sub-opcode field). 15 reg2 11 10 opcode 54 reg1 0 31 disp 17 16 disp/sub-opcode (8) Bit manipulation instruction (Format VIII) A 32-bit instruction format having a 6-bit opcode field, 2-bit sub-opcode field, 3-bit bit specification field, a general-purpose register specification field, and a 16-bit displacement field. 15 14 13 sub 11 10 bit # opcode 54 reg1 0 31 disp 16 (9) Extended instruction format 1 (Format IX) A 32-bit instruction format having a 6-bit opcode field, 6-bit sub-opcode field, and two general-purpose register specification fields (one field may be register number field (regID) or condition code field (cond)). 15 reg2 11 10 opcode 54 0 31 RFU 27 26 sub-opcode 21 20 RFU 17 16 0 reg1/regID/cond User's Manual U15943EJ2V0UM 37 CHAPTER 5 INSTRUCTION (10) Extended instruction format 2 (Format X) A 32-bit instruction format having a 6-bit opcode field and 6-bit sub-opcode field. 15 13 12 11 10 RFU opcode 54 0 31 RFU 27 26 sub-opcode 21 20 RFU 17 16 0 RFU/imm/vector RFU/sub-opcode (11) Extended instruction format 3 (Format XI) A 32-bit instruction format having a 6-bit opcode field, 6-bit and 1-bit sub-opcode field, and three generalpurpose register specification fields. 15 reg2 11 10 opcode 54 reg1 0 31 reg3 27 26 sub-opcode 21 20 18 17 16 RFU 0 sub-opcode (12) Extended instruction format 4 (Format XII) A 32-bit instruction format having a 6-bit opcode field, 4-bit and 1-bit sub-opcode field, 10-bit immediate field, and two general-purpose register specification fields. 15 reg2 11 10 opcode 54 imm (low) 0 31 reg3 27 26 23 22 18 17 16 0 sub-opcode imm (high) sub-opcode (13) Stack manipulation instruction 1 (Format XIII) A 32-bit instruction format having a 5-bit opcode field, 5-bit immediate field, 12-bit register list field, and one general-purpose register specification field (or 5-bit sub-opcode field). 15 RFU 11 10 opcode 65 imm 1 0 31 list 21 20 16 reg2/sub-opcode 38 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION 5.2 Outline of Instructions (1) Load instructions Transfer data from memory to a register. The following instructions (mnemonics) are provided. (a) LD instructions * LD.B: * LD.BU: * LD.H: * LD.HU: * LD.W: Load byte Load byte unsigned Load halfword Load halfword unsigned Load word (b) SLD instructions * SLD.B: * SLD.BU: * SLD.H: * SLD.HU: * SLD.W: (2) Store instructions Transfer data from register to a memory. The following instructions (mnemonics) are provided. (a) ST instructions * ST.B: * ST.H: * ST.W: Store byte Store halfword Store word Short format load byte Short format load byte unsigned Short format load halfword Short format load halfword unsigned Short format load word (b) SST instructions * SST.B: * SST.H: * SST.W: Short format store byte Short format store halfword Short format store word (3) Multiply instructions Execute multiply processing in 1 to 5 clocks with on-chip hardware multiplier. The following instructions (mnemonics) are provided. * MUL: * MULH: * MULHI: * MULU: Multiply word Multiply halfword Multiply halfword immediate Multiply word unsigned User's Manual U15943EJ2V0UM 39 CHAPTER 5 INSTRUCTION (4) Arithmetic operation instructions Add, subtract, divide, transfer, or compare data between registers. The following instructions (mnemonics) are provided. * ADD: * ADDI: * CMOV: * CMP: * DIV: * DIVH: * DIVHU: * DIVU: * MOV: * MOVEA: * MOVHI: * SASF: * SETF: * SUB: * SUBR: Add Add immediate Conditional move Compare Divide word Divide halfword Divide halfword unsigned Divide word unsigned Move Move effective address Move high halfword Shift and set flag condition Set flag condition Subtract Subtract reverse (5) Saturated operation instructions Execute saturation addition and subtraction. If the result of the operation exceeds the maximum positive value (7FFFFFFFH), 7FFFFFFFH is returned. If the result of the operation exceeds the maximum negative value (80000000H), 80000000H is returned. The following instructions (mnemonics) are provided. * SATADD: * SATSUB: * SATSUBI: Saturated add Saturated subtract Saturated subtract immediate * SATSUBR: Saturated subtract reverse (6) Logical operation instructions These instructions include logical operation and shift instructions. The shift instructions include arithmetic shift and logical shift instructions. Operands can be shifted by two or more bit positions in one clock cycle by the on-chip barrel shifter. The following instructions (mnemonics) are provided. * AND: * ANDI: * BSH: * BSW: * HSW: * NOT: * OR: * ORI: * SAR: * SHL: * SHR: * SXB: * SXH: AND AND immediate Byte swap halfword Byte swap word Halfword swap word NOT OR OR immediate Shift arithmetic right Shift logical left Shift logical right Sign extend byte Sign extend halfword User's Manual U15943EJ2V0UM 40 CHAPTER 5 INSTRUCTION * TST: * XOR: * XORI: * ZXB: * ZXH: Test Exclusive OR Exclusive OR immediate Zero extend byte Zero extend halfword (7) Branch instructions These instructions include unconditional branch instructions (JARL, JMP, JR) and conditional branch instruction (Bcond) which alters the control depending on the status of flags. transferred to the address specified by a branch instruction. provided. * Bcond (BC, BE, BGE, BGT, BH, BL, BLE, BLT, BN, BNC, BNE, BNH, BNL, BNV, BNZ, BP, BR, BSA, BV, BZ): * JARL: * JMP: * JR: Branch on condition code Jump and register link Jump register Jump relative Program control can be The following instructions (mnemonics) are (8) Bit manipulation instructions Execute a logical operation to the specified bit data in memory. The following instructions (mnemonics) are provided. * CLR1: * NOT1: * SET1: * TST1: Clear bit Not bit Set bit Test bit (9) Special instructions These instructions are instructions not included in the categories of instructions described above. The following instructions (mnemonics) are provided. * CALLT: * CTRET: * DI: * DISPOSE: * EI: * HALT: * LDSR: * NOP: * RETI: * STSR: * SWITCH: * TRAP: Call with table look up Return from CALLT Disable interrupt Function dispose Enable interrupt Halt Load system register No operation Return from trap or interrupt Store system register Jump with table look up Trap * PREPARE: Function prepare User's Manual U15943EJ2V0UM 41 CHAPTER 5 INSTRUCTION (10)Debug function instructions These instructions are instructions reserved for debug function. The following instructions (mnemonics) are provided. * DBRET: * DBTRAP: Return from debug trap Debug trap 42 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION 5.3 Instruction Set In this section, mnemonic of each instruction is described divided into the following items. * Instruction format: Indicates the description and operand of the instruction (for symbols, see Table 5-1). * Operation: * Format: * Opcode: * Flag: * Explanation: * Remark: * Caution: Indicates the function of the instruction (for symbols, see Table 5-2). Indicates the instruction format (see 5.1 Instruction Format). Indicates the bit field of the instruction opcode (for symbols, see Table 5-3). Indicates the operation of the flag which is altered after executing the instruction. 0 indicates clear (reset), 1 indicates set, and - indicates no change. Explains the operation of the instruction. Explains the supplementary information of the instruction. Indicates the cautions. Table 5-1. Conventions of Instruction Format Symbol reg1 reg2 reg3 bit#3 immx dispx regID vector cccc sp ep listx Meaning General-purpose register (used as source register) General-purpose register (mainly used as destination register. Some are also used as source registers) General-purpose register (mainly used as remainder of division results or higher 32 bits of multiply results) 3-bit data for specifying bit number x-bit immediate data x-bit displacement data System register number 5-bit data for trap vector (00H to1FH) specification 4-bit data for condition code specification Stack pointer (r3) Element pointer (r30) Lists of registers (x is a maximum number of registers) Table 5-2. Conventions of Operation (1/2) Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) Assignment General-purpose register System register Zero-extends n to word Sign-extends n to word Reads data of size b from address a Writes data b of size c to address a Reads bit b from address a Writes c to bit b of address a Meaning User's Manual U15943EJ2V0UM 43 CHAPTER 5 INSTRUCTION Table 5-2. Conventions of Operation (2/2) Symbol saturated (n) Meaning Performs saturation processing of n. If n > 7FFFFFFFH as result of calculation, n = 7FFFFFFFH. If n < 80000000H as result of calculation, n = 80000000H. Reflects result on flag Byte (8 bits) Halfword (16 bits) Word (32 bits) Add Subtract Bit concatenation Multiply Divide Remainder of division results And Or Exclusive Or Logical negate Logical left shift Logical right shift Arithmetic right shift result Byte Halfword Word + - || x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Table 5-3. Conventions of Opcode Symbol R r w d I i cccc CCCC bbb L 1-bit data of code specifying reg1 or regID 1-bit data of code specifying reg2 1-bit data of code specifying reg3 1-bit data of displacement 1-bit data of immediate (indicates higher bits of immediate) 1-bit data of immediate 4-bit data for condition code specification 4-bit data for condition code specification of Bcond instruction 3-bit data for bit number specification 1-bit data of code specifying program register in register list Meaning 44 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Add register/immediate ADD Add Instruction format (1) ADD reg1, reg2 (2) ADD imm5, reg2 Operation (1) GR [reg2] GR [reg2] + GR [reg1] (2) GR [reg2] GR [reg2] + sign-extend (imm5) Format (1) Format I (2) Format II Opcode (1) 15 rrrrr001110RRRRR 15 (2) 0 0 rrrrr010010iiiii Flag CY OV S Z SAT 1 if a carry occurs from MSB; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise 0. - Explanation (1) Adds the word data of general-purpose register reg1 to the word data of general-purpose register reg2, and stores the result to general-purpose register reg2. The data of generalpurpose register reg1 is not affected. (2) Adds 5-bit immediate data, sign-extended to word length, to the word data of generalpurpose register reg2, and stores the result to general-purpose register reg2. User's Manual U15943EJ2V0UM 45 CHAPTER 5 INSTRUCTION Add immediate ADDI Add Immediate Instruction format Operation Format Opcode ADDI imm16, reg1, reg2 GR [reg2] GR [reg1] + sign-extend (imm16) Format VI 15 rrrrr110000RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT 1 if a carry occurs from MSB; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise 0. - Explanation Adds 16-bit immediate data, sign-extended to word length, to the word data of generalpurpose register reg1, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. 46 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION AND AND And Instruction format Operation Format Opcode AND reg1, reg2 GR [reg2] GR [reg2] AND GR [reg1] Format I 15 0 rrrrr001010RRRRR Flag CY OV S Z SAT Explanation - 0 1 if the MBS of the word data of the operation result is 1; otherwise, 0. 1 if the operation result is 0; otherwise 0. - ANDs the word data of general-purpose register reg2 with the word data of general-purpose register reg1, and stores the result to general-purpose register reg2. The data of generalpurpose register reg1 is not affected. User's Manual U15943EJ2V0UM 47 CHAPTER 5 INSTRUCTION AND immediate ANDI And Immediate Instruction format Operation Format Opcode ANDI imm16, reg1, reg2 GR [reg2] GR [reg1] AND zero-extend (imm16) Format VI 15 rrrrr110110RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT - 0 1 if the MSB of the word data of the operation result is 1; otherwise, 0. 1 if the operation result is 0; otherwise 0. - Explanation ANDs the word data of general-purpose register reg1 with the value of the 16-bit immediate data, zero-extended to word length, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. 48 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Branch on condition code with 9-bit displacement Bcond Branch on Condition Code Instruction format Operation Bcond disp9 if conditions are satisfied then PC PC + sign-extend (disp9) Format Opcode Format III 15 ddddd1011dddCCCC dddddddd is the higher 8 bits of disp9. 0 Flag CY OV S Z SAT - - - - - Explanation Tests each flag of PSW specified by the instruction. Branches if a specified condition is satisfied; otherwise, executes the next instruction. The branch destination PC holds the sum of the current PC value and 9-bit displacement, which is 8-bit immediate shifted 1 bit and signextended to word length. Remark Bit 0 of the 9-bit displacement is masked to 0. The current PC value used for calculation is the address of the first byte of this instruction. If the displacement value is 0, therefore, the branch destination is this instruction itself. User's Manual U15943EJ2V0UM 49 CHAPTER 5 INSTRUCTION Table 5-4. Bcond Instructions Instruction Condition Code (CCCC) 1110 1111 0111 0110 1011 0001 0011 1001 0010 1010 0001 0100 1001 1000 1010 1100 0101 1101 0000 0010 Status of Flag Branch Condition Signed integer BGE BGT BLE BLT (S xor OV) = 0 ( (S xor OV) or Z) = 0 ( (S xor OV) or Z) = 1 (S xor OV) = 1 (CY or Z) = 0 CY = 1 (CY or Z) = 1 CY = 0 Z=1 Z=0 CY = 1 S=1 CY = 0 OV = 0 Z=0 S=0 - SAT = 1 OV = 1 Z=1 Greater than or equal signed Greater than signed Less than or equal signed Less than signed Higher (Greater than) Lower (Less than) Not higher (Less than or equal) Not lower (Greater than or equal) Equal Not equal Carry Negative No carry No overflow Not zero Positive Always (unconditional) Saturated Overflow Zero Unsigned integer BH BL BNH BNL Common BE BNE Others BC BN BNC BNV BNZ BP BR BSA BV BZ Caution If executing a conditional branch instruction of a signed integer (BGE, BGT, BLE, or BLT) when the SAT flag is set to 1 as a result of executing a saturated operation instruction, the branch condition loses its meaning. In ordinary operations, if an overflow occurs, the S flag is inverted (0 1 or 1 0). This is because the result is a negative value if it exceeds the maximum positive value and it is a positive value if it exceeds the maximum negative value. However, when a saturated operation instruction is executed, and if the result exceeds the maximum positive value, the result is saturated with a positive value; if the result exceeds the maximum negative value, the result is saturated with a negative value. Unlike the ordinary operation, therefore, the S flag is not inverted even if an overflow occurs. Hence, the S flag is affected differently when the instruction is a saturate operation, as opposed to an ordinary operation. A branch condition which is an XOR of S and OV flags will therefore have no meaning. 50 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Byte swap halfword BSH Byte Swap Halfword Instruction format Operation Format Opcode BSH reg2, reg3 GR [reg3] GR [reg2] (23:16) || GR [reg2] (31:24) || GR [reg2] (7:0) || GR [reg2] (15:8) Format XII 15 rrrrr11111100000 0 31 16 wwwww01101000010 Flag CY OV S Z SAT 1 if one or more bytes in result lower halfword is 0; otherwise 0. 0 1 if the MSB of the word data of the operation result is 1; otherwise, 0. 1 if the lower halfword data of the operation result is 0; otherwise, 0. - Explanation Endian translation. User's Manual U15943EJ2V0UM 51 CHAPTER 5 INSTRUCTION Byte swap word BSW Byte Swap Word Instruction format Operation Format Opcode BSW reg2, reg3 GR [reg3] GR [reg2] (7:0) || GR [reg2] (15:8) || GR [reg2] (23:16) || GR [reg2] (31:24) Format XII 15 rrrrr11111100000 0 31 16 wwwww01101000000 Flag CY OV S Z SAT 1 if one or more bytes in result word is 0; otherwise 0. 0 1 if the MSB of the word data of the operation result is 1; otherwise, 0. 1 if the word data of the operation result is 0; otherwise, 0. - Explanation Endian translation. 52 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Call with table look up CALLT Call with Table Look Up Instruction format Operation CALLT imm6 CTPC PC + 2 (return PC) CTPSW PSW adr CTBP + zero-extend (imm6 logically shift left by 1) PC CTBP + zero-extend (Load-memory (adr, Halfword)) Format Opcode Format II 15 0000001000iiiiii 0 Flag CY OV S Z SAT - - - - - Explanation Saves the restore PC and PSW to CTPC and CTPSW. Adds the CTBP and data of imm6, logically shifted left by 1 and zero-extended to word length, to generate a 32-bit table entry address. Then load the halfword entry data, zero-extended to word length, and adds the data and CTBP to generate a 32-bit target address. Then jump to a target address. Caution If an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. interrupt. Execution is resumed after returning from the User's Manual U15943EJ2V0UM 53 CHAPTER 5 INSTRUCTION Clear bit CLR1 Clear Bit Instruction format (1) CLR1 bit#3, disp16 [reg1] (2) CLR1 reg2, [reg1] Operation (1) adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 0) (2) adr GR [reg1] Z flag Not (Load-memory-bit (adr, reg2)) Store-memory-bit (adr, reg2, 0) Format (1) Format VIII (2) Format IX Opcode (1) 15 10bbb111110RRRRR 15 (2) rrrrr111111RRRRR - - - 0 31 16 dddddddddddddddd 0 31 16 0000000011100100 Flag CY OV S Z SAT 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 - Explanation (1) Adds the data of general-purpose register reg1 to the 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Then reads the byte data referenced by the generated address, clears the bit specified by the bit number of 3 bits, and rewrites the original address. (2) Reads the data of general-purpose register reg1 to generate a 32-bit address. Then reads the byte data referenced by the generated address, clears the bit specified by the data of lower 3 bits of reg2, and rewrites the original address. Remark The Z flag of the PSW indicates whether the specified bit was a 0 or 1 before this instruction is executed. It does not indicate the content of the specified bit after this instruction has been executed. 54 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Conditional move CMOV Conditional Move Instruction format (1) CMOV cccc, reg1, reg2, reg3 (2) CMOV cccc, imm5, reg2, reg3 Operation (1) if conditions are satisfied then GR [reg3] GR [reg1] else GR [reg3] GR [reg2] (2) if conditions are satisfied then GR [reg3] sign-extend (imm5) else GR [reg3] GR [reg2] Format (1) Format XI (2) Format XII Opcode (1) 15 0 31 16 rrrrr111111RRRRR 15 0 wwwww011001cccc0 31 16 (2) Flag CY OV S Z SAT Explanation rrrrr111111iiiii - - - - - wwwww011000cccc0 (1) The general-purpose register reg3 is set to the data of general-purpose register reg1 if a condition specified by condition code "cccc" is satisfied; otherwise, set to the data of general-purpose register reg2. One of the codes shown in Table 5-5 Condition Codes should be specified as the condition code "cccc". (2) The general-purpose register reg3 is set to the data of 5-bit immediate, sign-extended to word length, if a condition specified by condition code "cccc" is satisfied; otherwise, set to the data of general-purpose register reg2. One of the codes shown in Table 5-5 Condition Codes should be specified as the condition code "cccc". Remark See SETF instruction. User's Manual U15943EJ2V0UM 55 CHAPTER 5 INSTRUCTION Compare register/immediate (5-bit) CMP Compare Instruction format (1) CMP reg1, reg2 (2) CMP imm5, reg2 Operation (1) result GR [reg2] - GR [reg1] (2) result GR [reg2] - sign-extend (imm5) Format (1) Format I (2) Format II Opcode (1) 15 rrrrr001111RRRRR 15 (2) rrrrr010011iiiii 0 0 Flag CY OV S Z SAT 1 if a borrow to MSB occurs; otherwise, 0. 1 if overflow occurs; otherwise 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation (1) Compares the word data of general-purpose register reg2 with the word data of generalpurpose register reg1, and indicates the result by using the flags of PSW. To compare, the contents of general-purpose register reg1 are subtracted from the word data of general-purpose register reg2. The data of general-purpose registers reg1 and reg2 are not affected. (2) Compares the word data of general-purpose register reg2 with 5-bit immediate data, signextended to word length, and indicates the result by using the flags of PSW. To compare, the contents of the sign-extended immediate data is subtracted from the word data of general-purpose register reg2. The data of general-purpose register reg2 is not affected. 56 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Return from CALLT CTRET Return from CALLT Instruction format Operation CTRET PC CTPC PSW CTPSW Format Opcode Format X 15 0000011111100000 Flag CY OV S Z SAT Explanation 0 31 16 0000000101000100 Value read from CTPSW is restored. Value read from CTPSW is restored. Value read from CTPSW is restored. Value read from CTPSW is restored. Value read from CTPSW is restored. Fetches the restore PC and PSW from the appropriate system register and returns from a routine called by CALLT instruction. The operations of this instruction are as follows: (1) The restore PC and PSW are read from the CTPC and CTPSW. (2) Once the PC and PSW are restored to the return values, control is transferred to the return address. User's Manual U15943EJ2V0UM 57 CHAPTER 5 INSTRUCTION Return from debug trap DBRET Return from debug trap Instruction format Operation DBRET PC DBPC PSW DBPSW Format Opcode Format X 15 0000011111100000 Flag CY OV S Z SAT Explanation 0 31 16 0000000101000110 Value read from DBPSW is restored. Value read from DBPSW is restored. Value read from DBPSW is restored. Value read from DBPSW is restored. Value read from DBPSW is restored. Fetches the restore PC and PSW from the appropriate system register and returns from debug mode. Caution Because the DBRET instruction is for debugging, it is essentially used by debug tools. When a debug tool is using this instruction, therefore, use of it in the application may cause a malfunction. 58 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Debug trap DBTRAP Debug trap Instruction format Operation DBTRAP DBPC PC + 2 (restore PC) DBPSW PSW PSW.NP 1 PSW.EP 1 PSW.ID 1 PC 00000060H Format Opcode Format I 15 1111100001000000 0 Flag CY OV S Z SAT - - - - - Explanation Saves the contents of the restore PC (address of the instruction following the DBTRAP instruction) and the PSW to the DBPC and DBPSW, respectively, and sets the NP, EP, and ID flags of PSW to 1. Next, the handler address (00000060H) of the exception trap is set to the PC, and control shifts to the PC. PSW flags other than NP, EP, and ID flags are unaffected. Note that the value saved to the DBPC is the address of the instruction following the DBTRAP instruction. Caution Because the DBTRAP instruction is for debugging, it is essentially used by debug tools. When a debug tool is using this instruction, therefore, use of it in the application may cause a malfunction. User's Manual U15943EJ2V0UM 59 CHAPTER 5 INSTRUCTION Disable interrupt DI Disable Interrupt Instruction format Operation Format Opcode DI PSW.ID 1 (Disables maskable interrupt) Format X 15 0000011111100000 0 31 16 0000000101100000 Flag CY OV S Z SAT ID - - - - - 1 Explanation Sets the ID flag of the PSW to 1 to disable the acknowledgement of maskable interrupts during execution of this instruction. Remark Interrupts are not sampled during execution of this instruction. during instruction execution, interrupts are immediately disabled. (NMI) are not affected by this instruction. The PSW flag actually Non-maskable interrupts becomes valid at the start of the next instruction. But because interrupts are not sampled 60 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Function dispose DISPOSE Function Dispose Instruction format (1) DISPOSE imm5, list12 (2) DISPOSE imm5, list12, [reg1] Operation (1) sp sp + zero-extend (imm5 logically shift left by 2) GR [reg in list12] Load-memory (sp, Word) sp sp + 4 repeat 2 steps above until all regs in list12 are loaded (2) sp sp + zero-extend (imm5 logically shift left by 2) GR [reg in list12] Load-memory (sp, Word) sp sp + 4 repeat 2 states above until all regs in list12 are loaded PC GR [reg1] Format Opcode Format XIII 15 (1) 0000011001iiiiiL 15 (2) 0000011001iiiiiL RRRRR must not be 00000. In addition, LLLLLLLLLLLL indicates the value of corresponding bit in the register list (list12) (for example, "L" of the bit 21 in the opcode indicates the value of bit 21 of the list12). The list12 is a 32-bit register list defined as follows. 31 30 29 28 27 26 25 24 23 22 21 20 ... 0 31 16 LLLLLLLLLLL00000 0 31 16 LLLLLLLLLLLRRRRR 1 0 r30 r24 r25 r26 r27 r20 r21 r22 r23 r28 r29 r31 - General-purpose registers (r20 to r31) correspond to the bits 31 to 21 and 0, and the register corresponding to the bit being set (to 1) is specified as the target of manipulation. Any values can be set to bits 20 to 1 since these bits are not corresponding to registers. User's Manual U15943EJ2V0UM 61 CHAPTER 5 INSTRUCTION Flag CY OV S Z SAT - - - - - Explanation (1) Adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. Then pop (load data from the address specified by sp and adds 4 to sp) general-purpose registers listed in list12. Bit 0 of the address is masked to 0. (2) Adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. Then pop (load data from the address specified by sp and adds 4 to sp) general-purpose registers listed in list12, transfers control to the address specified by general-purpose register reg1. Bit 0 of the address is masked to 0. Remark General-purpose registers in list12 are loaded in the downward direction. (r31, r30, ... r20) The 5-bit immediate imm5 is used to restore a stack frame for auto variables and temporary data. The lower 2-bit of address specified by sp is always masked to 0 even if misaligned access is enabled. If an interrupt occurs before updating the sp, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction (sp will retain their original values prior to the start of execution). Caution If an interrupt is generated during instruction execution, due to manipulation of the stack, the execution of that instruction may stop after the read/write cycle and register value rewriting are complete. Execution is resumed after returning from the interrupt. 62 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Divide word DIV Divide Word Instruction format Operation DIV reg1, reg2, reg3 GR [reg2] GR [reg2] / GR [reg1] GR [reg3] GR [reg2] % GR [reg1] Format Opcode Format XI 15 rrrrr111111RRRRR 0 31 16 wwwww01011000000 Flag CY OV S Z SAT - 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Divides the word data of general-purpose register reg2 by the word data of general-purpose register reg1, and stores the quotient to general-purpose register reg2, and the remainder to general-purpose register reg3. If the data is divided by 0, overflow occurs, and the quotient is undefined. The data of general-purpose register reg1 is not affected. Remark Overflow occurs when the maximum negative value (80000000H) is divided by -1 (in which case the quotient is 80000000H) and when data is divided by 0 (in which case the quotient is undefined). If an interrupt occurs while this instruction is executed, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. If the address of reg2 is the same as the address of reg3, the remainder is stored in reg2 (= reg3). User's Manual U15943EJ2V0UM 63 CHAPTER 5 INSTRUCTION Divide halfword DIVH Divide Halfword Instruction format (1) DIVH reg1, reg2 (2) DIVH reg1, reg2, reg3 Operation (1) GR [reg2] GR [reg2] / GR [reg1] (2) GR [reg2] GR [reg2] / GR [reg1] GR [reg3] GR [reg2] % GR [reg1] Format (1) Format I (2) Format XI Opcode (1) 15 0 rrrrr000010RRRRR 15 0 31 16 (2) Flag CY OV S Z SAT Explanation rrrrr111111RRRRR - wwwww01010000000 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - (1) Divides the word data of general-purpose register reg2 by the lower halfword data of general-purpose register reg1, and stores the quotient to general-purpose register reg2. If the data is divided by 0, overflow occurs, and the quotient is undefined. The data of general-purpose register reg1 is not affected. (2) Divides the word data of general-purpose register reg2 by the lower halfword data of general-purpose register reg1, and stores the quotient to general-purpose register reg2, the remainder to general-purpose register reg3. If the data is divided by 0, overflow occurs, and the quotient is undefined. The data of general-purpose register reg1 is not affected. Remark (1) The remainder is not stored. Overflow occurs when the maximum negative value (80000000H) is divided by -1 (in which case the quotient is 80000000H) and when data is divided by 0 (in which case the quotient is undefined). If an interrupt occurs while this instruction is executed, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. Do not specify r0 as the destination register reg2. The higher 16 bits of general-purpose register reg1 are ignored when division is executed. 64 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION (2) Overflow occurs when the maximum negative value (80000000H) is divided by -1 (in which case the quotient is 80000000H) and when data is divided by 0 (in which case the quotient is undefined). If an interrupt occurs while this instruction is executed, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. The higher 16 bits of general-purpose register reg1 are ignored when division is executed. If the address of reg2 is the same as the address of reg3, the remainder is stored in reg2 (= reg3). User's Manual U15943EJ2V0UM 65 CHAPTER 5 INSTRUCTION Divide halfword unsigned DIVHU Divide Halfword Unsigned Instruction format Operation DIVHU reg1, reg2, reg3 GR [reg2] GR [reg2] / GR [reg1] GR [reg3] GR [reg2] % GR [reg1] Format Opcode Format XI 15 rrrrr111111RRRRR 0 31 16 wwwww01010000010 Flag CY OV S Z SAT - 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Divides the word data of general-purpose register reg2 by the lower halfword data of generalpurpose register reg1, and stores the quotient to general-purpose register reg2, and the remainder to general-purpose register reg3. If the data is divided by 0, overflow occurs, and the quotient is undefined. The data of general-purpose register reg1 is not affected. Remark Overflow occurs when data is divided by 0 (in which case the quotient is undefined). If an interrupt occurs while this instruction is executed, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. If the address of reg2 is the same as the address of reg3, the remainder is stored in reg2 (= reg3). 66 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Divide word unsigned DIVU Divide Word Unsigned Instruction format Operation DIVU reg1, reg2, reg3 GR [reg2] GR [reg2] / GR [reg1] GR [reg3] GR [reg2] % GR [reg1] Format Opcode Format XI 15 rrrrr111111RRRRR 0 31 16 wwwww01011000010 Flag CY OV S Z SAT - 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Divides the word data of general-purpose register reg2 by the word data of general-purpose register reg1, and stores the quotient to general-purpose register reg2, and the remainder to general-purpose register reg3. If the data is divided by 0, overflow occurs, and the quotient is undefined. The data of general-purpose register reg1 is not affected. Remark Overflow occurs when data is divided by 0 (in which case the quotient is undefined). If an interrupt occurs while this instruction is executed, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. If the address of reg2 is the same as the address of reg3, the remainder is stored in reg2 (= reg3). User's Manual U15943EJ2V0UM 67 CHAPTER 5 INSTRUCTION Enable interrupt EI Enable Interrupt Instruction format Operation Format Opcode EI PSW.ID 0 (enables maskable interrupt) Format X 15 1000011111100000 0 31 16 0000000101100000 Flag CY OV S Z SAT ID - - - - - 0 Explanation Clears the ID flag of the PSW to 0 and enables the acknowledgement of maskable interrupts beginning at the next instruction. Remark Interrupts are not sampled during instruction execution. 68 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Halt HALT Halt Instruction format Operation Format Opcode HALT Halts Format X 15 0000011111100000 0 31 16 0000000100100000 Flag CY OV S Z SAT - - - - - Explanation Remark Stops the operating clock of the CPU and places the CPU in the HALT mode. The HALT mode is exited by any of the following three events: * Reset input * Non-maskable interrupt request (NMI input) * Unmasked maskable interrupt request (when ID of PSW = 0) If an interrupt is acknowledged during the HALT mode, the address of the following instruction is stored in EIPC or FEPC. User's Manual U15943EJ2V0UM 69 CHAPTER 5 INSTRUCTION Halfword swap word HSW Halfword Swap Word Instruction format Operation Format Opcode HSW reg2, reg3 GR [reg3] GR [reg2] (15:0) || GR [reg2] (31:16) Format XII 15 rrrrr11111100000 0 31 16 wwwww01101000100 Flag CY OV S Z SAT 1 if one or more halfwords in result word is 0; otherwise 0. 0 1 if the MSB of the word data of the operation result is 1; otherwise, 0. 1 if the word data of the operation result is 0; otherwise, 0. - Explanation Endian translation. 70 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Jump and register link JARL Jump and Register Link Instruction format Operation JARL disp22, reg2 GR [reg2] PC + 4 PC PC + sign-extend (disp22) Format Opcode Format V 15 rrrrr11110dddddd 0 31 16 ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. Flag CY OV S Z SAT Explanation - - - - - Saves the current PC value plus 4 to general-purpose register reg2, adds the current PC value and 22-bit displacement, sign-extended to word length, and transfers control to that PC. Bit 0 of the 22-bit displacement is masked to 0. Remark The current PC value used for calculation is the address of the first byte of this instruction. If the displacement value is 0, the branch destination is this instruction itself. This instruction is equivalent to a call subroutine instruction, and saves the restore PC address to general-purpose register reg2. The JMP instruction, which is equivalent to a subroutinereturn instruction, can be used to specify as reg1 the general-purpose register containing the return address saved during the JARL subroutine-call instruction, to restore the program counter. User's Manual U15943EJ2V0UM 71 CHAPTER 5 INSTRUCTION Jump register JMP Jump Register Instruction format Operation Format Opcode JMP [reg1] PC GR [reg1] Format I 15 00000000011RRRRR 0 Flag CY OV S Z SAT - - - - - Bit 0 of the Explanation Transfers control to the address specified by general-purpose register reg1. address is masked to 0. Remark When using this instruction as the subroutine-return instruction, specify the general-purpose register containing the return address saved during the JARL subroutine-call instruction, to restore the program counter. When using the JARL instruction, which is equivalent to the subroutine-call instruction, store the PC return address in general-purpose register reg2. 72 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Jump relative JR Jump Relative Instruction format Operation Format Opcode JR disp22 PC PC + sign-extend (disp22) Format V 15 0000011110dddddd 0 31 16 ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. Flag CY OV S Z SAT Explanation - - - - - Adds the 22-bit displacement, sign-extended to word length, to the current PC value and stores the value in the PC, and then transfers control to that PC. displacement is masked to 0. Bit 0 of the 22-bit Remark The current PC value used for the calculation is the address of the first byte of this instruction itself. Therefore, if the displacement value is 0, the jump destination is this instruction. User's Manual U15943EJ2V0UM 73 CHAPTER 5 INSTRUCTION Load byte LD.B Load Instruction format Operation LD.B disp16 [reg1], reg2 adr GR [reg1] + sign-extend (disp16) GR [reg2] sign-extend (Load-memory (adr, Byte)) Format Opcode Format VII 15 0 31 16 rrrrr111000RRRRR Flag CY OV S Z SAT Explanation - - - - - dddddddddddddddd Adds the data of general-purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. Byte data is read from the generated address, signextended to word length, and stored in general-purpose register reg2. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). 74 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Load byte unsigned LD.BU Load Instruction format Operation LD.BU disp16 [reg1], reg2 adr GR [reg1] + sign-extend (disp16) GR [reg2] zero-extend (Load-memory (adr, Byte)) Format Opcode Format VII 15 0 31 16 rrrrr11110bRRRRR ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. b is the bit 0 of disp16. Flag CY OV S Z SAT Explanation - - - - - Adds the data of general-purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. Byte data is read from the generated address, zeroextended to word length, and stored in general-purpose register reg2. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). User's Manual U15943EJ2V0UM 75 CHAPTER 5 INSTRUCTION Load halfword LD.H Load Instruction format Operation LD.H disp16 [reg1], reg2 adr GR [reg1] + sign-extend (disp16) GR [reg2] sign-extend (Load-memory (adr, Halfword)) Format Opcode Format VII 15 0 31 16 rrrrr111001RRRRR ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. Flag CY OV S Z SAT Explanation - - - - - Adds the data of general-purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. Halfword data is read from the generated address, sign-extended to word length, and stored in general-purpose register reg2. Caution Remark For notes on misaligned access occurrence, see 3.3 Data Alignment. If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). 76 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Load halfword unsigned LD.HU Load Instruction format Operation LD.HU disp16 [reg1], reg2 adr GR [reg1] + sign-extend (disp16) GR [reg2] zero-extend (Load-memory (adr, Halfword)) Format Opcode Format VII 15 0 31 16 rrrrr111111RRRRR ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. Flag CY OV S Z SAT Explanation - - - - - Adds the data of general-purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. Halfword data is read from the generated address, zero-extended to word length, and stored in general-purpose register reg2. Caution Remark For notes on misaligned access occurrence, see 3.3 Data Alignment. If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). User's Manual U15943EJ2V0UM 77 CHAPTER 5 INSTRUCTION Load word LD.W Load Instruction format Operation LD.W disp16 [reg1], reg2 adr GR [reg1] + sign-extend (disp16) GR [reg2] Load-memory (adr, Word) Format Opcode Format VII 15 0 31 16 rrrrr111001RRRRR ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. Flag CY OV S Z SAT Explanation - - - - - Adds the data of general-purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. Word data is read from the generated address. Caution Remark For notes on misaligned access occurrence, see 3.3 Data Alignment. If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). 78 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Load to system register LDSR Load to System Register Instruction format Operation Format Opcode LDSR reg2, regID SR [regID] GR [reg2] Format IX 15 rrrrr111111RRRRR Caution 0 31 16 0000000000100000 The source register in this instruction is represented by reg2 for convenience of describing its mnemonic . In the opcode, however, the reg1 field is used for the source register. Unlike other instructions therefore, the register specified in the mnemonic description has a different meaning in the opcode. rrrrr: regID specification RRRRR: reg2 specification Flag CY OV S Z SAT - (See Remark below.) - (See Remark below.) - (See Remark below.) - (See Remark below.) - (See Remark below.) Explanation Loads the word data of general-purpose register reg2 to a system register specified by the system register number (regID). The data of general-purpose register reg2 is not affected. Remark If the system register number (regID) is equal to 5 (PSW register), the values of the corresponding bits of the PSW are set according to the contents of reg2. Also, interrupts are not sampled when the PSW is being written with a new value. If the ID flag is enabled with this instruction, interrupt disabling begins at the start of execution, even though the ID flag does not become valid until the beginning of the next instruction. Caution The system register number regID is a number which identifies a system register. Accessing system registers which are reserved or write-prohibited is prohibited and will lead to undefined results. User's Manual U15943EJ2V0UM 79 CHAPTER 5 INSTRUCTION Move register/immediate (5-bit)/immediate (32-bit) MOV Move Instruction format (1) MOV reg1, reg2 (2) MOV imm5, reg2 (3) MOV imm32, reg1 Operation (1) GR [reg2] GR [reg1] (2) GR [reg2] sign-extend (imm5) (3) GR [reg1] imm32 Format (1) Format I (2) Format II (3) Format VI Opcode (1) 15 0 rrrrr000000RRRRR 15 0 (2) rrrrr010000iiiii 15 0 31 16 47 32 (3) 00000110001RRRRR iiiiiiiiiiiiiiii IIIIIIIIIIIIIIII i (bits 31 to 16) refers to the lower 16 bits of 32-bit immediate data. I (bits 47 to 32) refers to the higher 16 bits of 32-bit immediate data. Flag CY OV S Z SAT Explanation - - - - - (1) Transfers the word data of general-purpose register reg1 to general-purpose register reg2. The data of general-purpose register reg1 is not affected. (2) Transfers the value of a 5-bit immediate data, sign-extended to word length, to generalpurpose register reg2. Do not specify r0 as the destination register reg2. (3) Transfers the value of a 32-bit immediate data to general-purpose register reg1. 80 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Move effective address MOVEA Move Effective Address Instruction format Operation Format Opcode MOVEA imm16, reg1, reg2 GR [reg2] GR [reg1] + sign-extend (imm16) Format VI 15 rrrrr110001RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT - - - - - Explanation Adds the 16-bit immediate data, sign-extended to word length, to the word data of generalpurpose register reg1, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. The flags are not affected by the addition. Do not specify r0 as the destination register reg2. Remark This instruction calculates a 32-bit address and stores the result without affecting the PSW flags. User's Manual U15943EJ2V0UM 81 CHAPTER 5 INSTRUCTION Move high halfword MOVHI Move High Halfword Instruction format Operation Format Opcode MOVHI imm16, reg1, reg2 GR [reg2] GR [reg1] + (imm16 II 016) Format VI 15 rrrrr110010RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT - - - - - Explanation Adds a word data, whose higher 16 bits are specified by the 16-bit immediate data and lower 16 bits are 0, to the word data of general-purpose register reg1 and stores the result in general-purpose register reg2. The data of general-purpose register reg1 is not affected. The flags are not affected by the addition. Do not specify r0 as the destination register reg2. Remark This instruction is used to generate the higher 16 bits of a 32-bit address. 82 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Multiply word by register/immediate (9-bit) MUL Multiply Word Instruction format (1) MUL reg1, reg2, reg3 (2) MUL imm9, reg2, reg3 Operation (1) GR [reg3] || GR [reg2] GR [reg2] x GR [reg1] (2) GR [reg3] || GR [reg2] GR [reg2] x sign-extend (imm9) Format (1) Format XI (2) Format XII Opcode (1) 15 rrrrr111111RRRRR 15 (2) rrrrr111111iiiii 0 31 16 wwwww01000100000 0 31 16 wwwww01001IIII00 iiiii is the lower 5 bits of 9-bit immediate data. IIII is the higher 4 bits of 9-bit immediate data. Flag CY OV S Z SAT Explanation - - - - - (1) Multiplies the word data of general-purpose register reg2 by the word data of generalpurpose register reg1, and stores the higher 32 bits of the result (64-bit data) in generalpurpose register reg3 and the lower 32 bits in general-purpose register reg2. The data of general-purpose register reg1 is not affected. (2) Multiplies the word data of general-purpose register reg2 by a 9-bit immediate data, signextended to word length, and stores the higher 32 bits of the result (64-bit data) in general-purpose register reg3 and the lower 32 bits in general-purpose register reg2. Remark If the address of reg2 is the same as the address of reg3, the higher 32 bits of the result are stored in reg2 (= reg3). Caution Do not specify the same register for general-purpose register reg1 and general-purpose register reg3. User's Manual U15943EJ2V0UM 83 CHAPTER 5 INSTRUCTION Multiply halfword by register/immediate (5-bit) MULH Multiply Halfword Instruction format (1) MULH reg1, reg2 (2) MULH imm5, reg2 Operation (1) GR [reg2] (32) GR [reg2] (16) x GR [reg1] (16) (2) GR [reg2] GR [reg2] x sign-extend (imm5) Format (1) Format I (2) Format II Opcode (1) 15 0 rrrrr000111RRRRR 15 0 (2) rrrrr010111iiiii Flag CY OV S Z SAT - - - - - Explanation (1) Multiplies the lower halfword data of general-purpose register reg2 by the halfword data of general-purpose register reg1, and stores the result to general-purpose register reg2 as word data. The data of general-purpose register reg1 is not affected. Do not specify r0 as the destination register reg2. (2) Multiplies the lower halfword data of general-purpose register reg2 by a 5-bit immediate data, sign-extended to halfword length, and stores the result to general-purpose register reg2. Do not specify r0 as the destination register reg2. Remark The higher 16 bits of general-purpose registers reg1 and reg2 are ignored in this operation. 84 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Multiply halfword by immediate (16-bit) MULHI Multiply Halfword Immediate Instruction format Operation Format Opcode MULHI imm16, reg1, reg2 GR [reg2] GR [reg1] x imm16 Format VI 15 rrrrr110111RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT - - - - - Explanation Multiplies the lower halfword data of general-purpose register reg1 by the 16-bit immediate data, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. Do not specify r0 as the destination register reg2. Remark The higher 16 bits of general-purpose register reg1 are ignored in this operation. User's Manual U15943EJ2V0UM 85 CHAPTER 5 INSTRUCTION Multiply word by register/immediate (9-bit) MULU Multiply Word Unsigned Instruction format (1) MULU reg1, reg2, reg3 (2) MULU imm9, reg2, reg3 Operation (1) GR [reg3] || GR [reg2] GR [reg2] x GR [reg1] (2) GR [reg3] || GR [reg2] GR [reg2] x zero-extend (imm9) Format (1) Format XI (2) Format XII Opcode (1) 15 rrrrr111111RRRRR 15 (2) rrrrr111111iiiii 0 31 16 wwwww01000100010 0 31 16 wwwww01001IIII10 iiiii is the lower 5 bits of 9-bit immediate data. IIII is the higher 4 bits of 9-bit immediate data. Flag CY OV S Z SAT Explanation - - - - - (1) Multiplies the word data of general-purpose register reg2 by the word data of generalpurpose register reg1, and stores the higher 32 bits of the result (64-bit data) in generalpurpose register reg3 and the lower 32 bits in general-purpose register reg2. The data of general-purpose register reg1 is not affected. (2) Multiplies the word data of general-purpose register reg2 by a 9-bit immediate data, zeroextended to word length, and stores the higher 32 bits of the result (64-bit data) in general-purpose register reg3 and the lower 32 bits in general-purpose register reg2. Remark If the address of reg2 is the same as the address of reg3, the higher 32 bits of the result are stored in reg2 (= reg3). Caution Do not specify the same register for general-purpose register reg1 and general-purpose register reg3. 86 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION No operation NOP No Operation Instruction format Operation Format Opcode NOP Executes nothing and consumes at least one clock. Format I 15 0000000000000000 0 Flag CY OV S Z SAT - - - - - Explanation Remark Executes nothing and consumes at least one clock cycle. The contents of the PC are incremented by two. The opcode is the same as that of MOV r0, r0. User's Manual U15943EJ2V0UM 87 CHAPTER 5 INSTRUCTION NOT NOT Not Instruction format Operation Format Opcode NOT reg1, reg2 GR [reg2] NOT (GR [reg1]) Format I 15 rrrrr000001RRRRR 0 Flag CY OV S Z SAT - 0 1 if the MSB of the word data of the operation result is 1; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Logically negates (takes the 1's complement of) the word data of general-purpose register reg1, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. 88 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION NOT bit NOT1 Not Bit Instruction format (1) NOT1 bit#3, disp16 [reg1] (2) NOT1 reg2, [reg1] Operation (1) adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, Z flag) (2) adr GR [reg1] Z flag Not (Load-memory-bit (adr, reg2)) Store-memory-bit (adr, reg2, Z flag) Format (1) Format VIII (2) Format IX Opcode (1) 15 01bbb111110RRRRR 15 (2) rrrrr111111RRRRR - - - 0 31 16 dddddddddddddddd 0 31 16 0000000011100010 Flag CY OV S Z SAT 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 - Explanation (1) Adds the data of general-purpose register reg1 to a 16-bit displacement, sign-extended to word length to generate a 32-bit address. Reads the byte data referenced by the generated address, inverts the bit specified by the 3-bit bit number (0 1 or 1 0), and rewrites the original address. (2) Reads the data of general-purpose register reg1 to generate a 32-bit address. Reads the byte data referenced by the generated address, inverts the bit specified by the data of lower 3 bits of reg2 (0 1 or 1 0), and rewrites the original address. Remark The Z flag of the PSW indicates whether the specified bit was 0 or 1 before this instruction is executed, and does not indicate the content of the specified bit after this instruction has been executed. User's Manual U15943EJ2V0UM 89 CHAPTER 5 INSTRUCTION OR OR Or Instruction format Operation Format Opcode OR reg1, reg2 GR [reg2] GR [reg2] OR GR [reg1] Format I 15 rrrrr001000RRRRR 0 Flag CY OV S Z SAT - 0 1 if the MSB of the word data of the operation result is 1; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation ORs the word data of general-purpose register reg2 with the word data of general-purpose register reg1, and stores the result to general-purpose register reg2. The data of generalpurpose register reg1 is not affected. 90 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION OR immediate (16-bit) ORI Or Immediate Instruction format Operation Format Opcode ORI imm16, reg1, reg2 GR [reg2] GR [reg1] OR zero-extend (imm16) Format VI 15 rrrrr110100RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT - 0 1 if the MSB of the word data of the operation result is 1; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation ORs the word data of general-purpose register reg1 with the value of the 16-bit immediate data, zero-extended to word length, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. User's Manual U15943EJ2V0UM 91 CHAPTER 5 INSTRUCTION Function prepare PREPARE Function Prepare Instruction format (1) PREPARE list12, imm5 (2) PREPARE list12, imm5, sp/imm Note Note sp/imm is specified by sub-opcode bits 20 and 19. Operation (1) Store-memory (sp - 4, GR [reg in list12], Word) sp sp - 4 repeat 1 step above until all regs in list12 is stored sp sp - zero-extend (imm5) (2) Store-memory (sp - 4, GR [reg in list12], Word) sp sp - 4 repeat 1 step above until all regs in list12 is stored sp sp - zero-extend (imm5) ep sp/imm Format Opcode Format XIII 15 (1) 0000011110iiiiiL 15 (2) 0 0 31 16 LLLLLLLLLLL00001 31 16 Optional(47 to 32 or 63 to 32) imm16 / imm32 0000011110iiiiiL LLLLLLLLLLLff011 In the case of 32-bit immediate data (imm32), bits 47 to 32 are the lower 16 bits of imm32, bits 63 to 48 are the higher 16 bits of imm32. ff = 00: load sp to ep ff = 01: load 16-bit immediate data (bits 47 to 32), sign-extended, to ep ff = 10: load 16-bit immediate data (bits 47 to 32), logically shifted left by 16, to ep ff = 11: load 32-bit immediate data (bits 63 to 32) to ep In addition, LLLLLLLLLLLL indicates the value of corresponding bit in the register list (list12) (for example, "L" of the bit 21 in the opcode indicates the value of bit 21 of the list12). The list12 is a 32-bit register list defined as follows. 31 30 29 28 27 26 25 24 23 22 21 20 ... 1 0 r30 r24 r25 r26 r27 r20 r21 r22 r23 r28 r29 r31 - General-purpose registers (r20 to r31) correspond to the bits 31 to 21 and 0, and the register corresponding to the bit being set (to 1) is specified as the target of manipulation. Any values can be set to bits 20 to 1 since these bits are not corresponding to registers. 92 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Flag CY OV S Z SAT - - - - - Explanation (1) Push (subtract 4 from sp and store the data to that address) general-purpose registers listed in list12. Then subtract the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, from sp. (2) Push (subtract 4 from sp and store the data to that address) general-purpose registers listed in list12. Then subtract the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, from sp. Next, load the data specified by 3rd operand (sp/imm) to ep. Remark General-purpose registers in list12 is stored on the upward direction. (r20, r21, ... r31) The 5-bit immediate imm5 is used to make a stack frame for auto variables and temporary data. The lower 2 bits of the address specified by sp are always masked to 0 even if misaligned access is enabled. If an interrupt occurs before updating the sp, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction (sp and ep will retain their original values prior to the start of execution). Caution If an interrupt is generated during instruction execution, due to manipulation of the stack, the execution of that instruction may stop after the read/write cycle and register value rewriting are complete. User's Manual U15943EJ2V0UM 93 CHAPTER 5 INSTRUCTION Return from trap or interrupt RETI Return from Trap or Interrupt Instruction format Operation RETI if PSW.EP = 1 then PC EIPC PSW EIPSW else if PSW.NP = 1 then PC else PC FEPC PSW FEPSW EIPC PSW EIPSW Format Opcode Format X 15 0000011111100000 0 31 16 0000000101000000 Flag CY OV S Z SAT Value read from FEPSW or EIPSW is restored. Value read from FEPSW or EIPSW is restored. Value read from FEPSW or EIPSW is restored. Value read from FEPSW or EIPSW is restored. Value read from FEPSW or EIPSW is restored. Explanation This instruction reads the restore PC and PSW from the appropriate system register, and operation returns from a software exception or interrupt routine. instruction are as follows: (1) If the EP flag of the PSW is 1, the restore PC and PSW are read from the EIPC and EIPSW, regardless of the status of the NP flag of the PSW. If the EP flag of the PSW is 0 and the NP flag of the PSW is 1, the restore PC and PSW are read from the FEPC and FEPSW. If the EP flag of the PSW is 0 and the NP flag of the PSW is 0, the restore PC and PSW are read from the EIPC and EIPSW. (2) Once the restore PC and PSW values are set to the PC and PSW, the operation returns to the address immediately before the trap or interrupt occurred. The operations of this 94 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Caution When returning from a non-maskable interrupt or software exception routine using the RETI instruction, the NP and EP flags of PSW must be set accordingly to restore the PC and PSW: * When returning from non-maskable interrupt routine using the RETI instruction: NP = 1 and EP = 0 * When returning from a software exception routine using the RETI instruction: EP = 1 Use the LDSR instruction for setting the flags. Interrupts are not accepted in the latter half of the ID stage during LDSR execution because of the operation of the interrupt controller. User's Manual U15943EJ2V0UM 95 CHAPTER 5 INSTRUCTION Shift arithmetic right by register/immediate (5-bit) SAR Shift Arithmetic Right Instruction format (1) SAR reg1, reg2 (2) SAR imm5, reg2 Operation (1) GR [reg2] GR [reg2] arithmetically shift right by GR [reg1] (2) GR [reg2] GR [reg2] arithmetically shift right by zero-extend Format (1) Format IX (2) Format II Opcode (1) 15 0 31 16 rrrrr111111RRRRR 15 0 0000000010100000 (2) Flag CY OV S Z SAT Explanation rrrrr010101iiiii 1 if the bit shifted out last is 1; otherwise, 0. However, if the number of shifts is 0, the result is 0. 0 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - (1) Arithmetically shifts the word data of general-purpose register reg2 to the right by `n' positions, where `n' is a value from 0 to +31, specified by the lower 5 bits of generalpurpose register reg1 (after the shift, the MSB prior to shift execution is copied and set as the new MSB value), and then writes the result to general-purpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. The data of general-purpose register reg1 is not affected. (2) Arithmetically shifts the word data of general-purpose register reg2 to the right by `n' positions, where `n' is a value from 0 to +31, specified by the 5-bit immediate data, zeroextended to word length (after the shift, the MSB prior to shift execution is copied and set as the new MSB value), and then writes the result to general-purpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. 96 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Shift and set flag condition SASF Shift and Set Flag Condition Instruction format Operation SASF cccc, reg2 if conditions are satisfied then GR [reg2] (GR [reg2] Logically shift left by 1) OR 00000001H else GR [reg2] (GR [reg2] Logically shift left by 1) OR 00000000H Format Opcode Format IX 15 rrrrr1111110cccc 0 31 16 0000001000000000 Flag CY OV S Z SAT - - - - - Explanation The general-purpose register reg2 is logically shifted left by 1, and its LSB is set to 1 if a condition specified by condition code "cccc" is satisfied; otherwise, the general-purpose register reg2 is logically shifted left by 1, and its LSB is set to 0. One of the codes shown in Table 5-5 Condition Codes should be specified as the condition code "cccc". Remark See SETF instruction. User's Manual U15943EJ2V0UM 97 CHAPTER 5 INSTRUCTION Saturated add register/immediate (5-bit) SATADD Saturated Add Instruction format (1) SATADD reg1, reg2 (2) SATADD imm5, reg2 Operation (1) GR [reg2] saturated (GR [reg2] + GR [reg1]) (2) GR [reg2] saturated (GR [reg2] + sign-extend (imm5)) Format (1) Format I (2) Format II Opcode (1) 15 0 rrrrr000110RRRRR 15 0 (2) Flag CY OV S Z SAT Explanation rrrrr010001iiiii 1 if a carry occurs from MSB; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. (1) Adds the word data of general-purpose register reg1 to the word data of general-purpose register reg2, and stores the result to general-purpose register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general-purpose register reg1 is not affected. Do not specify r0 as the destination register reg2. (2) Adds a 5-bit immediate data, sign-extended to word length, to the word data of generalpurpose register reg2, and stores the result to general-purpose register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. Do not specify r0 as the destination register reg2. Remark The SAT flag is a cumulative flag. Once the result of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operation is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To clear the SAT flag to 0, load data to the PSW by using the LDSR instruction. 98 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Saturated subtract SATSUB Saturated Subtract Instruction format Operation Format Opcode SATSUB reg1, reg2 GR [reg2] saturated (GR [reg2] - GR [reg1]) Format I 15 rrrrr000101RRRRR 0 Flag CY OV S Z SAT 1 if a borrow to MSB occurs; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. Explanation Subtracts the word data of general-purpose register reg1 from the word data of generalpurpose register reg2, and stores the result to general-purpose register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general-purpose register reg1 is not affected. Do not specify r0 as the destination register reg2. Remark The SAT flag is a cumulative flag. Once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operations is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To clear the SAT flag to 0, load data to the PSW by using the LDSR instruction. User's Manual U15943EJ2V0UM 99 CHAPTER 5 INSTRUCTION Saturated subtract immediate SATSUBI Saturated Subtract Immediate Instruction format Operation Format Opcode SATSUBI imm16, reg1, reg2 GR [reg2] saturated (GR [reg1] - sign-extend (imm16)) Format VI 15 rrrrr110011RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT 1 if a borrow to MSB occurs; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. Explanation Subtracts the 16-bit immediate data, sign-extended to word length, from the word data of general-purpose register reg1, and stores the result to general-purpose register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general-purpose register reg1 is not affected. Do not specify r0 as the destination register reg2. Remark The SAT flag is a cumulative flag. Once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operations is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To clear the SAT flag to 0, load data to the PSW by using the LDSR instruction. 100 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Saturated subtract reverse SATSUBR Saturated Subtract Reverse Instruction format Operation Format Opcode SATSUBR reg1, reg2 GR [reg2] saturated (GR [reg1] - GR [reg2]) Format I 15 rrrrr000100RRRRR 0 Flag CY OV S Z SAT 1 if a borrow to MSB occurs; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. Explanation Subtracts the word data of general-purpose register reg2 from the word data of generalpurpose register reg1, and stores the result to general-purpose register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general-purpose register reg1 is not affected. Do not specify r0 as the destination register reg2. Remark The SAT flag is a cumulative flag. Once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operations is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To clear the SAT flag to 0, load data to the PSW by using the LDSR instruction. User's Manual U15943EJ2V0UM 101 CHAPTER 5 INSTRUCTION Set bit SET1 Set Bit Instruction format (1) SET1 bit#3, disp16 [reg1] (2) SET1 reg2, [reg1] Operation (1) adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 1) (2) adr GR [reg1] Z flag Not (Load-memory-bit (adr, reg2)) Store-memory-bit (adr, reg2, 1) Format (1) Format VIII (2) Format IX Opcode (1) 15 00bbb111110RRRRR 15 (2) rrrrr111111RRRRR - - - 0 31 16 dddddddddddddddd 0 31 16 0000000011100000 Flag CY OV S Z SAT 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 - Explanation (1) Adds the 16-bit displacement, sign-extended to word length, to the data of generalpurpose register reg1 to generate a 32-bit address. Reads the byte data referenced by the generated address, sets the bit specified by the 3-bit bit number (to 1), and rewrites the original address. (2) Reads the data of general-purpose register reg1 to generate a 32-bit address. Reads the byte data referenced by the generated address, sets the bit specified by the 3-bit bit number (to 1), and rewrites the original address. Remark The Z flag of the PSW indicates whether the specified bit was 0 or 1 before this instruction is executed, and does not indicate the content of the specified bit after this instruction has been executed. 102 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Set flag condition SETF Set Flag Condition Instruction format Operation SETF cccc, reg2 if conditions are satisfied then GR [reg2] 00000001H else GR [reg2] 00000000H Format Opcode Format IX 15 rrrrr1111110cccc 0 31 16 0000000000000000 Flag CY OV S Z SAT - - - - - Explanation The general-purpose register reg2 is set to 1 if a condition specified by condition code "cccc" is satisfied; otherwise, 0 are stored in the register. One of the codes shown in Table 5-5 Condition Codes should be specified as the condition code "cccc". Remark Here are some examples of using this instruction: (1) Translation of two or more condition clauses If A of statement if (A) in C language consists of two or more condition clauses (a1, a2, a3, and so on), it is usually translated to a sequence of if (a1) then, if (a2) then. The object code executes "conditional branch" by checking the result of evaluation equivalent to an. Since a pipeline processor takes more time to execute "condition judgment" + "branch" than to execute an ordinary operation, the result of evaluating each condition clause if (an) is stored in register Ra. By performing a logical operation to Ran after all the condition clauses have been evaluated, the delay due to the pipeline can be prevented. (2) Double-length operation To execute a double-length operation such as Add with Carry, the result of the CY flag can be stored in general-purpose register reg2. Therefore, a carry from the lower bits can be expressed as a numeric value. User's Manual U15943EJ2V0UM 103 CHAPTER 5 INSTRUCTION Table 5-5. Condition Codes Condition Code (cccc) 0000 1000 0001 1001 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 V NV C/L NC/NL Z NZ NH H S/N NS/P T SA LT GE LE GT Condition Name Condition Expression OV = 1 OV = 0 CY = 1 CY = 0 Z=1 Z=0 (CY or Z) = 1 (CY or Z) = 0 S=1 S=0 always (unconditional) SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0 104 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Shift logical left by register/immediate (5-bit) SHL Shift Logical Left Instruction format (1) SHL reg1, reg2 (2) SHL imm5, reg2 Operation (1) GR [reg2] GR [reg2] logically shift left by GR [reg1] (2) GR [reg2] GR [reg2] logically shift left by zero-extend (imm5) Format (1) Format IX (2) Format II Opcode (1) 15 0 31 16 rrrrr111111RRRRR 15 0 0000000011000000 (2) Flag CY OV S Z SAT Explanation rrrrr010110iiiii 1 if the bit shifted out last is 1; otherwise, 0. However, if the number of shifts is 0, the result is 0. 0 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - (1) Logically shifts the word data of general-purpose register reg2 to the left by `n' positions, where `n' is a value from 0 to +31, specified by the lower 5 bits of general-purpose register reg1 (0 is shifted to the LSB side), and then writes the result to general-purpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. The data of general-purpose register reg1 is not affected. (2) Logically shifts the word data of general-purpose register reg2 to the left by `n' positions, where `n' is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (0 is shifted to the LSB side), and then writes the result to general-purpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the value prior to instruction execution. User's Manual U15943EJ2V0UM 105 CHAPTER 5 INSTRUCTION Shift logical right by register/immediate (5-bit) SHR Shift Logical Right Instruction format (1) SHR reg1, reg2 (2) SHR imm5, reg2 Operation (1) GR [reg2] GR [reg2] logically shift right by GR [reg1] (2) GR [reg2] GR [reg2] logically shift right by zero-extend (imm5) Format (1) Format IX (2) Format II Opcode (1) 15 0 31 16 rrrrr111111RRRRR 15 0 0000000010000000 (2) Flag CY OV S Z SAT Explanation rrrrr010100iiiii 1 if the bit shifted out last is 1; otherwise, 0. However, if the number of shifts is 0, the result is 0. 0 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - (1) Logically shifts the word data of general-purpose register reg2 to the right by `n' positions where `n' is a value from 0 to +31, specified by the lower 5 bits of general-purpose register reg1 (0 is shifted to the MSB side). This instruction then writes the result to generalpurpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. The data of general-purpose register reg1 is not affected. (2) Logically shifts the word data of general-purpose register reg2 to the right by `n' positions, where `n' is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (0 is shifted to the MSB side). This instruction then writes the result to general-purpose register reg2. If the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. 106 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Short format load byte SLD.B Load Instruction format Operation SLD.B disp7 [ep], reg2 adr ep + zero-extend (disp7) GR [reg2] sign-extend (Load-memory (adr, Byte)) Format Opcode Format IV 15 0 rrrrr0110ddddddd Flag CY OV S Z SAT Explanation - - - - - Adds the 7-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Byte data is read from the generated address, sign-extended to word length, and stored in reg2. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). Caution If an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. In this case, the instruction is re-executed after returning from the interrupt. Therefore, except in cases when clearly no interrupt is generated, the LD instruction should be used for accessing I/O, FIFO types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the LD or store instruction is being executed). User's Manual U15943EJ2V0UM 107 CHAPTER 5 INSTRUCTION Short format load byte unsigned SLD.BU Load Instruction format Operation SLD.BU disp4 [ep], reg2 adr ep + zero-extend (disp4) GR [reg2] zero-extend (Load-memory (adr, Byte)) Format Opcode Format IV 15 0 rrrrr0000110dddd rrrrr must not be 00000. Flag CY OV S Z SAT Explanation - - - - - Adds the 4-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Byte data is read from the generated address, zero-extended to word length, and stored in reg2. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). Caution If an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. In this case, the instruction is re-executed after returning from the interrupt. Therefore, except in cases when clearly no interrupt is generated, the LD instruction should be used for accessing I/O, FIFO types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the LD or store instruction is being executed). 108 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Short format load halfword SLD.H Load Instruction format Operation SLD.H disp8 [ep], reg2 adr ep + zero-extend (disp8) GR [reg2] sign-extend (Load-memory (adr, Halfword)) Format Opcode Format IV 15 rrrrr1000ddddddd ddddddd is the higher 7 bits of disp8. 0 Flag CY OV S Z SAT - - - - - Explanation Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Halfword data is read from the generated address, sign-extended to word length, and stored in reg2. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). Caution For notes on misaligned access occurrence, see 3.3 Data Alignment. Also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. In this case, the instruction is re-executed after returning from the interrupt. Therefore, except in cases when clearly no interrupt is generated, the LD instruction should be used for accessing I/O, FIFO types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the LD or store instruction is being executed). User's Manual U15943EJ2V0UM 109 CHAPTER 5 INSTRUCTION Short format load halfword unsigned SLD.HU Load Instruction format Operation SLD.HU disp5 [ep], reg2 adr ep + zero-extend (disp5) GR [reg2] zero-extend (Load-memory (adr, Halfword)) Format Opcode Format IV 15 rrrrr0000111dddd dddd is the higher 4 bits of disp5. rrrrr must not be 00000. 0 Flag CY OV S Z SAT - - - - - Explanation Adds the 5-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Halfword data is read from the generated address, zero-extended to word length, and stored in reg2. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). Caution For notes on misaligned access occurrence, see 3.3 Data Alignment. Also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. In this case, the instruction is re-executed after returning from the interrupt. Therefore, except in cases when clearly no interrupt is generated, the LD instruction should be used for accessing I/O, FIFO types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the LD or store instruction is being executed). 110 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Short format load word SLD.W Load Instruction format Operation SLD.W disp8 [ep], reg2 adr ep + zero-extend (disp8) GR [reg2] Load-memory (adr, Word) Format Opcode Format IV 15 0 rrrrr1010dddddd0 dddddd is the higher 6 bits of disp8. Flag CY OV S Z SAT Explanation - - - - - Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Word data is read from the generated address, and stored in reg2. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). Caution For notes on misaligned access occurrence, see 3.3 Data Alignment. Also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. In this case, the instruction is re-executed after returning from the interrupt. Therefore, except in cases when clearly no interrupt is generated, the LD instruction should be used for accessing I/O, FIFO types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the LD or store instruction is being executed). User's Manual U15943EJ2V0UM 111 CHAPTER 5 INSTRUCTION Short format store byte SST.B Store Instruction format Operation SST.B reg2, disp7 [ep] adr ep + zero-extend (disp7) Store-memory (adr, GR [reg2], Byte) Format Opcode Format IV 15 0 rrrrr0111ddddddd Flag CY OV S Z SAT Explanation - - - - - Adds the 7-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 in the generated address. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). 112 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Short format store halfword SST.H Store Instruction format Operation SST.H reg2, disp8 [ep] adr ep + zero-extend (disp8) Store-memory (adr, GR [reg2], Halfword) Format Opcode Format IV 15 0 rrrrr1001ddddddd ddddddd is the higher 7 bits of disp8. Flag CY OV S Z SAT Explanation - - - - - Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the lower halfword data of reg2 in the generated address. Caution Remark For notes on misaligned access occurrence, see 3.3 Data Alignment. If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). User's Manual U15943EJ2V0UM 113 CHAPTER 5 INSTRUCTION Short format store word SST.W Store Instruction format Operation SST.W reg2, disp8 [ep] adr ep + zero-extend (disp8) Store-memory (adr, GR [reg2], Word) Format Opcode Format IV 15 0 rrrrr1010dddddd1 dddddd is the higher 6 bits of disp8. Flag CY OV S Z SAT Explanation - - - - - Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the word data of reg2 in the generated address. Caution Remark For notes on misaligned access occurrence, see 3.3 Data Alignment. If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). 114 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Store byte ST.B Store Instruction format Operation ST.B reg2, disp16 [reg1] adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Byte) Format Opcode Format VII 15 0 31 16 rrrrr111010RRRRR Flag CY OV S Z SAT Explanation - - - - - dddddddddddddddd Adds the 16-bit displacement, sign-extended to word length, to the data of general-purpose register reg1 to generate a 32-bit address, and stores the lowest byte data of general-purpose register reg2 to the generated address. Remark If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). User's Manual U15943EJ2V0UM 115 CHAPTER 5 INSTRUCTION Store halfword ST.H Store Instruction format Operation ST.H reg2, disp16 [reg1] adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Halfword) Format Opcode Format VII 15 rrrrr111011RRRRR 0 31 16 ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. Flag CY OV S Z SAT Explanation - - - - - Adds the 16-bit displacement, sign-extended to word length, to the data of general-purpose register reg1 to generate a 32-bit address, and stores the lower halfword data of generalpurpose register reg2 in the generated address. Caution Remark For notes on misaligned access occurrence, see 3.3 Data Alignment. If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). 116 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Store word ST.W Store Instruction format Operation ST.W reg2, disp16 [reg1] adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Word) Format Opcode Format VII 15 0 31 16 rrrrr111011RRRRR ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. Flag CY OV S Z SAT Explanation - - - - - Adds the 16-bit displacement, sign-extended to word length, to the data of general-purpose register reg1 to generate a 32-bit address, and stores the word data of general-purpose register reg2 in the generated address. Caution Remark For notes on misaligned access occurrence, see 3.3 Data Alignment. If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. Upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the start address of this instruction. Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral I/O, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). User's Manual U15943EJ2V0UM 117 CHAPTER 5 INSTRUCTION Store contents of system register STSR Store Contents of System Register Instruction format Operation Format Opcode STSR regID, reg2 GR [reg2] SR [regID] Format IX 15 rrrrr111111RRRRR 0 31 16 0000000001000000 Flag CY OV S Z SAT - - - - - Explanation Stores the contents of a system register specified by system register number (regID) to general-purpose register reg2. The contents of the system register are not affected. Caution The system register number regID is a number which identifies a system register. Accessing a system register which is reserved is prohibited and will lead to undefined results. 118 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Subtract SUB Subtract Instruction format Operation Format Opcode SUB reg1, reg2 GR [reg2] GR [reg2] - GR [reg1] Format I 15 rrrrr001101RRRRR 0 Flag CY OV S Z SAT 1 if a borrow to MSB occurs; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Subtracts the word data of general-purpose register reg1 from the word data of generalpurpose register reg2, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. User's Manual U15943EJ2V0UM 119 CHAPTER 5 INSTRUCTION Subtract reverse SUBR Subtract Reverse Instruction format Operation Format Opcode SUBR reg1, reg2 GR [reg2] GR [reg1] - GR [reg2] Format I 15 rrrrr001100RRRRR 0 Flag CY OV S Z SAT 1 if a borrow to MSB occurs; otherwise, 0. 1 if overflow occurs; otherwise, 0. 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Subtracts the word data of general-purpose register reg2 from the word data of generalpurpose register reg1, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. 120 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Jump with table look up SWITCH Jump with Table Look Up Instruction format Operation SWITCH reg1 adr (PC + 2) + (GR [reg1] logically shift left by 1) PC (PC + 2) + (sign-extend (Load-memory (adr, Halfword))) logically shift left by 1 Format Opcode Format I 15 00000000010RRRRR 0 Flag CY OV S Z SAT - - - - - Adds the table entry address (address following SWITCH instruction) and data of general-purpose register reg1 logically shifted left by 1, and generates 32-bit table entry address. Explanation <1> <2> <3> Loads halfword data pointed by address generated in <1>. Sign-extends the loaded halfword data to word length, and adds the table entry address after logically shifts it left by 1 bit (next address following SWITCH instruction) to generate a 32-bit target address. <4> Then jumps to the target address generated in <3>. User's Manual U15943EJ2V0UM 121 CHAPTER 5 INSTRUCTION Sign extend byte SXB Sign Extend Byte Instruction format Operation Format Opcode SXB reg1 GR [reg1] sign-extend (GR [reg1] (7:0)) Format I 15 00000000101RRRRR 0 Flag CY OV S Z SAT - - - - - Explanation Sign-extends the lowest byte of general-purpose register reg1 to word length. 122 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Sign extend halfword SXH Sign Extend Halfword Instruction format Operation Format Opcode SXH reg1 GR [reg1] sign-extend (GR [reg1] (15:0)) Format I 15 00000000111RRRRR 0 Flag CY OV S Z SAT - - - - - Explanation Sign-extends the lower halfword of general-purpose register reg1 to word length. User's Manual U15943EJ2V0UM 123 CHAPTER 5 INSTRUCTION Trap TRAP Trap Instruction format Operation TRAP vector EIPC PC + 4 (restore PC) EIPSW PSW ECR.EICC interrupt code PSW.EP 1 PSW.ID 1 PC 00000040H (vector = 00H to 0FH) 00000050H (vector = 10H to 1FH) Format Opcode Format X 15 00000111111iiiii 0 31 16 0000000100000000 Flag CY OV S Z SAT - - - - - Explanation Saves the restore PC and PSW to EIPC and EIPSW, respectively; sets the exception code (EICC of ECR) and the flags of the PSW (sets EP and ID flags to 1); jumps to the handler address corresponding to the trap vector (00H to 1FH) specified by vector, and starts exception processing. The flags of PSW other than EP and ID flags are not affected. The restore PC is the address of the instruction following the TRAP instruction. 124 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Test TST Test Instruction format Operation Format Opcode TST reg1, reg2 result GR [reg2] AND GR [reg1] Format I 15 rrrrr001011RRRRR 0 Flag CY OV S Z SAT - 0 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation ANDs the word data of general-purpose register reg2 with the word data of general-purpose register reg1. The result is not stored, and only the flags are changed. The data of generalpurpose registers reg1 and reg2 are not affected. User's Manual U15943EJ2V0UM 125 CHAPTER 5 INSTRUCTION Test bit TST1 Test Bit Instruction format (1) TST1 bit#3, disp16 [reg1] (2) TST1 reg2, [reg1] Operation (1) adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) (2) adr GR [reg1] Z flag Not (Load-memory-bit (adr, reg2)) Format (1) Format VIII (2) Format IX Opcode (1) 15 11bbb111110RRRRR 15 (2) rrrrr111111RRRRR - - - 0 31 16 dddddddddddddddd 0 31 16 0000000011100110 Flag CY OV S Z SAT 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 - Explanation (1) Adds the data of general-purpose register reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Performs the test on the bit, specified by the 3bit bit number, at the byte data location referenced by the generated address. If the specified bit is 0, the Z flag of PSW is set to 1; if the bit is 1, the Z flag is cleared to 0. The byte data, including the specified bit, is not affected. (2) Reads the data of general-purpose register reg1 to generate a 32-bit address. Performs the test on the bit, specified by the lower 3-bits of reg2, at the byte data location referenced by the generated address. If the specified bit is 0, the Z flag of PSW is set to 1; if the bit is 1, the Z flag is cleared to 0. The byte data, including the specified bit, is not affected. 126 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Exclusive OR XOR Exclusive Or Instruction format Operation Format Opcode XOR reg1, reg2 GR [reg2] GR [reg2] XOR GR [reg1] Format I 15 rrrrr001001RRRRR 0 Flag CY OV S Z SAT - 0 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Exclusively ORs the word data of general-purpose register reg2 with the word data of generalpurpose register reg1, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. User's Manual U15943EJ2V0UM 127 CHAPTER 5 INSTRUCTION Exclusive OR immediate (16-bit) XORI Exclusive Or Immediate Instruction format Operation Format Opcode XORI imm16, reg1, reg2 GR [reg2] GR [reg1] XOR zero-extend (imm16) Format VI 15 rrrrr110101RRRRR 0 31 16 iiiiiiiiiiiiiiii Flag CY OV S Z SAT - 0 1 if the operation result is negative; otherwise, 0. 1 if the operation result is 0; otherwise, 0. - Explanation Exclusively ORs the word data of general-purpose register reg1 with a 16-bit immediate data, zero-extended to word length, and stores the result to general-purpose register reg2. The data of general-purpose register reg1 is not affected. 128 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Zero extend byte ZXB Zero Extend Byte Instruction format Operation Format Opcode ZXB reg1 GR [reg1] zero-extend (GR [reg1] (7:0)) Format I 15 00000000100RRRRR 0 Flag CY OV S Z SAT - - - - - Explanation Zero-extends the lowest byte of general-purpose register reg1 to word length. User's Manual U15943EJ2V0UM 129 CHAPTER 5 INSTRUCTION Zero extend halfword ZXH Zero Extend Halfword Instruction format Operation Format Opcode ZXH reg1 GR [reg1] zero-extend (GR [reg1] (15:0)) Format I 15 00000000110RRRRR 0 Flag CY OV S Z SAT - - - - - Explanation Zero-extends the lower halfword of general-purpose register reg1 to word length. 130 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION 5.4 Number of Instruction Execution Clock Cycles A list of the number of instruction execution clocks when the internal ROM or internal RAM is used is shown below. The number of instruction execution clock cycles differ depending on the combination of instructions. For details, see CHAPTER 8 PIPELINE. Table 5-6. List of Number of Instruction Execution Clock Cycles (1/3) Type of Instruction Load instructions LD.B LD.H LD.W LD.BU LD.HU SLD.B SLD.BU SLD.H SLD.HU SLD.W Store instructions ST.B ST.H ST.W SST.B SST.H SST.W Multiply instructions MUL MUL MULH MULH MULHI MULU MULU Arithmetic operation instructions ADD ADD ADDI CMOV CMOV CMP CMP DIV DIVH DIVH DIVHU Mnemonic Operand Byte Number of Execution Clocks i disp16 [reg1] , reg2 disp16 [reg1] , reg2 disp16 [reg1] , reg2 disp16 [reg1] , reg2 disp16 [reg1] , reg2 disp7 [ep] , reg2 disp4 [ep] , reg2 disp8 [ep] , reg2 disp5 [ep] , reg2 disp8 [ep] , reg2 reg2, disp16 [reg1] reg2, disp16 [reg1] reg2, disp16 [reg1] reg2, disp7 [ep] reg2, disp8 [ep] reg2, disp8 [ep] reg1, reg2, reg3 imm9, reg2, reg3 reg1, reg2 imm5, reg2 imm16, reg1, reg2 reg1, reg2, reg3 imm9, reg2, reg3 reg1, reg2 imm5, reg2 imm16, reg1, reg2 cccc, reg1, reg2, reg3 cccc, imm5, reg2, reg3 reg1, reg2 imm5, reg2 reg1, reg2, reg3 reg1, reg2 reg1, reg2, reg3 reg1, reg2, reg3 4 4 4 4 4 2 2 2 2 2 4 4 4 2 2 2 4 4 2 2 4 4 4 2 2 4 4 4 2 2 4 2 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 35 35 35 34 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 1 1 1 4 4 1 1 1 1 1 1 1 35 35 35 34 r l Note 1 Note 1 Note 1 Note 1 Note 1 Note 2 Note 2 Note 2 Note 2 Note 2 1 1 1 1 1 1 5 5 2 2 2 5 5 1 1 1 1 1 1 1 35 35 35 34 User's Manual U15943EJ2V0UM 131 CHAPTER 5 INSTRUCTION Table 5-6. List of Number of Instruction Execution Clock Cycles (2/3) Type of Instruction Arithmetic operation instructions DIVU MOV MOV MOV MOVEA MOVHI SASF SETF SUB SUBR Saturated operation instructions SATADD SATADD SATSUB SATSUBI SATSUBR Logical operation instructions AND ANDI BSH BSW HSW NOT OR ORI SAR SAR SHL SHL SHR SHR SXB SXH TST XOR XORI ZXB ZXH Branch instructions Bcond Mnemonic Operand Byte Number of Execution Clocks i reg1, reg2, reg3 reg1, reg2 imm5, reg2 imm32, reg1 imm16, reg1, reg2 imm16, reg1, reg2 cccc, reg2 cccc, reg2 reg1, reg2 reg1, reg2 reg1, reg2 imm5, reg2 reg1, reg2 imm16, reg1, reg2 reg1, reg2 reg1, reg2 imm16, reg1, reg2 reg2, reg3 reg2, reg3 reg2, reg3 reg1, reg2 reg1, reg2 imm16, reg1, reg2 reg1, reg2 imm5, reg2 reg1, reg2 imm5, reg2 reg1, reg2 imm5, reg2 reg1 reg1 reg1, reg2 reg1, reg2 imm16, reg1, reg2 reg1 reg1 disp9 (When condition is satisfied) disp9 (When condition is not satisfied) 4 2 2 6 4 4 4 4 2 2 2 2 2 4 2 2 4 4 4 4 2 2 4 4 2 4 2 4 2 2 2 2 2 4 2 2 2 2 34 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 Note 3 r 34 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 Note 3 l 34 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2Note 3 1 132 User's Manual U15943EJ2V0UM CHAPTER 5 INSTRUCTION Table 5-6. List of Number of Instruction Execution Clock Cycles (3/3) Type of Instruction Branch instructions JARL JMP JR Bit manipulation instructions CLR1 CLR1 NOT1 NOT1 SET1 SET1 TST1 TST1 Special instructions CALLT CTRET DI DISPOSE DISPOSE EI HALT LDSR NOP PREPARE PREPARE PREPARE PREPARE RETI STSR SWITCH TRAP Debug function instructions DBRET DBTRAP Mnemonic Operand Byte Number of Execution Clocks i disp22, reg2 [reg1] disp22 bit#3, disp16 [reg1] reg2, [reg1] bit#3, disp16 [reg1] reg2, [reg1] bit#3, disp16 [reg1] reg2, [reg1] bit#3, disp16 [reg1] reg2, [reg1] imm6 - - imm5, list12 imm5, list12, [reg1] - - reg2, regID - list12, imm5 list12, imm5, sp list12, imm5, imm16 list12, imm5, imm32 - regID, reg2 reg1 vector - - 4 2 4 4 4 4 4 4 4 4 4 2 4 4 4 4 4 4 4 2 4 4 6 8 4 4 2 4 4 2 4 2 3 2 3 Note 4 r 2 3 2 3 Note 4 l 2 3 2 3Note 4 3Note 4 3Note 4 3Note 4 3Note 4 3Note 4 3Note 4 3Note 4 4 3 1 3Note 4 3Note 4 3 Note 4 3Note 4 3Note 4 3 Note 4 3Note 4 3Note 4 3Note 4 3Note 4 4 3 1 n+1 Note 5 3Note 4 3Note 4 3Note 4 3Note 4 4 3 1 n+1 Note 5 n+1Note 5 n+3Note 5 1 1 1 1 n+3Note 5 1 1 1 1 n+1 Note 5 n+3Note 5 1 1 1 1 n+1 Note 5 n+1Note 5 n+2Note 5 n+2Note 5 n+3Note 5 3 1 5 3 3 3 3 n+2Note 5 n+2 Note 5 n+2Note 5 n+2 Note 5 n+3Note 5 3 1 5 3 3 3 3 n+3Note 5 3 1 5 3 3 3 3 Undefined instruction code Notes 1. 2. 3. 4. 5. Depends on the number of wait states (2 if no wait states). Depends on the number of wait states (1 if no wait states). 3 if there is an instruction rewriting the PSW contents immediately before. In case of no wait states (3 + number of read access wait states). n is the total number of cycles to load registers in list12 (Depends on the number of wait states, n is the number of registers in list12 if no wait states. The operation when n = 0 is the same as when n = 1). User's Manual U15943EJ2V0UM 133 CHAPTER 5 INSTRUCTION Remarks 1. Operand convention Symbol reg1 reg2 Meaning General-purpose register (used as source register) General-purpose register (mainly used as destination register. Some are also used as source registers.) General-purpose register (mainly used as remainder of division results or higher 32 bits of multiply results) 3-bit data for bit number specification x-bit immediate data x-bit displacement data System register number 5-bit data for trap vector (00H to 1FH) specification 4-bit data condition code specification Stack pointer (r3) Element pointer (r30) List of registers (x is a maximum number of registers) reg3 bit#3 immx dispx regID vector cccc sp ep listx 2. Execution clock convention Symbol i r Meaning When other instruction is executed immediately after executing an instruction (issue) When the same instruction is repeatedly executed immediately after the instruction has been executed (repeat) When a subsequent instruction uses the result of execution of the preceding instruction immediately after its execution (latency) l 134 User's Manual U15943EJ2V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS Interrupts are events that occur independently of the program execution and are divided into two types: maskable interrupts and non-maskable interrupts (NMI). In contrast, exceptions are events whose occurrence is dependent on the program execution and are divided into three types: software exception, exception trap, and debug trap. When an interrupt or exception occurs, control is transferred to a handler whose address is determined by the source of the interrupt or exception. The source of the interrupt/exception is specified by the exception code that is stored in the exception cause register (ECR). Each handler analyzes the ECR register and performs appropriate interrupt servicing or exception processing. registers (EIPC, EIPSW or FEPC, FEPSW). To restore execution from interrupt or software exception processing, use the RETI instruction. the status saving register, and transfer control to the restore PC. Table 6-1. Interrupt/Exception Codes Interrupt/Exception Source Name Non-maskable interrupt (NMI) Note 1 The restore PC and restore PSW are written to the status saving To restore execution from exception trap or debug trap, use the DBRET instruction. Read the restore PC and restore PSW from Classification Trigger NMI0 input NMI1 input NMI2 inputNote 4 Interrupt Interrupt Interrupt Interrupt Exception Exception Exception Exception Code 0010H 0020H 0030H Note 5 004nH 005nH 0060H Handler Address 00000010H 00000020H 00000030H Note 6 00000040H 00000050H 00000060H Restore PC next PCNote 2 next PCNotes 2, 3 next PCNotes 2, 3 next PCNote 2 next PC next PC next PCNote 7 Maskable interrupt Software exception TRAP0n (n = 0 to FH) TRAP1n (n = 0 to FH) Exception trap (ILGOP) Note 5 TRAP instruction TRAP instruction Illegal instruction code DBTRAP instruction Debug trap Exception 0060H 00000060H next PC Notes 1. 2. The trigger of the non-maskable interrupt incorporated differs depending on the product. Except when an interrupt is acknowledged during execution of the one of the instructions listed below (if an interrupt is acknowledged during instruction execution, execution is stopped, and then resumed after the completion of interrupt servicing. In this case, the address of the stopped instruction is the restored PC.). * * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W), divide instructions (DIV, DIVH, DIVU, DIVHU) PREPARE, DISPOSE instruction (only if an interrupt is generated before the stack pointer is updated) 3. 4. 5. 6. 7. Remark The PC cannot be restored by the RETI instruction. Perform a system reset after interrupt servicing. Acknowledged even if the NP flag of PSW is set to 1. Differs depending on the type of the interrupts. Higher 16 bits are 0000H and lower 16 bits are the same value as the exception code. The execution address of the illegal instruction is obtained by "Restore PC - 4". Restore PC: PC value saved to the EIPC or FEPC when interrupt/exception processing is started next PC: PC value that starts processing after interrupt/exception processing User's Manual U15943EJ2V0UM 135 CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.1 Interrupt Servicing 6.1.1 Maskable interrupt The maskable interrupt can be masked by the interrupt control register of the interrupt controller (INTC). The INTC issues an interrupt request to the CPU, based on the acknowledged interrupt with the highest priority. If a maskable interrupt occurs due to interrupt request input (INT input), the CPU performs the following steps, and transfers control to the handler routine. (1) Saves restore PC to EIPC. (2) Saves current PSW to EIPSW. (3) Writes exception code to lower halfword of ECR (EICC). (4) Sets ID flag of PSW to 1 and clears EP flag to 0. (5) Sets handler address for each interrupt to PC and transfers control. The EIPC and EIPSW are used as the status saving registers. INT inputs are held pending in the interrupt controller (INTC) when one of the following two conditions occur: when the INT input is masked by its interrupt controller, or when an interrupt service routine is currently being executed (when the NP flag of the PSW is 1 or when the ID flag of the PSW is 1). Interrupts are enabled by clearing the mask condition or by setting the NP and ID flags of the PSW to 0 with the LDSR instruction, which will be enabling new maskable interrupt servicing by a pending INT input. The EIPC and EIPSW registers must be saved by program to enable nesting of interrupts because there is only one set of EIPC and EIPSW is provided. Maskable interrupt servicing format is shown below. 136 User's Manual U15943EJ2V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS Figure 6-1. Maskable Interrupt Servicing Format Interrupt request input (INT input) INTC processing xxIF = 1 Yes xxMK = 0 Yes Priority higher than that of interrupt currently serviced? No Interrupt request? No Is the interrupt mask released? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request CPU processing PSW.NP = 0 Yes PSW.ID = 0 Yes EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restore PC PSW Exception code 0 1 Handler address No No Interrupt request pending Interrupt servicing Interrupt servicing pending User's Manual U15943EJ2V0UM 137 CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.1.2 Non-maskable interrupt The non-maskable interrupt cannot be disabled by an instruction and therefore can always be acknowledged. The non-maskable interrupt is generated by the NMI input. When the non-maskable interrupt is generated, the CPU performs the following steps, and transfers control to the handler routine. (1) Saves restore PC to FEPC. (2) Saves current PSW to FEPSW. (3) Writes exception code (0010H) to higher halfword of ECR (FECC). (4) Sets NP and ID flags of PSW to 1 and clears EP flag to 0. (5) Sets handler address for the non-maskable interrupt to PC and transfers control. The FEPC and FEPSW are used as the status saving registers. Non-maskable interrupts are held pending in the interrupt controller when another non-maskable interrupt is currently being executed (when the NP flag of the PSW is 1). Non-maskable interrupts are enabled by setting the NP flag of the PSW to 0 with the RETI and LDSR instructions, which will be enabling new non-maskable interrupt servicing by a pending non-maskable interrupt request. In the case of products that incorporate an interrupt trigger for NMI2, only when NMI2 is generated during the interrupt servicing of NMI0 and NMI1, NMI2 servicing is executed regardless of the value of NP flag. Non-maskable interrupt servicing format is shown below. Figure 6-2. Non-Maskable Interrupt Servicing Format NMI input INTC acknowledgement Non-maskable interrupt request CPU processing PSW.NP = 0 Yes FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC Restore PC PSW Exception code 1 0 1 Handler address No Interrupt servicing Interrupt request pending 138 User's Manual U15943EJ2V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.2 Exception Processing 6.2.1 Software exception A software exception is generated when the TRAP instruction is executed and is always acknowledged. If a software exception occurs, the CPU performs the following steps, and transfers control to the handler routine. (1) Saves restore PC to EIPC. (2) Saves current PSW to EIPSW. (3) Writes exception code to lower 16 bits (EICC) of ECR (interrupt source). (4) Sets EP and ID flags of PSW to 1. (5) Sets handler address (00000040H or 00000050H) for software exception to PC and transfers control. Software exception processing format is shown below. Figure 6-3. Software Exception Processing Format TRAP instruction CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restore PC PSW Exception code 1 1 Handler address Exception processing User's Manual U15943EJ2V0UM 139 CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.2.2 Exception trap An exception trap is an exception requested when an instruction is illegally executed. The illegal opcode trap (ILGOP) is the exception trap. An illegal opcode instruction has an instruction code with an opcode (bits 10 through 5) of 111111B and a subopcode (bits 26 through 23) of 0111B through 1111B and a sub-opcode (bit 16) of 0B. When this kind of an illegal opcode instruction is executed, an exception trap occurs. Figure 6-4. Illegal Instruction Code 15 13 12 11 10 5 11 1 4 0 31 27 26 01 to 11 1 1 23 22 21 20 1 1 17 16 xxx xx111 xxxxxxxxxx xxxxxx0 Remark x: don't care, : opcode/sub-opcode If an exception trap occurs, the CPU performs the following steps, and transfers control to the handler routine. (1) Saves restore PC to DBPC. (2) Saves current PSW to DBPSW. (3) Sets NP, EP, and ID flags of PSW to 1. (4) Sets handler address (00000060H) for exception trap to PC and transfers control. Exception trap processing format is shown below. Figure 6-5. Exception Trap Processing Format Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restore PC PSW 1 1 1 00000060H Exception processing Caution The operation when executing the instruction not defined as an instruction or illegal instruction is not guaranteed. Remark The execution address of the illegal instruction is obtained by "Restore PC - 4". 140 User's Manual U15943EJ2V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.2.3 Debug trap A debug trap is generated when the DBTRAP instruction is executed and is always acknowledged. If a debug trap occurs, the CPU performs the following steps. (1) Saves restore PC to DBPC. (2) Saves current PSW to DBPSW. (3) Sets NP, EP, and ID flags of PSW to 1. (4) Sets handler address (00000060H) for debug trap to PC and transfers control. Debug trap processing format is shown below. Figure 6-6. Debug Trap Processing Format DBTRAP instruction CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restore PC PSW 1 1 1 00000060H Debug monitor routine processing User's Manual U15943EJ2V0UM 141 CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.3 Restoring from Interrupt/Exception Processing 6.3.1 Restoring from interrupt and software exception All restoration from interrupt servicing and software exception is executed by the RETI instruction. With the RETI instruction, the CPU performs the following steps, and transfers control to the address of the restore PC. (1) If the EP flag of the PSW is 0 and the NP flag of the PSW is 1, the restore PC and PSW are read from the FEPC and FEPSW. Otherwise, the restore PC and PSW are read from the EIPC and EIPSW. (2) Control is transferred to the address of the restored PC and PSW. When execution has returned from each interrupt servicing, the NP and EP flags of the PSW must be set to the following values by using the LDSR instruction immediately before the RETI instruction, in order to restore the PC and PSW normally: * To restore from non-maskable interrupt servicing * To restore from maskable interrupt servicing: * To restore from exception processing: Note : NP flag of PSW = 1, EP flag = 0 NP flag of PSW = 0, EP flag = 0 EP flag of PSW = 1 Note In the case of the products that incorporate interrupt trigger for NMI1 and NMI2, NMI1 and NMI2 cannot be restored by the RETI instruction. Execute the system reset after the interrupt servicing. NMI2 can be acknowledged even if the NP flag of PSW is set to 1. Restoration from interrupt/exception processing format is shown below. Figure 6-7. Restoration from Interrupt/Software Exception Processing Format RETI instruction PSW.EP = 0 Yes No PSW.NP = 0 Yes Jump to address of restore PC 142 User's Manual U15943EJ2V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.3.2 Restoring from exception trap and debug trap Restoration from exception trap and debug trap is executed by the DBRET instruction. With the DBRET instruction, the CPU performs the following steps, and transfers control to the address of the restore PC. (1) The restore PC and PSW are read from the DBPC and DBPSW. (2) Control is transferred to the address of the restored PC and PSW. Restoration from exception trap/debug trap processing format is shown below. Figure 6-8. Restoration from Exception Trap/Debug Trap Processing Format DBRET instruction PC PSW DBPC DBPSW Jump to address of restore PC User's Manual U15943EJ2V0UM 143 CHAPTER 7 RESET 7.1 Register Status After Reset When a low-level signal is input to the reset pin, the system is reset, and program registers and system registers are set in the status shown in Table 7-1. When the reset signal goes high, the reset status is cleared, and program execution begins. If necessary, initialize the contents of each register by program control. Table 7-1. Register Status After Reset Register Program registers General-purpose register (r0) General-purpose register (r1 to r31) Program counter (PC) System registers Interrupt status saving register (EIPC) Interrupt status saving register (EIPSW) NMI status saving register (FEPC) NMI status saving register (FEPSW) Exception cause register (ECR) Program status word (PSW) CALLT caller status saving register (CTPC) CALLT caller status saving register (CTPSW) Exception/debug trap status saving register (DBPC) Exception/debug trap status saving register (DBPSW) CALLT base pointer (CTBP) Status After Reset (Initial Value) 00000000H (Fixed) Undefined 00000000H 0xxxxxxxH 00000xxxH 0xxxxxxxH 00000xxxH 00000000H 00000020H 0xxxxxxxH 00000xxxH 0xxxxxxxH 00000xxxH 0xxxxxxxH Remark x: Undefined 7.2 Starting Up The CPU begins program execution from address 00000000H after it has been reset. After reset, no immediate interrupt requests are acknowledged. To enable interrupts by program, clear the ID flag of the PSW to 0. 144 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE The V850ES CPU is based on the RISC architecture and executes almost all the instructions in one clock cycle under control of a 5-stage pipeline. The instruction execution sequence usually consists of five stages including fetch (IF) to write back (WB) stages. The execution time of each stage differs depending on the type of the instruction and the type of the memory to be accessed. As an example of pipeline operation, Figure 8-1 shows the processing of the CPU when 9 standard instructions are executed in succession. Figure 8-1. Example of Executing Nine Standard Instructions Time flow (state) Internal system clock Processing CPU performs simultaneously Instruction 1 ...... <1> IF <2> ID IF <3> EX ID IF <4> <5> <6> <7> <8> <9> <10> <11> <12> <13> MEM WB EX ID IF MEM WB EX ID IF MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID WB MEM EX WB MEM WB Instruction 2 ................. Instruction 3 ............................ Instruction 4 ...................................... Instruction 5 ................................................. Instruction 6 ............................................................ Instruction 7 ...................................................................... Instruction 8 ................................................................................. Instruction 9 ........................................................................................... End of End of End of End of End of End of End of End of End of instruc- instruc- instruc- instruc- instruc- instruc- instruc- instruc- instruction 1 tion 2 tion 3 tion 4 tion 5 tion 6 tion 7 tion 8 tion 9 Executes instruction every 1 clock cycle IF (instruction fetch): ID (instruction decode): MEM (memory access): WB (write back): Instruction is fetched and fetch pointer is incremented. Instruction is decoded, immediate data is generated, and register is read. The decoded instruction is executed. The memory at specified address is accessed. The result of execution is written to register. EX (execution of ALU, multiplier, and barrel shifter): <1> through <13> in the figure above indicate the states of the CPU. In each state, write back (WB) of instruction n, memory access (MEM) of instruction n+1, execution (EX) of instruction n+2, decoding (ID) of instruction n+3, and fetching (IF) of instruction n+4 are simultaneously performed. It takes five clock cycles to process a standard instruction, including IF stage to WB stage. Because five instructions can be processed at the same time, however, a standard instruction can be executed in 1 clock on the average. User's Manual U15943EJ2V0UM 145 CHAPTER 8 PIPELINE 8.1 Features The V850ES CPU, by optimizing the pipeline, improves the CPI (Cycle per instruction) rate over the previous V850 CPU. The pipeline configuration of the V850ES CPU is shown in Figure 8-2. Figure 8-2. Pipeline Configuration Master pipeline (V850 CPU compatible) ID EX DF WB IF Bcond/SLD Pipeline ID Address calculation stage Asynchronous WB pipeline MEM WB Load, store buffer (1 stage each) Remark DF (data fetch): Execution data is transferred to the WB stage. 146 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.1.1 Non-blocking load/store As the pipeline does not stop during external memory access, efficient processing is possible. For example, Figure 8-3 shows a comparison of pipeline operations between the V850 CPU and the V850ES CPU when an ADD instruction is executed after the execution of a load instruction for external memory. Figure 8-3. Non-Blocking Load/Store (a) Previous version (V850 CPU): Pipeline is stopped until MEM stage is complete MEM (external memory) T1 T2 EX Note Load instruction IF ID EX T3 WB ADD instruction IF ID (MEM) WB Next instruction IF ID EX MEM WB Note The basic bus cycle for the external memory is 3 clocks. (b) V850ES CPU: Efficient pipeline processing through use of asynchronous WB pipeline M E M ( e xt er n al m e m or y) Not e Load instruction IF ID EX T1 EX T2 DF WB ADD instruction IF ID WB Next instruction IF ID EX MEM WB Note The basic bus cycle for the external memory of MEMC is 2 clocks. (1) V850 CPU The EX stage of the ADD instruction is usually executed in 1 clock. However, a wait time is generated in the EX stage of the ADD instruction during execution of the MEM stage of the previous load instruction. This is because the same stage of the 5 instructions on the pipeline cannot be executed in the same internal clock interval. This also causes a wait time to be generated in the ID stage of the next instruction after the ADD instruction. (2) V850ES CPU An asynchronous WB pipeline for the instructions that are necessary for the MEM stage is provided in addition to the master pipeline. The MEM stage of the load instruction is therefore processed on this asynchronous WB pipeline. Because the ADD instruction is processed on the master pipeline, a wait time is not generated, making it possible to execute instructions efficiently as shown in Figure 8-3. User's Manual U15943EJ2V0UM 147 CHAPTER 8 PIPELINE 8.1.2 2-clock branch When executing a branch instruction, the branch destination is decided in the ID stage. In the case of the conventional V850 CPU, the branch destination of when the branch instruction is executed was decided after execution of the EX stage, but in the case of the V850ES CPU, due to the addition of a address calculation stage for branch/SLD instruction, the branch destination is decided in the ID stage. Therefore, it is possible to fetch the branch destination instruction 1 clock faster than in the conventional V850 CPU. Figure 8-4 shows a comparison between the V850 CPU and the V850ES CPU of pipeline operations with branch instructions. Figure 8-4. Pipeline Operations with Branch Instructions (a) Previous version (V850 CPU) Branch destination decided in EX stage Branch instruction IF ID EX MEM WB Branch destination instruction IF 3 clocks ID EX MEM WB (b) V850ES CPU Branch destination decided in ID stage Branch instruction IF ID EX MEM WB Branch destination instruction IF 2 clocks ID EX MEM WB 148 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.1.3 Efficient pipeline processing Because the V850ES CPU has an ID stage for branch/SLD instructions in addition to the ID stage on the master pipeline, it is possible to perform efficient pipeline processing. Figure 8-5 shows an example of a pipeline operation where the next branch instruction was fetched in the IF stage of the ADD instruction (Instruction fetch from the ROM directly connected to the dedicated bus is performed in 32-bit units. Both ADD instructions and branch instructions in Figure 8-5 use a 16-bit format instruction). Figure 8-5. Parallel Execution of Branch Instructions (a) Previous version (V850 CPU) ADD instruction IF ID EX (MEM) WB Branch instruction IF ID EX MEM WB Branch destination instruction 5 clocks IF ID EX MEM (b) V850ES CPU ADD instruction IF ID EX DF WB Branch instruction IF ID EX MEM WB Branch destination instruction 3 clocks IF ID EX MEM WB (1) V850 CPU Although the instruction codes up to the next branch instruction are fetched in the IF stage of the ADD instruction, the ID stage of the ADD instruction and the ID stage of the branch instruction cannot execute together within the same clock. Therefore, it takes 5 clocks from the branch instruction fetch to the branch destination instruction fetch. (2) V850ES CPU Because V850ES CPU has an ID stage for branch/SLD instructions in addition to the ID stage on the master pipeline, the parallel execution of the ID stage of the ADD instruction and the ID stage of the branch instruction within the same clock is possible. Therefore, it takes only 3 clocks from the branch instruction fetch start to the branch destination instruction completion. Caution Be aware that the SLD and Bcond instructions are sometimes executed at the same time as other 16-bit format instructions. For example, if the SLD and NOP instructions are executed simultaneously, the NOP instruction may keep the delay time from being generated. User's Manual U15943EJ2V0UM 149 CHAPTER 8 PIPELINE 8.2 Pipeline Flow During Execution of Instructions This section explains the pipeline flow during the execution of instructions. In pipeline processing, the CPU is already processing the next instruction when the memory or I/O write cycle is generated. As a result, I/O manipulations and interrupt request masking will be reflected later than next instructions are issued (ID stage). When an interrupt mask manipulation is performed, maskable interrupt acknowledgement is disabled from the instruction immediately after an instruction because the CPU detects access to the internal INTC (ID stage) and performs interrupt request mask processing. 8.2.1 Load instructions Caution Due to non-blocking control, there is no guarantee that the bus cycle is complete between the MEM stages. However, when accessing the peripheral I/O area, blocking control is effected, making it possible to wait for the end of the bus cycle at the MEM stage. (1) LD instructions [Instructions] [Pipeline] LD instruction Next instruction LD.B, LD.BU, LD.H, LD.HU, LD.W <1> IF <2> ID IF <3> EX ID <4> MEM EX <5> WB MEM WB <6> [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. If an instruction using the execution result is placed immediately after the LD instruction, data wait time occurs. (2) SLD instructions [Instructions] [Pipeline] SLD instruction Next instruction SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W <1> IF <2> ID IF <3> MEM ID <4> WB EX MEM WB <5> <6> [Description] The pipeline consists of 4 stages, IF, ID, MEM, and WB. If an instruction using the execution result is placed immediately after the SLD instruction, data wait time occurs. 150 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.2.2 Store instructions Caution Due to non-blocking control, there is no guarantee that the bus cycle is complete between the MEM stages. However, when accessing the peripheral I/O area, blocking control is effected, making it possible to wait for the end of the bus cycle at the MEM stage. [Instructions] ST.B, ST.H, ST.W, SST.B, SST.H, SST.W <1> <2> ID IF <3> EX ID <4> MEM EX <5> WB MEM WB <6> [Pipeline] Store instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. performed in the WB stage, because no data is written to registers. However, no operation is 8.2.3 Multiply instructions (1) Halfword data multiply instruction [Instructions] [Pipeline] MULH, MULHI (a) When next instruction is not multiply instruction <1> Multiply instruction Next instruction <2> ID IF <3> EX1 ID <4> EX2 EX <5> WB MEM <6> IF WB (b) When next instruction is multiply instruction <1> Multiply instruction 1 Multiply instruction 2 <2> ID IF <3> EX1 ID <4> EX2 EX1 <5> WB EX2 <6> IF WB [Description] The pipeline consists of 5 stages, IF, ID, EX1, EX2, and WB. The EX stage takes 2 clocks because it is executed by a multiplier. EX1 and EX2 stages (different from the normal EX stage) can operate independently. Therefore, the number of clocks for instruction execution is always 1 clock, even if several multiply instructions are executed in a row. However, if an instruction using the execution result is placed immediately after a multiply instruction, data wait time occurs. User's Manual U15943EJ2V0UM 151 CHAPTER 8 PIPELINE (2) Word data multiply instructions [Instructions] [Pipeline] MUL, MULU (a) When the next three instructions are not multiply instructions <1> Multiply instruction Instruction 1 Instruction 2 Instruction 3 <2> ID IF <3> EX1 ID IF <4> EX1 EX ID IF <5> EX1 MEM EX ID <6> EX1 WB MEM EX <7> EX2 <8> WB IF WB MEM WB (b) When the next instruction is a multiply instruction <1> Multiply instruction 1 Multiply instruction 2 (halfword) <2> ID IF <3> EX1 <4> EX1 <5> EX1 <6> EX1 ID <7> EX2 EX1 <8> WB EX2 <9> IF - - - WB -: Idle inserted for wait (c) When the instruction following the next two instructions is a multiply instruction <1> Multiply instruction 1 Instruction 1 Instruction 2 Multiply instruction 2 (halfword) <2> ID IF <3> EX1 ID IF <4> EX1 EX ID IF <5> EX1 MEM EX <6> EX1 WB MEM ID <7> EX2 <8> WB <9> IF WB EX1 EX2 WB - -: Idle inserted for wait [Description] The pipeline consists of 8 stages, IF, ID, EX1 (4 stages), EX2, and WB. The EX stage takes 5 clocks because it is executed by a multiplier. EX1 and EX2 stages (different from the normal EX stage) can operate independently. Therefore, the number of clocks for instruction execution is always 4 clocks, even if several multiply instructions are executed in a row. However, if an instruction using the execution result is placed immediately after a multiply instruction, data wait time occurs. 152 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.2.4 Arithmetic operation instructions (1) Instructions other than divide/move word instructions [Instructions] ADD, ADDI, CMOV, CMP, MOV, MOVEA, MOVHI, SASF, SETF, SUB, SUBR <1> <2> ID IF <3> EX ID <4> DF EX <5> WB MEM WB <6> [Pipeline] Arithmetic operation instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, DF, and WB. (2) Move word instruction [Instructions] MOV imm32 <1> <2> ID IF <3> EX1 <4> EX2 ID <5> DF EX <6> WB MEM WB <7> [Pipeline] Arithmetic operation instruction Next instruction IF - -: Idle inserted for wait [Description] The pipeline consists of 6 stages, IF, ID, EX1, EX2 (normal EX stage), DF, and WB. (3) Divide instructions [Instructions] [Pipeline] DIV, DIVH, DIVHU, DIVU (a) DIV, DIVH instructions <1> Divide instruction Next instruction Next to next instruction IF <2> ID IF <3> EX1 - <4> EX2 - <35> <36> <37> <38> <39> EX33 EX34 EX35 DF - - ID IF EX ID WB MEM WB EX MEM WB <40> <41> -: Idle inserted for wait (b) DIVHU, DIVU instructions <1> Divide instruction Next instruction Next to next instruction IF <2> ID IF <3> EX1 - <4> EX2 - <35> <36> <37> <38> <39> EX33 EX34 DF - ID IF EX ID WB MEM WB EX MEM WB <40> -: Idle inserted for wait [Description] The pipeline consists of 39 stages, IF, ID, EX1 to EX35 (normal EX stage), DF, and WB for DIV and DIVH instructions. The pipeline consists of 38 stages, IF, ID, EX1 to EX34 (normal EX stage), DF, and WB for DIVHU and DIVU instructions. [Remark] If an interrupt occurs while a division instruction is executed, execution of the instruction is stopped, and the interrupt is processed, assuming that the return address is the first address of that instruction. After interrupt servicing has been completed, the division instruction is executed again. In this case, general-purpose registers reg1 and reg2 hold the value before the instruction is executed. User's Manual U15943EJ2V0UM 153 CHAPTER 8 PIPELINE 8.2.5 Saturated operation instructions [Instructions] SATADD, SATSUB, SATSUBI, SATSUBR <1> <2> ID IF <3> EX ID <4> DF EX <5> WB MEM WB <6> [Pipeline] Saturated operation instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, DF, and WB. 8.2.6 Logical operation instructions [Instructions] AND, ANDI, BSH, BSW, HSW, NOT, OR, ORI, SAR, SHL, SHR, SXB, SXH, TST, XOR, XORI, ZXB, ZXH <1> <2> ID IF <3> EX ID <4> DF EX <5> WB MEM WB <6> [Pipeline] Logical operation instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, DF, and WB. 8.2.7 Branch instructions (1) Conditional branch instructions (except BR instruction) [Instructions] Bcond instructions (BC, BE, BGE, BGT, BH, BL, BLE, BLT, BN, BNC, BNE, BNH, BNL, BNV, BNZ, BP, BSA, BV, BZ) [Pipeline] (a) When the condition is not satisfied <1> Conditional branch instruction Next instruction <2> ID IF <3> EX ID <4> MEM EX <5> WB MEM <6> IF WB (b) When the condition is satisfied <1> Conditional branch instruction Next instruction Branch destination instruction <2> ID (IF) <3> EX <4> MEM <5> WB <6> <7> IF IF ID EX MEM WB (IF): Instruction fetch that is not executed 154 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. ID stage. (a) When the condition is not satisfied The number of execution clocks for the branch instruction is 1. (b) When the condition is satisfied However, no operation is performed in the EX, MEM, and WB stages, because the branch destination is decided in the The number of execution clocks for the branch instruction is 2. IF stage of the next instruction of the branch instruction is not executed. If an instruction overwriting the contents of PSW occurs immediately before, the number of execution clocks is 3 because of flag hazard occurrence. (2) BR instruction, unconditional branch instructions (except JMP instruction) [Instructions] [Pipeline] BR, JARL, JR <1> BR instruction, unconditional IF branch instruction Next instruction Branch destination instruction <2> ID (IF) <3> EX <4> MEM <5> WB* <6> <7> IF ID EX MEM WB (IF): WB*: Instruction fetch that is not executed No operation is performed in the case of the JR and BR instructions but in the case of the JARL instruction, data is written to the restore PC. [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed in the EX, MEM, and WB stages, because the branch destination is decided in the ID stage. However, in the case of the JARL instruction, data is written to the restore PC in the WB stage. Also, the IF stage of the next instruction of the branch instruction is not executed. (3) JMP instruction [Pipeline] JMP instruction Next instruction Branch destination instruction <1> IF <2> ID (IF) <3> EX <4> MEM <5> WB <6> <7> IF ID EX MEM WB (IF): Instruction fetch that is not executed [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. ID stage. However, no operation is performed in the EX, MEM, and WB stages, because the branch destination is decided in the User's Manual U15943EJ2V0UM 155 CHAPTER 8 PIPELINE 8.2.8 Bit manipulation instructions (1) CLR1, NOT1, SET1 instructions [Pipeline] Bit manipulation instruction Next instruction Next to next instruction <1> IF <2> ID IF <3> EX1 <4> MEM <5> EX2 ID IF <6> MEM EX ID <7> WB MEM EX <8> <9> - - WB MEM WB -: Idle inserted for wait [Description] The pipeline consists of 7 stages, IF, ID, EX1, MEM, EX2 (normal stage), MEM, and WB. However, no operation is performed in the WB stage, because no data is written to registers. In the case of these instructions, the memory access is read modify write, the EX stage requires a total of 2 clocks, and the MEM stage requires a total of 2 cycles. (2) TST1 instruction [Pipeline] Bit manipulation instruction Next instruction Next to next instruction <1> IF <2> ID IF <3> EX1 <4> MEM <5> EX2 ID IF <6> MEM EX ID <7> WB MEM EX <8> <9> - - WB MEM WB -: Idle inserted for wait [Description] The pipeline consists of 7 stages, IF, ID, EX1, MEM, EX2 (normal stage), MEM, and WB. However, no operation is performed in the second MEM and WB stages, because there is no second memory access nor data write to registers. In all, this instruction requires 2 clocks. 8.2.9 Special instructions (1) CALLT instruction [Pipeline] CALLT instruction Next instruction Branch destination instruction <1> IF <2> ID (IF) <3> MEM <4> EX <5> MEM <6> WB <7> <8> <9> IF ID EX MEM WB (IF): Instruction fetch that is not executed [Description] The pipeline consists of 6 stages, IF, ID, MEM, EX, MEM, and WB. However, no operation is performed in the second MEM and WB stages, because there is no memory access and no data is written to registers. 156 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE (2) CTRET instruction [Pipeline] CTRET instruction Next instruction Branch destination instruction <1> IF <2> ID (IF) <3> EX <4> MEM <5> WB <6> <7> IF ID EX MEM WB (IF): Instruction fetch that is not executed [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. ID stage. (3) DI, EI instructions <1> <2> ID IF <3> EX ID <4> MEM EX <5> WB MEM WB <6> However, no operation is performed in the EX, MEM, and WB stages, because the branch destination is decided in the [Pipeline] DI, EI instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. written to registers. However, no operation is performed in the MEM and WB stages, because memory is not accessed and data is not [Remark] Both the DI and EI instructions do not sample an interrupt request. An interrupt is sampled as follows while these instructions are executed. Instruction immediately before IF DI, EI instruction Instruction immediately after ID IF EX ID IF MEM EX ID WB MEM EX WB MEM WB Last sampling of interrupt before execution of EI or DI instruction First sampling of interrupt after execution of EI or DI instruction User's Manual U15943EJ2V0UM 157 CHAPTER 8 PIPELINE (4) DISPOSE instruction [Pipeline] (a) When branch is not executed <1> DISPOSE instruction Next instruction Next to next instruction <2> ID IF <3> EX <4> MEM IF - - - -: Idle inserted for wait n: Number of registers specified in the register list (list12) (b) When branch is executed <1> DISPOSE instruction Next instruction Branch destination instruction <2> ID (IF) <3> EX <4> MEM IF IF ID EX (IF): Instruction fetch that is not executed -: n: [Description] Idle inserted for wait Number of registers specified in the register list (list12) The pipeline consists of n + 5 stages (n: register list number), IF, ID, EX, n + 1 times MEM, and WB. The MEM stage requires n + 1 cycles. (5) HALT instruction [Pipeline] <1> HALT instruction Next instruction Next to next instruction <2> ID IF <3> EX <4> MEM <5> WB <6> HALT mode release IF - - - - - ID IF EX ID MEM EX WB MEM WB [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM and WB. No operation is performed in the MEM and WB stages, because memory is not accessed and no data is written to registers. Also, for the next instruction, the ID stage is delayed until the HALT mode is released. (6) LDSR, STSR instructions <1> <2> ID IF <3> EX ID <4> DF EX <5> WB MEM WB <6> [Pipeline] LDSR, STSR instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, DF, and WB. If the STSR instruction using the EIPC and FEPC system registers is placed immediately after the LDSR instruction setting these registers, data wait time occurs. 158 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE (7) NOP instruction <1> <2> ID IF <3> EX ID <4> MEM EX <5> WB MEM WB <6> [Pipeline] NOP instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. executed, and no data is written to registers. However, no operation is performed in the EX, MEM, and WB stages, because no operation and no memory access is Caution Be aware that the SLD and Bcond instructions are sometimes executed at the same time as other 16-bit format instructions. For example, if the SLD and NOP instructions are executed simultaneously, the NOP instruction may keep the delay time from being generated. (8) PREPARE instruction [Pipeline] <1> PREPARE instruction IF Next instruction Next to next instruction <2> ID IF <3> EX <4> MEM - - - ID IF -: Idle inserted for wait n: Number of registers specified in the register list (list12) [Description] The pipeline consists of n + 5 stages (n: register list number), IF, ID, EX, n + 1 times MEM, and WB. The MEM stage requires n + 1 cycles. (9) RETI instruction <1> <2> ID1 (IF) (IF) IF ID EX MEM WB <3> ID2 <4> EX <5> MEM <6> WB <7> <8> [Pipeline] RETI instruction Next instruction Next to next instruction IF Jump destination instruction (IF): Instruction fetch that is not executed ID1: Register selection ID2: Read EIPC/FEPC [Description] The pipeline consists of 6 stages, IF, ID1, ID2, EX, MEM, and WB. However, no operation is performed in the MEM and WB stages, because memory is not accessed and no data is written to registers. The ID stage requires 2 clocks. Also, the IF stages of the next instruction and next to next instruction are not executed. User's Manual U15943EJ2V0UM 159 CHAPTER 8 PIPELINE (10) SWITCH instruction [Pipeline] SWITCH instruction Next instruction Branch destination instruction <1> IF <2> ID (IF) <3> EX1 <4> MEM <5> EX2 <6> MEM <7> WB <8> <9> <10> IF ID EX MEM WB (IF): Instruction fetch that is not executed [Description] The pipeline consists of 7 stages, IF, ID, EX1 (normal EX stage), MEM, EX2, MEM, and WB. However, no operation is performed in the second MEM and WB stages, because there is no memory access and no data is written to registers. (11) TRAP instruction <1> <2> ID1 (IF) (IF) IF ID EX MEM WB <3> ID2 <4> EX <5> DF <6> WB <7> <8> [Pipeline] TRAP instruction Next instruction Next to next instruction IF Jump destination instruction (IF): Instruction fetch that is not executed ID1: Exception code (004nH, 005nH) detection (n = 0 to FH) ID2: Address generation [Description] The pipeline consists of 6 stages, IF, ID1, ID2, EX, DF, and WB. The ID stage requires 2 clocks. Also, the IF stages of the next instruction and next to next instruction are not executed. 160 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.2.10 Debug function instructions (1) DBRET instruction <1> <2> ID1 (IF) (IF) IF ID EX MEM WB <3> ID2 <4> EX <5> MEM <6> WB <7> <8> [Pipeline] DBRET instruction Next instruction Next to next instruction IF Jump destination instruction (IF): Instruction fetch that is not executed ID1: Register selection ID2: Read DBPC [Description] The pipeline consists of 6 stages, IF, ID1, ID2, EX, MEM, and WB. However, no operation is performed in the MEM and WB stages, because the memory is not accessed and no data is written to registers. The ID stage requires 2 clocks. Also, the IF stages of the next instruction and next to next instruction are not executed. (2) DBTRAP instruction <1> <2> ID1 (IF) (IF) IF ID EX MEM WB <3> ID2 <4> EX <5> DF <6> WB <7> <8> [Pipeline] DBTRAP instruction Next instruction Next to next instruction IF Jump destination instruction (IF): Instruction fetch that is not executed ID1: Exception code (0060H) detection ID2: Address generation [Description] The pipeline consists of 6 stages, IF, ID1, ID2, EX, MEM, and WB. The ID stage requires 2 clocks. Also, the IF stages of the next instruction and next to next instruction are not executed. User's Manual U15943EJ2V0UM 161 CHAPTER 8 PIPELINE 8.3 Pipeline Disorder The pipeline consists of 5 stages from IF (Instruction Fetch) to WB (Write Back). Each stage basically requires 1 clock for processing, but the pipeline may become disordered, causing the number of execution clocks to increase. This section describes the main causes of pipeline disorder. 8.3.1 Alignment hazard If the branch destination instruction address is not word aligned (A1 = 1, A0 = 0) and is 4 bytes in length, it is necessary to repeat IF twice in order to align instructions in word units. This is called an align hazard. For example, the instructions a to e are placed from address X0H, and that instruction b consists of 4 bytes, and the other instructions each consist of 2 bytes. In this case, instruction b is placed at X2H (A1 = A0 = 0), and is not word aligned (A1 = 0, A0 = 0). Therefore, when this instruction b becomes the branch destination instruction, an align hazard occurs. becomes 4. Figure 8-6. Align Hazard Example (a) Memory map 32 bits Instruc- InstrucX8H tion d tion e Instruc- InstrucX4H tion b tion c Instruc- InstrucX0H tion a tion b When an align hazard occurs, the number of execution clocks of the branch instruction (b) Pipeline <1> <2> <3> <4> MEM IF2 <5> WB ID IF EX ID MEM EX WB MEM <6> <7> <8> <9> Branch instruction IF ID EX Next instruction IF x Branch destination instruction (instruction b) IF1 Branch destination's next instruction (instruction c) WB IF x: Instruction fetch that is not executed IF1: First instruction fetch that occurs during align hazard. It is a 2-byte fetch that fetches the 2 bytes on the lower address of instruction b. IF2: Second instruction fetch that occurs during align hazard. It is Address of branch destination instruction (instruction b) normally a 4-byte fetch that fetches the 2 bytes on the higher address of instruction b in addition to instruction c (2-byte length). Align hazards can be prevented through the following handling in order to obtain faster instruction execution. * Use 2-byte branch destination instruction. * Use 4-byte instructions placed at word boundaries (A1 = 0, A0 = 0) for branch destination instructions. 162 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.3.2 Referencing execution result of load instruction For load instructions (LD, SLD), data read in the MEM stage is saved during the WB stage. Therefore, if the contents of the same register are used by the instruction immediately after the load instruction, it is necessary to delay the use of the register by this later instruction until the load instruction has ended using that register. This is called a hazard. The V850ES CPU has an interlock function to automatically handle this hazard by delaying the ID stage of the next instruction. The V850ES CPU also has a short path that allows the data read during the MEM stage to be used in the ID stage of the next instruction. This short path allows data to be read with the load instruction during the MEM stage and the use of this data in the ID stage of the next instruction with the same timing. As a result of the above, when using the execution result in the instruction following immediately after, the number of execution clocks of the load instruction is 2. Figure 8-7. Example of Execution Result of Load Instruction <1> Load instruction 1 IF (LD [R4], R6) Instruction 2 (ADD 2, R6) Instruction 3 Instruction 4 <2> ID IF <3> EX IL IF <4> MEM ID - <5> WB EX ID IF <6> MEM EX ID <7> WB MEM EX <8> <9> WB MEM WB IL: Idle inserted for data wait by interlock function -: : Idle inserted for wait Short path As shown in Figure 8-7, when an instruction placed immediately after a load instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. This drop in execution speed can be avoided by placing instructions that use the execution result of a load instruction at least 2 instructions after the load instruction. User's Manual U15943EJ2V0UM 163 CHAPTER 8 PIPELINE 8.3.3 Referencing execution result of multiply instruction For multiply instructions, the operation result is saved to the register in the WB stage. Therefore, if the contents of the same register are used by the instruction immediately after the multiply instruction, it is necessary to delay the use of the register by this later instruction until the multiply instruction has ended using that register (occurrence of hazard). The V850ES CPU's interlock function delays the ID stage of the instruction following immediately after. A short path is also provided that allows the EX2 stage of the multiply instruction and the multiply instruction's operation result to be used in the ID stage of the instruction following immediately after with the same timing. Figure 8-8. Example of Execution Result of Multiply Instruction (a) In the case of halfword data multiply instruction <1> Multiply instruction 1 IF (MULH 3, R6) Instruction 2 (ADD 2, R6) Instruction 3 Instruction 4 <2> ID IF <3> EX1 IL IF <4> EX2 ID <5> WB EX ID IF <6> MEM EX ID <7> WB MEM EX <8> <9> WB MEM WB IL: Idle inserted for data wait by interlock function -: Idle inserted for wait : Short path (b) In the case of word data multiply instruction <1> Multiply instruction 1 IF (MULH 3, R6) Instruction 2 (ADD 2, R6) Instruction 3 Instruction 4 <2> ID IF <3> EX1 IL IF <4> EX1 IL <5> EX1 IL <6> EX1 IL <7> EX2 ID <8> WB EX ID IF <9> MEM EX ID <10> WB MEM EX <11> <12> WB MEM WB IL: Idle inserted for data wait by interlock function -: Idle inserted for wait : Short path As shown in Figure 8-8, when an instruction placed immediately after a multiply instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. This drop in execution speed can be avoided by placing instructions that use the execution result of a multiply instruction at least 2 instructions after the multiply instruction. However, in the case of the word data multiply instructions (MUL, MULU), if the instruction that uses the result of the multiply instruction is not place at least five instructions after the multiply instruction, an IL stage is inserted between 1 and 4. 164 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.3.4 Referencing execution result of LDSR instruction for EIPC and FEPC When using the LDSR instruction to set the data of the EIPC and FEPC system registers, and immediately after referencing the same system registers with the STSR instruction, the use of the system registers for the STSR instruction is delayed until the setting of the system registers with the LDSR instruction is completed (occurrence of hazard). The V850ES CPU's interlock function delays the ID stage of the STSR instruction immediately after. As a result of the above, when using the execution result of the LDSR instruction for EIPC and FEPC for an STSR instruction following immediately after, the number of execution clocks of the LDSR instruction becomes 3. Figure 8-9. Example of Referencing Execution Result of LDSR Instruction for EIPC and FEPC <1> LDSR instruction (LDSR R6, 0) Note IF STSR instruction (STSR 0, R7) Note Next instruction Next to next instruction <2> ID IF <3> EX IL IF <4> MEM IL - <5> WB ID - <6> EX ID IF <7> MEM EX ID <8> WB MEM EX <9> <10> WB MEM WB IL: Idle inserted for data wait by interlock function -: Idle inserted for wait Note System register 0 used for the LDSR and STSR instructions designates EIPC. As shown in Figure 8-9, when an STSR instruction is placed immediately after an LDSR instruction that uses the operand EIPC or FEPC, and that STSR instruction uses the LDSR instruction execution result, the interlock function causes a data wait time to occur, and the execution speed is lowered. This drop in execution speed can be avoided by placing STSR instructions that reference the execution result of the preceding LDSR instruction at least 3 instructions after the LDSR instruction. 8.3.5 Cautions when creating programs When creating programs, pipeline disorder can be avoided and instruction execution speed can be raised by observing the following cautions. * Place instructions that use the execution result of load instructions (LD, SLD) at least 2 instructions after the load instruction. * Place instructions that use the execution result of multiply instructions (MULH, MULHI) at least 2 instructions after the multiply instruction. * If using the STSR instruction to read the setting results written to the EIPC or FEPC registers with the LDSR instruction, place the STSR instruction at least 3 instructions after the LDSR instruction. * For the first branch destination instruction, use a 2-byte instruction, or a 4-byte instruction placed at the word boundary. User's Manual U15943EJ2V0UM 165 CHAPTER 8 PIPELINE 8.4 Additional Items Related to Pipeline 8.4.1 Harvard architecture The V850ES CPU uses the Harvard architecture to operate an instruction fetch path from internal ROM and a memory access path to internal RAM independently. This eliminates bus arbitration conflicts between the IF and MEM stages and allows orderly pipeline operation. (1) V850ES CPU (Harvard architecture) The MEM stage of instruction 1 and the IF stage of instruction 4, as well as the MEM stage of instruction 2 and the IF stage of instruction 5 can be executed simultaneously with orderly pipeline operation. <1> Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 IF <2> ID IF <3> EX ID IF <4> MEM EX ID IF <5> WB MEM EX ID IF <6> WB MEM EX ID <7> <8> <9> WB MEM EX WB MEM WB (2) Not V850ES CPU (Other than Harvard architecture) The MEM stage of instruction 1 and the IF stage of instruction 4, in addition to the MEM stage of instruction 2 and the IF stage of instruction 5 are in contention, causing bus waiting to occur and slower execution time due to disorderly pipeline operation. <1> Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 IF <2> ID IF <3> EX ID IF <4> MEM - <5> WB EX ID IF <6> MEM - <7> WB EX ID IF <8> <9> <10> <11> MEM EX ID WB MEM EX WB MEM WB -: Idle inserted for wait 166 User's Manual U15943EJ2V0UM CHAPTER 8 PIPELINE 8.4.2 Short path The V850ES CPU provides on chip a short path that allows the use of the execution result of the preceding instruction by the following instruction before write back (WB) is completed for the previous instruction. Example 1. Execution result of arithmetic operation instruction and logical operation used by instruction following immediately after * V850ES CPU (on-chip short path) The execution result of the preceding instruction can be used for the ID stage of the instruction following immediately after as soon as the result is out (EX stage), without having to wait for write back to be completed. <1> ADD 2, R6 MOV R6, R7 IF <2> ID IF <3> EX ID <4> MEM EX <5> WB MEM <6> WB * Not V850ES CPU (No short path) The ID stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. <1> ADD 2, R6 MOV R6, R7 IF <2> ID IF <3> EX - <4> MEM - <5> WB ID <6> EX <7> MEM <8> WB -: : Idle inserted for wait Short path User's Manual U15943EJ2V0UM 167 CHAPTER 8 PIPELINE Example 2. Data read from memory by the load instruction used by instruction following immediately after * V850ES CPU (on-chip short path) The execution result of the preceding instruction can be used for the ID stage of the instruction following immediately after as soon as the result is out (MEM stage), without having to wait for write back to be completed. <1> IF LD [R4], R6 ADD 2, R6 Next instruction Next to next instruction <2> ID IF <3> EX IL IF <4> MEM ID - <5> WB EX ID IF <6> MEM EX ID <7> WB MEM EX <8> <9> WB MEM WB * Not V850ES CPU (No short path) The ID stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. <1> LD [R4], R6 ADD 2, R6 Next instruction Next to next instruction IF <2> ID IF <3> EX - <4> MEM - <5> WB ID IF <6> EX ID IF <7> MEM EX ID <8> WB MEM EX <9> <10> WB MEM WB IL: Idle inserted for data wait by interlock function -: : Idle inserted for wait Short path 168 User's Manual U15943EJ2V0UM APPENDIX A INSTRUCTION LIST The instruction function list in alphabetical order is shown in Table A-1, and instruction list in format order is shown in Table A-2. Table A-1. Instruction Function List (in Alphabetical Order) (1/11) Mnemonic Operand Format CY ADD reg1, reg2 I 0/1 OV 0/1 Flag S 0/1 Z 0/1 SAT - - Add. Adds the word data of reg1 to the word data of reg2, and stores the result to reg2. Add. Adds the 5-bit immediate data, signextended to word length, to the word data of reg2, and stores the result to reg2. Add Immediate. Adds the 16-bit immediate data, sign-extended to word length, to the word data of reg1, and stores the result to reg2. And. ANDs the word data of reg2 with the word data of reg1, and stores the result to reg2. And. ANDs the word data of reg1 with the 16bit immediate data, zero-extended to word length, and stores the result to reg2. Branch on Condition Code. Tests a condition flag specified by an instruction. Branches if a specified condition is satisfied; otherwise, executes the next instruction. The branch destination PC holds the sum of the current PC value and 9-bit displacement which is the 8-bit immediate shifted 1 bit and signextended to word length. Byte Swap conversion. Byte Swap conversion. Halfword. Performs endian Instruction Function ADD imm5, reg2 II 0/1 0/1 0/1 0/1 ADDI imm16, reg1, reg2 VI 0/1 0/1 0/1 0/1 - AND reg1, reg2 I - 0 0/1 0/1 - ANDI imm16, reg1, reg2 VI - 0 0/1 0/1 - Bcond disp9 III - - - - - BSH reg2, reg3 XII 0/1 0 0/1 0/1 - - - BSW reg2, reg3 XII 0/1 - 0 - 0/1 - 0/1 - Word. Performs endian CALLT imm6 II Call with Table Look Up. Based on CTBP contents, updates PC value and transfers control. Clear Bit. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Then clears the bit, specified by the instruction bit field, of the byte data referenced by the generated address. CLR1 bit#3, disp16 [reg1] VIII - - - 0/1 - User's Manual U15943EJ2V0UM 169 APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (2/11) Mnemonic Operand Format CY CLR1 reg2 [reg1] IX - OV - Flag S - Z 0/1 SAT - Clear Bit. First, reads the data of reg1 to generate a 32-bit address. Then clears the bit, specified by the data of lower 3 bits of reg2 of the byte data referenced by the generated address. Conditional Move. reg3 is set to reg1 if a condition specified by condition code "cccc" is satisfied; otherwise, set to the data of reg2. Conditional Move. reg3 is set to the data of 5immediate, sign-extended to word length, if a condition specified by condition code "cccc" is satisfied; otherwise, set to the data of reg2. Compare. Compares the word data of reg2 with the word data of reg1, and indicates the result by using the PSW flags. To compare, the contents of reg1 are subtracted from the word data of reg2. Compare. Compares the word data of reg2 with the 5-bit immediate data, sign-extended to word length, and indicates the result by using the PSW flags. To compare, the contents of the sign-extended immediate data are subtracted from the word data of reg2. Restore from CALLT. Restores the restore PC and PSW from the appropriate system register and restores from a routine called by CALLT. Return from debug trap. Restores the restore PC and PSW from the appropriate system register and restores from a debug monitor routine. Debug trap. Saves the restore PC and PSW to the appropriate system register and transfers control by setting the PC to handler address (00000060H). Disables Interrupt. Sets the ID flag of the PSW to 1 to disable the acknowledgement of maskable interrupts from acceptance; interrupts are immediately disabled at the start of this instruction execution. Function Dispose. Adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. Then pop (load data from the address specified by sp and adds 4 to sp) general-purpose registers listed in list12. Instruction Function CMOV cccc, reg1, reg2, reg3 XI - - - - - CMOV cccc, imm5, reg2, reg3 XII - - - - - CMP reg1, reg2 I 0/1 0/1 0/1 0/1 - CMP imm5, reg2 II 0/1 0/1 0/1 0/1 - CTRET (None) X 0/1 0/1 0/1 0/1 0/1 DBRET (None) X 0/1 0/1 0/1 0/1 0/1 DBTRAP (None) I - - - - - DI (None) X - - - - - DISPOSE imm5, list12 XIII - - - - - 170 User's Manual U15943EJ2V0UM APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (3/11) Mnemonic Operand Format CY DISPOSE imm5, list12, [reg1] XIII - OV - Flag S - Z - SAT - Function Dispose. Adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. Then pop (load data from the address specified by sp and adds 4 to sp) general-purpose registers listed in list12, transfers control to the address specified by reg1. Divide Word. Divides the word data of reg2 by the word data of reg1, and stores the quotient to reg2 and the remainder to reg3. Divide Halfword. Divides the word data of reg2 by the lower halfword data of reg1, and stores the quotient to reg2. Divide Halfword. Divides word data of reg2 by lower halfword data of reg1, and stores the quotient to reg2 and the remainder to reg3. Divide Halfword Unsigned. Divides word data of reg2 by lower halfword data of reg1, and stores the quotient to reg2 and the remainder to reg3. Divide Word Unsigned. Divides the word data of reg2 by the word data of reg1, and stores the quotient to reg2 and the remainder to reg3. Enable Interrupt. Clears the ID flag of the PSW to 0 and enables the acknowledgement of maskable interrupts at the beginning of next instruction. Halt. Stops the operating clock of the CPU and places the CPU in the HALT mode. Halfword Swap conversion. Word. Performs endian Instruction Function DIV reg1, reg2, reg3 XI - 0/1 0/1 0/1 - DIVH reg1, reg2 I - 0/1 0/1 0/1 - DIVH reg1, reg2, reg3 XI - 0/1 0/1 0/1 - DIVHU reg1, reg2, reg3 XI - 0/1 0/1 0/1 - DIVU reg1, reg2, reg3 XI - 0/1 0/1 0/1 - EI (None) X - - - - - HALT (None) X - 0/1 - - 0 - - 0/1 - - 0/1 - - - - HSW reg2, reg3 XII JARL disp22, reg2 V Jump and Register Link. Saves the current PC value plus 4 to general-purpose register reg2, adds a 22-bit displacement, sign-extended to word length, to the current PC value, and transfers control to the PC. Bit 0 of the 22-bit displacement is masked to 0. Jump Register. Transfers control to the address specified by reg1. Bit 0 of the address is masked to 0. Jump Relative. Adds a 22-bit displacement, sign-extended to word length, to the current PC value, and transfers control to the PC. Bit 0 of the 22-bit displacement is masked to 0. JMP [reg1] I - - - - - JR disp22 V - - - - - User's Manual U15943EJ2V0UM 171 APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (4/11) Mnemonic Operand Format CY LD.B disp16 [reg1], reg2 VII - OV - Flag S - Z - SAT - Byte Load. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Byte data is read from the generated address, sign-extended to word length, and then stored in reg2. Unsigned Byte Load. Adds the data of reg1 and the 16-bit displacement sign-extended to word length, and generates a 32-bit address. Then reads the byte data from the generated address, zero-extends it to word length, and stores it in reg2. Halfword Load. Adds the data of reg1 to a 16bit displacement, sign-extended to word length, to generate a 32-bit address. Halfword data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored in reg2. Unsigned Halfword Load. Adds the data of reg1 and the 16-bit displacement signextended to word length to generate a 32-bit address. Reads the halfword data from the address masking bit 0 of this 32-bit address to 0, zero-extends it to word length, and stores it in reg2. Word Load. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored in reg2. Load to System Register. Set the word data of reg2 to a system register specified by regID. If regID is PSW, the values of the corresponding bits of reg2 are set to the respective flags of the PSW. Move. Transfers the word data of reg1 to reg2. Move. Transfers the value of a 5-bit immediate data, sign-extended to word length, to reg2. Move. Transfers the 32-bit immediate data to reg1. Move Effective Address. Adds a 16-bit immediate data, sign-extended to word length, to the word data of reg1, and stores the result in reg2. Instruction Function LD.BU disp16 [reg1], reg2 VII - - - - - LD.H disp16 [reg1], reg2 VII - - - - - LD.HU disp16 [reg1], reg2 VII - - - - - LD.W disp16 [reg1], reg2 VII - - - - - LDSR reg2, regID IX - - - - - MOV MOV reg1, reg2 imm5, reg2 I II - - - - - - - - - - MOV imm32, reg1 VI - - - - - - - - - - MOVEA imm16, reg1, reg2 VI 172 User's Manual U15943EJ2V0UM APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (5/11) Mnemonic Operand Format CY MOVHI imm16, reg1, reg2 VI - OV - Flag S - Z - SAT - Move High Halfword. Adds word data, in which the higher 16 bits are defined by the 16bit immediate data while the lower 16 bits are set to 0, to the word data of reg1 and stores the result in reg2. Multiply Word. Multiplies the word data of reg2 by the word data of reg1, and stores the result in reg2 and reg3 as double-word data. Multiply Word. Multiplies the word data of reg2 by the 9-bit immediate data sign-extended to word length, and stores the result in reg2 and reg3. Multiply Halfword. Multiplies the lower halfword data of reg2 by the lower halfword data of reg1, and stores the result in reg2 as word data. Multiply Halfword. Multiplies the lower halfword data of reg2 by a 5-bit immediate data, sign-extended to halfword length, and stores the result in reg2 as word data. Multiply Halfword Immediate. Multiplies the lower halfword data of reg1 by a 16-bit immediate data, and stores the result in reg2. Multiply Word Unsigned. Multiplies the word data of reg2 by the word data of reg1, and stores the result in reg2 and reg3 as doubleword data. reg1 is not affected. Multiply Word Unsigned. Multiplies the word data of reg2 by the 9-bit immediate data signextended to word length, and store the result in reg2 and reg3. No Operation. Not. Logically negates (takes 1's complement of) the word data of reg1, and stores the result in reg2. Not Bit. First, adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. The bit specified by the 3-bit bit number is inverted at the byte data location referenced by the generated address. Not Bit. First, reads reg1 to generate a 32-bit address. The bit specified by the lower 3 bits of reg2 of the byte data of the generated address is inverted. Instruction Function MUL reg1, reg2, reg3 XI - - - - - MUL imm9, reg2, reg3 XII - - - - - MULH reg1, reg2 I - - - - - MULH imm5, reg2 II - - - - - MULHI imm16, reg1, reg2 VI - - - - - MULU reg1, reg2, reg3 XI - - - - - MULU imm9, reg2, reg3 XII - - - - - NOP NOT (None) reg1, reg2 I I - - - 0 - 0/1 - 0/1 - - NOT1 bit#3, disp16 [reg1] VIII - - - 0/1 - NOT1 reg2, [reg1] IX - - - 0/1 - User's Manual U15943EJ2V0UM 173 APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (6/11) Mnemonic Operand Format CY OR reg1, reg2 I - - OV 0 Flag S 0/1 Z 0/1 SAT - - Or. ORs the word data of reg2 with the word data of reg1, and stores the result in reg2. Or Immediate. ORs the word data of reg1 with the 16-bit immediate data, zero-extended to word length, and stores the result in reg2. Function Prepare. The general-purpose register displayed in list12 is saved (4 is subtracted from sp, and the data is stored in that address). Next, the data is logically shifted 2 bits to the left, and the 5-bit immediate data zero-extended to word length is subtracted from sp. Function Prepare. The general-purpose register displayed in list12 is saved (4 is subtracted from sp, and the data is stored in that address). Next, the data is logically shifted 2 bits to the left, and the 5-bit immediate data zero-extended to word length is subtracted from sp. Then, the data specified by the third operand is loaded to ep. Return from Trap or Interrupt. Reads the restore PC and PSW from the appropriate system register, and restores from interrupt or exception processing routine. Shift Arithmetic Right. Arithmetically shifts the word data of reg2 to the right by `n' positions, where `n' is specified by the lower 5 bits of reg1 (the MSB prior to shift execution is copied and set as the new MSB), and then writes the result to reg2. Shift Arithmetic Right. Arithmetically shifts the word data of reg2 to the right by `n' positions specified by the lower 5-bit immediate data, zero-extended to word length (the MSB prior to shift execution is copied and set as the new MSB), and then writes the result to reg2. Shift and Set Flag Condition. reg2 is logically shifted left by 1, and its LSB is set to 1 in a condition specified by condition code "cccc" is satisfied; otherwise, LSB is set to 0. Instruction Function ORI imm16, reg1, reg2 VI 0 0/1 0/1 PREPARE list12, imm5 XIII - - - - - PREPARE list12, imm5, sp/imm XIII - - - - - RETI (None) X 0/1 0/1 0/1 0/1 0/1 SAR reg1, reg2 IX 0/1 0 0/1 0/1 - SAR imm5, reg2 II 0/1 0 0/1 0/1 - SASF cccc, reg2 IX - - - - - 174 User's Manual U15943EJ2V0UM APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (7/11) Mnemonic Operand Format CY SATADD reg1, reg2 I 0/1 OV 0/1 Flag S 0/1 Z 0/1 SAT 0/1 Saturated Add. Adds the word data of reg1 to the word data of reg2, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Saturated Add. Adds the 5-bit immediate data, sign-extended to word length, to the word data of reg2, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Saturated Subtract. Subtracts the word data of reg1 from the word data of reg2, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Saturated Subtract Immediate. Subtracts a 16-bit immediate data, sign-extended to word length, from the word data of reg1, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Saturated Subtract Reverse. Subtracts the word data of reg2 from the word data of reg1, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Set Bit. First, adds a 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address. The bits, specified by the 3-bit bit number, are set at the byte data location specified by the generated address. Instruction Function SATADD imm5, reg2 II 0/1 0/1 0/1 0/1 0/1 SATSUB reg1, reg2 I 0/1 0/1 0/1 0/1 0/1 SATSUBI imm16, reg1, reg2 VI 0/1 0/1 0/1 0/1 0/1 SATSUBR reg1, reg2 I 0/1 0/1 0/1 0/1 0/1 SET1 bit#3, disp16 [reg1] VIII - - - 0/1 - User's Manual U15943EJ2V0UM 175 APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (8/11) Mnemonic Operand Format CY SET1 reg2, [reg1] IX - OV - Flag S - Z 0/1 SAT - Set Bit. First, reads the data of generalpurpose register reg1 to generate a 32-bit address. The bit, specified by the data of lower 3 bits of reg2, is set at the byte data location referenced by the generated address. Set Flag Condition. The reg2 is set to 1 if a condition specified by condition code "cccc" is satisfied; otherwise, a 0 is stored in reg2. Shift Logical Left. Logically shifts the word data of reg2 to the left by `n' positions (0 is shifted to the LSB side), where `n' is specified by the lower 5 bits of reg1, and then writes the result to reg2. Shift Logical Left. Logically shifts the word data of reg2 to the left by `n' positions (0 is shifted to the LSB side), where `n' is specified by a 5-bit immediate data, zero-extended to word length, and then writes the result to reg2. Shift Logical Right. Logically shifts the word data of reg2 to the right by `n' positions (0 is shifted to the MSB side), where `n' is specified by the lower 5 bits of reg1, and then writes the result to reg2. Shift Logical Right. Logically shifts the word data of reg2 to the right by `n' positions (0 is shifted to the MSB side), where `n' is specified by a 5-bit immediate data, zero-extended to word length, and then writes the result to reg2. Byte Load. Adds the 7-bit displacement, zeroextended to word length, to the element pointer to generate a 32-bit address. Byte data is read from the generated address, signextended to word length, and then stored in reg2. Unsigned Byte Load. Adds the 4-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Byte data is read from the generated address, zero-extended to word length, and stored in reg2. Halfword Load. Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Halfword data is read from the generated address, signextended to word length, and stored in reg2. Instruction Function SETF cccc, reg2 IX - - - - - SHL reg1, reg2 IX 0/1 0 0/1 0/1 - SHL imm5, reg2 II 0/1 0 0/1 0/1 - SHR reg1, reg2 IX 0/1 0 0/1 0/1 - SHR imm5, reg2 II 0/1 0 0/1 0/1 - SLD.B disp7 [ep], reg2 IV - - - - - SLD.BU disp4 [ep], reg2 IV - - - - - SLD.H disp8 [ep], reg2 IV - - - - - 176 User's Manual U15943EJ2V0UM APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (9/11) Mnemonic Operand Format CY SLD.HU disp5 [ep], reg2 IV - OV - Flag S - Z - SAT - Unsigned Halfword Load. Adds the 5-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Halfword data is read from the generated address, zero-extended to word length, and stored in reg2. Word Load. Adds the 8-bit displacement, zeroextended to word length, to the element pointer to generate a 32-bit address. Word data is read from the generated address, and stored in reg2. Byte Store. Adds the 7-bit displacement, zeroextended to word length, to the element pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 in the generated address. Halfword Store. Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the lower halfword of reg2 in the generated address. Word Store. Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the word data of reg2 in the generated addres. Byte Store. Adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the lowest byte data of reg2 in the generated address. Halfword Store. Adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the lower halfword of reg2 in the generated address. Word Store. Adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the word data of reg2 in the generated address. Store Contents of System Register. Stores the contents of a system register specified by regID in reg2. Instruction Function SLD.W disp8 [ep], reg2 IV - - - - - SST.B reg2, disp7 [ep] IV - - - - - SST.H reg2, disp8 [ep] IV - - - - - SST.W reg2, disp8 [ep] IV - - - - - ST.B reg2, disp16 [reg1] VII - - - - - ST.H reg2, disp16 [reg1] VII - - - - - ST.W reg2, disp16 [reg1] VII - - - - - STSR regID, reg2 IX - - - - - User's Manual U15943EJ2V0UM 177 APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (10/11) Mnemonic Operand Format CY SUB reg1, reg2 I 0/1 OV 0/1 Flag S 0/1 Z 0/1 SAT - Subtract. Subtracts the word data of reg1 from the word data of reg2, and stores the result in reg2. Subtract Reverse. Subtracts the word data of reg2 from the word data of reg1, and stores the result in reg2. Jump with Table Look Up. Adds the table entry address (address following SWITCH instruction) and data of reg1 logically shifted to the left by 1 bit, and loads the halfword entry data specified by the table entry address. Next, logically shifts to the left by 1 bit the loaded data, and after sign-extending it to word length, branches to the target address added to the table entry address (instruction following SWITCH instruction). Sign Extend Byte. Sign-extends the lowermost byte of reg1 to word length. Sign Extend Halfword. Sign-extends lower halfword of reg1 to word length. Trap. Saves the restore PC and PSW; sets the exception code and the flags of the PSW; jumps to the address of the trap handler corresponding to the trap vector specified by vector, and starts exception processing. Test. ANDs the word data of reg2 with the word data of reg1. The result is not stored, and only the flags are changed. Test Bit. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Performs the test on the bit, specified by the 3-bit bit number, at the byte data location referenced by the generated address. If the specified bit is 0, the Z flag is set to 1; if the bit is 1, the Z flag is cleared to 0. Test Bit. First, reads the data of reg1 to generate a 32-bit address. If the bits indicated by the lower 3 bits of reg2 of the byte data of the generated address are 0, the Z flag is set to 1, and if they are 1, the Z flag is cleared to 0. Exclusive Or. Exclusively ORs the word data of reg2 with the word data of reg1, and stores the result in reg2. Instruction Function SUBR reg1, reg2 I 0/1 0/1 0/1 0/1 - SWITCH reg1 I - - - - - SXB reg1 I - - - - - - - - - - - - - - - SXH reg1 I TRAP vector X TST reg1, reg2 I - 0 0/1 0/1 - TST1 bit#3, disp16 [reg1] VIII - - - 0/1 - TST1 reg2, [reg1] IX - - - 0/1 - XOR reg1, reg2 I - 0 0/1 0/1 - 178 User's Manual U15943EJ2V0UM APPENDIX A INSTRUCTION LIST Table A-1. Instruction Function List (in Alphabetical Order) (11/11) Mnemonic Operand Format CY XORI imm16, reg1, reg2 VI - OV 0 Flag S 0/1 Z 0/1 SAT - Exclusive Or Immediate. Exclusively ORs the word data of reg1 with a 16-bit immediate data, zero-extended to word length, and stores the result in reg2. Zero Extend Byte. Zero-extends to word length the lowest byte of reg1. Zero Extend Halfword. Zero-extends to word length the lower halfword of reg1. Instruction Function ZXB reg1 I - - - - - - - - - - ZXH reg1 I User's Manual U15943EJ2V0UM 179 APPENDIX A INSTRUCTION LIST Table A-2. Instruction List (in Format Order) (1/3) Format Opcode Mnemonic Operand 15 I 0 31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16 NOP MOV NOT DIVH SWITCH JMP SATSUBR SATSUB SATADD MULH ZXB SXB ZXH SXH OR XOR AND TST SUBR SUB ADD CMP DBTRAP MOV SATADD ADD CMP CALLT SHR SAR SHL MULH Bcond imm5, reg2 imm5, reg2 imm5, reg2 imm5, reg2 imm6 imm5, reg2 imm5, reg2 imm5, reg2 imm5, reg2 disp9 reg1, reg2 reg1, reg2 reg1, reg2 reg1 [reg1] reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1 reg1 reg1 reg1 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 - - 0000000000000000 rrrrr000000RRRRR rrrrr000001RRRRR rrrrr000010RRRRR 00000000010RRRRR 00000000011RRRRR rrrrr000100RRRRR rrrrr000101RRRRR rrrrr000110RRRRR rrrrr000111RRRRR 00000000100RRRRR 00000000101RRRRR 00000000110RRRRR 00000000111RRRRR rrrrr001000RRRRR rrrrr001001RRRRR rrrrr001010RRRRR rrrrr001011RRRRR rrrrr001100RRRRR rrrrr001101RRRRR rrrrr001110RRRRR rrrrr001111RRRRR 1111100001000000 II rrrrr010000iiiii rrrrr010001iiiii rrrrr010010iiiii rrrrr010011iiiii 0000001000iiiiii rrrrr010100iiiii rrrrr010101iiiii rrrrr010110iiiii rrrrr010111iiiii III ddddd1011dddCCCC 180 User's Manual U15943EJ2V0UM APPENDIX A INSTRUCTION LIST Table A-2. Instruction List (in Format Order) (2/3) Format Opcode Mnemonic Operand 15 IV 0 31 - - - - - - - - 16 SLD.BU SLD.HU SLD.B SST.B SLD.H SST.H SLD.W SST.W JARL JR ADDI MOVEA MOVHI SATSUBI MOV ORI XORI ANDI MULHI LD.B LD.H LD.W ST.B ST.H ST.W LD.BU LD.HU SET1 NOT1 CLR1 TST1 disp4 [ep], reg2 disp5 [ep], reg2 disp7 [ep], reg2 reg2, disp7 [ep] disp8 [ep], reg2 reg2, disp8 [ep] disp8 [ep], reg2 reg2, disp8 [ep] disp22, reg2 disp22 imm16, reg1, reg2 imm16, reg1, reg2 imm16, reg1, reg2 imm16, reg1, reg2 imm32, reg1 imm16, reg1, reg2 imm16, reg1, reg2 imm16, reg1, reg2 imm16, reg1, reg2 disp16 [reg1], reg2 disp16 [reg1], reg2 disp16 [reg1], reg2 reg2, disp16 [reg1] reg2, disp16 [reg1] reg2, disp16 [reg1] disp16 [reg1], reg2 disp16 [reg1], reg2 bit#3, disp16 [reg1] bit#3, disp16 [reg1] bit#3, disp16 [reg1] bit#3, disp16 [reg1] rrrrr0000110dddd rrrrr0000111dddd rrrrr0110ddddddd rrrrr0111ddddddd rrrrr1000ddddddd rrrrr1001ddddddd rrrrr1010dddddd0 rrrrr1010dddddd1 V rrrrr11110dddddd 0000011110dddddd ddddddddddddddd0 ddddddddddddddd0 iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii Note VI rrrrr110000RRRRR rrrrr110001RRRRR rrrrr110010RRRRR rrrrr110011RRRRR 00000110001RRRRR rrrrr110100RRRRR rrrrr110101RRRRR rrrrr110110RRRRR rrrrr110111RRRRR iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii dddddddddddddddd ddddddddddddddd0 ddddddddddddddd1 dddddddddddddddd ddddddddddddddd0 ddddddddddddddd1 ddddddddddddddd1 ddddddddddddddd1 dddddddddddddddd dddddddddddddddd dddddddddddddddd dddddddddddddddd VII rrrrr111000RRRRR rrrrr111001RRRRR rrrrr111001RRRRR rrrrr111010RRRRR rrrrr111011RRRRR rrrrr111011RRRRR rrrrr11110bRRRRR rrrrr111111RRRRR VIII 00bbb111110RRRRR 01bbb111110RRRRR 10bbb111110RRRRR 11bbb111110RRRRR Note 32-bit immediate data. The higher 32 bits (bits 16 to 47) are as follows. 31 16 47 32 iiiiiiiiiiiiiiii IIIIIIIIIIIIIIII User's Manual U15943EJ2V0UM 181 APPENDIX A INSTRUCTION LIST Table A-2. Instruction List (in Format Order) (3/3) Format Opcode Mnemonic Operand 15 IX 0 31 16 SETF LDSR STSR SHR SAR SHL SET1 NOT1 CLR1 TST1 SASF TRAP HALT RETI CTRET DBRET DI EI MUL MULU DIVH DIVHU DIV DIVU CMOV MUL MULU CMOV BSW BSH HSW DISPOSE DISPOSE PREPARE PREPARE cccc, reg2 reg2, regID regID, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg2, [reg1] reg2, [reg1] reg2, [reg1] reg2, [reg1] cccc, reg2 vector - - - - - - reg1, reg2, reg3 reg1, reg2, reg3 reg1, reg2, reg3 reg1, reg2, reg3 reg1, reg2, reg3 reg1, reg2, reg3 cccc, reg1, reg2, reg3 imm9, reg2, reg3 imm9, reg2, reg3 cccc, imm5, reg2, reg3 reg2, reg3 reg2, reg3 reg2, reg3 imm5, list12, [reg1] imm5, list12 list12, imm5 list12, imm5, sp/imm rrrrr1111110cccc rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr1111110cccc 0000000000000000 0000000000100000 0000000001000000 0000000010000000 0000000010100000 0000000011000000 0000000011100000 0000000011100010 0000000011100100 0000000011100110 0000001000000000 0000000100000000 0000000100100000 0000000101000000 0000000101000100 0000000101000110 0000000101100000 0000000101100000 wwwww01000100000 wwwww01000100010 wwwww01010000000 wwwww01010000010 wwwww01011000000 wwwww01011000010 wwwww011001cccc0 wwwww01001IIII00 wwwww01001IIII10 wwwww011000cccc0 wwwww01101000000 wwwww01101000010 wwwww01101000100 LLLLLLLLLLLRRRRR LLLLLLLLLLL00000 LLLLLLLLLLL00001 LLLLLLLLLLLff011 X 00000111111iiiii 0000011111100000 0000011111100000 0000011111100000 0000011111100000 0000011111100000 1000011111100000 XI rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR rrrrr111111RRRRR XII rrrrr111111iiiii rrrrr111111iiiii rrrrr111111iiiii rrrrr11111100000 rrrrr11111100000 rrrrr11111100000 XIII 0000011001iiiiiL 0000011001iiiiiL 0000011110iiiiiL 0000011110iiiiiL 182 User's Manual U15943EJ2V0UM APPENDIX B INSTRUCTION OPCODE MAP This chapter shows the opcode map for the instruction code shown below. (1) 16-bit format instruction 15 11 10 Opcode (see [a]) Sub-opcode (see [b]) 5 4 0 (2) 32-bit format instruction 15 14 13 12 11 10 Opcode (see [a]) Sub-opcode (see [h]) Sub-opcode (see [d], [h]) 5 4 0 31 27 26 Sub-opcode (see [e]) Sub-opcode (see [c]) Sub-opcode (see [f], [g], [i]) 21 20 19 18 17 16 Remark Operand convention Symbol R r Meaning reg1: General-purpose register (used as source register) reg2: General-purpose register (mainly used as destination register. Some are also used as source registers.) reg3: General-purpose register (mainly used as remainder of division results or higher 32 bits of multiply results) 3-bit data for bit number specification x-bit immediate data x-bit displacement data 4-bit data condition code specification w bit#3 immx dispx cccc User's Manual U15943EJ2V0UM 183 APPENDIX B INSTRUCTION OPCODE MAP [a] Opcode Bit 10 0 Bit 9 0 Bit 8 0 Bit 7 0 0,0 MOV R, r NOPNote 1 NOT 0,1 Bits 6, 5 1,0 DIVH SWITCHNote 2 DBTRAP UndefinedNote 3 SATADD R, r ZXHNote 4 AND ADD R, r ADD imm5, r Note 4 Format 1,1 JMP SLD.BUNote 5 SLD.HUNote 6 I, IV 0 0 0 1 SATSUBR ZXBNote 4 OR SUBR MOV imm5, r CALLT Note 4 SATSUB SXBNote 4 XOR SUB SATADD imm5, r MULH SXHNote 4 TST CMP R, r CMP imm5, r I 0 0 0 0 0 1 1 1 0 0 1 0 II 0 1 0 1 SHR imm5, r SAR imm5, r SHL imm5, r MULH imm5, r UndefinedNote 4 IV 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 SLD.B SST.B SLD.H SST.H SLD.WNote 7 SST.WNote 7 Bcond ADDI MOVEA MOV imm32, RNote 4 XORI LD.HNote 8 LD.WNote 8 MOVHI DISPOSE ANDI Note 4 1 1 0 1 1 0 1 0 III SATSUBI VI, XIII 1 1 0 1 ORI MULHI UndefinedNote 4 ST.HNote 8 ST.WNote 8 VI 1 1 1 0 LD.B ST.B VII 1 1 1 1 JR JARL LD.BUNote 10 PREPARENote 11 Bit manipulation 1Note 9 LD.HUNote 10 UndefinedNote 11 Expansion 1Note 12 V, VII, VIII, XIII Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. If R (reg1) = r0 and r (reg2) = r0 (instruction without reg1 and reg2) If R (reg1) r0 and r (reg2) = r0 (instruction with reg1 and without reg2) If R (reg1) = r0 and r (reg2) r0 (instruction without reg1 and with reg2) If r (reg2) = r0 (instruction without reg2) If bit 4 = 0 and r (reg2) r0 (instruction with reg2) If bit 4 = 1 and r (reg2) r0 (instruction with reg2) See [b] See [c] See [d] 10. If bit 16 = 1 and r (reg2) r0 (instruction with reg2) 11. If bit 16 = 1 and r (reg2) = r0 (instruction without reg2) 12. See [e] 184 User's Manual U15943EJ2V0UM APPENDIX B INSTRUCTION OPCODE MAP [b] Short format load/store instruction (displacement/sub-opcode) Bit 10 Bit 9 Bit 8 Bit 7 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 SLD.B SST.B SLD.H SST.H SLD.W SST.W Bit 0 1 [c] Load/store instruction (displacement/sub-opcode) Bit 6 Bit 5 0 0 0 1 1 0 1 0 1 LD.B LD.H ST.B ST.H ST.W LD.W Bit 16 1 [d] Bit manipulation instruction 1 (sub-opcode) Bit 15 0 0 1 SET1 bit#3, disp16 [R] CLR1 bit#3, disp16 [R] Bit 14 1 NOT1 bit#3, disp16 [R] TST1 bit#3, disp16 [R] User's Manual U15943EJ2V0UM 185 APPENDIX B INSTRUCTION OPCODE MAP [e] Expansion 1 (sub-opcode) Bit 26 Bit 25 Bit 24 Bit 23 0,0 0 0 0 0 0 0 0 0 1 0 1 0 SETF SHR TRAP LDSR SAR HALT 0,1 STSR SHL RETI CTRETNote 2 DBRETNote 2 Undefined Undefined MUL R, r, w MULU R, r, wNote 4 MUL imm9, r, w MULU imm9, r, wNote 4 DIV DIVUNote 4 CMOV cccc, R, r, w BSWNote 5 BSHNote 5 HSWNote 5 Undefined Note 2 Bits 22, 21 1,0 1,1 Undefined Bit manipulation 2 EINote 3 DINote 3 Undefined Note 1 Format IX X 0 0 0 1 1 0 1 0 Undefined SASF - IX, XI, XII 0 1 0 1 DIVH DIVHUNote 4 CMOV cccc, imm5, r, w XI 0 1 1 0 XI, XII 0 1 1 x 1 x 1 x Illegal instruction - Notes 1. 2. 3. 4. 5. See [f] See [g] See [h] If bit 17 = 1 See [i] [f] Bit manipulation instruction 2 (sub-opcode) Bit 18 0 0 1 SET1 r, [R] CLR1 r, [R] Bit 17 1 NOT1 r, [R] TST1 r, [R] [g] Return instruction (sub-opcode) Bit 18 0 0 1 RETI CTRET Bit 17 1 Undefined DBRET 186 User's Manual U15943EJ2V0UM APPENDIX B INSTRUCTION OPCODE MAP [h] PSW operation instruction (sub-opcode) Bit 15 Bit 14 0,0,0 0 0 1 1 0 1 0 1 DI Undefined EI Undefined Undefined 0,0,1 Undefined 0,1,0 Bits 13, 12, 11 0,1,1 1,0,0 1,0,1 1,1,0 1,1,1 [i] Endian conversion instruction (sub-opcode) Bit 18 0 0 1 BSW HSW BSH Undefined Bit 17 1 User's Manual U15943EJ2V0UM 187 APPENDIX C DIFFERENCES IN ARCHITECTURE OF V850 CPU AND V850E1 CPU (1/3) Item Instructions (including operand) BSH reg2, reg3 BSW reg2, reg3 CALLT imm6 CLR1 reg2, [reg1] CMOV cccc, imm5, reg2, reg3 CMOV cccc, reg1, reg2, reg3 CTRET DBRET DBTRAP DISPOSE imm5, list12 DISPOSE imm5, list12 [reg1] DIV reg1, reg2, reg3 DIVH reg1, reg2, reg3 DIVHU reg1, reg2, reg3 DIVU reg1, reg2, reg3 HSW reg2, reg3 LD.BU disp16 [reg1], reg2 LD.HU disp16 [reg1], reg2 MOV imm32, reg1 MUL imm9, reg2, reg3 MUL reg1, reg2, reg3 MULU reg1, reg2, reg3 MULU imm9, reg2, reg3 NOT1 reg2, [reg1] PREPARE list12, imm5 PREPARE list12, imm5, sp/imm SASF cccc, reg2 SET1 reg2, [reg1] SLD.BU disp4 [ep], reg2 SLD.HU disp5 [ep], reg2 SWITCH reg1 SXB reg1 SXH reg1 TST1 reg2, [reg1] ZXB reg1 ZXH reg1 Provided Provided ProvidedNote V850ES CPU Provided V850E1 CPU V850 CPU Not provided Note Not supported in the NB85E and NB85ET 188 User's Manual U15943EJ2V0UM APPENDIX C DIFFERENCES IN ARCHITECTURE OF V850 CPU AND V850E1 CPU (2/3) Item Instruction format Format IV Format XI Format XII Format XIII Number of instruction clocks executed (except MUL, MULU instructions) MUL, MULU instructions Program space Number of clocks differs partially between the V850ES and V850E1 CPUs and the V850 CPU 1/4/5 clocks 64 MB linear (usable area: 16 MB + 60 KB) Lower 26 bits Provided 1/2/2 clocks 64 MB linear Not provided 16 MB linear V850ES CPU V850E1 CPU V850 CPU Format of some instructions differs between the V850ES and V850E1 CPUs and the V850 CPU. Provided Not provided Valid bits of program counter (PC) System register CALLT execution status saving registers (CTPC, CTPSW) Exception/debug trap status saving registers (DBPC, DBPSW) CALLT base pointer (CTBP) Debug interface register (DIR) Breakpoint control registers 0 and 1 (BPC0, BPC1) Program ID register (ASID) Breakpoint address setting registers 0 and 1 (BPAV0, BPAV1) Breakpoint address mask registers 0 and 1 (BPAM0, BPAM1) Breakpoint data setting registers 0 and 1 (BPDV0, BPDV1) Breakpoint data mask registers 0 and 1 (BPDM0, BPDM1) Exception trap status saving registers Illegal instruction code Misaligned access enable/disable setting Lower 24 bits Not provided Not provided ProvidedNote 1 DBPC, DBPSW Instruction code areas differ. Fixed to enable Can be set depending on product EIPC, EIPSW Cannot be set. (misaligned access disabled) 1 Non-maskable interrupt (NMI) Input Exception code Handler address 3Note 2 0010H, 0020H Note 2 , 0030H Note 2 0010H 00000010H Not provided 00000010H, 00000020H 00000030HNote 2 Provided Note 2 , Debug trap ProvidedNote 3 Notes 1. 2. 3. Used only for the NU85E and NU85ET Some products do not have this function. Not supported in the NB85E and NB85ET User's Manual U15943EJ2V0UM 189 APPENDIX C DIFFERENCES IN ARCHITECTURE OF V850 CPU AND V850E1 CPU (3/3) Item Pipeline * Word data multiply instruction * Arithmetic operation instruction other than word data multiply instruction * Branch instruction * Bit manipulation instruction * Special instruction (TRAP, RETI) V850ES CPU Note 1 Note 2 V850E1 CPU Note 1 V850 CPU No instructions Note 2 Notes 1. 2. The pipeline flow differs between the V850ES CPU core and the V850E1 CPU core. For details, refer to CHAPTER 8 PIPELINE and V850E1 Architecture User's Manual (U14559E). The pipeline flow differs between the V850ES and V850E1 CPU cores and the V850 CPU core. For details, refer to CHAPTER 8 PIPELINE, V850E1 Architecture User's Manual (U14559E), and V850 Series Architecture User's Manual (U10243E). 190 User's Manual U15943EJ2V0UM APPENDIX D INSTRUCTIONS ADDED FOR V850ES CPU COMPARED WITH V850 CPU Compared with the instruction codes of the V850 CPU, the instruction codes of the V850ES CPU are upwardly compatible at the object code level. In the case of the V850ES CPU, instructions that even if executed have no meaning in the case of the V850 CPU (mainly instructions performing write to the r0 register) are extended as additional instructions. The following table shows the V850 CPU instructions corresponding to the instruction codes added in the V850ES CPU. See the table when switching from products that incorporate the V850 CPU to products that incorporate the V850ES CPU. Since the V850ES CPU is compatible with all the instruction codes of the V850E1 CPU, these products are replaced easily. Table D-1. Instructions Added to V850ES CPU and V850 CPU Instructions with Same Instruction Code (1/2) Instructions Added in V850ES CPU V850 CPU Instructions with Same Instruction Code as V850ES CPU CALLT imm6 DISPOSE imm5, list12 DISPOSE imm5, list12 [reg1] MOV imm32, reg1 SWITCH reg1 SXB reg1 SXH reg1 ZXB reg1 ZXH reg1 (RFU) (RFU) BSH reg2, reg3 BSW reg2, reg3 CMOV cccc, imm5, reg2, reg3 CMOV cccc, reg1, reg2, reg3 CTRET DIV reg1, reg2, reg3 DIVH reg1, reg2, reg3 DIVHU reg1, reg2, reg3 DIVU reg1, reg2, reg3 HSW reg2, reg3 MUL imm9, reg2, reg3 MUL reg1, reg2, reg3 MULU reg1, reg2, reg3 MULU imm9, reg2, reg3 SASF cccc, reg2 User's Manual U15943EJ2V0UM MOV imm5, r0 or SATADD imm5, r0 MOVHI imm16, reg1, r0 or SATSUBI imm16, reg1, r0 MOVHI imm16, reg1, r0 or SATSUBI imm16, reg1, r0 MOVEA imm16, reg1, r0 DIVH reg1, r0 SATSUB reg1, r0 MULH reg1, r0 SATSUBR reg1, r0 SATADD reg1, r0 MULH imm5, r0 MULHI imm16, reg1, r0 Illegal instruction 191 APPENDIX D INSTRUCTIONS ADDED FOR V850ES CPU COMPARED WITH V850 CPU Table D-1. Instructions Added to V850ES CPU and V850 CPU Instructions with Same Instruction Code (2/2) Instructions Added in V850ES CPU V850 CPU Instructions with Same Instruction Code as V850ES CPU CLR1 reg2, [reg1] DBRET DBTRAP LD.BU disp16 [reg1], reg2 LD.HU disp16 [reg1], reg2 NOT1 reg2, [reg1] PREPARE list12, imm5 PREPARE list12, imm5, sp/imm SET1 reg2, [reg1] SLD.BU disp4 [ep], reg2 SLD.HU disp5 [ep], reg2 TST1 reg2, [reg1] Undefined 192 User's Manual U15943EJ2V0UM APPENDIX E INDEX [Numeral] 16-bit format instruction ........................................ 183 16-bit load/store instruction format ......................... 36 2-clock branch ...................................................... 148 3-operand instruction format ................................... 37 32-bit format instruction ........................................ 183 32-bit load/store instruction format ......................... 37 CTPSW .................................................................. 24 CTRET ................................................................... 57 CTRET instruction (pipeline) ................................ 157 [D] Data alignment ....................................................... 28 Data format ............................................................. 26 Data representation ................................................ 28 Data type ................................................................ 26 DBPC ..................................................................... 25 DBPSW .................................................................. 25 DBRET ................................................................... 58 DBRET instruction (pipeline) ................................ 161 DBTRAP ................................................................. 59 DBTRAP instruction (pipeline) .............................. 161 Debug function instructions .................................... 42 Debug function instructions (pipeline) .................. 161 Debug trap ............................................................ 141 DI ............................................................................ 60 DI instruction (pipeline) ......................................... 157 DISPOSE ................................................................ 61 DISPOSE instruction (pipeline) ............................ 158 DIV ......................................................................... 63 DIVH ....................................................................... 64 DIVHU .................................................................... 66 Divide instructions (pipeline) ................................ 153 DIVU ....................................................................... 67 [A] ADD ........................................................................ 45 ADDI ....................................................................... 46 Additional items related to pipeline ....................... 166 Address space ........................................................ 29 Addressing mode .................................................... 31 Alignment hazard................................................... 162 AND ........................................................................ 47 ANDI ....................................................................... 48 Arithmetic operation instructions ............................. 40 Arithmetic operation instructions (pipeline) ........... 153 [B] Based addressing ................................................... 33 Bcond ...................................................................... 49 Bit ...................................................................... 27, 28 Bit addressing ......................................................... 34 Bit manipulation instruction format .......................... 37 Bit manipulation instructions ................................... 41 Bit manipulation instructions (pipeline) ................. 156 BR instruction (pipeline) ........................................ 155 Branch instructions ................................................. 41 Branch instructions (pipeline) ............................... 154 BSH ........................................................................ 51 BSW ........................................................................ 52 Byte ......................................................................... 27 [E] ECR ........................................................................ 22 Efficient pipeline processing ................................. 149 EI ............................................................................ 68 EIPC ....................................................................... 21 EIPSW .................................................................... 21 EI instruction (pipeline) ......................................... 157 Exception cause register ........................................ 22 Exception/debug trap status saving registers ......... 25 Exception processing ........................................... 139 Exception trap ...................................................... 140 Extended instruction format 1 ................................. 37 Extended instruction format 2 ................................. 38 Extended instruction format 3 ................................. 38 Extended instruction format 4 ................................. 38 [C] CALLT ..................................................................... 53 CALLT base pointer ................................................ 25 CALLT caller status saving registers ...................... 24 CALLT instruction (pipeline) ................................. 156 Cautions when creating programs ........................ 165 CLR1 ....................................................................... 54 CLR1 instruction (pipeline) ................................... 156 CMOV ..................................................................... 55 CMP ........................................................................ 56 Conditional branch instruction format ..................... 36 CTBP ...................................................................... 25 CTPC ...................................................................... 24 [F] FEPC ...................................................................... 22 FEPSW ................................................................... 22 Format I .................................................................. 35 Format II ................................................................. 35 User's Manual U15943EJ2V0UM 193 APPENDIX E INDEX Format III .................................................................36 Format IV ................................................................36 Format IX ................................................................37 Format V .................................................................36 Format VI ................................................................37 Format VII ...............................................................37 Format VIII ..............................................................37 Format X .................................................................38 Format XI ................................................................38 Format XII ...............................................................38 Format XIII ..............................................................38 Load instructions .................................................... 39 Load instructions (pipeline) .................................. 150 Logical operation instructions ................................. 40 Logical operation instructions (pipeline) ............... 154 [M] Maskable interrupt ................................................ 136 Memory map ........................................................... 30 MOV ....................................................................... 80 MOVEA ................................................................... 81 Move word instruction (pipeline) ........................... 153 MOVHI .................................................................... 82 MUL ........................................................................ 83 MULH ..................................................................... 84 MULHI .................................................................... 85 Multiply instructions ................................................ 39 Multiply instructions (pipeline) .............................. 151 MULU ..................................................................... 86 [G] General-purpose registers ......................................19 [H] Halfword ..................................................................27 HALT .......................................................................69 HALT instruction (pipeline) ....................................158 Harvard architecture .............................................166 HSW ........................................................................70 [N] NMI status saving registers .................................... 22 Non-blocking load/store......................................... 147 Non-maskable interrupt ........................................ 138 NOP ........................................................................ 87 NOP instruction (pipeline) ..................................... 159 NOT ........................................................................ 88 NOT1 ...................................................................... 89 NOT1 instruction (pipeline) ................................... 156 [I] imm-reg instruction format ......................................35 Immediate addressing .............................................33 Instruction address ..................................................31 Instruction format ....................................................35 Instruction opcode map .........................................183 Instruction set ..........................................................43 Integer .....................................................................28 Internal configuration ..............................................17 Interrupt servicing .................................................136 Interrupt status saving registers ..............................21 [O] Operand address .................................................... 33 OR .......................................................................... 90 ORI ......................................................................... 91 [J] JARL .......................................................................71 JMP .........................................................................72 JMP instruction (pipeline) ......................................155 JR ............................................................................73 Jump instruction format ...........................................36 [P] PC ........................................................................... 19 Pipeline ................................................................. 145 Pipeline disorder ................................................... 162 Pipeline flow during execution of instructions ....... 150 PREPARE ............................................................... 92 PREPARE instruction (pipeline) ........................... 159 Program counter...................................................... 19 Program registers ................................................... 19 Program status word .............................................. 23 PSW ....................................................................... 23 [L] LD instructions ........................................................39 LD instructions (pipeline) ......................................150 LD.B ........................................................................74 LD.BU .....................................................................75 LD.H ........................................................................76 LD.HU .....................................................................77 LD.W .......................................................................78 LDSR ......................................................................79 LDSR instruction (pipeline) ...................................158 [R] r0 to r31 .................................................................. 19 reg-reg instruction format ....................................... 35 Register addressing ................................................ 33 Register addressing (register indirect) .................... 32 194 User's Manual U15943EJ2V0UM APPENDIX E INDEX Register set ............................................................. 18 Register status after reset ..................................... 144 Relative addressing (PC relative) ........................... 31 Reset .................................................................... 144 Restoring from exception trap and debug trap ..... 143 Restoring from interrupt/exception processing ..... 142 RETI ........................................................................ 94 RETI instruction (pipeline) .................................... 159 [T] TRAP .................................................................... 124 TRAP instruction (pipeline) ................................... 160 TST ....................................................................... 125 TST1 ..................................................................... 126 TST1 instruction (pipeline) ................................... 156 [U] [S] SAR ........................................................................ 96 SASF ...................................................................... 97 SATADD ................................................................. 98 SATSUB .................................................................. 99 SATSUBI ............................................................... 100 SATSUBR ............................................................. 101 Saturated operation instructions ............................. 40 Saturated operation instructions (pipeline) ........... 154 SET1 ..................................................................... 102 SET1 instruction (pipeline) .................................... 156 SETF ..................................................................... 103 SHL ....................................................................... 105 Short path ............................................................. 167 SHR ...................................................................... 106 SLD.B ................................................................... 107 SLD.BU ................................................................. 108 SLD.H ................................................................... 109 SLD.HU ................................................................. 110 SLD.W .................................................................. 111 SLD instructions ...................................................... 39 SLD instructions (pipeline) .................................... 150 Software exception ............................................... 139 Special instructions ................................................. 41 Special instructions (pipeline) ............................... 156 SST.B ................................................................... 112 SST.H ................................................................... 113 SST.W .................................................................. 114 SST instructions ...................................................... 39 ST.B ...................................................................... 115 ST.H ...................................................................... 116 ST.W ..................................................................... 117 ST instructions ........................................................ 39 Stack manipulation instruction format 1 .................. 38 Starting up ............................................................ 144 Store instructions .................................................... 39 Store instructions (pipeline) .................................. 151 STSR .................................................................... 118 STSR instruction (pipeline) ................................... 158 SUB ...................................................................... 119 SUBR .................................................................... 120 SWITCH ................................................................ 121 SWITCH instruction (pipeline) .............................. 160 SXB ....................................................................... 122 SXH ...................................................................... 123 System registers ..................................................... 20 Unconditional branch instructions ........................ 155 Unsigned integer .................................................... 28 [W] Word ....................................................................... 26 [X] XOR ...................................................................... 127 XORI ..................................................................... 128 [Z] ZXB ...................................................................... 129 ZXH ...................................................................... 130 User's Manual U15943EJ2V0UM 195 APPENDIX F REVISION HISTORY A history of the revisions up to this edition is shown below. "Applied to:" indicates the chapters to which the revision was applied. Edition 2nd Revisions from Previous Edition Modification of description of V850ES CPU core in Figure 1-1 V850 Series CPU Development Addition of description of Caution in 5.3 Instruction Set MUL Addition of description of Caution in 5.3 Instruction Set MULU Modification of description of pipeline in APPENDIX C DIFFERENCES IN ARCHITECTURE OF V850 CPU AND V850E1 CPU APPENDIX C DIFFERENCES IN ARCHITECTURE OF V850 CPU AND V850E1 CPU APPENDIX F REVISION HISTORY Applied to: CHAPTER 1 GENERAL CHAPTER 5 INSTRUCTION Addition of APPENDIX F REVISION HISTORY 196 User's Manual U15943EJ2V0UM Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: +1-800-729-9288 +1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Market Communication Dept. Fax: +82-2-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6462-6829 P.R. China NEC Electronics Shanghai, Ltd. Fax: +86-21-6841-1137 Taiwan NEC Electronics Taiwan Ltd. Fax: +886-2-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: +81- 44-435-9608 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. 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