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| 8VHU(c)V 0DQXDO V850ES/KF1, V850ES/KG1, V850ES/KJ1 %LW 6LQJOH&KLS 0LFURFRQWUROOHUV +DUGZDUH 9(6.) 3' 3' $ $ $ 3'< 3'< $ $ $ 3' 3' $ $ $ 3'< 3'< $ $ $ 3' 3' $ $ $ 3'< 3'< $ $ $ 3') 3') $ 3')< 3')< $ 9(6.* 3' 3' $ $ $ 3'< 3'< $ $ $ 3' 3' $ $ $ 3'< 3'< $ $ $ 3' 3' $ $ $ 3'< 3'< $ $ $ 3') 3') $ 3')< 3')< $ 9(6.- 3' 3' $ $ $ 3'< 3'< $ $ $ 3' 3' $ $ $ 3'< 3'< $ $ $ 3') 3') $ 3')< 3')< $ 'RFXPHQW 1R 8(-98' WK HGLWLRQ 'DWH 3XEOLVKHG $XJXVW 16 &3 . 3ULQWHG LQ -DSDQ [MEMO] 2 User's Manual U15862EJ4V1UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC Electronics I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. 2 2 2 2 User's Manual U15862EJ4V1UD 3 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of May, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U15862EJ4V1UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 J03.4 User's Manual U15862EJ4V1UD 5 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 and design application systems using these products. The target products are as follows. * Standard products: PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y, 703212, 703212Y, 703213, 703213Y, 703214, 703214Y, 703216, 703216Y, 703217, 703217Y, 70F3210, 70F3210Y, 70F3214, 70F3214Y, 70F3217, 70F3217Y * Special products: PD703208(A), 703208Y(A), 703209(A), 703209Y(A), 703210(A), 703210Y(A), 703212(A), 703212Y(A), 703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A), 70F3210Y(A), 70F3214(A), 70F3214Y(A), 703208Y(A1), 703210Y(A1), 703213Y(A1), 703216Y(A1), 703208Y(A2), 703210Y(A2), 703213Y(A2), 70F3217(A), 703209(A1), 703212(A1), 703214(A1), 703217(A1), 703209(A2), 703212(A2), 703214(A2), 70F3217Y(A), 703209Y(A1), 703212Y(A1), 703214Y(A1), 703217Y(A1), 703209Y(A2), 703212Y(A2), 703214Y(A2), 703208(A1), 703210(A1), 703213(A1), 703216(A1), 703208(A2), 703210(A2), 703213(A2), 703216(A2), 703216Y(A2), 703217(A2), 703217Y(A2) Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User's Manual). Hardware * Pin functions * CPU function * On-chip peripheral functions * Flash memory programming * Electrical specifications Architecture * Data types * Register set * Instruction format and instruction set * Interrupts and exceptions * Pipeline operation 6 User's Manual U15862EJ4V1UD How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. Cautions 1. The application examples in this manual apply to "standard" quality grade products for general electronic systems. When using an example in this manual for an application that requires a "special" quality grade product, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. When using this manual as a manual for a special grade product, read the part numbers as follows. PD703208 PD703208Y PD703209 PD703209Y PD703210 PD703210Y PD703212 PD703212Y PD703213 PD703213Y PD703214 PD703214Y PD703216 PD703216Y PD703217 PD703217Y PD70F3210 PD70F3214 PD70F3217 PD703208(A), 703208(A1), 703208(A2) PD703208Y(A), 703208Y(A1), 703208Y(A2) PD703209(A), 703209(A1), 703209(A2) PD703209Y(A), 703209Y(A1), 703209Y(A2) PD703210(A), 703210(A1), 703210(A2) PD703210Y(A), 703210Y(A1), 703210Y(A2) PD703212(A), 703212(A1), 703212(A2) PD703212Y(A), 703212Y(A1), 703212Y(A2) PD703213(A), 703213(A1), 703213(A2) PD703213Y(A), 703213Y(A1), 703213Y(A2) PD703214(A), 703214(A1), 703214(A2) PD703214Y(A), 703214Y(A1), 703214Y(A2) PD703216(A), 703216(A1), 703216(A2) PD703216Y(A), 703216Y(A1), 703216Y(A2) PD703217(A), 703217(A1), 703217(A2) PD703217Y(A), 703217Y(A1), 703217Y(A2) PD70F3210(A) PD70F3214(A) PD70F3217(A) PD70F3210Y PD70F3210Y(A) PD70F3214Y PD70F3214Y(A) PD70F3217Y PD70F3217Y(A) To find the details of a register where the name is known Refer to APPENDIX A REGISTER INDEX. To understand the details of an instruction function Refer to the V850ES Architecture User's Manual. Register format The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the overall functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Read this manual according to the CONTENTS. User's Manual U15862EJ4V1UD 7 To know the electrical specifications of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Refer to CHAPTER 26 ELECTRICAL SPECIFICATIONS. The mark Conventions shows major revised points. Higher digits on the left and lower digits on the right Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary Decimal Hexadecimal K (kilo): G (giga): 10 20 30 Data significance: Memory map address: Note: Caution: Remark: Numeric representation: Active low representation: xxx (overscore over pin or signal name) ... xxxx or xxxxB ... xxxx ... xxxxH Prefix indicating power of 2 (address space, memory capacity): 2 = 1,024 2 3 M (mega): 2 = 1,024 2 = 1,024 8 User's Manual U15862EJ4V1UD Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Document Name V850ES Architecture User's Manual V850ES/KF1, V850ES/KG1, V850ES/KJ1 Hardware User's Manual Document No. U15943E This manual Documents related to development tools (user's manuals) Document Name IE-V850ES-G1 (In-Circuit Emulator) IE-703217-G1-EM1 (In-Circuit Emulator Option Board) CA850 Ver. 2.50 C Compiler Package Operation C Language Assembly Language PM plus Ver. 5.10 ID850 Ver. 2.50 Integrated Debugger SM850 Ver. 2.50 System Simulator SM850 Ver. 2.00 or Later System Simulator RX850 Ver. 3.13 or Later Real-Time OS Operation Operation External Part User Open Interface Specifications Fundamental Installation Technical RX850 Pro Ver. 3.15 Real-Time OS Fundamental Installation Technical RD850 Ver. 3.01 Task Debugger RD850 Pro Ver. 3.01 Task Debugger AZ850 Ver. 3.0 System Performance Analyzer PG-FP3 Flash Memory Programmer PG-FP4 Flash Memory Programmer Document No. U16313E U16594E U16053E U16054E U16042E U16569E U16217E U15182E U14873E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U13502E U15260E User's Manual U15862EJ4V1UD 9 CONTENTS CHAPTER 1 INTRODUCTION..................................................................................................................19 1.1 K1 Family Product Lineup......................................................................................................... 19 1.1.1 1.1.2 V850ES/Kx1 Series lineup............................................................................................................. 19 78K0/Kx1 Series lineup ................................................................................................................. 21 Features (V850ES/KF1) ................................................................................................................ 23 Applications (V850ES/KF1) ........................................................................................................... 24 Ordering information (V850ES/KF1) .............................................................................................. 25 Pin configuration (top view) (V850ES/KF1) ................................................................................... 27 Function block configuration (V850ES/KF1) .................................................................................. 30 Features (V850ES/KG1)................................................................................................................ 34 Applications (V850ES/KG1)........................................................................................................... 35 Ordering information (V850ES/KG1) ............................................................................................. 35 Pin configuration (top view) (V850ES/KG1) ................................................................................... 37 Function block configuration (V850ES/KG1) ................................................................................. 40 Features (V850ES/KJ1)................................................................................................................. 44 Applications (V850ES/KJ1)............................................................................................................ 45 Ordering information (V850ES/KJ1) .............................................................................................. 45 Pin configuration (top view) (V850ES/KJ1).................................................................................... 47 Function block configuration (V850ES/KJ1) .................................................................................. 50 1.2 V850ES/KF1 ................................................................................................................................ 23 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.3 V850ES/KG1................................................................................................................................ 34 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.4 V850ES/KJ1................................................................................................................................. 44 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.5 Overview of Functions............................................................................................................... 54 CHAPTER 2 PIN FUNCTIONS ................................................................................................................57 2.1 List of Pin Functions.................................................................................................................. 58 2.2 Pin Status.................................................................................................................................... 67 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 70 2.4 Pin I/O Circuits............................................................................................................................ 73 CHAPTER 3 CPU FUNCTIONS...............................................................................................................75 3.1 Features ...................................................................................................................................... 75 3.2 CPU Register Set........................................................................................................................ 76 3.2.1 3.2.2 Program register set ...................................................................................................................... 77 System register set ........................................................................................................................ 78 3.3 3.4 Operation Modes ........................................................................................................................ 84 Address Space ........................................................................................................................... 85 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 CPU address space....................................................................................................................... 85 Wraparound of CPU address space .............................................................................................. 86 Memory map.................................................................................................................................. 87 Areas ............................................................................................................................................. 89 Recommended use of address space ........................................................................................... 94 Peripheral I/O registers .................................................................................................................. 97 Special registers .......................................................................................................................... 109 Cautions ...................................................................................................................................... 112 User's Manual U15862EJ4V1UD 10 CHAPTER 4 PORT FUNCTIONS ..........................................................................................................115 4.1 Features .....................................................................................................................................115 4.1.1 4.1.2 4.1.3 V850ES/KF1.................................................................................................................................115 V850ES/KG1 ................................................................................................................................115 V850ES/KJ1 .................................................................................................................................115 V850ES/KF1.................................................................................................................................116 V850ES/KG1 ................................................................................................................................117 V850ES/KJ1 .................................................................................................................................118 Port 0............................................................................................................................................125 Port 1............................................................................................................................................129 Port 3............................................................................................................................................131 Port 4............................................................................................................................................138 Port 5............................................................................................................................................141 Port 6............................................................................................................................................145 Port 7............................................................................................................................................151 Port 8............................................................................................................................................153 Port 9............................................................................................................................................157 4.2 Basic Port Configuration..........................................................................................................116 4.2.1 4.2.2 4.2.3 4.3 Port Configuration ....................................................................................................................119 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 Port CD.........................................................................................................................................169 4.3.11 Port CM ........................................................................................................................................172 4.3.12 Port CS.........................................................................................................................................176 4.3.13 Port CT .........................................................................................................................................180 4.3.14 Port DH.........................................................................................................................................184 4.3.15 Port DL .........................................................................................................................................188 4.4 4.5 4.6 Block Diagrams .........................................................................................................................191 Port Register Setting When Alternate Function Is Used.......................................................217 Cautions.....................................................................................................................................225 4.6.1 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) ...................................................225 Hysteresis Characteristics ............................................................................................................226 CHAPTER 5 BUS CONTROL FUNCTION...........................................................................................227 5.1 Features .....................................................................................................................................227 5.2 Bus Control Pins .......................................................................................................................227 5.2.1 5.2.2 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ...................229 Pin status in each operation mode ...............................................................................................229 Chip select control function ..........................................................................................................233 5.3 5.4 5.5 Memory Block Function ...........................................................................................................230 5.3.1 External Bus Interface Mode Control Function .....................................................................233 Bus Access................................................................................................................................234 5.5.1 5.5.2 5.5.3 Number of clocks for access ........................................................................................................234 Bus size setting function...............................................................................................................234 Access by bus size .......................................................................................................................235 Programmable wait function .........................................................................................................242 External wait function ...................................................................................................................243 Relationship between programmable wait and external wait........................................................244 Programmable address wait function ...........................................................................................245 User's Manual U15862EJ4V1UD 5.6 Wait Function ............................................................................................................................242 5.6.1 5.6.2 5.6.3 5.6.4 11 5.7 5.8 Idle State Insertion Function................................................................................................... 246 Bus Hold Function ................................................................................................................... 247 5.8.1 5.8.2 5.8.3 Functional outline......................................................................................................................... 247 Bus hold procedure...................................................................................................................... 248 Operation in power save mode .................................................................................................... 248 5.9 5.10 5.11 Bus Priority ............................................................................................................................... 249 Bus Timing................................................................................................................................ 250 Cautions .................................................................................................................................... 256 CHAPTER 6 CLOCK GENERATION FUNCTION................................................................................257 6.1 Overview ................................................................................................................................... 257 6.2 Configuration............................................................................................................................ 258 6.3 Control Registers ..................................................................................................................... 260 6.4 Operation .................................................................................................................................. 264 6.4.1 6.4.2 6.4.3 Operation of each clock ............................................................................................................... 264 Clock output function ................................................................................................................... 264 External clock input function ........................................................................................................ 264 Overview...................................................................................................................................... 265 Control register ............................................................................................................................ 265 Usage .......................................................................................................................................... 266 6.5 PLL Function ............................................................................................................................ 265 6.5.1 6.5.2 6.5.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05.............................................................267 7.1 Functions .................................................................................................................................. 267 7.2 Configuration............................................................................................................................ 268 7.3 Control Registers ..................................................................................................................... 274 7.4 Operation .................................................................................................................................. 287 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 Operation as interval timer (16 bits)............................................................................................. 287 PPG output operation .................................................................................................................. 290 Pulse width measurement ........................................................................................................... 294 Operation as external event counter............................................................................................ 305 Square-wave output operation..................................................................................................... 308 One-shot pulse output operation.................................................................................................. 311 Cautions ...................................................................................................................................... 317 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51............................................................322 8.1 Functions .................................................................................................................................. 322 8.2 Configuration............................................................................................................................ 323 8.3 Control Registers ..................................................................................................................... 326 8.4 Operation .................................................................................................................................. 329 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 Operation as interval timer (8 bits)............................................................................................... 329 Operation as external event counter (8 bits) ................................................................................ 331 Square-wave output operation (8-bit resolution) .......................................................................... 332 8-bit PWM output operation ......................................................................................................... 334 Operation as interval timer (16 bits)............................................................................................. 337 Operation as external event counter (16 bits) .............................................................................. 339 Square-wave output operation (16-bit resolution) ........................................................................ 340 Cautions ...................................................................................................................................... 341 User's Manual U15862EJ4V1UD 12 CHAPTER 9 8-BIT TIMERS H0 AND H1 ...........................................................................................342 9.1 Functions ...................................................................................................................................342 9.2 Configuration.............................................................................................................................342 9.3 Control Registers ......................................................................................................................345 9.4 Operation ...................................................................................................................................349 9.4.1 9.4.2 9.4.3 Operation as interval timer/square wave output ...........................................................................349 PWM output mode operation........................................................................................................352 Carrier generator mode operation ................................................................................................358 CHAPTER 10 INTERVAL TIMER, WATCH TIMER ............................................................................365 10.1 Interval Timer BRG ...................................................................................................................365 10.1.1 Functions ......................................................................................................................................365 10.1.2 Configuration ................................................................................................................................365 10.1.3 Registers ......................................................................................................................................367 10.1.4 Operation......................................................................................................................................369 10.2 Watch Timer...............................................................................................................................370 10.2.1 Functions ......................................................................................................................................370 10.2.2 Configuration ................................................................................................................................370 10.2.3 Registers ......................................................................................................................................371 10.2.4 Operation......................................................................................................................................373 10.3 Cautions.....................................................................................................................................374 CHAPTER 11 WATCHDOG TIMER FUNCTIONS ...............................................................................376 11.1 Watchdog Timer 1 .....................................................................................................................376 11.1.1 Functions ......................................................................................................................................376 11.1.2 Configuration ................................................................................................................................378 11.1.3 Watchdog timer 1 control register.................................................................................................378 11.1.4 Operation......................................................................................................................................380 11.2 Watchdog Timer 2 .....................................................................................................................382 11.2.1 Functions ......................................................................................................................................382 11.2.2 Configuration ................................................................................................................................383 11.2.3 Watchdog timer 2 control register.................................................................................................383 11.2.4 Operation......................................................................................................................................385 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)....................................................................386 12.1 Function .....................................................................................................................................386 12.2 Configuration.............................................................................................................................387 12.3 RTO Control Registers .............................................................................................................388 12.4 Operation ...................................................................................................................................390 12.5 Usage .........................................................................................................................................391 12.6 Cautions.....................................................................................................................................391 12.7 Security Function......................................................................................................................392 CHAPTER 13 A/D CONVERTER ..........................................................................................................394 13.1 Function .....................................................................................................................................394 13.2 Configuration.............................................................................................................................395 13.3 Registers....................................................................................................................................397 13.4 Relationship Between Analog Input Voltage and A/D Conversion Results........................403 User's Manual U15862EJ4V1UD 13 13.5 Operation .................................................................................................................................. 404 13.5.1 Basic operation ............................................................................................................................ 404 13.5.2 Conversion operation................................................................................................................... 405 13.5.3 Power fail monitoring function...................................................................................................... 405 13.6 13.7 Cautions on Use ....................................................................................................................... 407 How to Read A/D Converter Characteristics Table............................................................... 412 CHAPTER 14 D/A CONVERTER ..........................................................................................................416 14.1 Functions .................................................................................................................................. 416 14.2 Configuration............................................................................................................................ 417 14.3 Registers ................................................................................................................................... 417 14.4 Operation .................................................................................................................................. 419 14.4.1 Operation in normal mode ........................................................................................................... 419 14.4.2 Operation in real-time output mode ............................................................................................. 419 14.4.3 Cautions ...................................................................................................................................... 420 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART)......................................................421 2 15.1 Selecting UART2 or I C1 Mode................................................................................................ 421 15.2 Features .................................................................................................................................... 422 15.3 Configuration............................................................................................................................ 423 15.4 Registers ................................................................................................................................... 425 15.5 Interrupt Requests ................................................................................................................... 431 15.6 Operation .................................................................................................................................. 432 15.6.1 Data format .................................................................................................................................. 432 15.6.2 Transmit operation....................................................................................................................... 433 15.6.3 Continuous transmission operation.............................................................................................. 435 15.6.4 Receive operation........................................................................................................................ 439 15.6.5 Reception error ............................................................................................................................ 440 15.6.6 Parity types and corresponding operation ................................................................................... 442 15.6.7 Receive data noise filter .............................................................................................................. 443 15.7 Dedicated Baud Rate Generator n (BRGn) ............................................................................ 444 15.7.1 Baud rate generator n (BRGn) configuration ............................................................................... 444 15.7.2 Serial clock generation ................................................................................................................ 445 15.7.3 Baud rate setting example ........................................................................................................... 448 15.7.4 Allowable baud rate range during reception ................................................................................ 449 15.7.5 Transfer rate during continuous transmission .............................................................................. 451 15.8 Cautions .................................................................................................................................... 451 CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0) .................................................................452 16.1 Features .................................................................................................................................... 452 16.2 Configuration............................................................................................................................ 453 16.3 Registers ................................................................................................................................... 456 16.4 Operation .................................................................................................................................. 465 16.4.1 Transmission/reception completion interrupt request signal (INTCSI0n) ..................................... 465 16.4.2 Single transfer mode.................................................................................................................... 467 16.4.3 Continuous transfer mode ........................................................................................................... 470 16.5 Output Pins ............................................................................................................................... 478 14 User's Manual U15862EJ4V1UD CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION..........................................................479 17.1 Functions ...................................................................................................................................479 17.2 Configuration.............................................................................................................................480 17.3 Registers....................................................................................................................................482 17.4 Operation ...................................................................................................................................491 17.4.1 3-wire serial I/O mode ..................................................................................................................491 17.4.2 3-wire serial I/O mode with automatic transmit/receive function...................................................495 CHAPTER 18 I C BUS...........................................................................................................................511 2 18.1 Selecting UART2 or I C1 Mode ................................................................................................511 18.2 Features .....................................................................................................................................512 18.3 Configuration.............................................................................................................................515 18.4 Control Registers ......................................................................................................................517 18.5 Functions ...................................................................................................................................530 18.5.1 Pin configuration...........................................................................................................................530 2 18.6 I C Bus Definitions and Control Methods...............................................................................531 18.6.1 Start condition...............................................................................................................................531 18.6.2 Addresses ....................................................................................................................................532 18.6.3 Transfer direction specification .....................................................................................................533 18.6.4 Acknowledge signal (ACK) ...........................................................................................................534 18.6.5 Stop condition...............................................................................................................................535 18.6.6 Wait signal (WAIT)........................................................................................................................536 2 18.7 I C Interrupt Requests (INTIICn) ..............................................................................................538 18.7.1 Master device operation ...............................................................................................................538 18.7.2 Slave device operation (when receiving slave address data (match with SVAn)) ........................541 18.7.3 Slave device operation (when receiving extension code) .............................................................545 18.7.4 Operation without communication ................................................................................................549 18.7.5 Arbitration loss operation (operation as slave after arbitration loss) .............................................549 18.7.6 Operation when arbitration loss occurs (no communication after arbitration loss)........................551 2 18.8 18.9 18.10 18.11 18.12 18.13 18.14 Interrupt Request (INTIICn) Generation Timing and Wait Control .......................................556 Address Match Detection Method ...........................................................................................557 Error Detection ..........................................................................................................................557 Extension Code .........................................................................................................................557 Arbitration..................................................................................................................................558 Wakeup Function ......................................................................................................................559 Communication Reservation ...................................................................................................560 18.14.1 When communication reservation function is enabled (IICRSVn bit of IICFn register = 0)...........560 18.14.2 When communication reservation function is disabled (IICRSVn bit of IICFn register = 1) ..........563 18.15 Cautions.....................................................................................................................................564 18.16 Communication Operations.....................................................................................................564 18.16.1 Master operation 1........................................................................................................................564 18.16.2 Master operation 2........................................................................................................................566 18.16.3 Slave operation.............................................................................................................................567 18.17 Timing of Data Communication...............................................................................................570 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................577 19.1 Overview ....................................................................................................................................577 User's Manual U15862EJ4V1UD 15 19.1.1 Features ...................................................................................................................................... 577 19.2 Non-Maskable Interrupts ......................................................................................................... 584 19.2.1 Operation ..................................................................................................................................... 587 19.2.2 Restore ........................................................................................................................................ 588 19.2.3 NP flag......................................................................................................................................... 589 19.3 Maskable Interrupts ................................................................................................................. 590 19.3.1 Operation ..................................................................................................................................... 590 19.3.2 Restore ........................................................................................................................................ 592 19.3.3 Priorities of maskable interrupts................................................................................................... 593 19.3.4 Interrupt control register (xxlCn) .................................................................................................. 597 19.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2)............................................................................ 602 19.3.6 In-service priority register (ISPR)................................................................................................. 605 19.3.7 Maskable interrupt status flag ...................................................................................................... 606 19.3.8 Watchdog timer mode register 1 (WDTM1) ................................................................................. 607 19.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP6).............................................. 608 19.4.1 Noise elimination ......................................................................................................................... 608 19.4.2 Edge detection............................................................................................................................. 608 19.5 Software Exceptions ................................................................................................................ 611 19.5.1 Operation ..................................................................................................................................... 611 19.5.2 Restore ........................................................................................................................................ 612 19.5.3 Exception status flag (EP) ........................................................................................................... 613 19.6 Exception Trap ......................................................................................................................... 614 19.6.1 Illegal op code.............................................................................................................................. 614 19.6.2 Debug trap ................................................................................................................................... 616 19.7 19.8 19.9 19.10 Multiple Interrupt Servicing Control....................................................................................... 618 Interrupt Response Time......................................................................................................... 620 Periods in Which Interrupts Are Not Acknowledged by CPU.............................................. 621 Cautions .................................................................................................................................... 621 CHAPTER 20 KEY INTERRUPT FUNCTION ......................................................................................622 20.1 Function .................................................................................................................................... 622 20.2 Key Interrupt Control Register................................................................................................ 623 CHAPTER 21 STANDBY FUNCTION ...................................................................................................624 21.1 Overview ................................................................................................................................... 624 21.2 Registers ................................................................................................................................... 627 21.3 HALT Mode ............................................................................................................................... 630 21.3.1 Setting and operation status ........................................................................................................ 630 21.3.2 Releasing HALT mode................................................................................................................. 630 21.4 IDLE Mode................................................................................................................................. 632 21.4.1 Setting and operation status ........................................................................................................ 632 21.4.2 Releasing IDLE mode.................................................................................................................. 632 21.5 STOP Mode ............................................................................................................................... 634 21.5.1 Setting and operation status ........................................................................................................ 634 21.5.2 Releasing STOP mode ................................................................................................................ 634 21.6 21.7 Securing Oscillation Stabilization Time................................................................................. 636 Subclock Operation Mode....................................................................................................... 637 21.7.1 Setting and operation status ........................................................................................................ 637 16 User's Manual U15862EJ4V1UD 21.7.2 Releasing subclock operation mode.............................................................................................637 21.8 Sub-IDLE Mode..........................................................................................................................639 21.8.1 Setting and operation status.........................................................................................................639 21.8.2 Releasing sub-IDLE mode............................................................................................................639 CHAPTER 22 RESET FUNCTION ........................................................................................................641 22.1 Overview ....................................................................................................................................641 22.2 Configuration.............................................................................................................................641 22.3 Operation ...................................................................................................................................642 CHAPTER 23 REGULATOR ..................................................................................................................645 23.1 Overview ....................................................................................................................................645 23.2 Operation ...................................................................................................................................645 CHAPTER 24 ROM CORRECTION FUNCTION..................................................................................647 24.1 Overview ....................................................................................................................................647 24.2 Control Registers ......................................................................................................................648 24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) ........................................................648 24.2.2 Correction control register (CORCN)............................................................................................649 24.3 ROM Correction Operation and Program Flow......................................................................649 CHAPTER 25 FLASH MEMORY...........................................................................................................651 25.1 Features .....................................................................................................................................651 25.2 Writing with Flash Programmer...............................................................................................652 25.3 Programming Environment......................................................................................................658 25.4 Communication Mode ..............................................................................................................658 25.5 Pin Processing ..........................................................................................................................661 25.5.1 VPP pin ..........................................................................................................................................661 25.5.2 Serial interface pins ......................................................................................................................662 25.5.3 RESET pin....................................................................................................................................664 25.5.4 Port pins .......................................................................................................................................664 25.5.5 Other signal pins...........................................................................................................................664 25.5.6 Power supply ................................................................................................................................664 25.6 Programming Method...............................................................................................................665 25.6.1 Controlling flash memory..............................................................................................................665 25.6.2 Flash memory programming mode...............................................................................................666 25.6.3 Selecting communication mode....................................................................................................666 25.6.4 Communication commands ..........................................................................................................667 CHAPTER 26 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, SPECIAL GRADE (A) PRODUCTS) .............................669 CHAPTER 27 ELECTRICAL SPECIFICATIONS (SPECIAL GRADE (A1) PRODUCTS) ...............712 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SPECIAL GRADE (A2) PRODUCTS) ...............734 CHAPTER 29 PACKAGE DRAWINGS .................................................................................................756 User's Manual U15862EJ4V1UD 17 CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS ............................................................760 APPENDIX A REGISTER INDEX ..........................................................................................................763 APPENDIX B REVISION HISTORY ......................................................................................................770 B.1 Major Revisions in This Edition.............................................................................................. 770 B.2 Revision History up to Previous Edition................................................................................ 772 18 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION 1.1 K1 Family Product Lineup 1.1.1 V850ES/Kx1 Series lineup V850ES/KF1 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) PD703208 PD703208Y PD703209 PD703209Y PD703210 PD703210Y PD70F3210 PD70F3210Y Mask ROM: 64 KB, RAM: 4 KB I2C bus version Mask ROM: 96 KB, RAM: 4 KB I2C bus version Mask ROM: 128 KB, RAM: 6 KB I2C bus version Flash memory: 128 KB, RAM: 6 KB I2C bus version V850ES/KG1 100-pin plastic LQFP (fine pitch) (14 x 14) PD703212 PD703212Y PD703213 PD703213Y PD703214 PD703214Y PD70F3214 PD70F3214Y Mask ROM: 64 KB, RAM: 4 KB I2C bus version Mask ROM: 96 KB, RAM: 4 KB I2C bus version Mask ROM: 128 KB, RAM: 6 KB I2C bus version Flash memory: 128 KB, RAM: 6 KB I2C bus version V850ES/KJ1 144-pin plastic LQFP (fine pitch) (20 x 20) PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y Mask ROM: 96 KB, RAM: 6 KB I2C bus version Mask ROM: 128 KB, RAM: 6 KB I2C bus version Flash memory: 128 KB, RAM: 6 KB I2C bus version User's Manual U15862EJ4V1UD 19 CHAPTER 1 INTRODUCTION The following shows the function list of the V850ES/Kx1. Function Part No. Timer 8-Bit 16-Bit TMH Watch WDT 2 ch 2 ch 2 ch 1 ch 2 ch CSI 2 ch Serial Interface CSIA UART 1 ch 2 ch IC - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch - 2 ch - 2 ch - 2 ch 16 ch 2 ch 12 ch 128 - 8 ch 2 ch 6 ch 84 - 8 ch - 6 ch 67 - 2 A/D D/A RTO I/O Other PD703208 PD703208Y V850ES/KF1 V850ES/KG1 V850ES/KJ1 2 PD703209 PD703209Y PD703210 PD703210Y PD70F3210 PD70F3210Y PD703212 PD703212Y PD703213 PD703213Y PD703214 PD703214Y PD70F3214 PD70F3214Y PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y Remark In this manual, the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 product names are used as follows. * Mask ROM versions V850ES/KF1: PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y V850ES/KG1: PD703212, 703212Y, 703213, 703213Y, 703214, 703214Y V850ES/KJ1: PD703216, 703216Y, 703217, 703217Y * Flash memory versions V850ES/KF1: PD70F3210, 70F3210Y V850ES/KG1: PD70F3214, 70F3214Y V850ES/KJ1: PD70F3217, 70F3217Y * I C bus versions V850ES/KF1: PD703208Y, 703209Y, 703210Y, 70F3210Y V850ES/KG1: PD703212Y, 703213Y, 703214Y, 70F3214Y V850ES/KJ1: PD703216Y, 703217Y, 70F3217Y 20 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION 1.1.2 78K0/Kx1 Series lineup The lineup of products in the 78K0/Kx1 Series is shown below. 78K0/KB1: 30-pin (7.62 mm 0.65 mm pitch) PD78F0103 PD780103 PD780102 PD780101 Flash memory: 24 KB, RAM: 768 bytes Mask ROM: 24 KB, RAM: 768 bytes Mask ROM: 16 KB, RAM: 768 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KC1: 44-pin (10x10 mm 0.8 mm pitch) PD78F0114 PD780114 PD780113 PD780112 PD780111 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KD1: 52-pin (10x10 mm 0.65 mm pitch) PD78F0124 PD780124 PD780123 PD780122 PD780121 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KE1: 64-pin (10x10 mm 0.5 mm pitch, 12x12 mm 0.65 mm pitch, 14x14 mm 0.8 mm pitch) PD78F0134 PD780134 PD780133 PD780132 PD780131 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes PD78F0138 PD780138 Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB PD780136 78K0/KF1: 80-pin (12x12 mm 0.5 mm pitch, 14x14 mm 0.65 mm pitch) PD78F0148 PD780148 PD780146 PD780144 PD780143 Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB User's Manual U15862EJ4V1UD 21 CHAPTER 1 INTRODUCTION The following shows the function list of the 78K0/Kx1 Series. Product Name Item Package Internal memory Flash memory RAM 512 bytes Supply voltage Minimum instruction execution time 0.2 s (10 MHz, when VDD = 4.0 to 5.5 V) 0.24 s (8.38 MHz, when VDD = 3.3 to 5.5 V) 0.4 s (5 MHz, when VDD = 2.7 to 5.5 V) Mask ROM 30-pin 8 KB 16 KB 24 KB - 24 KB 768 bytes 512 bytes - 44-pin 8 KB 24 KB 16 KB 32 KB - 32 KB 1 KB 512 bytes - 52-pin 8 KB 24 KB 16 KB 32 KB - 32 KB 1 KB 512 bytes VDD = 2.7 to 5.5 V Note If the pin is an alternate-function pin, either function is selected for use. 22 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION 1.2 V850ES/KF1 1.2.1 Features (V850ES/KF1) Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers CPU features: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space Memory block division function: 2 MB, 64 KB (Total of 2 blocks) * External bus interface PD703208, 703208Y (Mask ROM: 64 KB/RAM: 4 KB) PD703209, 703209Y (Mask ROM: 96 KB/RAM: 4 KB) PD703210, 703210Y (Mask ROM: 128 KB/RAM: 6 KB) PD70F3210, 70F3210Y (Flash memory: 128 KB/RAM: 6 KB) * Internal memory 16-bit data bus Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer function 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels 8-bit timer H: 2 channels 8-bit interval timer BRG: 1 channel Watch timer/interval timer: 1 channel Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: 1 channel Serial interface (SIO) Asynchronous serial interface (UART): 2 channels 3-wire serial I/O (CSI0): 2 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 1 channel I C bus interface (I C): 1 channel (PD703208Y, 703209Y, 703210Y, 70F3210Y) A/D converter: 10-bit resolution x 8 channels Real-time output port: 6 bits x 1 channel Power-save functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes 2 2 30 sources (PD703208, 703209, 703210, 70F3210) 31 sources (PD703208Y, 703209Y, 703210Y, 70F3210Y) 32 sources 1 source Total: 67 Key interrupt function User's Manual U15862EJ4V1UD 23 CHAPTER 1 INTRODUCTION ROM correction: 4 correction addresses specifiable Packages: 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 1.2.2 Applications (V850ES/KF1) Automotive * System control of body electrical system (power windows, keyless entry reception, etc.) * Submicrocontroller of control system Home audio, car audio AV equipment PC peripheral devices (keyboards, etc.) Household appliances * Outdoor units of air conditioners * Microwave ovens, rice cookers Industrial devices * Pumps * Vending machines * FA 24 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION 1.2.3 Ordering information (V850ES/KF1) (1) Standard products, (A) grade products Part Number Package 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special PD703208GC-xxx-8BT PD703208YGC-xxx-8BT PD703208GK-xxx-9EU PD703208YGK-xxx-9EU PD703209GC-xxx-8BT PD703209YGC-xxx-8BT PD703209GK-xxx-9EU PD703209YGK-xxx-9EU PD703210GC-xxx-8BT PD703210YGC-xxx-8BT PD703210GK-xxx-9EU PD703210YGK-xxx-9EU PD70F3210GC-8BT PD70F3210YGC-8BT PD70F3210GK-9EU PD70F3210YGK-9EU PD703208GC(A)-xxx-8BT PD703208YGC(A)-xxx-8BT PD703208GK(A)-xxx-9EU PD703208YGK(A)-xxx-9EU PD703209GC(A)-xxx-8BT PD703209YGC(A)-xxx-8BT PD703209GK(A)-xxx-9EU PD703209YGK(A)-xxx-9EU PD703210GC(A)-xxx-8BT PD703210YGC(A)-xxx-8BT PD703210GK(A)-xxx-9EU PD703210YGK(A)-xxx-9EU PD70F3210GC(A)-8BT PD70F3210YGC(A)-8BT PD70F3210GK(A)-9EU PD70F3210YGK(A)-9EU Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U15862EJ4V1UD 25 CHAPTER 1 INTRODUCTION (2) (A1) grade products, (A2) grade products Part Number Package 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) Quality Grade Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special PD703208GC(A1)-xxx-8BT PD703208YGC(A1)-xxx-8BT PD703208GK(A1)-xxx-9EU PD703208YGK(A1)-xxx-9EU PD703209GC(A1)-xxx-8BT PD703209YGC(A1)-xxx-8BT PD703209GK(A1)-xxx-9EU PD703209YGK(A1)-xxx-9EU PD703210GC(A1)-xxx-8BT PD703210YGC(A1)-xxx-8BT PD703210GK(A1)-xxx-9EU PD703210YGK(A1)-xxx-9EU PD703208GC(A2)-xxx-8BTNote PD703208YGC(A2)-xxx-8BT Note PD703208GK(A2)-xxx-9EUNote PD703208YGK(A2)-xxx-9EU PD703209YGC(A2)-xxx-8BT Note PD703209GC(A2)-xxx-8BTNote Note PD703209GK(A2)-xxx-9EUNote PD703209YGK(A2)-xxx-9EU PD703210YGC(A2)-xxx-8BT Note PD703210GC(A2)-xxx-8BTNote Note PD703210GK(A2)-xxx-9EUNote PD703210YGK(A2)-xxx-9EU Note Under development Note Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. 26 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION 1.2.4 Pin configuration (top view) (V850ES/KF1) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) PD703208GC-xxx-8BT PD703208YGC-xxx-8BT PD703208GK-xxx-9EU PD703208YGK-xxx-9EU PD703209GC-xxx-8BT PD703209YGC-xxx-8BT PD703208GK(A)-xxx-9EU PD703208YGK(A)-xxx-9EU PD703209GC(A)-xxx-8BT PD703209YGC(A)-xxx-8BT PD703209GK(A)-xxx-9EU PD703209YGK(A)-xxx-9EU PD703209GK-xxx-9EU PD703209YGK-xxx-9EU PD703210GC-xxx-8BT PD703210YGC-xxx-8BT PD703210GK-xxx-9EU PD703210YGK-xxx-9EU PD703210GC(A)-xxx-8BT PD703210YGC(A)-xxx-8BT PD703210GK(A)-xxx-9EU PD703210YGK(A)-xxx-9EU PD70F3210GC(A)-8BT PD70F3210YGC(A)-8BT PD70F3210GC-8BT PD70F3210YGC-8BT PD70F3210GK-9EU PD70F3210YGK-9EU PD703208GC(A)-xxx-8BT PD703208YGC(A)-xxx-8BT PD70F3210GK(A)-9EU PD70F3210YGK(A)-9EU PD703208GC(A1)-xxx-8BT PD703208YGC(A1)-xxx-8BT PD703208GK(A1)-xxx-9EU PD703208YGK(A1)-xxx-9EU PD703209GC(A1)-xxx-8BT PD703209YGC(A1)-xxx-8BT PD703209GK(A1)-xxx-9EU PD703209YGK(A1)-xxx-9EU PD703210GC(A1)-xxx-8BT PD703210YGC(A1)-xxx-8BT PD703210GK(A1)-xxx-9EU PD703210YGK(A1)-xxx-9EU PD703208GC(A2)-xxx-8BT PD703208YGC(A2)-xxx-8BT PD703208GK(A2)-xxx-9EU PD703208YGK(A2)-xxx-9EU PD703209GC(A2)-xxx-8BT PD703209YGC(A2)-xxx-8BT PD703209GK(A2)-xxx-9EU PD703209YGK(A2)-xxx-9EU PD703210GC(A2)-xxx-8BT PD703210YGC(A2)-xxx-8BT PD703210GK(A2)-xxx-9EU PD703210YGK(A2)- xxx-9EU User's Manual U15862EJ4V1UD 27 CHAPTER 1 INTRODUCTION PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVREF0 AVss P00/TOH0 P01/TOH1 P02/NMI P03/INTP0 P04/INTP1 VPPNote 1/ICNote 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P05/INTP2 P06/INTP3 P40/SI00 P41/SO00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS1/CS1 PCS0/CS0 P915/INTP6 P914/INTP5 P913/INTP4 P99/SCK01 P98/SO01 P97/SI01 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P50/TI011/RTP00/KR0 P39/SCL0Note 3 P51/TI50/RTP01/KR1 P52/TO50/RTP02/KR2 P35/TI010/TO01 P38/SDA0Note 3 P53/SIA0/RTP03/KR3 P54/SOA0/RTP04/KR4 P55/SCKA0/RTP05/KR5 P90/TXD1/KR6 EVDD EVSS P33/TI000/TO00 P91/RXD1/KR7 P42/SCK00 P31/RXD0 P32/ASCK0 P34/TI001 P30/TXD0 Notes 1. IC: Connect directly to VSS (PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y). VPP: Connect to VSS in normal operation mode (PD70F3210, 70F3210Y). 2. When using a regulator, connect the REGC pin to VSS via a 10 pF capacitor. When not using a regulator, connect the REGC pin directly to VDD. 3. SCL0 and SDA0 can be used only in the PD703208Y, 703209Y, 703210Y, and 70F3210Y. Caution Make EVDD the same potential as VDD. 28 User's Manual U15862EJ4V1UD P96/TI51/TO51 PDL4/AD4 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 CHAPTER 1 INTRODUCTION Pin identification (V850ES/KF1) AD0 to AD15: ANI0 to ANI7: ASCK0: ASTB: AVREF0: AVSS: CLKOUT: CS0, CS1: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: NMI: P00 to P06: P30 to P35, P38, P39: P40 to P42: P50 to P55: P70 to P77: P90, P91, P96 to P99,: P913 to P915 PCM0 to PCM3: PCS0, PCS1: PCT0, PCT1, PCT4, PCT6: PDL0 to PDL15: Port CT Port DL Port CM Port CS Address/data bus Analog input Asynchronous serial clock Address strobe Analog reference voltage Ground for analog Clock output Chip select Power supply for port Ground for port Hold acknowledge Hold request Internally connected External interrupt input Key return Non-maskable interrupt request Port 0 Port 3 Port 4 Port 5 Port 7 Port 9 RD: REGC: RESET: RTP00 to RTP05: RXD0, RXD1: SCK00, SCK01, SCKA0: SCL0: SDA0: SI00, SI01, SIA0: SO00, SO01, SOA0: TI000, TI001, TI010, TI011, TI50, TI51: TO00, TO01, TO50, TO51, TOH0, TOH1: TXD0, TXD1: VDD: VPP: VSS: WAIT: WR0: WR1: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Wait Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock Timer input Serial output Serial input Serial clock Serial clock Serial data Read strobe Regulator control Reset Real-time output port Receive data User's Manual U15862EJ4V1UD 29 CHAPTER 1 INTRODUCTION 1.2.5 Function block configuration (V850ES/KF1) (1) Internal block diagram NMI INTP0 to INTP6 ROM INTC CPU PC Note 1 16-bit timer/event counter: 2 ch 8-bit timer/event counter: 2 ch Instruction queue Multiplier 16 x 1632 BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0, CS1 AD0 to AD15 TI000, TI001,TI010, TI011 TO00, TO01 RAM 32-bit barrel shifter System registers General-purpose registers 32 bits x 32 Note 2 TI50, TI51 TO50, TO51 ROM correction TOH0, TOH1 8-bit timer H: 2 ch SO00, SO01 SI00, SI01 SCK00, SCK01 SOA0 SIA0 SCKA0 SDA0Note 3 SCL0Note 3 TXD0, TXD1 RXD0, RXD1 ASCK0 Ports CSI0: 2 ch A/D converter CLKOUT PLL X1 X2 XT1 XT2 RESET I2CNote 3: 1 ch AVREF0 AVSS ANI0 to ANI7 CSIA: 1 ch PDL0 to PDL15 PCT0, PCT1, PCT4, PCT6 PCS0, PCS1 PCM0 to PCM3 P90, P91, P96 to P99, P913 to P915 P70 to P77 P50 to P55 P40 to P42 P30 to P35, P38, P39 P00 to P06 CG Regulator REGC VDD ICNote 4 EVDD EVSS VPPNote 5 VSS UART: 2 ch Watchdog timer: 2 ch RTP00 to RTP05 Key interrupt function Watch timer KR0 to KR7 RTO: 1 ch Notes 1. PD703208, 703208Y: 64 KB (mask ROM) 96 KB (mask ROM) 128 KB (mask ROM) 4 KB PD703209, 703209Y: PD703210, 703210Y: PD70F3210, 70F3210Y: 128 KB (flash memory) 2. PD703208, 703208Y, 703209, 703209Y: PD703210, 703210Y, 70F3210, 70F3210Y: 6 KB 3. Only in the PD703208Y, 703209Y, 703210Y, and 70F3210Y 4. Only in the PD703208, 703208Y, 703209, 703209Y, 703210, and 703210Y 5. Only in the PD70F3210 and 70F3210Y 30 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (c) ROM This consists of a 128 KB, 96 KB, or 64 KB mask ROM or flash memory mapped to the address spaces from 0000000H to 001FFFFH, 0000000H to 0017FFFH, or 0000000H to 000FFFFH, respectively. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 6 KB or 4 KB RAM mapped to the address spaces from 3FFD800H to 3FFEFFFH or 3FFE000H to 3FFEFFFH, respectively. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (f) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (g) Timer/counter Two 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer channels enabling programmable pulse output are provided on chip. (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer. User's Manual U15862EJ4V1UD 31 CHAPTER 1 INTRODUCTION (i) Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs. (j) Serial interface The V850ES/KF1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface with an automatic transmit/receive function (CSIA0), and an I C bus interface (I C0). The PD703208, 703209, 703210, and 70F3210 can 2 2 simultaneously use up to five channels, and the PD703208Y, 703209Y, 703210Y, and 70F3210Y up to six channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For CSIA0, data is transferred via the SOA0, SIA0, and SCKA0 pins. For I C0, data is transferred via the SDA0 and SCL0 pins. I C0 is provided only in the PD703208Y, 703209Y, 703210Y, and 70F3210Y. 2 2 Remark n = 0, 1 (k) A/D converter This 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive approximation method. (l) ROM correction This function is used to replace part of a program in the mask ROM with that contained in the internal RAM. Up to four correction addresses can be specified. (m) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. (n) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. For the V850ES/KF1, a 1-channel 6-bit data real-time output function is provided on chip. 32 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION (o) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port P0 P3 P4 P5 P7 P9 PCM PCS PCT PDL I/O 7-bit I/O 8-bit I/O 3-bit I/O 6-bit I/O 8-bit input 9-bit I/O 4-bit I/O 2-bit I/O 4-bit I/O 16-bit I/O Alternate Function NMI, external interrupt, timer output Serial interface, timer I/O Serial interface Serial interface, timer I/O, key interrupt function, real-time output function A/D converter analog input Serial interface, timer I/O, external interrupt, key interrupt function External bus control signal Chip select output External bus control signal External address/data bus User's Manual U15862EJ4V1UD 33 CHAPTER 1 INTRODUCTION 1.3 V850ES/KG1 1.3.1 Features (V850ES/KG1) Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers CPU feature: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space Memory block division function: 2 MB, 2 MB (Total of 2 blocks) * External bus interface PD703212, 703212Y (Mask ROM: 64 KB/RAM: 4 KB) PD703213, 703213Y (Mask ROM: 96 KB/RAM: 4 KB) PD703214, 703214Y (Mask ROM: 128 KB/RAM: 6 KB) PD70F3214, 70F3214Y (Flash memory: 128 KB/RAM: 6 KB) * Internal memory 16-bit data bus Address bus: Separate output possible Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer function 16-bit timer/event counter: 4 channels 8-bit timer/event counter: 2 channels 8-bit timer H: 2 channels 8-bit interval timer BRG: 1 channel Watch timer/interval timer: 1 channel Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: 1 channel Serial interface Asynchronous serial interface (UART): 2 channels 3-wire serial I/O (CSI0): 2 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 2 channels I C bus interface (I C): 1 channel (PD703212Y, 703213Y, 703214Y, 70F3214Y) A/D converter: 10-bit resolution x 8 channels D/A converter: 8-bit resolution x 2 channels Real-time output port: 6 bits x 1 channel 2 2 35 sources (PD703212, 703213, 703214, 70F3214) 36 sources (PD703212Y, 703213Y, 703214Y, 70F3214Y) 32 sources 1 source Total: 84 Key interrupt function 34 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION Power-save functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes ROM correction: 4 correction addresses specifiable Packages: 100-pin plastic LQFP (fine pitch) (14 x 14) 1.3.2 Applications (V850ES/KG1) Automotive * System control of body electrical system (power windows, keyless entry reception, etc.) * Submicrocontroller of control system Home audio, car audio AV equipment PC peripheral devices (keyboards, etc.) Household appliances * Outdoor units of air conditioners * Microwave ovens, rice cookers Industrial devices * Pumps * Vending machines * FA 1.3.3 Ordering information (V850ES/KG1) (1) Standard products, (A) grade products Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special PD703212GC-xxx-8EU PD703212YGC-xxx-8EU PD703213GC-xxx-8EU PD703213YGC-xxx-8EU PD703214GC-xxx-8EU PD703214YGC-xxx-8EU PD70F3214GC-8EU PD70F3214YGC-8EU PD703212GC(A)-xxx-8EU PD703212YGC(A)-xxx-8EU PD703213GC(A)-xxx-8EU PD703213YGC(A)-xxx-8EU PD703214GC(A)-xxx-8EU PD703214YGC(A)-xxx-8EU PD70F3214GC(A)-8EU PD70F3214YGC(A)-8EU Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U15862EJ4V1UD 35 CHAPTER 1 INTRODUCTION (2) (A1) grade products, (A2) grade products Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) Quality Grade Special Special Special Special Special Special Special Special Special Special Special Special PD703212GC(A1)-xxx-8EU PD703212YGC(A1)-xxx-8EU PD703213GC(A1)-xxx-8EU PD703213YGC(A1)-xxx-8EU PD703214GC(A1)-xxx-8EU PD703214YGC(A1)-xxx-8EU PD703212GC(A2)-xxx-8EU PD703212YGC(A2)-xxx-8EU PD703213GC(A2)-xxx-8EU PD703213YGC(A2)-xxx-8EU PD703214GC(A2)-xxx-8EU PD703214YGC(A2)-xxx-8EU Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. 36 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION 1.3.4 Pin configuration (top view) (V850ES/KG1) 100-pin plastic LQFP (fine pitch) (14 x 14) PD703212GC-xxx-8EU PD703212YGC-xxx-8EU PD703213GC-xxx-8EU PD703213YGC-xxx-8EU PD703214GC-xxx-8EU PD703214YGC-xxx-8EU PD70F3214GC-8EU PD70F3214YGC-8EU PD703212GC(A)-xxx-8EU PD703212YGC(A)-xxx-8EU PD703213GC(A)-xxx-8EU PD703213YGC(A)-xxx-8EU PD703214GC(A)-xxx-8EU PD703214YGC(A)-xxx-8EU PD70F3214GC(A)-8EU PD70F3214YGC(A)-8EU PD703212GC(A1)-xxx-8EU PD703212YGC(A1)-xxx-8EU PD703213GC(A1)-xxx-8EU PD703213YGC(A1)-xxx-8EU PD703214GC(A1)-xxx-8EU PD703214YGC(A1)-xxx-8EU PD703212GC(A2)-xxx-8EU PD703212YGC(A2)-xxx-8EU PD703213GC(A2)-xxx-8EU PD703213YGC(A2)-xxx-8EU PD703214GC(A2)-xxx-8EU PD703214YGC(A2)-xxx-8EU User's Manual U15862EJ4V1UD 37 CHAPTER 1 INTRODUCTION AVREF0 AVSS P10/ANO0 P11/ANO1 AVREF1 P00/TOH0 P01/TOH1 VPPNote 1/ICNote 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0 P04/INTP1 P05/INTP2 P06/INTP3 P40/SI00 P41/SO00 P42/SCK00 P30/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 PDH5/A21 PDH4/A20 PDH3/A19 PDH2/A18 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS1/CS1 PCS0/CS0 P915/A15/INTP6 P914/A14/INTP5 P913/A13/INTP4 P912/A12/SCKA1 P911/A11/SOA1 P910/A10/SIA1 P99/A9/SCK01 P98/A8/SO01 Notes 1. IC: Connect directly to VSS (PD703212, 703212Y, 703213, 703213Y, 703214, 703214Y). VPP: Connect to VSS in normal operation mode (PD70F3214, 70F3214Y). 2. When using a regulator, connect the REGC pin to VSS via a 10 pF capacitor. When not using a regulator, connect the REGC pin directly to VDD. 3. SCL0 and SDA0 can be used only in the PD703212Y, 703213Y, 703214Y, and 70F3214Y. Caution Make EVDD the same potential as VDD. BVDD can be used when VDD = EVDD BVDD. 38 P31/RXD0 P32/ASCK0 P33/TI000/TO00 P34/TI001 P35/TI010/TO01 P36 P37 EVSS EVDD P38/SDA0Note 3 P39/SCL0Note 3 P50/TI011/RTP00/KR0 P51/TI50/RTP01/KR1 P52/TO50/RTP02/KR2 P53/SIA0/RTP03/KR3 P54/SOA0/RTP04/KR4 P55/SCKA0/RTP05/KR5 P90/A0/TXD1/KR6 P91/A1/RXD1/KR7 P92/A2/TI020/TO02 P93/A3/TI021 P94/A4/TI030/TO03 P95/A5/TI031 P96/A6/TI51/TO51 P97/A7/SI01 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION Pin identification (V850ES/KG1) A0 to A21: AD0 to AD15: ANI0 to ANI7: ANO0, ANO1: ASCK0: ASTB: AVREF0, AVREF1: AVSS: BVDD: BVSS: CLKOUT: CS0, CS1: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: NMI: P00 to P06: P10, P11: P30 to P39: P40 to P42: P50 to P55: P70 to P77: P90 to P915: PCM0 to PCM3: PCS0, PCS1: PCT0, PCT1, PCT4, PCT6: PDH0 to PDH5: PDL0 to PDL15: Port CT Port DH Port DL Address bus Address/data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Ground for analog Power supply for bus interface Ground for bus interface Clock output Chip select Power supply for port Ground for port Hold acknowledge Hold request Internally connected External interrupt input Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 7 Port 9 Port CM Port CS RD: REGC: RESET: RTP00 to RTP05: RXD0, RXD1: SCK00, SCK01, SCKA0, SCKA1: SCL0: SDA0: SI00, SI01, SIA0, SIA1: SO00, SO01, SOA0, SOA1: TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI50, TI51: TO00 to TO03, TO50, TO51, TOH0, TOH1: TXD0, TXD1: VDD: VPP: VSS: WAIT: WR0: WR1: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Wait Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock Timer input Serial output Serial input Serial clock Serial clock Serial data Read strobe Regulator control Reset Real-time output port Receive data User's Manual U15862EJ4V1UD 39 CHAPTER 1 INTRODUCTION 1.3.5 Function block configuration (V850ES/KG1) (1) Internal block diagram NMI INTP0 to INTP6 TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031 TO00 to TO03 ROM INTC CPU PC Note 1 16-bit timer/event counter: 4 ch 8-bit timer/event counter: 2 ch Instruction queue Multiplier 16 x 1632 BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0, CS1 A0 to A21 AD0 to AD15 RAM 32-bit barrel shifter System registers General-purpose registers 32 bits x 32 Note 2 TI50, TI51 TO50, TO51 ROM correction TOH0, TOH1 8-bit timer H: 2 ch SO00, SO01 SI00, SI01 SCK00, SCK01 SOA0, SOA1 SIA0, SIA1 SCKA0, SCKA1 SDA0Note 3 SCL0 Note 3 Ports CSI0: 2 ch D/A converter A/D converter CLKOUT PLL X1 X2 XT1 XT2 RESET I2CNote 3: 1 ch ANO0, ANO1 AVREF1 AVREF0 AVSS ANI0 to ANI7 CSIA: 2 ch PDL0 to PDL15 PDH0 to PDH5 PCT0, PCT1, PCT4, PCT6 PCS0, PCS1 PCM0 to PCM3 P90 to P915 P70 to P77 P50 to P55 P40 to P42 P30 to P39 P10, P11 P00 to P06 CG Regulator REGC VDD ICNote 4 BVDD BVSS EVDD TXD0, TXD1 RXD0, RXD1 ASCK0 UART: 2 ch Watchdog timer: 2 ch RTP00 to RTP05 Key interrupt function Watch timer KR0 to KR7 EVSS VPPNote 5 VSS RTO: 1 ch Notes 1. PD703212, 703212Y: 64 KB (mask ROM) 96 KB (mask ROM) 128 KB (mask ROM) 4 KB PD703213, 703213Y: PD703214, 703214Y: PD70F3214, 70F3214Y: 128 KB (flash memory) 2. PD703212, 703212Y, 703213, 703213Y: PD703214, 703214Y, 70F3214, 70F3214Y: 6 KB 3. Only in the PD703212Y, 703213Y, 703214Y, and 70F3214Y 4. Only in the PD703212, 703212Y, 703213, 703213Y, 703214, and 703214Y 5. Only in the PD70F3214 and 70F3214Y 40 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (c) ROM This consists of a 128 KB, 96 KB, or 64 KB mask ROM or flash memory mapped to the address spaces from 0000000H to 001FFFFH, 0000000H to 0017FFFH, or 0000000H to 000FFFFH, respectively. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 6 KB or 4 KB RAM mapped to the address spaces from 3FFD800H to 3FFEFFFH or 3FFE000H to 3FFEFFFH, respectively. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (f) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (g) Timer/counter Four 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer channels enabling programmable pulse output are provided on chip. (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer. User's Manual U15862EJ4V1UD 41 CHAPTER 1 INTRODUCTION (i) Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs. (j) Serial interface (SIO) The V850ES/KG1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface with an automatic transmit/receive function (CSIAn), and an I C bus interface (I C0). The PD703212, 703213, 703214, and 70F3214 can 2 2 simultaneously use up to six channels, and the PD703212Y, 703213Y, 703214Y, and 70F3214Y up to seven channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For CSIA0, data is transferred via the SOAn, SIAn, and SCKAn pins. For I C0, data is transferred via the SDA0 and SCL0 pins. I C0 is provided only in the PD703212Y, 703213Y, 703214Y, and 70F3214Y. 2 2 Remark n = 0, 1 (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive approximation method. (l) D/A converter Two 8-bit resolution D/A converter channels are included on chip. The D/A converter uses the R-2R ladder method. (m) ROM correction This function is used to replace part of a program in the mask ROM with that contained in the internal RAM. Up to four correction addresses can be specified. (n) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. (o) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. For the V850ES/KG1, a 1-channel 6-bit data real-time output function is provided on chip. 42 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION (p) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port P0 P1 P3 P4 P5 P7 P9 PCM PCS PCT PDH PDL I/O 7-bit I/O 2-bit I/O 10-bit I/O 3-bit I/O 6-bit I/O 8-bit input 16-bit I/O 4-bit I/O 2-bit I/O 4-bit I/O 6-bit I/O 16-bit I/O Alternate Function NMI, external interrupt, timer output D/A converter analog output Serial interface, timer I/O Serial interface Serial interface, timer I/O, key interrupt function, real-time output function A/D converter analog input External address bus, serial interface, timer I/O, external interrupt, key interrupt function External bus control signal Chip select output External bus control signal External address bus External address/data bus User's Manual U15862EJ4V1UD 43 CHAPTER 1 INTRODUCTION 1.4 V850ES/KJ1 1.4.1 Features (V850ES/KJ1) Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers CPU features: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB (Total of 4 blocks) * External bus interface PD703216, 703216Y (Mask ROM: 96 KB/RAM: 6 KB) PD703217, 703217Y (Mask ROM: 128 KB/RAM: 6 KB) PD70F3217, 70F3217Y (Flash memory: 128 KB/RAM: 6 KB) * Internal memory 16-bit data bus Address bus: Separate output possible Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer function 16-bit timer/event counter: 6 channels 8-bit timer/event counter: 8-bit timer H: 8-bit interval timer BRG: Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: Serial interface Asynchronous serial interface (UART): 3-wire serial I/O (CSI0): I C bus interface (I C): (PD703216Y, 703217Y, 70F3217Y) A/D converter: 10-bit resolution x 16 channels D/A converter: 8-bit resolution x 2 channels Real-time output port: 6 bit x 2 channels 2 2 43 sources (PD703216, 703217, 70F3217) 45 sources (PD703216Y, 703217Y, 70F3217Y) 32 sources 1 source Total: 128 Key interrupt function 2 channels 2 channels 1 channel Watch timer/interval timer: 1 channel 1 channel 3 channels 3 channels 2 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 2 channels 44 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION Power-save functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes ROM correction: 4 correction addresses specifiable Packages: 144-pin plastic LQFP (fine pitch) (20 x 20) 1.4.2 Applications (V850ES/KJ1) Automotive * System control of body electrical system (power windows, keyless entry reception, etc.) * Submicrocontroller of control system Home audio, car audio AV equipment PC peripheral devices (keyboards, etc.) Household appliances * Outdoor units of air conditioners * Microwave ovens, rice cookers Industrial devices * Pumps * Vending machines * FA 1.4.3 Ordering information (V850ES/KJ1) (1) Standard products, (A1) grade products Part Number Package 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) Quality Grade Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special PD703216GJ-xxx-UEN PD703216YGJ-xxx-UEN PD703217GJ-xxx-UEN PD703217YGJ-xxx-UEN PD70F3217GJ-UEN PD70F3217YGJ-UEN PD703216GJ(A)-xxx-UEN PD703216YGJ(A)-xxx-UEN PD703217GJ(A)-xxx-UEN PD703217YGJ(A)-xxx-UEN PD70F3217GJ(A)-UEN PD70F3217YGJ(A)-UEN Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U15862EJ4V1UD 45 CHAPTER 1 INTRODUCTION (2) Standard products, (A1) grade products Part Number Package 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) Quality Grade Special Special Special Special Special Special Special Special PD703216GJ(A1)-xxx-UEN PD703216YGJ(A1)-xxx-UEN PD703217GJ(A1)-xxx-UEN PD703217YGJ(A1)-xxx-UEN PD703216GJ(A2)-xxx-UENNote PD703216YGJ(A2)-xxx-UEN PD703217YGJ(A2)-xxx-UEN Note Under development Note PD703217GJ(A2)-xxx-UENNote Note Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. 46 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION 1.4.4 Pin configuration (top view) (V850ES/KJ1) 144-pin plastic LQFP (fine pitch) (20 x 20) PD703216GJ-xxx-UEN PD703216YGJ-xxx-UEN PD703217GJ-xxx-UEN PD703217YGJ-xxx-UEN PD70F3217GJ-UEN PD70F3217YGJ-UEN PD703216GJ(A)-xxx-UEN PD703216YGJ(A)-xxx-UEN PD703217GJ(A)-xxx-UEN PD703217YGJ(A)-xxx-UEN PD70F3217GJ(A)-UEN PD70F3217YGJ(A)-UEN PD703216GJ(A1)-xxx-UEN PD703216YGJ(A1)-xxx-UEN PD703217GJ(A1)-xxx-UEN PD703217YGJ(A1)-xxx-UEN PD703216GJ(A2)-xxx-UEN PD703216YGJ(A2)-xxx-UEN PD703217GJ(A2)-xxx-UEN PD703217YGJ(A2)-xxx-UEN User's Manual U15862EJ4V1UD 47 CHAPTER 1 INTRODUCTION AVREF0 AVSS P10/ANO0 P11/ANO1 AVREF1 P00/TOH0 P01/TOH1 VPPNote 1/ICNote 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0 P04/INTP1 P05/INTP2 P06/INTP3 P40/SI00 P41/SO00 P42/SCK00 P30/TXD0 P31/RXD0 P32/ASCK0 P33/TI000/TO00 P34/TI001 P35/TI010/TO01 P36 P37 EVSS EVDD P38/SDA0Note 3 Note 3 P39/SCL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P712/ANI12 P713/ANI13 P714/ANI14 P715/ANI15 PDH7/A23 PDH6/A22 PDH5/A21 PDH4/A20 PDH3/A19 PDH2/A18 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5 PDL4/AD4 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT7 PCT6/ASTB PCT5 PCT4/RD PCT3 PCT2 PCT1/WR1 PCT0/WR0 PCS7 PCS6 PCS5 PCS4 PCM5 PCM4 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS3/CS3 PCS2/CS2 PCS1/CS1 PCS0/CS0 PCD3 PCD2 PCD1 PCD0 P915/A15/INTP6 P914/A14/INTP5 P913/A13/INTP4 P912/A12/SCKA1 Notes 1. IC: Connect directly to VSS (PD703216, 703216Y, 703217, 703217Y). VPP: Connect to VSS in normal operation mode (PD70F3217, 70F3217Y). 2. When using a regulator, connect the REGC pin to VSS via a 10 pF capacitor. When not using a regulator, connect the REGC pin directly to VDD. 3. SCL0, SDA0, SCL1, and SDA1 can be used only in the PD703216Y, 703217Y, and 70F3217Y. Caution Make EVDD the same potential as VDD. BVDD can be used when VDD = EVDD BVDD. 48 P50/TI011/RTP00/KR0 P51/TI50/RTP01/KR1 P52/TO50/RTP02/KR2 P53/SIA0/RTP03/KR3 P54/SOA0/RTP04/KR4 P55/SCKA0/RTP05/KR5 P60/RTP10 P61/RTP11 P62/RTP12 P63/RTP13 P64/RTP14 P65/RTP15 P66/SI02 P67/SO02 P68/SCK02 P69/TI040 P610/TI041 P611/TO04 P612/TI050 P613/TI051/TO05 P614 P615 P80/RXD2/SDA1Note 3 P81/TXD2/SCL1Note 3 P90/A0/TXD1/KR6 P91/A1/RXD1/KR7 P92/A2/TI020/TO02 P93/A3/TI021 P94/A4/TI030/TO03 P95/A5/TI031 P96/A6/TI51/TO51 P97/A7/SI01 P98/A8/SO01 P99/A9/SCK01 P910/A10/SIA1 P911/A11/SOA1 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION Pin identification (V850ES/KJ1) A0 to A23: AD0 to AD15: ANI0 to ANI15: ANO0, ANO1: ASCK0: ASTB: AVREF0, AVREF1: AVSS: BVDD: BVSS: CLKOUT: CS0 to CS3: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: NMI: P00 to P06: P10, P11: P30 to P39: P40 to P42: P50 to P55: P60 to P615: P70 to P715: P80, P81: P90 to P915: PCD0 to PCD3: PCM0 to PCM5: PCS0 to PCS7: PCT0 to PCT7: PDH0 to PDH7: Address bus Address/data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Ground for analog Power supply for bus interface Ground for bus interface Clock output Chip select Power supply for port Ground for port Hold acknowledge Hold request Internally connected External interrupt input Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port CD Port CM Port CS Port CT Port DH PDL0 to PDL15: RD: REGC: RESET: RTP00 to RTP05, RTP10 to RTP15: RXD0 to RXD2: SCK00 to SCK02, SCKA0, SCKA1: SCL0, SCL1: SDA0, SDA1: SI00 to SI02, SIA0, SIA1: SO00 to SO02, SOA0, SOA1: TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI040, TI041, TI050, TI051, TI50, TI51: TO00 to TO05, TO50, TO51, TOH0, TOH1: TXD0 to TXD2: VDD: VPP: VSS: WAIT: WR0: WR1: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Wait Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock Timer input Serial output Serial input Serial clock Serial clock Serial data Real-time output port Receive data Port DL Read strobe Regulator control Reset User's Manual U15862EJ4V1UD 49 CHAPTER 1 INTRODUCTION 1.4.5 Function block configuration (V850ES/KJ1) (1) Internal block diagram NMI INTP0 to INTP6 TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI040, TI041, TI050, TI051 TO00 to TO05 ROM INTC CPU PC Note 1 16-bit timer/event counter: 6 ch 8-bit timer/event counter: 2 ch Instruction queue Multiplier 16 x 1632 BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0 to CS3 A0 to A23 AD0 to AD15 RAM 32-bit barrel shifter System registers General-purpose registers 32 bits x 32 6 KB TI50, TI51 TO50, TO51 ROM correction TOH0, TOH1 8-bit timer H: 2 ch SO00 to SO02 SI00 to SI02 SCK00 to SCK02 SOA0, SOA1 SIA0, SIA1 SCKA0, SCKA1 SDA0, SDA1Note 2 SCL0, SCL1Note 2 TXD0 to TXD2 RXD0 to RXD2 ASCK0 Ports CSI0: 3 ch PDL0 to PDL15 PDH0 to PDH7 PCT0 to PCT7 PCS0 to PCS7 PCM0 to PCM5 PCD0 to PCD3 P90 to P915 P80,P81 P70 to P715 P60 to P615 P50 to P55 P40 to P42 P30 to P39 P10,P11 P00 to P06 D/A converter A/D converter CLKOUT PLL X1 X2 XT1 XT2 RESET CG ANO0, ANO1 AVREF1 AVREF0 AVSS ANI0 to ANI15 CSIA: 2 ch I2CNote 3: 2 ch Regulator REGC VDD ICNote 3 BVDD BVSS EVDD UART: 3 ch Watchdog timer: 2 ch RTP00 to RTP05, RTP10 to RTP15 Key interrupt function Watch timer KR0 to KR7 EVSS VPPNote 4 VSS RTO: 2 ch Notes 1. PD703216, 703216Y: 96 KB (mask ROM) 128 KB (mask ROM) PD703217, 703217Y: PD70F3217, 70F3217Y: 128 KB (flash memory) 2. Only in the PD703216Y, 703217Y, 70F3217Y 3. Only in the PD703216, 703216Y, 703217, and 703217Y 4. Only in the PD70F3217 and 70F3217Y 50 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (c) ROM This consists of a 128 KB or 96 KB mask ROM or flash memory mapped to the address spaces from 0000000H to 001FFFFH or 0000000H to 0017FFFH, respectively. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 6 KB RAM mapped to the address spaces from 3FFD800H to 3FFEFFFH. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (f) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (g) Timer/counter Six 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer channels enabling programmable pulse output are provided on chip. (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer. User's Manual U15862EJ4V1UD 51 CHAPTER 1 INTRODUCTION (i) Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs. (j) Serial interface (SIO) The V850ES/KJ1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface with an automatic transmit/receive function (CSIAm), and an I C bus interface (I Cm). The PD703216, 703217, and 70F3217 can simultaneously 2 2 use up to eight channels, and the PD703216Y, 703217Y, and 70F3217Y up to nine channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For CSIAm, data is transferred via the SOAm, SIAm, and SCKAm pins. For I Cm, data is transferred via the SDAm and SCLm pins. I Cm is provided only in the PD703216Y, 703217Y, and 70F3217Y. 2 2 Remark n = 0 to 2 m = 0, 1 (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 16 analog input pins. Conversion is performed using the successive approximation method. (l) D/A converter Two 8-bit resolution D/A converter channels are included on chip. The D/A converter uses the R-2R ladder method. (m) ROM correction This function is used to replace part of a program in the mask ROM with that contained in the internal RAM. Up to four correction addresses can be specified. (n) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. (o) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. For the V850ES/KJ1, a 2-channel 6-bit data real-time output function is provided on chip. 52 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION (p) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port P0 P1 P3 P4 P5 P6 P7 P8 P9 PCD PCM PCS PCT PDH PDL I/O 7-bit I/O 2-bit I/O 10-bit I/O 3-bit I/O 6-bit I/O 16-bit I/O 16-bit input 2-bit I/O 16-bit I/O 4-bit I/O 6-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 16-bit I/O External bus control signal Chip select output External bus control signal External address bus External address/data bus Alternate Function NMI, external interrupt, timer output D/A converter analog output Serial interface, timer I/O Serial interface Serial interface, timer I/O, key interrupt function, real-time output function Serial interface, timer I/O, real-time output function A/D converter analog input Serial interface External address bus, serial interface, timer I/O, external interrupt, key interrupt function - User's Manual U15862EJ4V1UD 53 CHAPTER 1 INTRODUCTION 1.5 Overview of Functions * V850ES/KF1 Part Number Internal memory RAM Buffer RAM Memory space Logical space External memory area External bus interface Address bus: 16 bits Data bus: 8/16 bits Multiplex bus mode General-purpose registers Main clock (oscillation frequency) Ceramic/crystal/external clock When PLL not used When PLL used REGC pin connected directly to VDD 2 to 10 MHz: 2.7 to 5.5 V Standard products, (A) special grade products: 2 to 5 MHz: 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 2.5 MHz: 2.7 to 5.5 V (A1) special grade products: 2 to 5 MHz: 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V (A2) special grade products: 2 to 4 MHz: 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V 10 F capacitor connected to REGC pin Subclock (oscillation frequency) Minimum instruction execution time DSP function 32 x 32 = 64: 200 to 250 ns (at 20 MHz) 32 x 32 + 32 = 32: 300 ns (at 20 MHz) 16 x 16 = 32: 50 to 100 ns (at 20 MHz) 16 x 16 + 32 = 32: 150 ns (at 20 MHz) I/O ports 67 Input: 8 I/O: 59 (among these, N-ch open-drain output selectable: 2, fixed to N-ch open-drain output: 6) Timer 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels (16-bit timer/event counter: Usable as 1 channel) 8-bit timer: 2 channels Watchdog timer: 2 channels Watch timer: 1 channel 8-bit interval timer: 1 channel Real-time output port A/D converter D/A converter Serial interface CSI: 2 channels CSIA (with automatic transmit/receive function): 1 channel UART: 2 channels I2C bus: 1 channel Interrupt sources Power save function Operating supply voltage External: 9 (9)Note 2, internal: 22/23Note 1 STOP/IDLE/HALT Standard products, (A) special grade products: 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V (at 16 MHz)/2.7 to 5.5 V (at 10 MHz) (A1) special grade products (mask version only): 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V (at 16MHz)/3.5 to 5.5 V (at 12 MHz) (A2) special grade products (mask version only): 4.0 to 5.5 V (at 16 MHz)/3.5 to 5.5 V (at 12 MHz) Package 80-pin plastic TQFP (fine pitch) (12 x 12 mm), 80-pin plastic QFP (14 x 14 mm) 4 bits x 1, 2 bits x 1, or 6 bits x 1 10-bit resolution x 8 channels - Standard products, (A) special grade products, (A1) special grade products, (A2) special grade products: 2 to 4 MHz: 4.0 to 5.5 V Crystal/external clock (32.768 kHz) When main clock operated at (fXX) = 20 MHz 32 bits x 32 registers 4 KB 32 bytes 64 MB 128 KB 6 KB ROM PD703208/PD703208Y 64 KB PD703209/PD703209Y 96 KB PD703210/PD703210Y 128 KB PD70F3210/PD70F3210Y 128 KB (flash memory) Notes 1. Y products only. 2. The figure in parentheses indicates the number of external interrupts for which STOP mode can be released. 54 User's Manual U15862EJ4V1UD CHAPTER 1 INTRODUCTION * V850ES/KG1 Part Number Internal memory RAM Buffer RAM Memory space Logical space External memory area 4 KB 64 bytes 64 MB 3 MB Address bus: 22 bits Data bus: 8/16 bits Multiplex bus mode/separate bus mode General-purpose registers Main clock (oscillation frequency) Ceramic/crystal/external clock When PLL not used When PLL used REGC pin connected directly to VDD 2 to 10 MHz: 2.7 to 5.5 V Standard products, (A) special grade products: 2 to 5 MHz: 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 2.5 MHz: 2.7 to 5.5 V (A1) special grade products: 2 to 5 MHz, 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V (A2) special grade products: 2 to 4 MHz, 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V 10 F capacitor connected to REGC pin Subclock (oscillation frequency) Minimum instruction execution time DSP function 32 x 32 = 64: 200 to 250 ns (at 20 MHz) 32 x 32 + 32 = 32: 300 ns (at 20 MHz) 16 x 16 = 32: 50 to 100 ns (at 20 MHz) 16 x 16 + 32 = 32: 150 ns (at 20 MHz) I/O port 84 * Input: 8 * I/O: 76 (among these, N-ch open-drain output selectable: 4, fixed to N-ch open-drain output: 8) Timer 16-bit timer/event counter: 4 channels 8-bit timer/event counter: 2 channels (16-bit timer/event counter: Usable as 1 channel) 8-bit timer: 2 channels Watchdog timer: 2 channels Watch timer: 1 channel 8-bit interval timer: 1 channel Real-time output port A/D converter D/A converter Serial interface CSI: 2 channels CSIA (with automatic transmit/receive function): 2 channels UART: 2 channels I2C bus: 1 channelNote 1 Interrupt sources Power save function Operating supply voltage External: 9 (9)Note 2, internal: 27/28Note 1 STOP/IDLE/HALT Standard products, (A) special grade products: 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V/(at 16 MHz)/2.7 to 5.5 V (at 10 MHz) (A1) special grade products (mask version only): 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V/(at 16 MHz)/3.5 to 5.5 V (at 12 MHz) (A2) special grade products (mask version only): 4.0 to 5.5 V (at 16 MHz)/3.5 to 5.5 V/(at 12 MHz) Package 100-pin plastic TQFP (fine pitch) (14 x 14 mm) 4 bits x 1, 2 bits x 1, or 6 bits x 1 10-bit resolution x 8 channels 8-bit resolution x 2 channels Standard products, (A) special grade products, (A1) special grade products, (A2) special grade products: 2 to 4 MHz: 4.0 to 5.5 V Crystal/external clock (32.768 kHz) When main clock operated at (fXX) = 20 MHz 32 bits x 32 registers 6 KB ROM PD703212/PD703212Y 64 KB PD703213/PD703213Y 96 KB PD703214/PD703214Y 128 KB PD70F3214/PD70F3214Y 128 KB (flash memory) External bus interface Notes 1. Y products only. 2. The figure in parentheses indicates the number of external interrupts for which STOP mode can be released. User's Manual U15862EJ4V1UD 55 CHAPTER 1 INTRODUCTION * V850ES/KJ1 Part Number Internal memory ROM High-speed RAM Buffer RAM Memory space Logical space External memory area 64 bytes 64 MB 15 MB Address bus: 24 bits Data bus: 8/16 bits Multiplex bus mode/separate bus mode 32 bits x 32 registers Ceramic/crystal/external clock When PLL not used When PLL used REGC pin connected directly to VDD 2 to 10 MHz: 2.7 to 5.5 V Standard products, (A) special grade products: 2 to 5 MHz: 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 2.5 MHz: 2.7 to 5.5 V (A1) special grade products: 2 to 5 MHz: 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V (A2) special grade products: 2 to 4 MHz: 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V Standard products, (A) special grade products, (A1) special grade products, (A2) special grade products: 2 to 4 MHz: 4.0 to 5.5 V Crystal/external clock (32.768 kHz) When main clock operated at (fXX) = 20 MHz 32 x 32 = 64: 200 to 250 ns (at 20 MHz) 32 x 32 + 32 = 32: 300 ns (at 20 MHz) 16 x 16 = 32: 50 to 100 ns (at 20 MHz) 16 x 16 + 32 = 32: 150 ns (at 20 MHz) 128 * Input: 16 * I/O: 112 (among these, N-ch open-drain output selectable: 6, fixed to N-ch open-drain output: 12) 16-bit timer/event counter: 6 channels 8-bit timer/event counter: 2 channels (16-bit timer/event counter: usable as 1 channel) 8-bit timer: 2 channels Watchdog timer: 2 channels Watch timer: 1 channel 8-bit interval timer: 1 channel 2 channels: 4 bits x 1, 2 bits x 1, or 6 bits x 1 10-bit resolution x 16 channels 8-bit resolution x 2 channels CSI: 3 channels CSIA (with automatic transmit/receive function): 2 channels UART: 3 channels/2 channelsNote 1 2 UART/I C bus: 1 channelNote 1 Dedicated baud rate generator: 3 channels External: 9 (9)Note 2, internal: 35/37Note 1 STOP/IDLE/HALT Standard products, (A) special grade products: 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V (at 16 MHz)/2.7 to 5.5 V (at 10 MHz) (A1) special grade products (mask version only): 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V (at 16 MHz)/3.5 to 5.5 V (at 12 MHz) (A2) special grade products (mask version only): 4.0 to 5.5 V (at 16 MHz)/3.5 to 5.5 V (at 12 MHz) 144-pin plastic TQFP (fine pitch) (20 x 20 mm) PD703216/PD703216Y 96 KB PD703217/PD703217Y 128 KB 6 KB PD70F3217/PD70F3217Y 128 KB (flash memory) External bus interface General-purpose registers Main clock (oscillation frequency) 10 F capacitor connected to REGC pin Subclock (oscillation frequency) Minimum instruction execution time DSP function I/O ports Timer Real-time output port A/D converter D/A converter Serial interface Interrupt sources Power save function Operating supply voltage Package Notes 1. Y products only. 2. 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ZLWK H[WHUQDO GHYLFHV LV SHUIRUPHG E\ ZULWLQJ WR DQG UHDGLQJ IURP WKH SRUW Q UHJLVWHU 3Q 7KH SRUW Q UHJLVWHU LV FRQILJXUHG RI D SRUW ODWFK WKDW UHWDLQV WKH RXWSXW GDWD DQG D FLUFXLW WKDW UHDGV WKH SLQ VWDWXV (DFK ELW RI WKH SRUW Q UHJLVWHU FRUUHVSRQGV WR RQH SLQ RI SRUW Q DQG FDQ EH UHDGZULWWHQ LQ ELW XQLWV After reset: 00HNote (output latch) 7 6 5 R/W 7 3 2 1 0 Pn Pn7 Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 Pnm 0 1 0 is output 1 is output Control of output data (in output mode) 1RWH ,QSXWRQO\ SRUW SLQV DUH XQGHILQHG :ULWLQJ WR DQG UHDGLQJ IURP WKH 3Q UHJLVWHU LV H[HFXWHG DV IROORZV LQGHSHQGHQW RI WKH VHWWLQJ RI WKH SRUW Q PRGH FRQWURO UHJLVWHU 30&Q 7DEOH 5HDGLQJ WR:ULWLQJ IURP 3RUW Q 5HJLVWHU 3Q 6HWWLQJ RI 30Q 5HJLVWHU 2XWSXW PRGH 30QP ,QSXW PRGH 30QP :ULWLQJ WR 3Q 5HJLVWHU :ULWH WR WKH RXWSXW ODWFK Note 5HDGLQJ IURP 3Q 5HJLVWHU 7KH YDOXH RI WKH RXWSXW ODWFK LV UHDG ,Q WKH SRUW PRGH 30&Q WKH FRQWHQWV RI WKH RXWSXW ODWFK DUH RXWSXW IURP WKH SLQ :ULWH WR WKH RXWSXW ODWFK 7KH VWDWXV RI WKH SLQ LV QRW DIIHFWHGNote 7KH SLQ VWDWXV LV UHDG 1RWH 7KH YDOXH ZULWWHQ WR WKH RXWSXW ODWFK LV UHWDLQHG XQWLO D YDOXH LV QH[W ZULWWHQ WR WKH RXWSXW ODWFK 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW Q PRGH UHJLVWHU 30Q 30Q VSHFLILHV WKH LQSXW PRGHRXWSXW PRGH RI WKH SRUW (DFK ELW RI WKH SRUW Q PRGH UHJLVWHU FRUUHVSRQGV WR RQH SLQ RI SRUW Q DQG FDQ EH VSHFLILHG LQ ELW XQLWV After reset: FFH R/W PMn PMn7 PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0 PMnm 0 1 Output mode Input mode Control of I/O mode 3RUW Q PRGH FRQWURO UHJLVWHU 30&Q 30&Q VSHFLILHV WKH SRUW PRGHDOWHUQDWH IXQFWLRQ (DFK ELW RI WKH SRUW Q PRGH FRQWURO UHJLVWHU FRUUHVSRQGV WR RQH SLQ RI SRUW Q DQG FDQ EH VSHFLILHG LQ ELW XQLWV After reset: 00H R/W PMCn PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0 PMCnm 0 1 Port mode Specification of operation mode Alternate function mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW Q IXQFWLRQ FRQWURO UHJLVWHU 3)&Q 3)&Q LV D UHJLVWHU WKDW VSHFLILHV WKH DOWHUQDWH IXQFWLRQ WR EH XVHG ZKHQ RQH SLQ KDV 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3)QP ELW 30QP ELW 30&QP ELW 1FK RSHQGUDLQ RXWSXW LV VSHFLILHG 2XWSXW PRGH LV VSHFLILHG RU 1FK RSHQGUDLQ RXWSXW LV VSHFLILHG ,QSXW PRGH LV VSHFLILHG RU ! :KHQ WKH YDOXH RI WKH 3)Q UHJLVWHU LV LQYDOLG 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38Q 38Q LV D UHJLVWHU WKDW VSHFLILHV WKH FRQQHFWLRQ RI DQ RQFKLS SXOOXS UHVLVWRU (DFK ELW RI WKH SXOOXS UHVLVWRU RSWLRQ UHJLVWHU FRUUHVSRQGV WR RQH SLQ RI SRUW Q DQG FDQ EH VSHFLILHG LQ ELW XQLWV After reset: 00H R/W PUn PUn7 PUn6 PUn5 PUn4 PUn3 PUn2 PUn1 PUn0 PUnm 0 1 Not connected Connected Control of on-chip pull-up resistor connection 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW VHWWLQJV 6HW WKH SRUWV DV IROORZV )LJXUH 5HJLVWHU 6HWWLQJV DQG 3LQ )XQFWLRQV Port mode Output mode Input mode "0" PMn "1" Port n mode register "0" Alternate function (when two alternate functions are provided) "1" PFCn Alternate function 2 "1" Port n function control register PMCn Port n mode control register "0" Alternate function 1 5HPDUN 6ZLWFK WR WKH DOWHUQDWH IXQFWLRQ XVLQJ WKH IROORZLQJ SURFHGXUH ! 6HW WKH 3)&Q UHJLVWHU ! 6HW WKH 30&Q UHJLVWHU ! 6HW H[WHUQDO LQWHUUXSW ULVLQJIDOOLQJ HGJH VSHFLILFDWLRQ UHJLVWHU Q ,175Q,17)Q LQWHUUXSW SLQ LV VHW ,I WKH 30&Q UHJLVWHU LV VHW ILUVW DQRWKHU XQLQWHQGHG DOWHUQDWH IXQFWLRQ PD\ EH VHW ZKLOH WKH 3)&Q UHJLVWHU LV EHLQJ VHW ZKHQ H[WHUQDO 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW ,QSXWRXWSXW IRU SRUW FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH 9(6.) 9(6.* DQG 9(6.- KDYH WKH VDPH QXPEHU RI ,2 SRUW SLQV IRU SRUW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 3LQ 1DPH 3RUW 3 3 3 3 3 3 3 $OWHUQDWH )XQFWLRQ 72+ 72+ 10, ,173 ,173 ,173 ,173 ,2 2XWSXW 2XWSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW $QDORJ QRLVH HOLPLQDWLRQ 38//Note 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 After reset: 00H (output latch) R/W Address: FFFFF400H P0 0 P06 P05 P04 P03 P02 P01 P00 P0n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 6) E 3RUW PRGH UHJLVWHU 30 After reset: FFH R/W Address: FFFFF420H PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 6) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW PRGH FRQWURO UHJLVWHU 30& After reset: 00H R/W Address: FFFFF440H PMC0 0 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 PMC06 0 1 PMC05 0 1 PMC04 0 1 PMC03 0 1 PMC02 0 1 PMC01 0 1 PMC00 0 1 I/O port TOH0 output I/O port TOH1 output I/O port NMI input I/O port INTP0 input I/O port INTP1 input I/O port INTP2 input I/O port INTP3 input Specification of P06 pin operation mode Specification of P05 pin operation mode Specification of P04 pin operation mode Specification of P03 pin operation mode Specification of P02 pin operation mode Specification of P01 pin operation mode Specification of P00 pin operation mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 G 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38 After reset: 00H R/W Address: FFFFFC40H PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00 PU0n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 6) Not connected Connected 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW ,QSXWRXWSXW IRU SRUW FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ELW ,2 SRUW ELW ,2 SRUW ,2 3RUW 3LQ &RXQW 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 9(6.* 9(6.- 3LQ 1DPH 3RUW 3 3 $OWHUQDWH )XQFWLRQ $12 $12 ,2 2XWSXW 2XWSXW 38//Note 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 L 9(6.* 9(6.- After reset: 00H (output latch) R/W Address: FFFFF402H P1 0 0 0 0 0 0 P11 P10 P1n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0, 1) E 3RUW PRGH UHJLVWHU 30 &DXWLRQ :KHQ XVHG DV WKH $12 DQG $12 SLQV VHW 30 ))+ DOO WRJHWKHU L 9(6.* 9(6.- After reset: FFH R/W Address: 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After reset: 00H (output latch) R/W Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H 15 14 13 12 11 10 9 8 P3 (P3HNote) 0 0 0 0 0 0 P39 P38 (P3L) 0 0 P35 P34 P33 P32 P31 P30 P3n 0 1 Control of output data (in output mode) (n = 0 to 5, 8, 9) 0 is output 1 is output LL 9(6.* 9(6.- After reset: 00H R/W Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H 13 12 11 10 9 8 15 14 P3 (P3HNote) 0 0 0 0 0 0 P39 P38 (P3L) P37 P36 P35 P34 P33 P32 P31 P30 P3n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 9) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3+ UHJLVWHU 5HPDUN 7KH SRUW UHJLVWHU 3 FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 3 UHJLVWHU DUH XVHG DV WKH 3+ UHJLVWHU DQG DV WKH 3/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW PRGH UHJLVWHU 30 L 9(6.) After reset: FFFFH R/W Address: PM3 FFFFF426H, PM3L FFFFF426H, PM3H FFFFF427H 13 12 11 10 9 8 15 14 PM3 (PM3HNote) 1 1 1 1 1 1 PM39 PM38 (PM3L) 1 1 PM35 PM34 PM33 PM32 PM31 PM30 PM3n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5, 8, 9) LL 9(6.* 9(6.- After reset: FFFFH R/W Address: PM3 FFFFF426H, PM3L FFFFF426H, PM3H FFFFF427H 13 12 11 10 9 8 15 14 PM3 (PM3HNote) 1 1 1 1 1 1 PM39 PM38 (PM3L) PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 9) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30+ UHJLVWHU 5HPDUN :KHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30 UHJLVWHU DUH XVHG DV WKH 30+ UHJLVWHU DQG DV WKH 30/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW PRGH FRQWURO UHJLVWHU 30& L 9(6.) 9(6.* 9(6.- After reset: 0000H R/W Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H 13 12 11 10 9 8 Note 15 14 PMC3 (PMC3H Note 1 ) 0 0 0 0 0 0 PMC39 PMC38Note (PMC3L) 0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 PMC30 0 1 I/O port TXD0 output I/O port RXD0 input I/O port ASCK0 input I/O port TI000/TO00 I/O I/O port TI001 input I/O port TI010/TO01 I/O I/O port SDA0 I/O I/O port SCL0 I/O Specification of P39 pin operation mode Specification of P38 pin operation mode Specification of P35 pin operation mode Specification of P34 pin operation mode Specification of P33 pin operation mode Specification of P32 pin operation mode Specification of P31 pin operation mode Specification of P30 pin operation mode 1RWHV :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30& UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30&+ UHJLVWHU 2QO\ LQ SURGXFWV ZLWK DQ , & EXV ,Q DOO RWKHU SURGXFWV VHW WKLV ELW WR 5HPDUN 7KLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ :KHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30& UHJLVWHU DUH XVHG DV WKH 30&+ UHJLVWHU DQG DV WKH 30&/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 G 3RUW IXQFWLRQ UHJLVWHU + 3)+ After reset: 00H R/W Address: FFFFFC67H PF3H 0 0 0 0 0 0 PF39 PF38 PF3n 0 1 Specification of normal port/alternate function (n = 8, 9) When used as normal port (N-ch open-drain output) When used as alternate-function (N-ch open-drain output) &DXWLRQ :KHQ XVLQJ 3 DQG 3 DV 1FK RSHQGUDLQRXWSXW DOWHUQDWHIXQFWLRQ SLQV VHW LQ WKH IROORZLQJ VHTXHQFH %H VXUH WR VHW WKH SRUW ODWFK WR EHIRUH VHWWLQJ WKH SLQ WR 1FK RSHQGUDLQ RXWSXW 3Q ELW 3)Q ELW 30&Q ELW H 3RUW IXQFWLRQ FRQWURO UHJLVWHU 3)& L 9(6.) 9(6.* 9(6.- After reset: 00H R/W Address: FFFFF466H PFC3 0 0 PFC35 0 PFC33 0 0 0 PFC35 0 1 PFC33 0 1 Specification of P35 pin operation mode in control mode TI010 input TO01 output Specification of P33 pin operation mode in control mode TI000 input TO00 output &DXWLRQ $OZD\V VHW ELWV WR DQG RI WKH 3)& UHJLVWHU WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 I 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38 L 9(6.) 9(6.* 9(6.- After reset: 00H R/W Address: FFFFFC46H PU3 0 0 PU35 PU34 PU33 PU32 PU31 PU30 PU3n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected &DXWLRQ $Q RQFKLS SXOOXS UHVLVWRU FDQ EH SURYLGHG IRU 3Q E\ D PDVN RSWLRQ Q Q ,Q WKH PDVN 520 YHUVLRQ RI WKH 9(6.) WR ,Q WKH PDVN 520 YHUVLRQV RI WKH 9(6.* DQG 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW ,QSXWRXWSXW IRU SRUW FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH 9(6.) 9(6.* DQG 9(6.- KDYH WKH VDPH QXPEHU RI ,2 SRUW SLQV IRU SRUW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 3LQ 1DPH 3RUW 3 3 3 $OWHUQDWH )XQFWLRQ 6, 62 6&. ,2 ,QSXW 2XWSXW ,2 38//Note 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 After reset: 00H (output latch) R/W Address: FFFFF408H P4 0 0 0 0 0 P42 P41 P40 P4n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 2) E 3RUW PRGH UHJLVWHU 30 After reset: FFH R/W Address: FFFFF428H PM4 1 1 1 1 1 PM42 PM41 PM40 PM4n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 2) F 3RUW PRGH FRQWURO UHJLVWHU 30& After reset: 00H R/W Address: FFFFF448H PMC4 0 0 0 0 0 PMC42 PMC41 PMC40 PMC42 0 1 PMC41 0 1 PMC40 0 1 I/O port SI00 input I/O port SO00 output I/O port SCK00 I/O Specification of P42 pin operation mode Specification of P41 pin operation mode Specification of P40 pin operation mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 G 3RUW IXQFWLRQ UHJLVWHU 3) After reset: 00H R/W Address: FFFFFC68H PF4 0 0 0 0 0 PF42 PF41 0 PF4n 0 1 Control of normal output/N-ch open-drain output Normal output N-ch open-drain output &DXWLRQ :KHQ XVLQJ 3 DQG 3 DV 1FK RSHQGUDLQRXWSXW DOWHUQDWHIXQFWLRQ SLQV VHW LQ WKH IROORZLQJ VHTXHQFH %H VXUH WR VHW WKH SRUW ODWFK WR EHIRUH VHWWLQJ WKH SLQ WR 1FK RSHQGUDLQ RXWSXW 3Q ELW 3)Q ELW 30&Q ELW H 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38 After reset: 00H R/W Address: FFFFFC48H PU4 0 0 0 0 0 PU42 PU41 PU40 PU4n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 2) Not connected Connected 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW ,QSXWRXWSXW IRU SRUW FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH 9(6.) 9(6.* DQG 9(6.- KDYH WKH VDPH QXPEHU RI ,2 SRUW SLQV IRU SRUW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 3LQ 1DPH 3RUW 3 3 3 3 3 3 $OWHUQDWH )XQFWLRQ 7,573.5 7,573.5 72573.5 6,$573.5 62$573.5 6&.$573.5 ,2 ,2 ,2 ,2 ,2 ,2 1FK RSHQGUDLQ RXWSXW FDQ EH VHOHFWHG ,2 38//Note 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 After reset: 00H (output latch) R/W Address: FFFFF40AH P5 0 0 P55 P54 P53 P52 P51 P50 P5n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 5) E 3RUW PRGH UHJLVWHU 30 After reset: FFH R/W Address: FFFFF42AH PM5 1 1 PM55 PM54 PM53 PM52 PM51 PM50 PM5n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW PRGH FRQWURO UHJLVWHU 30& After reset: 00H R/W Address: FFFFF44AH PMC5 0 0 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 PMC55 0 1 PMC54 0 1 PMC53 0 1 PMC52 0 1 PMC51 0 1 PMC50 0 1 Specification of P55 pin operation mode I/O port/KR5 input SCKA0/RTP05 I/O Specification of P54 pin operation mode I/O port/KR4 input SOA0/RTP04 output Specification of P53 pin operation mode I/O port/KR3 input SIA0/RTP03 I/O Specification of P52 pin operation mode I/O port/KR2 input TO50/RTP0 output Specification of P51 pin operation mode I/O port/KR1 input TI50/RTP01 I/O Specification of P50 pin operation mode I/O port/KR0 input TI011/RTP00 I/O G 3RUW IXQFWLRQ UHJLVWHU 3) After reset: 00H R/W Address: FFFFFC6AH PF5 0 0 PF55 PF54 0 0 0 0 PF5n 0 1 Control of normal output/N-ch open-drain output (n = 4, 5) Normal output N-ch open-drain output &DXWLRQV $OZD\V VHW ELWV WR DQG RI WKH 3) UHJLVWHU WR :KHQ XVLQJ 3 DQG 3 DV 1FK RSHQGUDLQRXWSXW DOWHUQDWHIXQFWLRQ SLQV VHW LQ WKH IROORZLQJ VHTXHQFH %H VXUH WR VHW WKH SRUW ODWFK WR EHIRUH VHWWLQJ WKH SLQ WR 1FK RSHQGUDLQ RXWSXW 3Q ELW 3)Q ELW 30&Q ELW 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 H 3RUW IXQFWLRQ FRQWURO UHJLVWHU 3)& After reset: 00H R/W Address: FFFFF46AH PFC5 0 0 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50 PFC55 0 1 PFC54 0 1 PFC53 0 1 PFC52 0 1 PFC51 0 1 PFC50 0 1 Specification of P55 pin operation mode in control mode SCKA0 I/O RTP05 output Specification of P54 pin operation mode in control mode SOA0 output RTP04 output Specification of P53 pin operation mode in control mode SIA0 input RTP03 output Specification of P52 pin operation mode in control mode TO50 output RTP02 output Specification of P51 pin operation mode in control mode TI50 input RTP01 output Specification of P50 pin operation mode in control mode TI011 input RTP00 output I 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38 After reset: 00H R/W Address: FFFFFC4AH PU5 0 0 PU55 PU54 PU53 PU52 PU51 PU50 PU5n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW ,QSXWRXWSXW IRU SRUW FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ELW ,2 SRUW ,2 3RUW 3LQ &RXQW 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 9(6.- 3LQ 1DPH 3RUW 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 $OWHUQDWH )XQFWLRQ 573 573 573 573 573 573 6, 62 6&. 7, 7, 72 7, 7,72 ,2 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW ,QSXW 2XWSXW ,2 ,QSXW ,QSXW 2XWSXW ,QSXW ,2 1R 1FK RSHQGUDLQ RXWSXW 38//Note 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 L 9(6.- After reset: 00H (output latch) R/W Address: P6 FFFFF40CH, P6L FFFFF40CH, P6H FFFFF40DH 12 11 10 9 8 15 14 13 P6 (P6H Note ) P615 P614 P613 P612 P611 P610 P69 P68 (P6L) P67 P66 P65 P64 P63 P62 P61 P60 P6n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 15) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3+ UHJLVWHU 5HPDUN 7KH SRUW UHJLVWHU 3 FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 3 UHJLVWHU DUH XVHG DV WKH 3+ UHJLVWHU DQG DV WKH 3/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW PRGH UHJLVWHU 30 L 9(6.- After reset: FFFFH R/W Address: PM6 FFFFF42CH, PM6L FFFFF42CH, PM6H FFFFF42DH 13 12 11 10 9 8 15 14 PM6 (PM6H Note ) PM615 PM614 PM613 PM612 PM611 PM610 PM69 PM68 (PM6L) PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM6n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 15) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30+ UHJLVWHU 5HPDUN 7KH 30 UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30 UHJLVWHU DUH XVHG DV WKH 30+ UHJLVWHU DQG DV WKH 30/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F L 3RUW PRGH FRQWURO UHJLVWHU 30& 9(6.- After reset: 0000H R/W Address: PMC6 FFFFF44CH, PMC6L FFFFF44CH, PMC6H FFFFF44DH 13 12 11 10 9 8 15 14 PMC6 (PMC6HNote) 0 0 PMC613 PMC612 PMC611 PMC610 PMC69 PMC68 (PMC6L) PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 PMC613 0 1 PMC612 0 1 PMC611 0 1 PMC610 0 1 PMC69 0 1 PMC68 0 1 PMC67 0 1 PMC66 0 1 PMC6n 0 1 I/O port RTP1n output I/O port SI02 input I/O port SO02 output I/O port SCK02 I/O I/O port TI040 input I/O port TI041 input I/O port TO04 output I/O port TI050 input I/O port TI051/TO05 I/O Specification of P613 pin operation mode Specification of P612 pin operation mode Specification of P611 pin operation mode Specification of P610 pin operation mode Specification of P69 pin operation mode Specification of P68 pin operation mode Specification of P67 pin operation mode Specification of P66 pin operation mode Specification of P6n pin operation mode (n = 0 to 5) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30& UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30&+ UHJLVWHU 5HPDUN 7KH 30& UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30& UHJLVWHU DUH XVHG DV WKH 30&+ UHJLVWHU DQG DV WKH 30&/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 G 3RUW IXQFWLRQ UHJLVWHU 3) L 9(6.- After reset: 0000H R/W Address: PF6 FFFFFC6CH, PF6L FFFFFC6CH, PF6H FFFFFC6DH 13 12 11 10 9 8 15 14 PF6 (PF6H Note ) 0 0 0 0 0 0 0 PF68 (PF6L) PF67 0 0 0 0 0 0 0 PF6n 0 1 Control of normal output/N-ch open-drain output (n = 7, 8) Normal output N-ch open-drain output 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3) UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3)+ UHJLVWHU &DXWLRQ $OZD\V VHW 3) UHJLVWHU ELWV WR DQG WR WR 5HPDUN 7KH 3) UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 3) UHJLVWHU DUH XVHG DV WKH 3)+ UHJLVWHU DQG DV WKH 3)/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV H 3RUW IXQFWLRQ FRQWURO UHJLVWHU 3)&+ L 9(6.- After reset: 00H R/W Address: FFFFF46DH PFC6H 0 0 PFC613 0 0 0 0 0 PFC613 0 1 Specification of P613 pin operation mode in control mode TI051 input TO05 output 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 I 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38 L 9(6.- After reset: 0000H R/W Address: PU6 FFFFFC4CH, PU6L FFFFFC4CH, PU6H FFFFFC4DH 15 14 13 12 11 10 9 8 PU6 (PU6H Note ) 0 0 PU613 PU612 PU611 PU610 PU69 PU68 (PU6L) PU67 PU66 PU65 PU64 PU63 PU62 PU61 PU60 PU6n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 13) Not connected Connected 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 38 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 38+ UHJLVWHU &DXWLRQ $Q RQFKLS SXOOXS UHVLVWRU FDQ EH SURYLGHG IRU 3 DQG 3 RQO\ LQ WKH PDVN 520 YHUVLRQ RI WKH 9(6.- 5HPDUN :KHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 38 UHJLVWHU DUH XVHG DV WKH 38+ UHJLVWHU DQG DV WKH 38/ UHJLVWHU UHDGZULWWHQ LQ ELW RU ELW XQLWV UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW $OO WKH SLQV RI SRUW DUH IL[HG WR LQSXW 7KH QXPEHU RI LQSXW SRUW SLQV IRU SRUW GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ,QSXW 3RUW 3LQ &RXQW ELW LQSXW SRUW ELW LQSXW SRUW ELW LQSXW SRUW 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 9(6.) 9(6.* 3LQ 1DPH 3RUW 3 3 3 3 3 3 3 3 $OWHUQDWH )XQFWLRQ $1, $1, $1, $1, $1, $1, $1, $1, ,2 ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW 38//Note 1R 5HPDUN %ORFN 7\SH $ $ $ $ $ $ $ $ 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 9(6.- 3LQ 1DPH 3RUW 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 $OWHUQDWH )XQFWLRQ $1, $1, $1, $1, $1, $1, $1, $1, $1, $1, $1, $1, $1, $1, $1, $1, ,2 ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW ,QSXW 38//Note 1R 5HPDUN %ORFN 7\SH $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 L 9(6.) 9(6.* After reset: Undefined R Address: FFFFF40EH P7 P77 P76 P75 P74 P73 P72 P71 P70 P7n 0 1 Input low level Input high level Input data read (n = 0 to 7) LL 9(6.- After reset: Undefined 15 14 R Address: FFFFF40EH (P7, P7L), FFFFF40FH (P7H) 13 12 11 10 9 8 P7 (P7HNote) P715 P714 P713 P712 P711 P710 P79 P78 (P7L) P77 P76 P75 P74 P73 P72 P71 P70 P7n 0 1 Input low level Input high level Input data read (n = 0 to 12) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3+ UHJLVWHU 5HPDUN 7KH SRUW UHJLVWHU 3 RI WKH 9(6.- FDQ EH UHDG RQO\ LQ ELW XQLWV +RZHYHU ZKHQ WKH KLJKHU ELWV RI WKH 3 UHJLVWHU DUH XVHG DV WKH 3+ UHJLVWHU DQG WKH ORZHU ELWV DV WKH 3/ UHJLVWHU WKH\ FDQ EH UHDG LQ ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW ,QSXWRXWSXW IRU SRUW FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ELW ,2 SRUW ,2 3RUW 3LQ &RXQW 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 9(6.- 3LQ 1DPH 3RUW 3 3 $OWHUQDWH )XQFWLRQ 5;'6'$ 7;'6&/ Note 2 ,2 ,2 ,2 38//Note 1 %ORFN 7\SH * * Note 2 1RWHV 6RIWZDUH SXOOXS IXQFWLRQ 2QO\ LQ WKH 3'< < DQG )< &DXWLRQ 3 DQG 3 KDYH K\VWHUHVLV FKDUDFWHULVWLFV ZKHQ WKH DOWHUQDWH IXQFWLRQ LV LQSXW EXW QRW LQ WKH SRUW PRGH 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 L 9(6.- After reset: 00H (output latch) R/W Address: FFFFF410H P8 0 0 0 0 0 0 P81 P80 P8n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0, 1) E 3RUW PRGH UHJLVWHU 30 L 9(6.- After reset: FFH R/W Address: FFFFF430H PM8 1 1 1 1 1 1 PM81 PM80 PM8n 0 1 Output mode Input mode Control of I/O mode (n = 0, 1) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW PRGH FRQWURO UHJLVWHU 30& L 9(6.- After reset: 00H R/W Address: FFFFF450H PMC8 0 PMC81 0 1 PMC80 0 1 0 0 0 0 0 PMC81 PMC80 Specification of P81 pin operation mode I/O port TXD2/SCL1Note I/O Specification of P80 pin operation mode I/O port RXD2/SDA1Note I/O 1RWH 2QO\ LQ WKH 3'< < DQG )< G 3RUW IXQFWLRQ UHJLVWHU 3) L 9(6.- After reset: 00H R/W Address: FFFFFC70H PF8 0 0 0 0 0 0 PF81 PF80 PF8n 0 1 Control of normal output/N-ch open-drain output (n = 0, 1) Normal output N-ch open-drain output &DXWLRQ :KHQ XVLQJ 3 DQG 3 DV 1FK RSHQGUDLQRXWSXW DOWHUQDWHIXQFWLRQ SLQV VHW LQ WKH IROORZLQJ VHTXHQFH %H VXUH WR VHW WKH SRUW ODWFK WR EHIRUH VHWWLQJ WKH SLQ WR 1FK RSHQGUDLQ RXWSXW 3Q ELW 3)&Q ELW 3)Q ELW 30&Q ELW 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 H 3RUW IXQFWLRQ FRQWURO UHJLVWHU 3)& L 9(6.- After reset: 00H R/W Address: FFFFF470H PFC8 0 0 0 0 0 0 PFC81 PFC80 PFC81 0 1 PFC80 0 1 Specification of P81 pin operation mode in control mode TXD2 output SCL1Note I/O Specification of P80 pin operation mode in control mode RXD2 input SDA1Note I/O 1RWH 2QO\ LQ WKH 3'< < DQG )< 6HW WR IRU DOO RWKHU SURGXFWV I 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38 L 9(6.- After reset: 00H R/W Address: FFFFFC50H PU8 0 0 0 0 0 0 PU81 PU80 PU8n 0 1 Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW ,QSXWRXWSXW IRU SRUW FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 9(6.) 3LQ 1DPH 3RUW 3 3 3 3 3 3 3 3 3 $OWHUQDWH )XQFWLRQ 7;'.5 5;'.5 7,72 6, 62 6&. ,173 ,173 ,173 ,2 ,QSXW ,2 ,QSXW 2XWSXW ,2 ,QSXW ,QSXW ,QSXW 1FK RSHQGUDLQ RXWSXW FDQ EH VSHFLILHG $QDORJ QRLVH HOLPLQDWLRQ ,2 38//Note 1R 5HPDUN %ORFN 7\SH ( ( ( ( * * + + + 1RWH 6RIWZDUH SXOOXS IXQFWLRQ &DXWLRQ 3 3 DQG 3 WR 3 KDYH K\VWHUHVLV FKDUDFWHULVWLFV ZKHQ WKH DOWHUQDWH IXQFWLRQ LV LQSXW EXW QRW LQ WKH SRUW PRGH 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW 9(6.* 9(6.- 3LQ 1DPH 3RUW 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 $OWHUQDWH )XQFWLRQ $7;'.5 $5;'.5 $7,72 $7, $7,72 $7, $7,72 $6, $62 $6&. $6,$ $62$ $6&.$ $,173 $,173 $,173 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 2XWSXW ,2 ,2 2XWSXW ,2 ,2 ,2 ,2 1FK RSHQGUDLQ RXWSXW FDQ EH VSHFLILHG 1FK RSHQGUDLQ RXWSXW FDQ EH VSHFLILHG $QDORJ QRLVH HOLPLQDWLRQ ,2 38//Note 1R 5HPDUN %ORFN 7\SH ( ( ( ( ( ( ( ( * * ( * * + + + 1RWH 6RIWZDUH SXOOXS IXQFWLRQ &DXWLRQ 3 3 3 3 3 DQG 3 WR 3 KDYH K\VWHUHVLV FKDUDFWHULVWLFV ZKHQ WKH DOWHUQDWH IXQFWLRQ LV LQSXW EXW QRW LQ WKH SRUW PRGH 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW UHJLVWHU 3 L 9(6.) After reset: 00H (output latch) R/W Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H 15 14 13 12 11 10 9 8 P9 (P9H Note ) P915 P914 P913 0 0 0 P99 P98 (P9L) P97 P96 0 0 0 0 P91 P90 P9n 0 1 Control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) 0 is output 1 is output LL 9(6.* 9(6.- After reset: 00H (output latch) R/W Address: P9H FFFFF412H, P9L FFFFF412H, P9H FFFFF413H 12 11 10 9 8 15 14 13 P9 (P9H Note ) P915 P914 P913 P912 P911 P910 P99 P98 (P9L) P97 P96 P95 P94 P93 P92 P91 P90 P9n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 15) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3+ UHJLVWHU 5HPDUN 7KH SRUW UHJLVWHU 3 FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 3 UHJLVWHU DUH XVHG DV WKH 3+ UHJLVWHU DQG DV WKH 3/ UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW PRGH UHJLVWHU 30 L 9(6.) After reset: FFFFH R/W Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H 13 12 11 10 9 8 15 14 PM9 (PM9H Note ) PM915 PM914 PM913 1 1 1 PM99 PM98 (PM9L) PM97 PM96 1 1 1 1 PM91 PM90 PM9n 0 1 Output mode Input mode Control of I/O mode (n = 0, 1, 6 to 9, 13 to 15) LL 9(6.* 9(6.- After reset: FFFFH R/W Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H 13 12 11 10 9 8 15 14 PM9 (PM9HNote) PM915 PM914 PM913 PM912 PM911 PM910 PM99 PM98 (PM9L) PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM9n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30+ UHJLVWHU 5HPDUN 7KH 30 UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30 UHJLVWHU DUH XVHG DV WKH 30+ UHJLVWHU DQG DV WKH 30/ UHJLVWHU UHVSHFWLYHO\ WKLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV F 3RUW PRGH FRQWURO UHJLVWHU 30& &DXWLRQ :KHQ XVLQJ SRUW DV WKH $ WR $ SLQV VHW WKH 30& UHJLVWHU WR ))))+ LQ ELW XQLWV RQO\ LQ 9(6.* 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 L 9(6.- After reset: 0000H R/W Address: PMC9 FFFFF452H, PMC9 FFFFF452H, PMC9H FFFFF453H 13 12 11 10 9 8 15 14 PMC9 (PMC9HNote) PMC915 PMC914 PMC913 0 0 0 PMC99 PMC98 (PMC9L) PMC97 PMC96 0 0 0 0 PMC91 PMC90 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC99 0 1 PMC98 0 1 PMC97 0 1 PMC96 0 1 PMC91 0 1 PMC90 0 1 I/O port SI01 input I/O port SO01 output I/O port SCK01 I/O I/O port INTP4 input I/O port INTP5 input I/O port INTP6 input Specification of P915 pin operation mode Specification of P914 pin operation mode Specification of P612 pin operation mode Specification of P99 pin operation mode Specification of P98 pin operation mode Specification of P97 pin operation mode Specification of P96 pin operation mode I/O port/TI51 input TO51 output Specification of P91 pin operation mode I/O port/KR7 input RXD1 input Specification of P90 pin operation mode I/O port/KR6 input TXD1 output 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30& UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30&+ UHJLVWHU 5HPDUN 7KH 30& UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30& UHJLVWHU DUH XVHG DV WKH 30&+ UHJLVWHU DQG DV WKH 30&/ UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 LL 9(6.* 9(6.- After reset: 0000H R/W Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H 13 12 11 10 9 8 15 14 PMC9 (PMC9HNote) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 (PMC9L) PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 1 PMC99 0 1 PMC98 0 1 I/O port A8/SO01 output I/O port A9/SCK01 I/O I/O port A10/SIA1 I/O I/O port I/O port A12/SCKA1 I/O I/O port A13/INTP4 I/O I/O port A14/INTP5 I/O I/O port A15/INTP6 I/O Specification of P915 pin operation mode Specification of P914 pin operation mode Specification of P913 pin operation mode Specification of P912 pin operation mode Specification of P911 pin operation mode A11/SOA1 output Specification of P910 pin operation mode Specification of P99 pin operation mode Specification of P98 pin operation mode 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30& UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30&+ UHJLVWHU 5HPDUN 7KH 30& UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30& UHJLVWHU DUH XVHG DV WKH 30&+ UHJLVWHU DQG DV WKH 30&/ UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 PMC97 0 1 PMC96 0 1 PMC95 0 1 PMC94 0 1 PMC93 0 1 PMC92 0 1 PMC91 0 1 PMC90 0 1 I/O port A3/TI021 I/O Specification of P92 pin operation mode I/O port/TI020 input A2/TO02 output Specification of P91 pin operation mode I/O port/KR7 input A1/RXD1 I/O Specification of P90 pin operation mode I/O port/KR6 input A0/TXD1 output I/O port A5/TI031 I/O Specification of P94 pin operation mode I/O port/TI030 input A4/TO03 output Specification of P93 pin operation mode I/O port/TI51 A6/TO51 output Specification of P95 pin operation mode I/O port A7/SI01 I/O Specification of P96 pin operation mode Specification of P97 pin operation mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 G 3RUW IXQFWLRQ UHJLVWHU + 3)+ L 9(6.) After reset: 00H R/W Address: FFFFFC73H PF9H 0 0 0 0 0 0 PF99 PF98 PF9n 0 1 Control of normal output/N-ch open-drain output (n = 0, 1) Normal output N-ch open-drain output LL 9(6.* 9(6.- After reset: 00H R/W Address: FFFFFC73H PF9H 0 0 0 PF912 PF911 0 PF99 PF98 PF9n 0 1 Control of normal output/N-ch open-drain output (n = 0, 1, 4, 5) Normal output N-ch open-drain output &DXWLRQ :KHQ XVLQJ 3 3 3 DQG 3 DV 1FK RSHQGUDLQRXWSXW DOWHUQDWH IXQFWLRQ SLQV VHW LQ WKH IROORZLQJ VHTXHQFH %H VXUH WR VHW WKH SRUW ODWFK WR EHIRUH VHWWLQJ WKH SLQ WR 1FK RSHQGUDLQ RXWSXW 3Q ELW 3)&Q ELW 3)Q ELW 30&Q ELW H 3RUW IXQFWLRQ FRQWURO UHJLVWHU 3)& &DXWLRQV :KHQ XVLQJ SRUW DV WKH $ WR $ SLQV VHW WKH 3)& UHJLVWHU WR + LQ ELW XQLWV RQO\ LQ 9(6.* 9(6.- :KHQ WKH FRQWURO PRGH LV VHW E\ WKH 30&Q ELW RI WKH 30& UHJLVWHU ZLWK WKH 3)&Q ELW RI WKH 3)& UHJLVWHU PDLQWDLQLQJ WKH LQLWLDO YDOXH RXWSXW EHFRPHV XQGHILQHG 7KHUHIRUH WR VHW FRQWURO PRGH RI SRUW VHW WKH 3)&Q ELW WR ILUVW DQG WKHQ VHW WKH 30&Q ELW WR Q WR WR 9(6.) RQO\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 L 9(6.) After reset: 0000H R/W Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H 15 14 13 12 11 10 9 8 PFC9 (PFC9H Note ) PFC910 PFC910 PFC910 0 0 0 PFC99 PFC98 (PFC9L) PFC97 PFC96 0 0 0 0 PFC91 PFC90 PFC915 1 PFC914 1 PFC913 1 PFC99 1 PFC98 1 PFC97 1 PFC96 1 PFC91 1 PFC90 1 Specification of P915 pin operation mode in control mode INTP6 input Specification of P914 pin operation mode in control mode INTP5 input Specification of P913 pin operation mode in control mode INTP4 input Specification of P99 pin operation mode in control mode SCK01 I/O Specification of P98 pin operation mode in control mode SO01 output Specification of P97 pin operation mode in control mode SI01 input Specification of P96 pin operation mode in control mode TO51 output Specification of P91 pin operation mode in control mode RXD1 input Specification of P90 pin operation mode in control mode TXD1 output 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3)& UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3)&+ UHJLVWHU 5HPDUN 7KH 3)& UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 3)& UHJLVWHU DUH XVHG DV WKH 3)&+ UHJLVWHU DQG DV WKH 3)&/ UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 LL 9(6.* 9(6.- After reset: 0000H R/W Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H 13 12 11 10 9 8 15 14 PFC9 (PFC9HNote) PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 (PFC9L) PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90 PFC915 0 1 PFC914 0 1 PFC913 0 1 PFC912 0 1 PFC911 0 1 PFC910 0 1 PFC99 0 1 PFC98 0 1 Specification of P915 pin operation mode in control mode A15 output INTP6 input Specification of P914 pin operation mode in control mode A14 output INTP5 input Specification of P913 pin operation mode in control mode A13 output INTP4 input Specification of P912 pin operation mode in control mode A12 output SCKA1 I/O Specification of P911 pin operation mode in control mode A11 output SOA1 output Specification of P910 pin operation mode in control mode A10 output SIA1 input Specification of P99 pin operation mode in control mode A9 output SCK01 I/O Specification of P98 pin operation mode in control mode A8 output SO01 output 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3)& UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3)&+ UHJLVWHU 5HPDUN 7KH 3)& UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 3)& UHJLVWHU DUH XVHG DV WKH 3)&+ UHJLVWHU DQG DV WKH 3)&/ UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 PFC97 0 1 PFC96 0 1 PFC95 0 1 PFC94 0 1 PFC93 0 1 PFC92 0 1 PFC91 0 1 PFC90 0 1 Specification of P97 pin operation mode in control mode A7 output SI01 input Specification of P96 pin operation mode in control mode A6 output TO51 output Specification of P95 pin operation mode in control mode A5 output TI031 input Specification of P94 pin operation mode in control mode A4 output TO03 output Specification of P93 pin operation mode in control mode A3 output TI021 input Specification of P92 pin operation mode in control mode A2 output TO02 output Specification of P91 pin operation mode in control mode A1 output RXD1 input Specification of P90 pin operation mode in control mode A0 output TXD1 output 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 I 3XOOXS UHVLVWRU RSWLRQ UHJLVWHU 38 L 9(6.) After reset: 0000H R/W Address: PU9 FFFFFC52H, PU9L FFFFFC52H, PU9H FFFFFC53H 13 12 11 10 9 8 15 14 PU9 (PU9H Note ) PU915 PU914 PU913 0 0 0 PU99 PU98 (PU9L) PU97 PU96 0 0 0 0 PU91 PU90 PU9n 0 1 Control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) Not connected Connected LL 9(6.* 9(6.- After reset: 0000H R/W Address: PU9 FFFFFC52H, PU9L FFFFFC52H, PU9H FFFFFC53H 13 12 11 10 9 8 15 14 PU9 (PU9H Note ) PU915 PU914 PU913 PU912 PU911 PU910 PU99 PU98 (PU9L) PU97 PU96 PU95 PU94 PU93 PU92 PU91 PU90 PU9n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 15) Not connected Connected 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 38 UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 38+ UHJLVWHU 5HPDUN 7KH 38 UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 38 UHJLVWHU DUH XVHG DV WKH 38+ UHJLVWHU DQG DV WKH 38/ UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW &' ,QSXWRXWSXW IRU SRUW &' EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW &' GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ELW ,2 SRUW ,2 3RUW 3LQ &RXQW 3RUW &' GRHV QRW KDYH DOWHUQDWHIXQFWLRQ SLQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW &' 9(6.- 3LQ 1DPH 3RUW &' 3&' 3&' 3&' 3&' $OWHUQDWH )XQFWLRQ ,2 38//Note 1R 5HPDUN %ORFN 7\SH % % % % 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW &' UHJLVWHU 3&' L 9(6.- After reset: 00H (output latch) R/W Address: FFFFF00EH PCD 0 0 0 0 PCD3 PCD2 PCD1 PCD0 PCDn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 3) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW &' PRGH UHJLVWHU 30&' L 9(6.- After reset: FFH R/W Address: FFFFF02EH PMCD 1 1 1 1 PMCD3 PMCD2 PMCD1 PMCD0 PMCDn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 3) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW &0 ,QSXWRXWSXW IRU SRUW &0 FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW &0 GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 3RUW &0 LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW &0 9(6.) 9(6.* 3LQ 1DPH 3RUW &0 3&0 3&0 3&0 3&0 $OWHUQDWH )XQFWLRQ :$,7 &/.287 +/'$. +/'45 ,2 ,QSXW 2XWSXW 2XWSXW ,QSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & & & 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW &0 9(6.- 3LQ 1DPH 3RUW &0 3&0 3&0 3&0 3&0 3&0 3&0 $OWHUQDWH )XQFWLRQ :$,7 &/.287 +/'$. +/'45 ,2 ,QSXW 2XWSXW 2XWSXW ,QSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & & & % % 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW &0 UHJLVWHU 3&0 L 9(6.) Y(6.* After reset: 00H (output latch) R/W Address: FFFFF00CH PCM 0 0 0 0 PCM3 PCM2 PCM1 PCM0 PCMn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 3) LL 9(6.- After reset: 00H (output latch) R/W Address: FFFFF00CH PCM 0 0 PCM5 PCM4 PCM3 PCM2 PCM1 PCM0 PCMn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 5) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW &0 PRGH UHJLVWHU 30&0 L 9(6.) 9(6.* After reset: FFH R/W Address: FFFFF02CH PMCM 1 1 1 1 PMCM3 PMCM2 PMCM1 PMCM0 PMCMn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 3) LL 9(6.- After reset: FFH R/W Address: FFFFF02CH PMCM 1 1 PMCM5 PMCM4 PMCM3 PMCM2 PMCM1 PMCM0 PMCMn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW &0 PRGH FRQWURO UHJLVWHU 30&&0 L 9(6.) 9(6.* 9(6.- After reset: 00H R/W Address: FFFFF04CH PMCCM 0 0 0 0 PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 0 1 PMCCM2 0 1 PMCCM1 0 1 PMCCM0 0 1 I/O port WAIT input I/O port CLKOUT output I/O port HLDAK output I/O port HLDQR input Specification of PCM3 pin operation mode Specification of PCM2 pin operation mode Specification of PCM1 pin operation mode Specification of PCM0 pin operation mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW &6 ,QSXWRXWSXW RI SRUW &6 FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW &6 GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 3RUW &6 LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW &6 9(6.) 9(6.* 3LQ 1DPH 3RUW &6 3&6 3&6 $OWHUQDWH )XQFWLRQ &6 &6 ,2 2XWSXW 2XWSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW &6 9(6.- 3LQ 1DPH 3RUW &6 3&6 3&6 3&6 3&6 3&6 3&6 3&6 3&6 $OWHUQDWH )XQFWLRQ &6 &6 &6 &6 ,2 2XWSXW 2XWSXW 2XWSXW 2XWSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & & & % % % % 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW &6 UHJLVWHU 3&6 L 9(6.) 9(6.* After reset: 00H (output latch) R/W Address: FFFFF008H PCS 0 0 0 0 0 0 PCS1 PCS0 PCSn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0, 1) LL 9(6.- After reset: 00H (output latch) R/W Address: FFFFF008H PCS PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 PCSn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 7) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW &6 PRGH UHJLVWHU 30&6 L 9(6.) 9(6.* After reset: FFH R/W Address: FFFFF028H PMCS 1 1 1 1 1 1 PMCS1 PMCS0 PMCSn 0 1 Output mode Input mode Control of I/O mode (n = 0, 1) LL 9(6.- After reset: FFH R/W Address: FFFFF028H PMCS PMCS7 PMCS6 PMCS5 PMCS4 PMCS3 PMCS2 PMCS1 PMCS0 PMCSn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW &6 PRGH FRQWURO UHJLVWHU 30&&6 L 9(6.) 9(6.* After reset: 00H R/W Address: FFFFF048H PMCCS 0 0 0 0 0 0 PMCCS1 PMCCS0 PMCCSn 0 1 I/O port CSn output Specification of PCSn pin operation mode (n = 0, 1) LL 9(6.- After reset: 00H R/W Address: FFFFF048H PMCCS 0 0 0 0 PMCCS3 PMCCS2 PMCCS1 PMCCS0 PMCCSn 0 1 I/O port Specification of PCSn pin operation mode (n = 0 to 3) CSn output 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW &7 ,QSXWRXWSXW IRU SRUW &7 FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW &7 GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 3RUW &7 LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW &7 9(6.) 9(6.* 3LQ 1DPH 3RUW &7 3&7 3&7 3&7 3&7 $OWHUQDWH )XQFWLRQ :5 :5 5' $67% ,2 2XWSXW 2XWSXW 2XWSXW 2XWSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & % % 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW &7 9(6.- 3LQ 1DPH 3RUW &7 3&7 3&7 3&7 3&7 3&7 3&7 3&7 3&7 $67% 5' $OWHUQDWH )XQFWLRQ :5 :5 ,2 2XWSXW 2XWSXW 2XWSXW 2XWSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & % % & % & % 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW &7 UHJLVWHU 3&7 L 9(6.) 9(6.* After reset: 00H (output latch) R/W Address: FFFFF00AH PCT 0 PCT6 0 PCT4 0 0 PCT1 PCT0 PCTn 0 1 Control of output data (in output mode) (n = 0, 1, 4, 6) 0 is output 1 is output LL 9(6.- After reset: 00H (output latch) R/W Address: FFFFF00AH PCT PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCT0 PCTn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 7) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW &7 PRGH UHJLVWHU 30&7 L 9(6.) 9(6.* After reset: FFH R/W Address: FFFFF02AH PMCT 1 PMCT6 1 PMCT4 1 1 PMCT1 PMCT0 PMCTn 0 1 Output mode Input mode Control of I/O mode (n = 0, 1, 4, 6) LL 9(6.- After reset: FFH R/W Address: FFFFF02AH PMCT PMCT7 PMCT6 PMCT5 PMCT4 PMCT3 PMCT2 PMCT1 PMCT0 PMCTn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW &7 PRGH FRQWURO UHJLVWHU 30&&7 L 9(6.) 9(6.* 9(6.- After reset: 00H R/W Address: FFFFF04AH PMCCT 0 PMCCT6 0 PMCCT4 0 0 PMCCT1 PMCCT0 PMCCT6 0 1 PMCCT4 0 1 PMCCT1 0 1 PMCCT0 0 1 I/O port WR0 output I/O port WR1 output I/O port RD output I/O port ASTB output Specification of PCT6 pin operation mode Specification of PCT4 pin operation mode Specification of PCT1 pin operation mode Specification of PCT0 pin operation mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW '+ ,QSXWRXWSXW IRU SRUW '+ FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW '+ GLIIHUV DFFRUGLQJ WR WKH SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ELW ,2 SRUW ELW ,2 SRUW ,2 3RUW 3LQ &RXQW 3RUW '+ LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW '+ 9(6.* 3LQ 1DPH 3RUW '+ 3'+ 3'+ 3'+ 3'+ 3'+ 3'+ $OWHUQDWH )XQFWLRQ $ $ $ $ $ $ ,2 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & & & & & 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW '+ 9(6.- 3LQ 1DPH 3RUW '+ 3'+ 3'+ 3'+ 3'+ 3'+ 3'+ 3'+ 3'+ $OWHUQDWH )XQFWLRQ $ $ $ $ $ $ $ $ ,2 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW 2XWSXW 38//Note 1R 5HPDUN %ORFN 7\SH & & & & & & & & 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW '+ UHJLVWHU 3'+ L 9(6.* After reset: 00H (output latch) R/W Address: FFFFF006H PDH 0 0 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 PDHn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 5) LL 9(6.- After reset: 00H (output latch) R/W Address: FFFFF006H PDH PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 PDHn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 7) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 E 3RUW '+ PRGH UHJLVWHU 30'+ L 9(6.* After reset: FFH R/W Address: FFFFF026H PMDH 1 1 PMDH5 PMDH4 PMDH3 PMDH2 PMDH1 PMDH0 PMDHn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) LL 9(6.- After reset: FFH R/W Address: FFFFF026H PMDH PMDH7 PMDH6 PMDH5 PMDH4 PMDH3 PMDH2 PMDH1 PMDH0 PMDHn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW '+ PRGH FRQWURO UHJLVWHU 30&'+ L 9(6.* After reset: 00H R/W Address: FFFFF046H PMCDH 0 0 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn 0 1 I/O port Specification of PDHn pin operation mode (n = 0 to 5) Am output (address bus output) (m = 16 to 21) &DXWLRQ :KHQ VSHFLI\LQJ WKH SRUW PRGHFRQWURO PRGH DOWHUQDWH IXQFWLRQ IRU HDFK ELW SD\ FDUHIXO DWWHQWLRQ WR WKH RSHUDWLRQ RI WKH DOWHUQDWH IXQFWLRQV LL 9(6.- After reset: 00H R/W Address: FFFFF046H PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn 0 1 I/O port Specification of PDHn pin operation mode (n = 0 to 7) Am output (address bus output) (m = 16 to 23) &DXWLRQ :KHQ VSHFLI\LQJ WKH SRUW PRGHFRQWURO PRGH DOWHUQDWH IXQFWLRQ IRU HDFK ELW SD\ FDUHIXO DWWHQWLRQ WR WKH RSHUDWLRQ RI WKH DOWHUQDWH IXQFWLRQV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 3RUW '/ ,QSXWRXWSXW RI SRUW '/ FDQ EH FRQWUROOHG LQ ELW XQLWV 7KH QXPEHU RI ,2 SRUW SLQV IRU SRUW '/ LV WKH VDPH LQ HDFK SURGXFW 3URGXFW 9(6.) 9(6.* 9(6.- ,2 3RUW 3LQ &RXQW ELW ,2 SRUW ELW ,2 SRUW ELW ,2 SRUW 3RUW '/ LQFOXGHV WKH IROORZLQJ DOWHUQDWH IXQFWLRQV 7DEOH $OWHUQDWH)XQFWLRQ 3LQV RI 3RUW '/ 3LQ 1DPH 3RUW '/ 3'/ 3'/ 3'/ 3'/ 3'/ 3'/ 3'/ 3'/ 3'/ 3'/'/ 3'/ 3'/ 3'/ 3'/ 3'/ 3'/ $OWHUQDWH )XQFWLRQ $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 38//Note 1R 5HPDUN %ORFN 7\SH & & & & & & & & & & & & & & & & 1RWH 6RIWZDUH SXOOXS IXQFWLRQ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 5HJLVWHUV D 3RUW '/ UHJLVWHU 3'/ After reset: 00H (output latch) R/W Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H 15 14 13 12 11 10 9 8 PDL (PDLH Note ) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 15) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 3'/ UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 3'/+ UHJLVWHU 5HPDUN 7KH SRUW '/ UHJLVWHU 3'/ FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 3'/ UHJLVWHU DUH XVHG DV WKH 3'/+ UHJLVWHU DQG DV WKH 3'// UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV E 3RUW '/ PRGH UHJLVWHU 30'/ After reset: FFFFH R/W Address: PMDL FFFFF024H, PMDLL FFFFF024H, PMDLH FFFFF025H 13 12 11 10 9 8 15 14 PMDL (PMDLH Note ) PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10 PMDL9 PMDL8 (PMDLL) PMDL7 PMDL6 PMDL5 PMDL4 PMDL3 PMDL2 PMDL1 PMDL0 PMDLn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 15) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30'/ UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30'/+ UHJLVWHU 5HPDUN 7KH 30'/ UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30'/ UHJLVWHU DUH XVHG DV WKH 30'/+ UHJLVWHU DQG DV WKH 30'// UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 F 3RUW '/ PRGH FRQWURO UHJLVWHU 30&'/ After reset: 0000H R/W Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H 13 12 11 10 9 8 15 14 PMCDL (PMCDLH Note ) PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 I/O port Specification of PDLn pin operation mode (n = 0 to 15) ADn I/O (address/data bus I/O) 1RWH :KHQ UHDGLQJ IURP RU ZULWLQJ WR ELWV WR RI WKH 30&'/ UHJLVWHU LQ ELW RU ELW XQLWV VSHFLI\ WKHVH ELWV DV ELWV WR RI WKH 30&'/+ UHJLVWHU &DXWLRQ :KHQ VSHFLI\LQJ WKH SRUW PRGHFRQWURO PRGH DOWHUQDWH IXQFWLRQ IRU HDFK ELW SD\ FDUHIXO DWWHQWLRQ WR WKH RSHUDWLRQ RI WKH DOWHUQDWH IXQFWLRQV 5HPDUN 7KH 30&'/ UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV RQO\ +RZHYHU ZKHQ WKH KLJKHU ELWV DQG WKH ORZHU ELWV RI WKH 30&'/ UHJLVWHU DUH XVHG DV WKH 30&'/+ UHJLVWHU DQG DV WKH 30&'// UHJLVWHU UHVSHFWLYHO\ WKHVH UHJLVWHUV FDQ EH UHDGZULWWHQ LQ ELW RU ELW XQLWV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 %ORFN 'LDJUDPV )LJXUH %ORFN 'LDJUDP RI 7\SH $ Internal bus Pmn RD Input signal of alternate-function pin )LJXUH EORFN 'LDJUDP RI 7\SH $ AVREF1 WRPU PUmn WRPM P-ch PMmn WRPORT Internal bus Output latch (Pmn) Pmn Selector Address RD D/A output signal Selector P-ch N-ch 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH % WRPM PMmn WRPORT Output latch (Pmn) Internal bus Pmn Selector Address RD 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH & WRPMC PMCmn WRPM PMmn Internal bus WRPORT Output latch (Pmn) Pmn Selector Address RD Input signal in control mode Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH & WRPMC PMCmn WRPM PMmn Internal bus Selector WRPORT Output signal in control mode Pmn Output latch (Pmn) Selector Address RD 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH & WRPMC PMCmn WRPM PMmn Internal bus Selector WRPORT Output signal in control mode Output latch (Pmn) Selector Output buffer off signal Pmn Selector Address RD Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH & WRPMC PMCmn Output enable signal in control mode Selector Selector WRPM Output buffer off signal Internal bus PMmn WRPORT Output signal in control mode Output latch (Pmn) Pmn Selector Address Input enable signal in control mode RD Input signal in control mode 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ' EVDD WRPU PUmn WRPMC P-ch PMCmn WRPM PMmn Internal bus WRPORT Output latch (Pmn) Pmn Selector Address RD Input signal in control mode Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ' EVDD WRPU PUmn WRPMC P-ch PMCmn WRPM PMmn Internal bus WRPORT Selector Output signal in control mode Output latch (Pmn) Pmn Selector Address RD 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ( EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn Output buffer off signal Internal bus PMmn WRPORT Output signal in control mode Output latch (Pmn) Selector Selector WRPM Pmn Selector RD Address Input signal during control mode Alternate-function input signal Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ( EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn Output buffer off signal PMmn Internal bus Selector WRPORT Output signal in control mode Output latch (Pmn) Selector WRPM Pmn Selector Address RD Input signal in control mode 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ( EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn Output buffer off signal WRPM PMmn Internal bus Selector Output signal in control mode WRPORT Output latch (Pmn) Selector Selector Pmn Selector RD Address Alternate-function input signal Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ( EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn WRPM Internal bus PMmn Selector WRPORT Selector Output signal in control mode Pmn Output latch (Pmn) Selector RD Address Alternate-function input signal 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ( EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn WRPM Internal bus PMmn Selector WRPORT Output signal in control mode Pmn Output latch (Pmn) Selector RD Address Input signal in control mode Alternate-function input signal Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ( EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn WRPM Internal bus PMmn WRPORT Selector Output signal in control mode Output latch (Pmn) Pmn Selector Address RD Input signal in control mode 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ) EVDD WRPU PUmn WRPF P-ch PFmn WRPMC PMCmn Internal bus WRPM PMmn EVDD WRPORT Selector Output signal in control mode Output latch (Pmn) P-ch Pmn N-ch Selector Selector EVSS Address RD 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH ) EVDD WRPU PUmn WRPF P-ch PFmn WRPMC Output enable signal in control mode PMCmn WRPM Internal bus PMmn EVDD WRPORT Selector Output signal in control mode Output latch (Pmn) P-ch Pmn N-ch Selector Selector EVSS Address Input enable signal in control mode Input signal in control mode RD 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH * EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC PMCmn Internal bus WRPM PMmn EVDD Selector Selector WRPORT Output signal in control mode P-ch Pmn N-ch Output latch (Pmn) Selector Selector EVSS RD Address Alternate-function input signal 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH * EVDD WRPU PUmn WRPF P-ch PFmn WRPFC Output enable signal in control mode PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Selector Selector WRPORT Output signal in control mode P-ch Pmn N-ch Output latch (Pmn) Selector Selector EVSS RD Address Input signal in control mode Alternate-function input signal 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH * EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC PMCmn Output enable signal in control mode Output buffer off signal WRPM PMmn EVDD Selector Internal bus Selector Selector WRPORT Output signal in control mode Selector P-ch Pmn N-ch Output latch (Pmn) Selector Selector EVSS Address RD Input signal in control mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH * EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC PMCmn Internal bus PMmn Selector WRPM Output buffer off signal EVDD Selector Selector WRPORT Output signal in control mode P-ch Pmn N-ch Output latch (Pmn) Selector Selector EVSS Address RD 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH * EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Selector WRPORT Output signal in control mode P-ch Pmn N-ch Output latch (Pmn) Selector Selector EVSS Address RD Input signal in control mode Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH * EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Selector Selector WRPORT Output signal in control signal P-ch Pmn N-ch Output latch (Pmn) Selector Selector EVSS Address RD Input signal in control mode 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH + EVDD WRPU PUmn WRINTR P-ch INTRmnNote WRINTF INTFmnNote WRPMC PMCmn Internal bus WRPM PMmn WRPORT Output latch (Pmn) Pmn Selector Address RD Input signal in control mode Detection of noise elimination edge 1RWH 5HIHU WR ([WHUQDO ,QWHUUXSW 5HTXHVW ,QSXW 3LQ 10, ,173 WR ,173 Selector 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH + EVDD WRPU PUmn WRINTR P-ch INTRmnNote WRINTF INTFmnNote WRPFC PFCmn WRPMC Internal bus PMCmn Output buffer off signal PMmn Selector WRPORT Output signal in control mode Output latch (Pmn) Selector WRPM Pmn Selector Address RD Input signal in control mode Detection of noise elimination edge 1RWH 5HIHU WR ([WHUQDO ,QWHUUXSW 5HTXHVW ,QSXW 3LQV 10, ,173 WR ,173 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH - WRPM Mask option EVDD PMmn WRPORT Output latch (Pmn) Internal bus Pmn N-ch EVSS EVDD Selector Selector P-ch Medium-voltage input buffer Address RD 8VHU(c)V 0DQXDO 8(-98' &+$37(5 3257 )81&7,216 )LJXUH %ORFN 'LDJUDP RI 7\SH . WRPF PFmn WRPMC PMCmn WRPM EVDD PMmn Internal bus Mask option Pmn Selector WRPORT Output signal in control mode Output latch (Pmn) N-ch EVSS Selector Address RD Input signal in control mode 8VHU(c)V 0DQXDO 8(-98' Selector &+$37(5 3257 )81&7,216 3RUW 5HJLVWHU 6HWWLQJ :KHQ $OWHUQDWH )XQFWLRQ ,V 8VHG 7DEOH VKRZV WKH SRUW UHJLVWHU VHWWLQJV ZKHQ HDFK SRUW LV XVHG IRU DQ DOWHUQDWH IXQFWLRQ :KHQ XVLQJ D SRUW SLQ DV DQ DOWHUQDWHIXQFWLRQ SLQ UHIHU WR GHVFULSWLRQ RI HDFK SLQ 8VHU(c)V 0DQXDO 8(-98' Table 4-29. Settings When Port Pins Are Used for Alternate Functions (1/7) Pnx Bit of Pn Register PMCn Register PFCn Register P00 = Setting not required PMC00 = 1 PMC01 = 1 PMC02 = 1 PMC03 = 1 PMC04 = 1 PMC05 = 1 PMC06 = 1 - - PMC30 = 1 PMC31 = 1 PMC32 = 1 PMC33 = 1 PMC33 = 1 PMC34 = 1 PMC35 = 1 PMC35 = 1 PMC38 = 1 PMC39 = 1 PMC40 = 1 PMC41 = 1 PMC42 = 1 - PFC33 = 0 PFC33 = 1 - PFC35 = 0 PFC35 = 1 - - - - - - - - - - - - - - - - - - - PF38 (PF3) = 1 PF39 (PF3) = 1 - PF41 (PF4) = Don't care PF42 (PF4) = Don't care - - - - - - - - - - - - - P01 = Setting not required P02 = Setting not required P03 = Setting not required P04 = Setting not required P05 = Setting not required P06 = Setting not required P10 = Setting not required P11 = Setting not required PM11 = 1 PM30 = Setting not required PM31 = Setting not required PM32 = Setting not required PM33 = Setting not required PM33 = Setting not required PM34 = Setting not required PM35 = Setting not required PM35 = Setting not required PM38 = Setting not required PM39 = Setting not required PM40 = Setting not required PM41 = Setting not required PM42 = Setting not required P30 = Setting not required P31 = Setting not required P32 = Setting not required P33 = Setting not required P33 = Setting not required P34 = Setting not required P35 = Setting not required P35 = Setting not required P38 = 1 P39 = 1 P40 = Setting not required P41 = Setting not required P42 = Setting not required 2 Note 1 Pin Name I/O PM00 = Setting not required PM01 = Setting not required PM02 = Setting not required PM03 = Setting not required PM04 = Setting not required PM05 = Setting not required PM06 = Setting not required PM10 = 1 Note 1 Alternate Function PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name - P00 TOH0 Output P01 TOH1 Output P02 NMI Input P03 INTP0 Input P04 INTP1 Input P05 INTP2 Input P06 INTP3 Input P10 ANO0 Output P11 ANO1 Output P30 TXD0 Output P31 RXD0 Input P32 ASCK0 Input P33 TI000 Input TO00 Output &+$37(5 3257 )81&7,216 8VHU(c)V 0DQXDO 8(-98' P34 TI001 Input P35 TI010 Input TO01 Output P38 SDA0 Note 2 I/O P39 SCL0 Note 2 I/O P40 SI00 Input P41 SO00 Output P42 SCK00 I/O Notes 1. When setting the ANO0 and ANO1 pins, set PM1 register = FFH all together. 2. Only in products with an I C bus Table 4-29. Settings When Port Pins Are Used for Alternate Functions (2/7) Pnx Bit of Pn Register PMCn Register PFCn Register P50 = Setting not required PMC50 = 1 PMC50 = 1 PMC50 = 0 PMC51 = 1 PMC51 = 1 PMC51 = 0 PMC52 = 1 PMC52 = 1 PMC52 = 0 PMC53 = 1 PMC53 = 1 PMC53 = 0 PMC54 = 1 PMC54 = 1 PMC54 = 0 PMC55 = 1 PMC55 = 1 PMC55 = 0 PFC52 = 1 PFC52 = 0 PFC53 = 0 PFC53 = 1 PFC53 = 0 PFC54 = 0 PFC54 = 1 PFC54 = 0 PFC55 = 0 PFC55 = 1 PFC55 = 0 PFC52 = 0 PFC51 = 0 PFC51 = 1 - KRM1 (KRM) = 1 - - KRM2 (KRM) = 1 - - KRM3 (KRM) = 1 PF54 (PF5) = Don't care PF54 (PF5) = 0 PF54 (PF5) = 0, KRM4 (KRM) = 1 PF55 (PF5) = Don't care PF55 (PF5) = 0 PF55 (PF5) = 0, KRM5 (KRM) = 1 PFC51 = 0 - PFC50 = 0 KRM0 (KRM) = 1 PFC50 = 1 - PFC50 = 0 P50 = Setting not required P50 = Setting not required P51 = Setting not required P51 = Setting not required P51 = Setting not required P52 = Setting not required P52 = Setting not required P52 = Setting not required P53 = Setting not required P53 = Setting not required P53 = Setting not required P54 = Setting not required P54 = Setting not required P54 = Setting not required P55 = Setting not required P55 = Setting not required P55 = Setting not required PM55 = 1 PM54 = 1 PM55 = Setting not required PM55 = Setting not required PM54 = Setting not required PM54 = Setting not required PM53 = 1 PM53 = Setting not required PM53 = Setting not required PM52 = 1 PM52 = Setting not required PM52 = Setting not required PM51 = 1 PM51 = Setting not required PM51 = Setting not required PM50 = 1 PM50 = Setting not required PM50 = Setting not required - PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Pin Name I/O Alternate Function Function Name P50 TI011 Input RTP00 Output KR0 Input P51 TI50 Input RTP01 Output KR1 Input P52 TO50 Output RTP02 Output KR2 Input P53 SIA0 Input RTP03 Output KR3 Input P54 SOA0 Output RTP04 Output &+$37(5 3257 )81&7,216 8VHU(c)V 0DQXDO 8(-98' KR4 Input P55 SCKA0 I/O RTP05 Output KR5 Input Table 4-29. Settings When Port Pins Are Used for Alternate Functions (3/7) Pnx Bit of Pn Register PMCn Register PFCn Register P60 = Setting not required PMC60 = 1 PMC61 = 1 PMC62 = 1 PMC63 = 1 PMC64 = 1 PMC65 = 1 PMC66 = 1 PMC67 = 1 PMC68 = 1 PMC69 = 1 PMC610 = 1 PMC611 = 1 PMC612 = 1 PMC613 = 1 PMC613 = 1 - - PFC613 = 0 PFC613 = 1 - - - - - - PF67 (PF6) = Don't care PF68 (PF6) = Don't care - - - - - - - - - - - - - - - - - P61 = Setting not required P62 = Setting not required P63 = Setting not required P64 = Setting not required P65 = Setting not required P66 = Setting not required P67 = Setting not required P68 = Setting not required P69 = Setting not required P610 = Setting not required P611 = Setting not required P612 = Setting not required P613 = Setting not required P613 = Setting not required PM613 = Setting not required PM613 = Setting not required PM612 = Setting not required PM611 = Setting not required PM610 = Setting not required PM69 = Setting not required PM68 = Setting not required PM67 = Setting not required PM66 = Setting not required PM65 = Setting not required PM64 = Setting not required PM63 = Setting not required PM62 = Setting not required PM61 = Setting not required PM60 = Setting not required - PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Pin Name Alternate Function Function Name P60 RTP10 Output P61 RTP11 Output P62 RTP12 Output P63 RTP13 Output P64 RTP14 Output P65 RTP15 Output P66 SI02 Input P67 SO02 Output P68 SCK02 I/O P69 TI040 Input P610 TI041 Input P611 TO04 Output P612 TI050 Input P613 TI051 Input &+$37(5 3257 )81&7,216 8VHU(c)V 0DQXDO 8(-98' TO05 Output Table 4-29. Settings When Port Pins Are Used for Alternate Functions (4/7) Pnx Bit of Pn Register PMCn Register PFCn Register P70 = Setting not required - - - - - - - - - - - - - - - - PMC80 = 1 PMC80 = 1 PMC81 = 1 PMC81 = 1 - - - - - - - PFC80 = 0 PFC80 = 1 PFC81 = 0 PFC81 = 1 - - - - - - - - - - - - - - - PF80 (PF8) = 0 PF80 (PF8) = 1 PF80 (PF8) = 0 PF81 (PF8) = 1 - - - - - - - - - P71 = Setting not required P72 = Setting not required P73 = Setting not required P74 = Setting not required P75 = Setting not required P76 = Setting not required P77 = Setting not required P78 = Setting not required P79 = Setting not required P710 = Setting not required P711 = Setting not required P712 = Setting not required P713 = Setting not required P714 = Setting not required P715 = Setting not required P80 = Setting not required P80 = Setting not required P81 = Setting not required P81 = Setting not required - PM80 = Setting not required PM80 = Setting not required PM81 = Setting not required PM81 = Setting not required - - - - - - - - - - - - - - - - PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Pin Name I/O Alternate Function Function Name P70 ANI0 Input P71 ANI1 Input P72 ANI2 Input P73 ANI3 Input P74 ANI4 Input P75 ANI5 Input P76 ANI6 Input P77 ANI7 Input P78 ANI8 Input P79 ANI9 Input P710 ANI10 Input P711 ANI11 Input P712 ANI12 Input P713 ANI13 Input &+$37(5 3257 )81&7,216 8VHU(c)V 0DQXDO 8(-98' P714 ANI14 Input P715 ANI15 Input P80 RXD2 Input SDA1 Note I/O P81 TXD2 Output SCL1 Note I/O Note Only in the PD703216Y, 703217Y, and 70F3217Y Table 4-29. Settings When Port Pins Are Used for Alternate Functions (5/7) Pnx Bit of Pn Register PMCn Register PFCn Register P90 = Setting not required PMC90 = 1 PMC90 = 1 PMC90 = 0 PMC91 = 1 PMC91 = 1 PMC91 = 0 PMC92 = 1 PMC92 = 0 PMC92 = 1 PMC93 = 1 PMC93 = 1 PMC94 = 1 PMC94 = 0 PMC94 = 1 PMC95 = 1 PMC95 = 1 PMC96 = 1 PMC96 = 0 PMC96 = 1 PMC97 = 1 PMC97 = 1 PMC98 = 1 PMC98 = 1 PM99 = Setting not required PM99 = Setting not required PMC99 = 1 PMC99 = 1 PFC93 = 0 PFC93 = 1 PFC94 = 0 PFC94 = 0 PFC94 = 1 PFC95 = 0 PFC95 = 1 PFC96 = 0 PFC96 = 0 PFC96 = 1 PFC97 = 0 PFC97 = 1 PFC98 = 0 PFC98 = 1 PFC99 = 0 PFC99 = 1 Note, PF98 (PF9) = 0 PF98 (PF9) = Don't care PM98 = Setting not required Note, PF98 (PF9) = 0 PF98 (PF9) = Don't care PFC92 = 1 PFC92 = 0 - - Note - Note - - Note - Note - - Note PFC92 = 0 Note PFC91 = 0 PFC91 = 1 - KRM7 (KRM) = 1 PFC91 = 0 Note PFC90 = 0 KRM6 (KRM) = 1 PFC90 = 1 - PFC90 = 0 Note P90 = Setting not required P90 = Setting not required P91 = Setting not required P91 = Setting not required P91 = Setting not required P92 = Setting not required P92 = Setting not required P92 = 1 P93 = Setting not required P93 = Setting not required P94 = Setting not required P94 = Setting not required P94 = Setting not required P95 = Setting not required P95 = Setting not required P96 = Setting not required P96 = Setting not required P96 = Setting not required P97 = Setting not required P97 = Setting not required P98 = Setting not required P98 = Setting not required P99 = Setting not required P99 = Setting not required PM96 = 1 PM96 = Setting not required PM97 = Setting not required PM97 = Setting not required PM98 = Setting not required PM96 = Setting not required PM95 = Setting not required PM95 = Setting not required PM94 = Setting not required PM94 = 1 PM94 = Setting not required PM93 = Setting not required PM93 = Setting not required PM92 = Setting not required PM92 = Setting not required PM92 = Setting not required PM91 = 1 PM91 = Setting not required PM91 = Setting not required PM90 = 1 PM90 = Setting not required PM90 = Setting not required PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Pin Name Alternate Function Function Name P90 A0 Output TXD1 Output KR6 Input P91 A1 Output RXD1 Input KR7 Input P92 A2 Output TI020 Input TO02 Output P93 A3 Output TI021 Input P94 A4 Output TI030 Input TO03 Output &+$37(5 3257 )81&7,216 8VHU(c)V 0DQXDO 8(-98' P95 A5 Output TI031 Input P96 A6 Output TI51 Input TO51 Output P97 A7 Output SI01 Input P98 A8 Output SO01 Output P99 A9 Output SCK01 I/O Note When setting the A0 to A15 pins, set the PFC9 register to 0000H and the PMC9 register to FFFFH in 16-bit units. Table 4-29. Settings When Port Pins Are Used for Alternate Functions (6/7) Pnx Bit of Pn Register PMCn Register PFCn Register P910 = Setting not required PMC910 = 1 PMC910 = 1 PMC911 = 1 PMC911 = 1 PMC912 = 1 PMC912 = 1 PMC913 = 1 PMC913 = 1 PMC914 = 1 PMC914 = 1 PMC915 = 1 PMC915 = 1 PMCCM0 = 1 PMCCM1 = 1 PMCCM2 = 1 PMCCM3 = 1 PMCCS0 = 1 PMCCS1 = 1 PMCCS2 = 1 PMCCS3 = 1 PMCCT0 = 1 PMCT1 = Setting not required PMCT4 = Setting not required PMCT6 = Setting not required PMCCT1 = 1 PMCCT4 = 1 PMCCT6 = 1 PFC913 = 0 PFC913 = 1 PFC914 = 0 PFC914 = 1 PFC915 = 0 PFC915 = 1 - - - - - - - - - - - - PFC912 = 1 PFC912 = 0 PFC911 = 1 PFC911 = 0 PFC910 = 1 - Note, PF911 (PF9) = 0 PF911 (PF9) = Don't care Note, PF912 (PF9) = 0 PF912 (PF9) = Don't care Note - Note I- Note - - - - - - - - - - PMCT0 = Setting not required - - - PFC910 = 0 Note P910 = Setting not required P911 = Setting not required P911 = Setting not required P912 = Setting not required P912 = Setting not required P913 = Setting not required P913 = Setting not required P914 = Setting not required P914 = Setting not required P915 = Setting not required P915 = Setting not required PCM0 = Setting not required PCM1 = Setting not required PCM2 = Setting not required PCM3 = Setting not required PCS0 = Setting not required PCS1 = Setting not required PCS2 = Setting not required PCS3 = Setting not required PCT0 = Setting not required PCT1 = Setting not required PCT4 = Setting not required PCT6 = Setting not required PMCM2 = Setting not required PMCM3 = Setting not required PMCS0 = Setting not required PMCS1 = Setting not required PMCS2 = Setting not required PMCS3 = Setting not required PMCM1 = Setting not required PMCM0 = Setting not required PM915 = Setting not required PM915 = Setting not required PM914 = Setting not required PM914 = Setting not required PM913 = Setting not required PM913 = Setting not required PM912 = Setting not required PM912 = Setting not required PM911 = Setting not required PM911 = Setting not required PM910 = Setting not required PM910 = Setting not required PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Pin Name I/O Alternate Function Function Name P910 A10 Output SIA1 Input P911 A11 Output SOA1 Output P912 A12 Output SCKA1 I/O P913 A13 Output INTP4 Input P914 A14 Output INTP5 Input P915 A15 Output INTP6 Input PCM0 WAIT Input PCM1 CLKOUT Output &+$37(5 3257 )81&7,216 8VHU(c)V 0DQXDO 8(-98' PCM2 HLDAK Output PCM3 HLDRQ Input PCS0 CS0 Output PCS1 CS1 Output PCS2 CS2 Output PCS3 CS3 Output PCT0 WR0 Output PCT1 WR1 Output PCT4 RD Output PCT6 ASTB Output Note When setting the A0 to A15 pins, set the PFC9 register to 0000H and the PMC9 register to FFFFH in 16-bit units. Table 4-29. Settings When Port Pins Are Used for Alternate Functions (7/7) Pnx Bit of Pn Register PMCn Register PFCn Register PDH0 = Setting not required PMCDH0 = 1 PMCDH1 = 1 PMCDH2 = 1 PMCDH3 = 1 PMCDH4 = 1 PMCDH5 = 1 PMCDH6 = 1 PMCDH7 = 1 PMCDL0 = 1 PMCDL1 = 1 PMCDL2 = 1 PMCDL3 = 1 PMCDL4 = 1 PMCDL5 = 1 PMCDL6 = 1 PMCDL7 = 1 PMCDL8 = 1 PMCDL9 = 1 - - - - - - - - - - - - PMDL15 = Setting not required PMCDL15 = 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PDH1 = Setting not required PDH2 = Setting not required PDH3 = Setting not required PDH4 = Setting not required PDH5 = Setting not required PDH6 = Setting not required PDH7 = Setting not required PDL0 = Setting not required PDL1 = Setting not required PDL2 = Setting not required PDL3 = Setting not required PDL4 = Setting not required PDL5 = Setting not required PDL6 = Setting not required PDL7 = Setting not required PDL8 = Setting not required PDL9 = Setting not required PDL10 = Setting not required PDL11 = Setting not required PDL12 = Setting not required PDL13 = Setting not required PDL14 = Setting not required PDL15 = Setting not required PMDL8 = Setting not required PMDL9 = Setting not required PMDL7 = Setting not required PMDL6 = Setting not required PMDL5 = Setting not required PMDL4 = Setting not required PMDL3 = Setting not required PMDL2 = Setting not required PMDL1 = Setting not required PMDL0 = Setting not required PMDH7 = Setting not required PMDH6 = Setting not required PMDH5 = Setting not required PMDH4 = Setting not required PMDH3 = Setting not required PMDH2 = Setting not required PMDH1 = Setting not required PMDH0 = Setting not required - PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O PMDL10 = Setting not required PMCDL10 = 1 PMDL11 = Setting not required PMCDL11 = 1 PMDL12 = Setting not required PMCDL12 = 1 PMDL13 = Setting not required PMCDL13 = 1 PMDL14 = Setting not required PMCDL14 = 1 Pin Name Alternate Function Function Name PDH0 A16 Output PDH1 A17 Output PDH2 A18 Output PDH3 A19 Output PDH4 A20 Output PDH5 A21 Output PDH6 A22 Output PDH7 A23 Output PDL0 AD0 I/O PDL1 AD1 I/O PDL2 AD2 I/O PDL3 AD3 I/O PDL4 AD4 I/O PDL5 AD5 I/O &+$37(5 3257 )81&7,216 8VHU(c)V 0DQXDO 8(-98' PDL6 AD6 I/O PDL7 AD7 I/O PDL8 AD8 I/O PDL9 AD9 I/O PDL10 AD10 I/O PDL11 AD11 I/O PDL12 AD12 I/O PDL13 AD13 I/O PDL14 AD14 I/O PDL15 AD15 I/O &+$37(5 3257 )81&7,216 &DXWLRQV &DXWLRQV RQ ELW PDQLSXODWLRQ LQVWUXFWLRQ IRU SRUW Q UHJLVWHU 3Q :KHQ D ELW PDQLSXODWLRQ LQVWUXFWLRQ LV H[HFXWHG RQ D SRUW WKDW SURYLGHV ERWK LQSXW DQG RXWSXW IXQFWLRQV WKH YDOXH RI WKH RXWSXW ODWFK RI DQ LQSXW SRUW WKDW LV QRW VXEMHFW WR PDQLSXODWLRQ PD\ EH ZULWWHQ LQ DGGLWLRQ WR WKH WDUJHWHG ELW 7KHUHIRUH LW LV UHFRPPHQGHG WR UHZULWH WKH RXWSXW ODWFK ZKHQ VZLWFKLQJ D SRUW IURP LQSXW PRGH WR RXWSXW PRGH ([DPSOH! :KHQ 3 LV DQ RXWSXW SRUW 3 WR 3 DUH LQSXW SRUWV DOO SLQ VWDWXVHV DUH KLJK OHYHO YLD D ELW PDQLSXODWLRQ LQVWUXFWLRQ WKH YDOXH RI WKH SRUW ODWFK LV [)) ([SODQDWLRQ 7KH WDUJHWV RI ZULWLQJ WR DQG UHDGLQJ IURP WKH 3Q UHJLVWHU RI D SRUW ZKRVH 30QP ELW LV DUH WKH RXWSXW ODWFK DQG SLQ VWDWXV UHVSHFWLYHO\ $ ELW PDQLSXODWLRQ LQVWUXFWLRQ LV H[HFXWHG LQ WKH IROORZLQJ RUGHU LQ WKH 9(6.[ ! 7KH 3Q UHJLVWHU LV UHDG LQ ELW XQLWV ! 7KH WDUJHWHG RQH ELW LV PDQLSXODWHG ! 7KH 3Q UHJLVWHU LV ZULWWHQ LQ ELW XQLWV ,Q VWHS ! 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RI ELW WLPHUHYHQW FRXQWHU Q ELW WLPHU FRXQWHU Q &5Q ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 7KH IROORZLQJ VKRZV WKH ,2 FRQILJXUDWLRQ RI HDFK FKDQQHO DQG WKH VHOHFWLRQ RI WKH 72Q RXWSXW LQYHUVLRQ WLPLQJ VHWWLQJ RI WKH 70&Q ELW 7DEOH ,2 &RQILJXUDWLRQ RI (DFK &KDQQHO &KDQQHO 70 70 70 70 70 70 72 - 2XWSXW 3LQ - - - - 7, 7, 7, 7, 7, 7, 7, ,QSXW 3LQ ,2 3LQ 7,72 7,72 7,72 7,72 - 7,72 6HWWLQJ RI 70&Q %LW $OZD\V VHW WR $OZD\V VHW WR UHDG RQO\ UHDG RQO\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q &5&Q FRQWUROV WKH RSHUDWLRQ RI ELW WLPHU FDSWXUHFRPSDUH UHJLVWHUV Q DQG Q &5Q DQG &5Q 7KH &5&Q UHJLVWHU LV VHW E\ DQ ELW RU ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ $IWHU UHVHW &5&Q LV FOHDUHG WR + After reset: 00H R/W Address: FFFFF608H, FFFFF618H, FFFFF628H FFFFF638H, FFFFF648H, FFFFF658H 5 0 4 0 3 0 2 1 0 7 CRC0n (n = 0 to 5) CRC0n2 0 1 0 6 0 CRC0n2 CRC0n1 CRC0n0 Selection of operation mode of CR0n1 register Operation as compare register Operation as capture register CRC0n1 0 1 Selection of capture trigger of CR0n0 register Capture at valid edge of TI0n1 Capture at inverse phase of valid edge of TI0n0 CRC0n0 0 1 Selection of operation mode of CR0n0 register Operation as compare register Operation as capture register &DXWLRQV %HIRUH VHWWLQJ WKH &5&Q UHJLVWHU EH VXUH WR VWRS WKH WLPHU RSHUDWLRQ :KHQ WKH PRGH LQ ZKLFK WKH WLPHU LV FOHDUHG DQG VWDUWHG XSRQ PDWFK RI WKH 70Q UHJLVWHU DQG &5Q UHJLVWHU LV VHOHFWHG E\ ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q GR QRW VSHFLI\ WKH &5Q UHJLVWHU DV WKH FDSWXUH UHJLVWHU :KHQ ERWK WKH ULVLQJ DQG IDOOLQJ HGJHV DUH VSHFLILHG IRU WKH 7,Q YDOLG HGJH FDSWXUH RSHUDWLRQ LV QRW SHUIRUPHG 7R HQVXUH UHOLDEOH FDSWXUH RSHUDWLRQ D SXOVH ORQJHU WKDQ WZR F\FOHV RI WKH FRXQW FORFN VHOHFWHG E\ SUHVFDOHU PRGH UHJLVWHU Q 350Q LV UHTXLUHG 5HPDUN 7,Q 7,Q ,QSXW SLQV RI ELW WLPHUHYHQW FRXQWHU Q 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 ELW WLPHU RXWSXW FRQWURO UHJLVWHU Q 72&Q 72&Q FRQWUROV WKH RSHUDWLRQ RI WKH ELW WLPHUHYHQW FRXQWHU Q RXWSXW FRQWUROOHU E\ VHWWLQJ RU UHVHWWLQJ WKH WLPHU RXWSXW )) HQDEOLQJ RU GLVDEOLQJ LQYHUVH RXWSXW HQDEOLQJ RU GLVDEOLQJ WKH WLPHU RI ELW WLPHUHYHQW FRXQWHU Q HQDEOLQJ RU GLVDEOLQJ WKH RQHVKRW SXOVH RXWSXW RSHUDWLRQ DQG VHOHFWLQJ DQ RXWSXW WULJJHU IRU D RQHVKRW SXOVH E\ VRIWZDUH ELW WLPHUHYHQW FRXQWHUV DQG GR QRW KDYH D RQHVKRW SXOVH RXWSXW IXQFWLRQ 7KH 72&Q UHJLVWHU LV VHW E\ DQ ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ $IWHU UHVHW 72&Q LV FOHDUHG WR + After reset: 00H R/W Address: FFFFF609H, FFFFF619H, FFFFF629H FFFFF639H, FFFFF649H, FFFFF659H 5 4 3 LVS0n 2 LVR0n 1 TOC0n1 0 TOE0n 7 TOC0n (n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5) 0 6 OSPT0mNote 1 OSPE0mNote 1 TOC0n4 OSPT0mNote 1 0 1 Output trigger for one-shot pulse by software - One-shot pulse output OSPE0mNote 1 0 1 Control of one-shot pulse output operation Successive pulse output One-shot pulse outputNote 2 TOC0n4 0 1 Control of timer output F/F upon match of CR0n1 register and TM0n register Inversion operation disabled Inversion operation enabled 1RWHV 70 DQG 70 GR QRW SURYLGH D RQHVKRW SXOVH RXWSXW IXQFWLRQ $OZD\V FOHDU ELWV DQG WR 70 DQG 70 DUH WKH DOWHUQDWHIXQFWLRQ SLQV RI WKH WLPHU ,2 SLQV VR RQO\ D VRIWZDUH WULJJHU LV YDOLG IRU RQHVKRW SXOVH RXWSXW &OHDU WKH 70& DQG 70& ELWV RI WKH 70& DQG 70& UHJLVWHUV WR 7KH RQHVKRW SXOVH RXWSXW RSHUDWHV QRUPDOO\ LQ WKH IUHHUXQQLQJ PRGH DQG WKH PRGH LQ ZKLFK FOHDU VWDUW RFFXUV RQ WKH YDOLG HGJH RI 7,N ,Q WKH PRGH LQ ZKLFK FOHDU VWDUW RFFXUV RQ PDWFK EHWZHHQ WKH 70P UHJLVWHU DQG WKH &5P UHJLVWHU RQHVKRW SXOVH RXWSXW LV QRW SHUIRUPHG EHFDXVH QR RYHUIORZ RFFXUV 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 LVS0n 0 0 1 1 LVR0n 0 1 0 1 Unchanged Reset timer output F/F (0) Set timer output F/F (1) Setting prohibited Setting of status of timer output F/F TOC0n1 0 1 Control of timer output F/F upon match of CR0n0 register and TM0n register Inversion operation disabled Inversion operation enabled TOE0n 0 1 Control of timer output Output disabled (output is fixed to 0 level) Output enabled &DXWLRQV %H VXUH WR VWRS WKH WLPHU RSHUDWLRQ EHIRUH VHWWLQJ RWKHU WKDQ WKH 72&Q ELW 7KH /96Q DQG /95Q ELWV DUH ZKHQ UHDG 7KH 2637P ELW LV ZKHQ UHDG EHFDXVH LW LV DXWRPDWLFDOO\ FOHDUHG DIWHU GDWD KDV EHHQ VHW 'R QRW VHW WR WKH 2637P ELW RWKHU WKDQ IRU RQHVKRW SXOVH RXWSXW :KHQ SHUIRUPLQJ VXFFHVVLYH ZULWHV WR WKH 2637P ELW SODFH DQ LQWHUYDO EHWZHHQ ZULWHV RI WZR RU PRUH F\FOHV RI WKH FRXQW FORFN VHOHFWHG E\ WKH 350Q UHJLVWHU 'R QRW WKH /96Q ELW WR EHIRUH VHWWLQJ WKH 72(Q ELW 'R QRW VHW WKH /96Q ELW DQG 72(Q ELW WR DW WKH VDPH WLPH 'R QRW VHW ! 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5HPDUN I;; 0DLQ FORFN IUHTXHQF\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 E 3UHVFDOHU PRGH UHJLVWHU 350 After reset: 00H 7 PRM01 ES111 R/W 6 ES110 Address: FFFFF617H 5 ES101 4 ES100 3 0 2 0 1 0 PRM011 PRM010 ES111 0 0 1 1 ES110 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI011 Setting prohibited Both rising and falling edges ES101 0 0 1 1 ES100 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI010 Setting prohibited Both rising and falling edges PRM011 PRM010 Selection of count clockNote 1 Count clock 20 MHz Setting prohibited fXX 16 MHz Setting prohibited 10 MHz 100 ns 400 ns - - 0 0 1 1 0 1 0 1 fXX fXX/4 INTWT Valid edge of TI010 Note 2 200 ns - - 250 ns - - 1RWHV :KHQ WKH LQWHUQDO FORFN LV VHOHFWHG VHW VR DV WR VDWLVI\ WKH IROORZLQJ FRQGLWLRQV 9'' 9'' WR 9 &RXQW FORFN 0+] WR 9 &RXQW FORFN 0+] 7KH H[WHUQDO FORFN UHTXLUHV D SXOVH ORQJHU WKDQ WZR F\FOHV RI WKH LQWHUQDO FORFN I;; 5HPDUN I;; 0DLQ FORFN IUHTXHQF\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 F 3UHVFDOHU PRGH UHJLVWHU 350 After reset: 00H 7 PRM02 ES211 R/W 6 ES210 Address: FFFFF627H 5 ES201 4 ES200 3 0 2 0 1 0 PRM021 PRM020 ES211 0 0 1 1 ES210 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI021 Setting prohibited Both rising and falling edges ES201 0 0 1 1 ES200 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI020 Setting prohibited Both rising and falling edges PRM021 PRM020 Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - 10 MHz 200 ns 400 ns 800 ns - 0 0 1 1 0 1 0 1 fXX/2 fXX/4 fXX/8 Valid edge of TI020 Note 2 100 ns 200 ns 400 ns - 1RWHV :KHQ WKH LQWHUQDO FORFN LV VHOHFWHG VHW VR DV WR VDWLVI\ WKH IROORZLQJ FRQGLWLRQV 9'' 9'' WR 9 &RXQW FORFN 0+] WR 9 &RXQW FORFN 0+] 7KH H[WHUQDO FORFN UHTXLUHV D SXOVH ORQJHU WKDQ WZR F\FOHV RI WKH LQWHUQDO FORFN I;; 5HPDUN I;; 0DLQ FORFN IUHTXHQF\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 G 3UHVFDOHU PRGH UHJLVWHU 350 After reset: 00H 7 PRM03 ES311 R/W 6 ES310 Address: FFFFF637H 5 ES301 4 ES300 3 0 2 0 1 0 PRM031 PRM030 ES311 0 0 1 1 ES310 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI031 Setting prohibited Both rising and falling edges ES301 0 0 1 1 ES300 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI030 Setting prohibited Both rising and falling edges PRM031 PRM030 Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 250 ns 1 s 32 s - 10 MHz 400 ns 1.6 s 51.2 s - 0 0 1 1 0 1 0 1 fXX/4 fXX/16 fXX/512 Valid edge of TI030 Note 2 200 ns 800 ns 25.6 s - 1RWHV :KHQ WKH LQWHUQDO FORFN LV VHOHFWHG VHW VR DV WR VDWLVI\ WKH IROORZLQJ FRQGLWLRQV 9'' 9'' WR 9 &RXQW FORFN 0+] WR 9 &RXQW FORFN 0+] 7KH H[WHUQDO FORFN UHTXLUHV D SXOVH ORQJHU WKDQ WZR F\FOHV RI WKH LQWHUQDO FORFN I;; 5HPDUN I;; 0DLQ FORFN IUHTXHQF\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 H 3UHVFDOHU PRGH UHJLVWHU 350 After reset: 00H 7 PRM04 ES411 R/W 6 ES410 Address: FFFFF647H 5 ES401 4 ES400 3 0 2 0 1 0 PRM041 PRM040 ES411 0 0 1 1 ES410 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI041 Setting prohibited Both rising and falling edges ES401 0 0 1 1 ES400 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI040 Setting prohibited Both rising and falling edges PRM041 PRM040 Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - 10 MHz 200 ns 400 ns 800 ns - 0 0 1 1 0 1 0 1 fXX/2 fXX/4 fXX/8 Valid edge of TI040 Note 2 100 ns 200 ns 400 ns - 1RWHV :KHQ WKH LQWHUQDO FORFN LV VHOHFWHG VHW VR DV WR VDWLVI\ WKH IROORZLQJ FRQGLWLRQV 9'' 9'' WR 9 &RXQW FORFN 0+] WR 9 &RXQW FORFN 0+] 7KH H[WHUQDO FORFN UHTXLUHV D SXOVH ORQJHU WKDQ WZR F\FOHV RI WKH LQWHUQDO FORFN I;; 5HPDUN I;; 0DLQ FORFN IUHTXHQF\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 I 3UHVFDOHU PRGH UHJLVWHU 350 After reset: 00H 7 PRM05 ES511 R/W 6 ES510 Address: FFFFF657H 5 ES501 4 ES500 3 0 2 0 1 0 PRM051 PRM050 ES511 0 0 1 1 ES510 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI051 Setting prohibited Both rising and falling edges ES501 0 0 1 1 ES500 0 1 0 1 Falling edge Rising edge Selection of valid edge of TI050 Setting prohibited Both rising and falling edges PRM051 PRM050 Selection of count clockNote 1 Count clock 20 MHz Setting prohibited fXX 16 MHz Setting prohibited 10 MHz 100 ns 400 ns 25.6 s - 0 0 1 1 0 1 0 1 fXX fXX/4 fXX/256 Valid edge of TI050 Note 2 200 ns 12.8 s - 250 ns 16 s - 1RWHV :KHQ WKH LQWHUQDO FORFN LV VHOHFWHG VHW VR DV WR VDWLVI\ WKH IROORZLQJ FRQGLWLRQV 9'' 9'' WR 9 &RXQW FORFN 0+] WR 9 &RXQW FORFN 0+] 7KH H[WHUQDO FORFN UHTXLUHV D SXOVH ORQJHU WKDQ WZR F\FOHV RI WKH LQWHUQDO FORFN I;; 5HPDUN I;; 0DLQ FORFN IUHTXHQF\ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 2SHUDWLRQ 2SHUDWLRQ DV LQWHUYDO WLPHU ELWV ELW WLPHUHYHQW FRXQWHU Q FDQ EH PDGH WR RSHUDWH DV DQ LQWHUYDO WLPHU E\ VHWWLQJ ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q DQG FDSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q DV VKRZQ LQ )LJXUH Q 6HWWLQJ SURFHGXUH 7KH EDVLF RSHUDWLRQ VHWWLQJ SURFHGXUH LV DV IROORZV ! 6HW WKH FRXQW FORFN XVLQJ WKH 350Q UHJLVWHU ! 6HW WKH &5&Q UHJLVWHU VHH )LJXUH IRU WKH VHWWLQJ YDOXH ! 6HW DQ\ YDOXH WR WKH &5Q UHJLVWHU ! 6HW WKH 70&Q UHJLVWHU 6WDUW RSHUDWLRQ VHH )LJXUH IRU WKH VHWWLQJ YDOXH &DXWLRQ 7KH &5Q UHJLVWHU FDQQRW EH UHZULWWHQ GXULQJ 70Q RSHUDWLRQ 5HPDUNV )RU WKH DOWHUQDWHIXQFWLRQ SLQ VHWWLQJV UHIHU WR 7DEOH 6HWWLQJV :KHQ 3RUW 3LQV $UH 8VHG IRU $OWHUQDWH )XQFWLRQV )RU ,1770Q LQWHUUXSW HQDEOH UHIHU WR &+$37(5 ,17(55837(;&(37,21 352&(66,1* )81&7,21 7KH LQWHUYDO WLPHU UHSHDWHGO\ JHQHUDWHV LQWHUUXSWV DW WKH LQWHUYDO RI WKH SUHVHW FRXQW YDOXH LQ ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q ,I WKH FRXQW YDOXH LQ ELW WLPHU FRXQWHU Q 70Q PDWFKHV WKH YDOXH VHW LQ WKH &5Q UHJLVWHU DQ LQWHUUXSW UHTXHVW VLJQDO ,1770Q LV JHQHUDWHG DW WKH VDPH WLPH WKDW WKH YDOXH RI WKH 70Q UHJLVWHU LV FOHDUHG WR DQG FRXQWLQJ LV FRQWLQXHG 7KH FRXQW FORFN RI ELW WLPHUHYHQW FRXQWHU Q FDQ EH VHOHFWHG ZLWK ELWV DQG RI SUHVFDOHU PRGH UHJLVWHU Q 350Q 5HPDUN Q WR WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQWURO 5HJLVWHU 6HWWLQJ &RQWHQWV 'XULQJ ,QWHUYDO 7LPHU 2SHUDWLRQ D ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0/1 OVF0n 0 Clears & starts upon match between TM0n and CR0n0 E &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0/1 0/1 0 CR0n0 used as compare register 5HPDUNV :KHQ WKHVH ELWV DUH UHVHW WR RU VHW WR RWKHU IXQFWLRQV FDQ EH XVHG WRJHWKHU ZLWK WKH LQWHUYDO WLPHU IXQFWLRQ )RU GHWDLOV UHIHU WR ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q DQG &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q Q WR )LJXUH &RQILJXUDWLRQ RI ,QWHUYDO 7LPHU 16-bit timer capture/compare register 0n0 (CR0n0) INTTM0n0 Count clockNote Selector TI0n0 Noise eliminator fxx/4 16-bit timer counter 0n (TM0n) OVF0n Clear circuit 1RWH 6HW ZLWK 350Q UHJLVWHU 5HPDUNV I;; 0DLQ FORFN IUHTXHQF\ Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH 7LPLQJ RI ,QWHUYDO 7LPHU 2SHUDWLRQ t Count clock TM0n count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N Timer operation enable CR0n0 INTTM0n0 N Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time 5HPDUNV ,QWHUYDO WLPH Q WR 1 x W 1 + WR ))))+ 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 33* RXWSXW RSHUDWLRQ ELW WLPHUHYHQW FRXQWHU Q FDQ EH XVHG IRU 33* 3URJUDPPDEOH 3XOVH *HQHUDWRU RXWSXW E\ VHWWLQJ ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q DQG FDSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q DV VKRZQ LQ )LJXUH 6HWWLQJ SURFHGXUH 7KH EDVLF RSHUDWLRQ VHWWLQJ SURFHGXUH LV DV IROORZV ! 6HW WKH &5&Q UHJLVWHU VHH )LJXUH IRU WKH VHWWLQJ YDOXH ! 6HW DQ\ YDOXH WR WKH &5Q UHJLVWHU ! 6HW DQ\ YDOXH DV D GXW\ WR WKH &5Q UHJLVWHU ! 6HW WKH 72&Q UHJLVWHU VHH )LJXUH IRU WKH VHWWLQJ YDOXH ! 6HW WKH FRXQW FORFN XVLQJ WKH 350Q UHJLVWHU ! 6HW WKH 70&Q UHJLVWHU 6WDUW RSHUDWLRQ VHH )LJXUH IRU WKH VHWWLQJ YDOXH 1RWH 7R FKDQJH WKH GXW\ YDOXH &5Q UHJLVWHU GXULQJ RSHUDWLRQ UHIHU WR 5HPDUN LQ )LJXUH 33* 2XWSXW 2SHUDWLRQ 7LPLQJ 5HPDUNV )RU WKH DOWHUQDWHIXQFWLRQ SLQ 72Q VHWWLQJV UHIHU WR 7DEOH 6HWWLQJV :KHQ 3RUW 3LQV $UH 8VHG IRU $OWHUQDWH )XQFWLRQ )RU ,1770Q LQWHUUXSW HQDEOH UHIHU WR &+$37(5 ,17(55837(;&(37,21 352&(66,1* )81&7,21 7KH 33* RXWSXW IXQFWLRQ RXWSXWV D UHFWDQJXODU ZDYH IURP WKH 72Q SLQ ZLWK WKH F\FOH VSHFLILHG E\ WKH FRXQW YDOXH VHW LQ DGYDQFH WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q DQG WKH SXOVH ZLGWK VSHFLILHG E\ WKH FRXQW YDOXH VHW LQ DGYDQFH WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQWURO 5HJLVWHU 6HWWLQJV LQ 33* 2XWSXW 2SHUDWLRQ D ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0 OVF0n 0 Clears and starts upon match between TM0n and CR0n0 E &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0 x 0 x: Don't care CR0n0 used as compare register CR0n1 used as compare register F ELW WLPHU RXWSXW FRQWURO UHJLVWHU Q 72&Q OSPT0n OSPE0n TOC0n4 TOC0n 0 0 0 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 Enables TO0n output Inverts output upon match between TM0n and CR0n0 Specifies initial value of TO0n output F/F Inverts output upon match between TM0n and CR0n1 Disables one-shot pulse output (other than TM02, TM03) G 3UHVFDOHU PRGH UHJLVWHU Q 350Q ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0/1 ESn00 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock Setting invalid (Setting to 10 is prohibited.) Setting invalid (Setting to 10 is prohibited.) &DXWLRQV 0DNH VXUH WKDW + &5Q &5Q ))))+ LV VHW WR WKH &5Q UHJLVWHU DQG &5Q UHJLVWHU 7KH F\FOH RI WKH SXOVH JHQHUDWHG E\ 33* RXWSXW LV &5Q VHWWLQJ YDOXH 7KH GXW\ IDFWRU LV &5Q VHWWLQJ YDOXH 5HPDUN Q WR 8VHU(c)V 0DQXDO 8(-98' &5Q VHWWLQJ YDOXH &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQILJXUDWLRQ RI 33* 2XWSXW 16-bit capture/compare register 0n0 (CR0n0) Selector Count clockNote TI0k0 Noise eliminator fxx/4 16-bit timer counter 0n (TM0n) Clear circuit Output controller TO0n 16-bit capture/compare register 0n1 (CR0n1) 1RWH 7KH FRXQW FORFN LV VHW E\ WKH 350Q UHJLVWHU 5HPDUN N Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH 33* 2XWSXW 2SHUDWLRQ 7LPLQJ t Count clock TM0n count value N 0000H 0001H Clear Value loaded to CR0n0 Value loaded to CR0n1 TO0n Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M M-1 M N-1 N 0000H 0001H Clear &DXWLRQ &5Q FDQQRW EH UHZULWWHQ GXULQJ 70Q RSHUDWLRQ 5HPDUNV + 0 1 ))))+ &KDQJH WKH SXOVH ZLGWK GXULQJ 70Q RSHUDWLRQ UHZULWH &5Q DV IROORZV LQ D 33* RXWSXW RSHUDWLRQ ! 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(QDEOH WKH ,1770Q LQWHUUXSW 700.Q Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 3XOVH ZLGWK PHDVXUHPHQW 7KH ELW WLPHU FRXQWHU 70Q FDQ EH XVHG WR PHDVXUH WKH SXOVH ZLGWKV RI WKH VLJQDOV LQSXW WR WKH 7,Q DQG 7,Q SLQV 0HDVXUHPHQW FDQ EH FDUULHG RXW ZLWK WKH 70Q UHJLVWHU XVHG DV D IUHHUXQQLQJ FRXQWHU RU E\ UHVWDUWLQJ WKH WLPHU LQ V\QFKURQL]DWLRQ ZLWK WKH HGJH RI WKH VLJQDO LQSXW WR WKH 7,Q SLQ :KHQ DQ LQWHUUXSW LV JHQHUDWHG UHDG WKH YDOLG FDSWXUH UHJLVWHU YDOXH $IWHU FRQILUPLQJ WKH 29) IODJ FOHDU LW E\ VRIWZDUH DQG PHDVXUH WKH SXOVH ZLGWK 6HWWLQJ SURFHGXUH 7KH EDVLF RSHUDWLRQ VHWWLQJ SURFHGXUH LV DV IROORZV ! 6HW WKH &5&Q UHJLVWHU VHH )LJXUHV DQG IRU WKH VHWWLQJ YDOXH ! 6HW WKH FRXQW FORFN XVLQJ WKH 350Q UHJLVWHU ! 6HW WKH 70&Q UHJLVWHU 6WDUW RSHUDWLRQ VHH )LJXUHV DQG IRU WKH VHWWLQJ YDOXH 1RWH :KHQ XVLQJ WZR FDSWXUH UHJLVWHUV VHW WKH 7,Q DQG 7,Q SLQV 5HPDUNV )RU WKH DOWHUQDWHIXQFWLRQ SLQ 7,Q 7,Q VHWWLQJV UHIHU 7DEOH 6HWWLQJV :KHQ 3RUW 3LQV $UH 8VHG IRU $OWHUQDWH )XQFWLRQV )RU ,1770Q DQG ,1770Q LQWHUUXSW HQDEOH UHIHU WR &+$37(5 ,17(55837(;&(37,21 352&(66,1* )81&7,21 7KH YDOLG HGJH LV GHWHFWHG WKURXJK VDPSOLQJ DW D FRXQW FORFN F\FOH VHOHFWHG ZLWK WKH 350Q UHJLVWHU DQG WKH FDSWXUH RSHUDWLRQ LV QRW SHUIRUPHG XQWLO WKH YDOLG HGJH LV GHWHFWHG WZLFH $V D UHVXOW QRLVH ZLWK D VKRUW SXOVH ZLGWK FDQ EH HOLPLQDWHG )LJXUH &5Q &DSWXUH 2SHUDWLRQ ZLWK 5LVLQJ (GJH 6SHFLILHG Count clock TM0n TI0n0 Rising edge detection CR0n1 INTTM0n1 N N-3 N-2 N-1 N N+1 5HPDUN Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 3XOVH ZLGWK PHDVXUHPHQW ZLWK IUHHUXQQLQJ FRXQWHU DQG RQH FDSWXUH UHJLVWHU ,I WKH HGJH VSHFLILHG E\ SUHVFDOHU PRGH UHJLVWHU Q 350Q LV LQSXW WR WKH 7,Q SLQ ZKHQ ELW WLPHU FRXQWHU Q 70Q LV RSHUDWHG DV D IUHHUXQQLQJ FRXQWHU UHIHU WR )LJXUH WKH YDOXH RI WKH 70Q UHJLVWHU LV ORDGHG WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q DQG DQ H[WHUQDO LQWHUUXSW UHTXHVW VLJQDO ,1770Q LV VHW 7KH HGJH LV VSHFLILHG E\ XVLQJ ELWV DQG (6Q (6Q RI WKH 350Q UHJLVWHU 7KH ULVLQJ HGJH IDOOLQJ HGJH RU ERWK WKH ULVLQJ DQG IDOOLQJ HGJHV FDQ EH VHOHFWHG 7KH YDOLG HGJH LV GHWHFWHG WKURXJK VDPSOLQJ DW D FRXQW FORFN F\FOH VHOHFWHG ZLWK WKH 350Q UHJLVWHU DQG WKH FDSWXUH RSHUDWLRQ LV QRW SHUIRUPHG XQWLO WKH YDOLG HGJH LV GHWHFWHG WZLFH $V D UHVXOW QRLVH ZLWK D VKRUW SXOVH ZLGWK FDQ EH HOLPLQDWHG 5HPDUN Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQWURO 5HJLVWHU 6HWWLQJV IRU 3XOVH :LGWK 0HDVXUHPHQW ZLWK )UHH5XQQLQJ &RXQWHU DQG 2QH &DSWXUH 5HJLVWHU :KHQ 7,Q 3LQ DQG &5Q 5HJLVWHUV $UH 8VHG D ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1 Note OVF0n 0 Free-running mode E &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 0/1 0 CR0n0 used as compare register CR0n1 used as capture register F 3UHVFDOHU PRGH UHJLVWHU Q 350Q ESn11 PRM0n 0/1 ESn10 0/1 ESn01 1 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies both edges for pulse detection Setting invalid (Setting to 10 is prohibited.) 1RWH $OZD\V VHW 70 WR 70 WR 5HPDUNV :KHQ WKHVH ELWV DUH UHVHW WR RU VHW WR RWKHU IXQFWLRQV FDQ EH XVHG WRJHWKHU ZLWK WKH SXOVH ZLGWK PHDVXUHPHQW IXQFWLRQ )RU GHWDLOV UHIHU WR ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q DQG &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQILJXUDWLRQ IRU 3XOVH :LGWK 0HDVXUHPHQW ZLWK )UHH5XQQLQJ &RXQWHU Selector Count clockNote 16-bit timer counter 0n (TM0n) OVF0n TI0n0 16-bit timer capture/compare register 0n1 (CR0n1) INTTM0n1 Internal bus 1RWH 7KH FRXQW FORFN LV VHW ZLWK WKH 350Q UHJLVWHU 5HPDUN Q WR )LJXUH 7LPLQJ RI 3XOVH :LGWK 0HDVXUHPHQW ZLWK )UHH5XQQLQJ &RXQWHU DQG 2QH &DSWXUH 5HJLVWHU ZLWK %RWK (GJHV 6SHFLILHG t Count clock TM0n count value TI0n0 pin input D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 Value loaded to CR0n1 INTTM0n1 OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t 5HPDUN Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 0HDVXUHPHQW RI WZR SXOVH ZLGWKV ZLWK IUHHUXQQLQJ FRXQWHU 7KH SXOVH ZLGWKV RI WZR VLJQDOV UHVSHFWLYHO\ LQSXW WR WKH 7,Q SLQ DQG WKH 7,Q SLQ FDQ EH VLPXOWDQHRXVO\ PHDVXUHG ZKHQ ELW WLPHU FRXQWHU Q 70Q LV XVHG DV D IUHHUXQQLQJ FRXQWHU UHIHU WR )LJXUH :KHQ WKH HGJH VSHFLILHG E\ ELWV DQG (6Q (6Q RI SUHVFDOHU PRGH UHJLVWHU Q 350Q LV LQSXW WR WKH 7,Q SLQ WKH YDOXH RI WKH 70Q UHJLVWHU LV ORDGHG WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q DQG DQ H[WHUQDO LQWHUUXSW UHTXHVW VLJQDO ,1770Q LV VHW :KHQ WKH HGJH VSHFLILHG E\ ELWV DQG (6Q DQG (6Q RI WKH 350Q UHJLVWHU LV LQSXW WR WKH 7,Q SLQ WKH YDOXH RI WKH 70Q UHJLVWHU LV ORDGHG WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q DQG DQ H[WHUQDO LQWHUUXSW UHTXHVW VLJQDO ,1770Q LV VHW 7KH HGJHV RI WKH 7,Q DQG 7,Q SLQV DUH VSHFLILHG E\ ELWV DQG (6Q DQG (6Q DQG ELWV DQG (6Q (6Q RI WKH 350Q UHJLVWHU UHVSHFWLYHO\ 6SHFLI\ ERWK ULVLQJ DQG IDOOLQJ HGJHV 7KH YDOLG HGJH RI WKH 7,Q SLQ LV GHWHFWHG WKURXJK VDPSOLQJ DW WKH FRXQW FORFN F\FOH VHOHFWHG ZLWK WKH 350Q UHJLVWHU DQG WKH FDSWXUH RSHUDWLRQ LV QRW SHUIRUPHG XQWLO WKH YDOLG OHYHO LV GHWHFWHG WZLFH $V D UHVXOW QRLVH ZLWK D VKRUW SXOVH ZLGWK FDQ EH HOLPLQDWHG 5HPDUN Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQWURO 5HJLVWHU 6HWWLQJV IRU 0HDVXUHPHQW RI 7ZR 3XOVH :LGWKV ZLWK )UHH5XQQLQJ &RXQWHU D ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1 Note OVF0n 0 Free-running mode E &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 0 1 CR0n0 used as capture register Captures to CR0n0 at valid edge of TI0n1 pin CR0n1 used as capture register F 3UHVFDOHU PRGH UHJLVWHU Q 350Q ESn11 PRM0n 1 ESn10 1 ESn01 1 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies both edges for pulse detection. Specifies both edges for pulse detection. 1RWH $OZD\V VHW 70 WR 70 WR 5HPDUNV :KHQ WKHVH ELWV DUH UHVHW WR RU VHW WR RWKHU IXQFWLRQV FDQ EH XVHG WRJHWKHU ZLWK WKH SXOVH ZLGWK PHDVXUHPHQW IXQFWLRQ )RU GHWDLOV UHIHU WR ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 * &DSWXUH RSHUDWLRQ IUHHUXQQLQJ PRGH 7KH IROORZLQJ ILJXUH LOOXVWUDWHV WKH RSHUDWLRQ RI WKH FDSWXUH UHJLVWHU ZKHQ WKH FDSWXUH WULJJHU LV LQSXW )LJXUH 7LPLQJ RI 3XOVH :LGWK 0HDVXUHPHQW ZLWK )UHH5XQQLQJ &RXQWHU ZLWK %RWK (GJHV 6SHFLILHG t Count clock TM0n count value TI0n0 pin input Value loaded to CR0n1 INTTM0n1 TI0n1 pin input Value loaded to CR0n0 INTTM0n0 OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (10000H - D1 + (D2 + 1)) x t (D3 - D2) x t D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 5HPDUN Q WR 3XOVH ZLGWK PHDVXUHPHQW ZLWK IUHHUXQQLQJ FRXQWHU DQG WZR FDSWXUH UHJLVWHUV :KHQ ELW WLPHU FRXQWHU Q 70Q LV XVHG DV D IUHHUXQQLQJ FRXQWHU UHIHU WR )LJXUH WKH SXOVH ZLGWK RI WKH VLJQDO LQSXW WR WKH 7,Q SLQ FDQ EH PHDVXUHG :KHQ WKH HGJH VSHFLILHG E\ ELWV DQG (6Q DQG (6Q RI SUHVFDOHU PRGH UHJLVWHU Q 350Q LV LQSXW WR WKH 7,Q SLQ WKH YDOXH RI WKH 70Q UHJLVWHU LV ORDGHG WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q DQG DQ H[WHUQDO LQWHUUXSW UHTXHVW VLJQDO ,1770Q LV VHW 7KH YDOXH RI WKH 70Q UHJLVWHU LV DOVR ORDGHG WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q ZKHQ DQ HGJH LQYHUVH WR WKH RQH WKDW WULJJHUV FDSWXULQJ WR WKH &5Q UHJLVWHU LV LQSXW 7KH YDOLG HGJH RI WKH 7,Q SLQ LV GHWHFWHG WKURXJK VDPSOLQJ DW D FRXQW FORFN F\FOH VHOHFWHG ZLWK WKH 350Q UHJLVWHU DQG WKH FDSWXUH RSHUDWLRQ LV QRW SHUIRUPHG XQWLO WKH YDOLG HGJH LV GHWHFWHG WZLFH $V D UHVXOW QRLVH ZLWK D VKRUW SXOVH ZLGWK FDQ EH HOLPLQDWHG 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQWURO 5HJLVWHU 6HWWLQJV IRU 3XOVH :LGWK 0HDVXUHPHQW ZLWK )UHH5XQQLQJ &RXQWHU DQG 7ZR &DSWXUH 5HJLVWHUV ZLWK 5LVLQJ (GJH 6SHFLILHG D ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1 Note OVF0n 0 Free-running mode E &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 1 1 CR0n0 used as capture register Captures to CR0n0 at edge inverse to valid edge of TI0n0 pin CR0n1 used as capture register F 3UHVFDOHU PRGH UHJLVWHU Q 350Q ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies rising edge of pulse width detection Setting invalid (Setting to 10 is prohibited.) 1RWH $OZD\V VHW 70 WR 70 WR 5HPDUNV :KHQ WKHVH ELWV DUH UHVHW WR RU VHW WR RWKHU IXQFWLRQV FDQ EH XVHG WRJHWKHU ZLWK WKH SXOVH ZLGWK PHDVXUHPHQW IXQFWLRQ )RU GHWDLOV UHIHU WR ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q Q WR 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH 7LPLQJ RI 3XOVH :LGWK 0HDVXUHPHQW ZLWK )UHH5XQQLQJ &RXQWHU DQG 7ZR &DSWXUH 5HJLVWHUV ZLWK 5LVLQJ (GJH 6SHFLILHG t Count clock TM0n count value TI0n0 pin input Value loaded to CR0n1 Value loaded to CR0n0 INTTM0n1 OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 5HPDUN Q WR 3XOVH ZLGWK PHDVXUHPHQW E\ UHVWDUWLQJ :KHQ WKH YDOLG HGJH RI WKH 7,Q SLQ LV GHWHFWHG WKH SXOVH ZLGWK RI WKH VLJQDO LQSXW WR WKH 7,Q SLQ FDQ EH PHDVXUHG E\ FOHDULQJ WKH 70Q UHJLVWHU DQG WKHQ UHVXPLQJ FRXQWLQJ DIWHU ORDGLQJ WKH FRXQW YDOXH RI ELW WLPHU FRXQWHU Q 70Q WR ELW WLPHU FDSWXUHFRPSDUH UHJLVWHU Q &5Q UHIHU WR )LJXUH 7KH HGJH LV VSHFLILHG E\ ELWV DQG (6Q DQG (6Q RI SUHVFDOHU PRGH UHJLVWHU Q 350Q 7KH ULVLQJ RU IDOOLQJ HGJH FDQ EH VSHFLILHG 7KH YDOLG HGJH LV GHWHFWHG WKURXJK VDPSOLQJ DW D FRXQW FORFN F\FOH VHOHFWHG ZLWK WKH 350Q UHJLVWHU DQG WKH FDSWXUH RSHUDWLRQ LV QRW SHUIRUPHG XQWLO WKH YDOLG OHYHO LV GHWHFWHG WZLFH $V D UHVXOW QRLVH ZLWK D VKRUW SXOVH FDQ EH HOLPLQDWHG 8VHU(c)V 0DQXDO 8(-98' &+$37(5 %,7 7,0(5(9(17 &2817(56 72 )LJXUH &RQWURO 5HJLVWHU 6HWWLQJV IRU 3XOVH :LGWK 0HDVXUHPHQW E\ 5HVWDUWLQJ D ELW WLPHU PRGH FRQWURO UHJLVWHU Q 70&Q TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 0 0/1 Note OVF0n 0 Clears and starts at valid edge of TI0n0 pin E &DSWXUHFRPSDUH FRQWURO UHJLVWHU Q &5&Q CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 1 1 CR0n0 used as capture register Captures to CR0n0 at edge inverse to valid edge of TI0n0 pin CR0n1 used as capture register F 3UHVFDOHU PRGH UHJLVWHU Q 350Q ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) 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Yes No Write transmit data to TXBn register Wait for interrupt End of transmission processing 8VHU(c)V 0DQXDO 8(-98' &+$37(5 $6<1&+521286 6(5,$/ ,17(5)$&( 8$57 6WDUWLQJ SURFHGXUH 7KH SURFHGXUH WR VWDUW FRQWLQXRXV WUDQVPLVVLRQ LV VKRZQ EHORZ )LJXUH &RQWLQXRXV 7UDQVPLVVLRQ 6WDUWLQJ 3URFHGXUH TXDn (output) <1> INTSTn (output) Start bit <2> Data (1) Stop bit <3> Start bit <4> Data (2) Stop bit <5> TXBn register FFH Data (1) Data (2) Data (3) TXSn register ASIFn register (TXBFn, TXSFn bits) FFH 10 11Note Data (1) Data (2) Data (3) 00 01 11 01 11 01 11 1RWH 5HIHU WR &DXWLRQV 7UDQVPLVVLRQ 6WDUWLQJ 3URFHGXUH ,QWHUQDO 2SHUDWLRQ $6,)Q 5HJLVWHU 7;%)Q 7;6)Q Note * 6HW WUDQVPLVVLRQ PRGH * :ULWH GDWD ! 6WDUW WUDQVPLVVLRQ XQLW ! *HQHUDWH VWDUW ELW 6WDUW GDWD WUDQVPLVVLRQ * 5HDG $6,)Q UHJLVWHU FRQILUP WKDW 7;%)Q ELW * :ULWH GDWD 7UDQVPLVVLRQ LQ SURJUHVV!! ! ,1767Q LQWHUUXSW RFFXUV * 5HDG $6,)Q UHJLVWHU FRQILUP WKDW 7;%)Q ELW * :ULWH GDWD ! *HQHUDWH VWDUW ELW 6WDUW GDWD WUDQVPLVVLRQ 7UDQVPLVVLRQ LQ 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SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E 6,5%Q/ UHJLVWHU After reset: 00H 7 SIRBnL SIRBn7 R 6 SIRBn6 Address: FFFFFD02H, FFFFFD12H, FFFFFD22H 5 SIRBn5 4 SIRBn4 3 SIRBn3 2 SIRBn2 1 SIRBn1 0 SIRBn0 5HPDUN Q 9(6.) 9(6.* Q WR 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( &6, &ORFNHG VHULDO LQWHUIDFH UHDGRQO\ UHFHLYH EXIIHU UHJLVWHUV Q Q/ 6,5%(Q 6,5%(Q/ 7KH 6,5%(Q UHJLVWHU LV D ELW EXIIHU UHJLVWHU WKDW VWRUHV UHFHLYH GDWD 7KLV UHJLVWHU LV UHDGRQO\ LQ ELW XQLWV +RZHYHU ZKHQ WKH ORZHU ELWV DUH XVHG DV WKH 6,5%(Q/ UHJLVWHU WKH UHJLVWHU LV UHDGRQO\ LQ ELW XQLWV ,Q DGGLWLRQ WR UHVHW LQSXW WKLV UHJLVWHU FDQ DOVR EH LQLWLDOL]HG E\ FOHDULQJ WKH &6,(Q ELW RI WKH &6,0Q UHJLVWHU 7KH 6,5%(Q UHJLVWHU LV WKH VDPH DV WKH 6,5%Q UHJLVWHU (YHQ LI WKH 6,5%Q UHJLVWHU LV UHDG WKH QH[W RSHUDWLRQ ZLOO QRW VWDUW 7KH 6,5%(Q UHJLVWHU LV XVHG WR UHDG WKH FRQWHQWV RI WKH 6,5%Q UHJLVWHU &DXWLRQV 7KH UHFHLYH RSHUDWLRQ LV QRW VWDUWHG HYHQ LI GDWD LV UHDG IURP WKH 6,5%(Q UHJLVWHU 7KH 6,5%(Q UHJLVWHU FDQ EH UHDG RQO\ LI D ELW GDWD OHQJWK LV VHW &&/Q ELW RI &6,0Q UHJLVWHU 7KH 6,5%(Q/ UHJLVWHU FDQ EH UHDG RQO\ LI DQ ELW GDWD OHQJWK KDV EHHQ VHW &&/Q ELW RI &6,0Q UHJLVWHU D 6,5%(Q UHJLVWHU After reset: 0000H 15 14 R 13 Address: FFFFFD06H, FFFFFD16H, FFFFFD26H 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 % 6,5%(Q/ UHJLVWHU After reset: 00H 7 R 6 Address: FFFFFD06H, FFFFFD16H, FFFFFD26H 5 4 3 2 1 0 SIRBEnL SIRBEn7 SIRBEn6 SIRBEn5 SIRBEn4 SIRBEn3 SIRBEn2 SIRBEn1 SIRBEn0 5HPDUN Q 9(6.) 9(6.* Q WR 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( &6, &ORFNHG VHULDO LQWHUIDFH WUDQVPLW EXIIHU UHJLVWHUV Q Q/ 627%Q 627%Q/ 7KH 627%Q UHJLVWHU LV D ELW EXIIHU UHJLVWHU WKDW VWRUHV WUDQVPLW GDWD :KHQ WKH WUDQVPLVVLRQUHFHSWLRQ PRGH LV VHW 750'Q ELW RI &6,0Q UHJLVWHU LV VWDUWHG E\ ZULWLQJ GDWD WR WKH 627%Q UHJLVWHU 7KLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV +RZHYHU ZKHQ WKH ORZHU ELWV DUH XVHG DV WKH 627%Q/ UHJLVWHU WKH UHJLVWHU LV UHDGRQO\ LQ ELW XQLWV &DXWLRQV $FFHVV WKH 627%Q UHJLVWHU RQO\ ZKHQ D ELW GDWD OHQJWK LV VHW &&/Q ELW RI &6,0Q UHJLVWHU SHUIRUP ,I WKH 627%Q UHJLVWHU LV $FFHVV WKH 627%Q/ UHJLVWHU RQO\ ZKHQ DQ ELW GDWD OHQJWK KDV EHHQ VHW &&/Q ELW RI &6,0Q UHJLVWHU :KHQ WKH VLQJOH WUDQVIHU PRGH LV VHW $872Q ELW RI &6,0Q UHJLVWHU DFFHVV RQO\ LQ WKH LGOH VWDWH &627Q ELW RI &6,0Q UHJLVWHU DFFHVVHG GXULQJ GDWD WUDQVIHU WKH GDWD FDQQRW EH JXDUDQWHHG WKH WUDQVPLVVLRQ RSHUDWLRQ D 627%Q/ UHJLVWHU After reset: 0000H 15 14 R/W 13 12 Address: FFFFFD04H, FFFFFD14H, FFFFFD24H 11 10 9 8 7 6 5 4 3 2 1 0 SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E 627%Q/ UHJLVWHU After reset: 00H 7 SOTBnL R/W 6 Address: FFFFFD04H, FFFFFD14H, FFFFFD24H 5 4 3 2 1 0 SOTBn7 SOTBn6 SOTBn5 SOTBn4 SOTBn3 SOTBn2 SOTBn1 SOTBn0 5HPDUN Q 9(6.) 9(6.* Q WR 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( &6, &ORFNHG VHULDO LQWHUIDFH LQLWLDO WUDQVPLW EXIIHU UHJLVWHUV Q Q/ 627%)Q 627%)Q/ 7KH 627%)Q UHJLVWHU LV D ELW EXIIHU UHJLVWHU WKDW VWRUHV LQLWLDO WUDQVPLVVLRQ GDWD LQ WKH FRQWLQXRXV WUDQVIHU PRGH 7KH WUDQVPLVVLRQ RSHUDWLRQ LV QRW VWDUWHG HYHQ LI GDWD LV ZULWWHQ WR WKH 627%)Q UHJLVWHU 7KLV UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV +RZHYHU ZKHQ WKH ORZHU ELWV DUH XVHG DV WKH 627%)Q/ UHJLVWHU WKH UHJLVWHU FDQ EH UHDGZULWWHQ LQ ELW XQLWV &DXWLRQ $FFHVV WKH 627%)Q UHJLVWHU DQG 627%)Q/ UHJLVWHU RQO\ ZKHQ D ELW GDWD OHQJWK KDV EHHQ VHW &&/Q ELW RI &6,0Q UHJLVWHU &&/Q ELW RI &6,0Q UHJLVWHU &6,0Q UHJLVWHU FDQQRW EH JXDUDQWHHG DQG RQO\ ZKHQ DQ ELW GDWD OHQJWK KDV EHHQ VHW UHVSHFWLYHO\ DQG RQO\ LQ WKH LGOH VWDWH &627Q ELW RI ,I WKH 627%)Q UHJLVWHU LV DFFHVVHG GXULQJ GDWD WUDQVIHU WKH GDWD D 627%)Q UHJLVWHU After reset: 0000H 15 14 R/W 13 12 Address: FFFFFD08H, FFFFFD18H, FFFFFD28H 11 10 9 8 7 6 5 4 3 2 1 0 SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E 627%)Q/ UHJLVWHU After reset: 00H 7 R/W 6 Address: FFFFFD08H, FFFFFD18H, FFFFFD28H 5 4 3 2 1 0 SOTBFnL SOTBFn7 SOTBFn6 SOTBFn5 SOTBFn4 SOTBFn3 SOTBFn2 SOTBFn1 SOTBFn0 5HPDUN Q 9(6.) 9(6.* Q WR 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( &6, 6HULDO ,2 VKLIW UHJLVWHUV Q Q/ 6,2Q 6,2Q/ 7KH 6,2Q UHJLVWHU LV D ELW VKLIW UHJLVWHU WKDW FRQYHUWV SDUDOOHO GDWD LQWR VHULDO GDWD 7KH WUDQVIHU RSHUDWLRQ LV QRW VWDUWHG HYHQ LI WKH 6,2Q UHJLVWHU LV UHDG 7KLV UHJLVWHU LV UHDGRQO\ LQ ELW XQLWV +RZHYHU ZKHQ WKH ORZHU ELWV DUH XVHG DV WKH 6,2Q/ UHJLVWHU WKH UHJLVWHU LV UHDGRQO\ LQ ELW XQLWV ,Q DGGLWLRQ WR UHVHW LQSXW WKLV UHJLVWHU FDQ DOVR EH LQLWLDOL]HG E\ FOHDULQJ WKH &6,(Q ELW RI WKH &6,0Q UHJLVWHU &DXWLRQ $FFHVV WKH 6,2Q UHJLVWHU DQG 6,2Q/ UHJLVWHU RQO\ ZKHQ D ELW GDWD OHQJWK KDV EHHQ VHW &&/Q ELW RI &6,0Q UHJLVWHU &&/Q ELW RI &6,0Q UHJLVWHU &6,0Q UHJLVWHU FDQQRW EH JXDUDQWHHG DQG RQO\ ZKHQ DQ ELW GDWD OHQJWK KDV EHHQ VHW UHVSHFWLYHO\ DQG RQO\ LQ WKH LGOH VWDWH &627Q ELW RI ,I WKH 6,2Q UHJLVWHU LV DFFHVVHG GXULQJ GDWD WUDQVIHU WKH GDWD D 6,2Q UHJLVWHU After reset: 0000H 15 14 13 R 12 Address: FFFFFD0AH, FFFFFD1AH, FFFFFD2AH 11 10 9 8 7 6 5 4 3 2 1 0 SIO0n SIOn15 SIOn14 SIOn13 SIOn12 SIOn11 SIOn10 SIOn9 SIOn8 SIOn7 SIOn6 SIOn5 SIOn4 SIOn3 SIOn2 SIOn1 SIOn0 E 6,2Q/ UHJLVWHU After reset: 00H 7 SIO0nL SIOn7 R 6 SIOn6 Address: FFFFFD0AH, FFFFFD1AH, FFFFFD2AH 5 SIOn5 4 SIOn4 3 SIOn3 2 SIOn2 1 SIOn1 0 SIOn0 5HPDUN Q 9(6.) 9(6.* Q WR 9(6.- 8VHU(c)V 0DQXDO 8(-98' Table 16-1. Use of Each Buffer Register Single Transfer Transmission/Reception Mode Storing received data Note 2 Register Name Receive-Only Mode * Reading starts reception * Storing received data Storing up to the (N - 1)th received data (other than the last)Note 2 When reception is complete, read the received data from this register. Repeat this operation until the (N - 1)th data has been received. * First, read dummy data and start transfer. * To perform reception of the next data after reception is complete, read the received data from this register. Transmission/Reception Mode Receive-Only Mode R/W Continuous Transfer Note 1 SIRBn (SirBnL) When transmission and reception are complete, read the received data from this register. Read Function * Reading starts reception * Storing up to the (N - 2)th data (other than the last two) When reception is complete, read the received data from this register. Repeat this operation until the (N - 2)th data has been received. (Supplement) Do not read the (N - 1)th data from this register. If read, a reception operation starts and continuous transfer cannot be completed. Storing the (N - 1)th received data Note 2 Use method SIRBEn (SIRBEnL) Not used. Not used If reception of the next data will not be performed after reception is complete, read the received data from this register. - Not used. Not used - Read Function - - Storing the data received lastNote 2 Use method Read the (N - 1)th received data from this register when the (N - 1)th or Nth (last) data has been received. Note 2 SIO0n (SIO0nL) Read Function Storing the Nth (last) received data Storing the Nth (last) received data When the Nth (last) data has been received, read the Nth (last) data. - Note 2 Use method When the Nth (last) transmission/reception is complete, read the Nth (last) data. - * Starting transmission/reception when written * Storing the data to be transmitted second and subsequently When transmission/reception is complete, write the data to be transmitted next to this register to start the next transmission/reception. - Storing the data to be transmitted firstNote 2 &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( &6, 8VHU(c)V 0DQXDO 8(-98' * Starting transmission/reception when written * Storing the data to be transmitted * First, write a dummy data (FFH) to start transmission/reception. * When transmission/reception is complete, write the data to be transmitted next. Not used - Not used Not used SOTBn (SOTBnL) Write Function Use method Not used SOTBFn (SOTBFnL) Write Function - Before starting transmission/reception (writing to SOTBn), write the data to be transmitted first. Not used Use method Notes 1. It is assumed that the number of data to be transmitted is N. 2. Neither reading nor writing will start communication. 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Block Diagram of CSIAn Buffer RAM Automatic data transfer address point specification register n (ADTPn) Automatic data transfer address count register n (ADTCn) Internal bus DIRn ATMn Serial I/O shift register An (SIOAn) Divisor selection register n (BRGCAn) Serial trigger register n (CSITn) SIAn RXEn ATSTPn ATSTAn SOAn TXEn 2 2 Serial clock counter Serial transfer controller Interrupt generator INTCSIAn Serial status register n (CSISn) CKSAn1 CKSAn0 TSFn &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( $ &6,$ :,7+ $8720$7,& 75$160,75(&(,9( )81&7,21 8VHU(c)V 0DQXDO 8(-98' SCKAn Selector fXX/6 to fXX/256 Selector fXX Automatic data transfer interval specification register n (ADTIn) 6-bit counter MASTERn &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( $ &6,$ :,7+ $8720$7,& 75$160,75(&(,9( )81&7,21 6HULDO ,2 VKLIW UHJLVWHU $Q 6,2$Q 7KLV LV DQ ELW UHJLVWHU XVHG WR VWRUH WUDQVPLWUHFHLYH GDWD LQ E\WH WUDQVIHU PRGH $7(Q ELW RI VHULDO RSHUDWLRQ PRGH VSHFLILFDWLRQ UHJLVWHU Q &6,0$Q UHJLVWHU Q &6,6Q :ULWLQJ WUDQVPLW GDWD WR 6,2$Q VWDUWV WKH WUDQVIHU ,Q DGGLWLRQ DIWHU D WUDQVIHU FRPSOHWLRQ LQWHUUXSW UHTXHVW VLJQDO ,17&6,$Q LV RXWSXW 76)Q ELW RI VHULDO VWDWXV GDWD FDQ EH UHFHLYHG E\ UHDGLQJ GDWD IURP 6,2$Q 7KLV UHJLVWHU FDQ EH ZULWWHQ RU UHDG E\ DQ ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ +RZHYHU ZULWLQJ WR WKH 6,2$Q UHJLVWHU LV SURKLELWHG ZKHQ 76)Q ELW RI VHULDO VWDWXV UHJLVWHU Q &6,6Q $IWHU UHVHW WKLV UHJLVWHU LV FOHDUHG WR + &DXWLRQV $ WUDQVIHU RSHUDWLRQ LV VWDUWHG E\ ZULWLQJ WR 6,2$Q UHJLVWHU WUDQVPLVVLRQ LV GLVDEOHG 7;(Q ELW RI &6,0$Q UHJLVWHU &RQVHTXHQWO\ ZKHQ ZULWH GXPP\ GDWD WR WKH 6,2$Q UHJLVWHU WR VWDUW WKH WUDQVIHU RSHUDWLRQ DQG WKHQ SHUIRUP D UHFHLYH RSHUDWLRQ 'R QRW ZULWH GDWD WR 6,2$Q ZKLOH WKH DXWRPDWLF WUDQVPLWUHFHLYH IXQFWLRQ LV RSHUDWLQJ 5HPDUN Q Q 9(6.) 9(6.* 9(6.- $XWRPDWLF GDWD WUDQVIHU DGGUHVV FRXQW UHJLVWHU Q $'7&Q 7KLV LV D UHJLVWHU XVHG WR LQGLFDWH EXIIHU 5$0 DGGUHVVHV GXULQJ DXWRPDWLF WUDQVIHU :KHQ DXWRPDWLF WUDQVIHU LV VWRSSHG WKH GDWD SRVLWLRQ ZKHQ WUDQVIHU VWRSSHG FDQ EH DVFHUWDLQHG E\ UHDGLQJ $'7&Q UHJLVWHU YDOXH 7KLV UHJLVWHU FDQ EH VHW E\ DQ ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ $IWHU UHVHW WKLV UHJLVWHU LV FOHDUHG WR + +RZHYHU UHDGLQJ IURP $'7&Q UHJLVWHU LV SURKLELWHG ZKHQ 76)Q ELW RI VHULDO VWDWXV UHJLVWHU Q &6,6Q After reset: 00H 7 ADTCn R 6 Address: FFFFFD47H, FFFFD57H 5 4 3 2 1 0 ADTCn0 ADTCn7 ADTCn6 ADTCn5 ADTCn4 ADTCn3 ADTCn2 ADTCn1 5HPDUN Q Q 9(6.) 9(6.* 9(6.- 5HJLVWHUV 6HULDO LQWHUIDFH &6,$Q LV FRQWUROOHG E\ WKH IROORZLQJ VL[ UHJLVWHUV * 6HULDO RSHUDWLRQ PRGH VSHFLILFDWLRQ UHJLVWHU Q &6,0$Q * 6HULDO VWDWXV UHJLVWHU Q &6,6Q * 6HULDO WULJJHU UHJLVWHU Q &6,7Q * 'LYLVRU VHOHFWLRQ UHJLVWHU Q %5*&$Q * $XWRPDWLF GDWD WUDQVIHU DGGUHVV SRLQW VSHFLILFDWLRQ UHJLVWHU Q $'73Q * $XWRPDWLF GDWD WUDQVIHU LQWHUYDO VSHFLILFDWLRQ UHJLVWHU Q $'7,Q 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( $ &6,$ :,7+ $8720$7,& 75$160,75(&(,9( )81&7,21 6HULDO RSHUDWLRQ PRGH VSHFLILFDWLRQ UHJLVWHU Q &6,0$Q 7KLV LV DQ ELW UHJLVWHU XVHG WR FRQWURO WKH VHULDO WUDQVIHU RSHUDWLRQ 7KLV UHJLVWHU FDQ EH VHW E\ D ELW RU ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ $IWHU UHVHW VHWV WKLV UHJLVWHU LV FOHDUHG WR + After reset: 00H <7> CSIMAn CSIAEn R/W 6 ATEn Address: FFFFFD40H, FFFFD50H 5 ATMn 4 MASTERn 3 TXEn 2 RXEn 1 DIRn 0 0 CSIAEn 0 1 CSIAn operation enable/disable control Disable CSIAn operation (SOAn: Low level, SCKAn: High level) Enable CSIAn operation * When CSIAEn = 0, the CSIAn unit is resetNote asynchronously. * When CSIAEn = 0, the CSIAn unit is reset, so to operate CSIAn, first set CSIAEn = 1. * If the CSIAEn bit is changed from 1 to 0, all the registers and bits shown in Note below are initialized. To set CSIAEn to 1 again, first re-set the registers of the CSIAn unit. * If the CSIAEn bit is changed from 1 to 0, the buffer RAM value is not held. Also, when the CSIAEn bit is 0, the buffer RAM cannot be accessed. ATEn 0 1 ATMn 0 1 Automatic transfer operation enable/disable control 1-byte transfer mode Automatic transfer mode Specification of automatic transfer mode Single transfer mode (stops at address specified with ADTPn register) Repeat transfer mode (Following transfer completion, the ADTCn register is cleared to 00H and transmission starts again.) Specification of CSIAn master/slave mode Slave mode (synchronized with SCKAn input clock) Master mode (synchronized with internal clock) Transmission enable/disable control Disable transmission (SOAn: Low level) Enable transmission Reception enable/disable control Disable reception Enable reception Specification of transfer data direction MSB first LSB first MASTERn 0 1 TXEn 0 1 RXEn 0 1 DIRn 0 1 1RWH 7KH $'7&Q &6,7Q DQG 6,2$Q UHJLVWHUV DQG WKH 76)Q ELW RI WKH &6,6 UHJLVWHU DUH UHVHW 5HPDUN Q Q 9(6.) 9(6.* 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( $ &6,$ :,7+ $8720$7,& 75$160,75(&(,9( )81&7,21 6HULDO VWDWXV UHJLVWHU Q &6,6Q 7KLV LV DQ ELW UHJLVWHU XVHG WR VHOHFW WKH VHULDO FORFN DQG WR LQGLFDWH WKH WUDQVIHU RSHUDWLRQ RI &6,$Q 7KLV UHJLVWHU FDQ EH VHW E\ D ELW RU ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ $IWHU UHVHW WKLV UHJLVWHU LV FOHDUHG WR + +RZHYHU UHZULWLQJ WKH &6,6Q UHJLVWHU LV SURKLELWHG ZKHQ WKH 76)Q ELW LV After reset: 00H 7 CSISn R/W 6 Address: FFFFFD41H, FFFFD51H 5 0 4 0 3 0 2 0 1 0 0 TSFn CKSAn1 CKSAn0 CKSAn1 CKSAn0 Serial clock (fSCKA) selectionNote 20 MHz 16 MHz 10 MHz 100 ns 200 ns 400 ns 800 ns 0 0 1 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 Setting prohibited Setting prohibited 100 ns 200 ns 400 ns 125 ns 250 ns 500 ns Rewriting CSISn is prohibited when the CSIAEn bit of the CSIMAn register is 1. TSFn 0 Transfer status CSIAEn bit of CSIMAn register = 0 At reset input At completion of specified transfer When transfer has been suspended by setting ATSTPn bit of CSITn register to 1 1 From transfer start to completion of specified transfer 1RWH 6HW I6&.$ VR DV WR VDWLVI\ WKH IROORZLQJ FRQGLWLRQV 9'' 9'' WR 9 I6&.$ 0+] WR I6&.$ 0+] &DXWLRQV 7KH 76)Q ELW LV UHDGRQO\ :KHQ WKH 76)Q ELW UHZULWLQJ WKH &6,0$Q &6,6Q %5*&$Q $'73Q $'7,Q 6,2$Q UHJLVWHUV LV SURKLELWHG +RZHYHU WKH WUDQVIHU EXIIHU 5$0 FDQ EH UHZULWWHQ :KHQ ZULWLQJ WR ELWV WR DOZD\V ZULWH 5HPDUN Q Q 9(6.) 9(6.* 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( $ &6,$ :,7+ $8720$7,& 75$160,75(&(,9( )81&7,21 6HULDO WULJJHU UHJLVWHU Q &6,7Q 7KLV LV DQ ELW UHJLVWHU XVHG WR FRQWURO H[HFXWLRQVWRS RI DXWRPDWLF GDWD WUDQVIHU 7KH &6,7Q UHJLVWHU EHWZHHQ WKH EXIIHU 5$0 DQG VKLIW UHJLVWHU FDQ EH VHW E\ DQ ELW RU ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ $IWHU UHVHW WKLV UHJLVWHU LV FOHDUHG WR + +RZHYHU PDQLSXODWH RQO\ ZKHQ WKH $7(Q ELW RI VHULDO RSHUDWLRQ PRGH VSHFLILFDWLRQ UHJLVWHU Q &6,0$Q LV PDQLSXODWLRQ SURKLELWHG ZKHQ $7(Q ELW After reset: 00H 7 CSITn 0 R/W 6 0 Address: FFFFFD42H, FFFFD52H 5 0 4 0 3 0 2 0 <1> ATSTPn <0> ATSTAn ATSTPn 0 1 Automatic data transfer suspension - Stop automatic data transfer Even when ATSTPn = 1 is set, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated, and ATSTPn is automatically cleared to 0 after that. After automatic transfer has been suspended, the data address at the point of suspension is stored in automatic data transfer address count register n (ADTCn). A function to resume automatic data transfer is not provided, so if transfer has been interrupted by setting the ATSTPn bit to 1, set each register again, and set the ATSTAn bit to start automatic data transfer. ATSTAn 0 1 Automatic data transfer start - Start automatic data transfer Even when ATSTAn = 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated, and ATSTAn is automatically cleared to 0 after that. 5HPDUN Q Q 9(6.) 9(6.* 9(6.- 8VHU(c)V 0DQXDO 8(-98' &+$37(5 &/2&.(' 6(5,$/ ,17(5)$&( $ &6,$ :,7+ $8720$7,& 75$160,75(&(,9( )81&7,21 'LYLVRU VHOHFWLRQ UHJLVWHU Q %5*&$Q 7KLV LV DQ ELW UHJLVWHU XVHG WR FRQWURO WKH VHULDO WUDQVIHU VSHHG GLYLVRU RI &6,$ FORFN 7KLV UHJLVWHU FDQ EH VHW E\ DQ ELW PHPRU\ PDQLSXODWLRQ LQVWUXFWLRQ +RZHYHU ZKHQ WKH 76)Q ELW RI VHULDO VWDWXV UHJLVWHU Q &6,6Q LV UHZULWLQJ WKH %5*&$Q UHJLVWHU LV SURKLELWHG $IWHU UHVHW WKLV UHJLVWHU LV VHW WR + After reset: 03H 7 BRGCAn 0 R/W 6 0 Address: FFFFFD43H, FFFFD53H 5 0 4 0 3 0 2 0 1 0 BRGCn1 BRGCn0 BRGCn1 BRGCn0 0 0 1 1 0 1 0 1 Selection of CSIAn serial clock (fSCKA division ratio) 6 (fSCKA/6) 8 (fSCKA/8) 16 (fSCKA/16) 32 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