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| LH79520 Preliminary Data Sheet FEATURES * Highly Integrated System-on-Chip * High Performance (77.4144 MHz CPU Speed) * ARM720TTM RISC Core - 32-bit ARM7TDMITM RISC Core - 8KB Cache - MMU (Windows CETM Enabled) - Write Buffer * 32KB On-Chip SRAM * Flexible, Programmable Memory Interface - SDRAM Interface - 15-bit External Address Bus - 32-bit External Data Bus - Two Segments (128MB each) - SRAM/Flash/ROM Interface - 26-bit External Address Bus - 32-bit External Data Bus - Seven Segments (64MB Each) * Multi-stream DMA Controller - Four 32-bit Burst-based Data Streams * Clock and Power Management - 32.768 kHz Oscillator for Real Time Clock - 14.7456 MHz Oscillator and On-chip PLL for CPU and Bus Clocks - Active, Standby, Sleep and Stop Power Modes - Externally-supplied Clock Options * Low Power Modes - Active Mode: 55 mA (MAX.) - Standby Mode: 35 mA (MAX.) - Sleep Mode: 5.5 mA (MAX.) - Stop Mode 2: 18 A * Watchdog Timer * Vectored Interrupt Controller - 16 Standard and 16 Vectored IRQ Interrupts - Hardware Interrupt Priority - Software Interrupts - FIQ Fast Interrupts * Three UARTs - 16-byte FIFOs for Rx and Tx - IrDA SIR Support - Supports Data Rates Up to 460.8 kb/s * Two 16-bit Pulse Width Modulators * Two Dual Channel Timer Modules * Real Time Clock - 32-bit Up-counter with Programmable Load - Programmable 32-bit Match Compare Register System-on-Chip * 64 Programmable General Purpose I/O Signals - Multiplexed with Peripheral I/O Signals * Programmable Color LCD Controller - Up to 800 x 600 Resolution - Supports STN, Color STN, HR-TFT, TFT - Supports 15 Shades of Gray - TFT: Supports 64 k Direct Colors or 256 Colors selected from a Palette of 64,000 Colors - Color STN: Supports 3,375 Direct Colors or 256 Colors Selected from a Palette of 3,375 Colors * Synchronous Serial Port - Supports Data Rates Up to 1.8452 Mb/s - Compatible with Common Interface Schemes - Motorola SPITM - National Semiconductor MICROWIRETM - Texas Instruments SSI * JTAG Debug Interface and Boundary Scan * 5 V Tolerant Inputs DESCRIPTION The LH79520, powered by an ARM720T, is a complete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. The LH79520 combines a 32-bit ARM720T RISC, Color LCD controller, Cache, Local SRAM, a number of essential peripherals such as Direct Memory Access, Serial and Parallel Interfaces, Infrared support, Timers, Real Time Clock, Watchdog Timer, Pulse Width Modulators, and an on-chip Phase Lock Loop. Debug is made simple by JTAG support. This high level of integration lowers overall system costs, reduces development cycle time and accelerates product introduction. The LH79520's fully static design, power management unit, low voltage operation (1.8 V Core, 3.3 V I/O, 1.8 V optional*), on-chip PLL, fast interrupt response time, on-chip cache and SRAM, powerful instruction set, and low power RISC core provide high performance. To build an advanced portable device, advanced processing capability is required. This capability must come with increased performance in the display system and peripherals, and yet demand less power from batteries. The LH79520 is an integrated solution to fit these needs. NOTE: *Under development. Results pending further characterization. ARM720T and ARM7TDMI are trademarks of Advanced RISC Machines, LTD. Motorola SPI is a trademark of Motorola, Inc. National Semiconductor MICROWIRE is a trademark of National Semiconductor Corporation. Windows CE is a trademark of Microsoft Corporation. Preliminary Data Sheet 8/21/02 1 LH79520 System-on-Chip PIN DIAGRAM 176-PIN LQFP PC4/LCDVD16 PC5/LCDLP PC6/LCDVD17 PC7/LCDFP/LCDSPS VSS LCDVD0 LCDVD1 VDD PD0/LCDVD2 PD1/LCDVD3 PD2/LCDVD4 PD3/LCDVD5 VSSC PD4/LCDVD6/LCDPS PD5/LCDVD7 PD6/LCDVD8 PD7/LCDVD9 INT6/LCDVD10 INT7/LCDVD11 VDDC PE0/DQM0 PE1/DQM1 PE2/DQM2 PE3/DQM3 nCAS nRAS PE4/nSDWE PE5/nDCS0 PE6/nDCS1 VSS PE7/SDCKE PF0/SDCLK VDD PF1/CLKEN CLKIN/UARTCLK nRESETOUT nRESETIN VDDC XTALOUT XTALIN VSSA VDDA XTAL32OUT XTAL32IN TOP VIEW PC3/LCDDCLK PC2/LCDDCLKIN PC1/LCDVDDEN/LCDCLS VDDC PC0/LCDENAB/LCDSPL VSSC PB7/LCDVD15/LCDDSPLEN PB6/LCDVD14 PB5/LCDVD13 PB4/LCDVD12/LCDREV VDD INT5/DREQ1/nWAIT CTOUT1B/DACK1 PB3/DREQ0 PB2/nDACK0 PB1/DEOT0 VSS INT4/PWM0 INT3/PWMSYNC0 PB0/INT2 PA7/INT1 VDDC PA6/INT0 PA5/CLKOUT PWM1/DEOT1 VSSC PA4/UARTTX1 PA3/UARTRX1 VDD UARTIRTX0/UARTTX0 UARTIRRX0/UARTRX0 PA2/SSPFRM PA1/SSPCLK PA0/SSPEN SSPTX/UARTTX2 VSS SSPRX/UARTRX2 TMS TDO TDI TCLK nTRST TEST1 TEST2 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 LH79520 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 CLKINSEL D0 D1 VDD D2 D3 D4 D5 VSS D6 D7 D8 D9 VDDC D10 D11 D12 D13 VSS D14 D15 PF2/D16 PF3/D17 PF4/D18 VDD PG5/D19 PF6/D20 PF7/D21 PG0/D22 PG1/D23 PG2/D24 PG3/D25 PG4/D26 VSS PG5/D27 PG6/D28 PG7/D29 PH0/D30 PH1/D31 VDD nCS0 nCS1 nCS2 VSSC nTSTA A25 A24 A23 A22 A21 A20 VDD A19 A18 A17 A16 VSS A15 A14 A13 A12 VDD A11 A10 A9 A8 VSS A7 A6 A5 A4 VDD A3 A2 A1 A0 VSS PH7/nBLE3 PH6/nBLE2 nBLE1 nBLE0 nOE nWE VDDC PH5/nCS6 PH4/nCS5 PH3/nCS4 PH2/nCS3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 79520-100 Figure 1. 176-Pin LQFP 2 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 DEBUG/TEST INTERFACE RESET EXTERNAL INTERRUPTS 14.7456 MHz 32.768 kHz OSCILLATOR, PLL POWER MANAGEMENT, and RESET CONTROL REAL TIME CLOCK TEST LOGIC/PIN MUXING 32KB SRAM GENERAL PURPOSE I/O ARM 720T CONDITIONED EXTERNAL INTERRUPTS VECTORED INTERRUPT CONTROLLER I/O CONFIGURATION SYNCHRONOUS SERIAL PORT EXTERNAL BUS INTERFACE STATIC MEMORY CONTROLLER TIMER (4) INTERNAL INTERRUPTS SDRAM CONTROLLER DMA CONTROLLER WATCHDOG TIMER DUAL CHANNEL PWM ADVANCED PERIPHERAL BUS BRIDGE UART (3) IrDA INTERFACE ADVANCED HIGH PERFORMANCE BUS (AHB) COLOR LCD CONTROLLER ADVANCED PERIPHERAL BUS (APB) HR-TFT LCD TIMING CONTROLLER 79520-1 Figure 2. LH79520 Block Diagram Preliminary Data Sheet 8/21/02 3 LH79520 System-on-Chip SIGNAL DESCRIPTIONS Table 1. LH79520 Signal Descriptions PIN NO. SIGNAL NAME TYPE DESCRIPTION MEMORY INTERFACE (MI) 2-7 9-12 14-17 19-22 24-27 29-32 50-54 56-63 65-66 67-69 71-74 76-79 81-84 86-87 101 109 110 111 112 102 104 105 107 108 106 41 42 43 44 46 47 48 38 34 35 36 37 39 144 148 147 146 157 145 144 NOTES A[25:0] Output Address Signals D[31:0] Input/Output Data Input/Output Signals 1 SDCLK DQM3 DQM2 DQM1 DQM0 SDCKE nDCS1 nDCS0 nRAS nCAS nSDWE nCS6 nCS5 nCS4 nCS3 nCS2 nCS1 nCS0 nOE nBLE3 nBLE2 nBLE1 nBLE0 nWE nWAIT DEOT0 nDACK0 DREQ0 DEOT1 DACK1 DREQ1 Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output Output Input Output Output Input SDRAM Clock Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs SDRAM Clock Enable SDRAM Chip Select SDRAM Chip Select Row Address Strobe Column Address Strobe SDRAM Write Enable Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Output Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Byte Lane Enable / Byte Write Enable Static Memory Controller Write Enable Static Memory Controller External Wait Control DMA CONTROLLER (DMAC) DMA 0 End of Transfer DMA 0 Acknowledge DMA 0 Request DMA 1 End of Transfer DMA 1 Acknowledge DMA 1 Request 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1, 3 1 1 1 1 1 1, 3 4 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Table 1. LH79520 Signal Descriptions (Cont'd) PIN NO. 130 132 139 140 141 142 114 115 116 117 118 119 121 122 123 124 126 127 137 129 131 133 139 134 135 135 129 142 137 119 164 165 166 167 169 150 151 157 163 162 163 162 SIGNAL NAME TYPE DESCRIPTION COLOR LCD CONTROLLER (CLCDC) NOTES LCDVD[17:0] Output LCD Panel Data bus 1 LCDENAB LCDFP LCDLP LCDDCLK LCDDSPLEN LCDDCLKIN LCDVDDEN LCDCLS LCDSPS LCDREV LCDSPL LCDPS SSPFRM SSPCLK SSPEN SSPTX SSPRX PWM0 PWMSYNC0 PWM1 UARTRX0 UARTTX0 UARTIRRX0 UARTIRTX0 Output Output Output Output Output Input Output Output Output Output Output Output Output Output Output Output Input Output Input Output Input Output Input Output LCD Data Enable Frame Pulse (STN), Vertical Synchronization Pulse (TFT) Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) LCD Panel Data Clock LCD Display Enable LCD External Clock Input LCD Digital Supply Enable LCD Clock Signal for Gate Driver (HR-TFT only) LCD Reset Signal for Row Display (HR-TFT only) LCD Reverse Signal (HR-TFT only) LCD Line Start Pulse (Left) (HR-TFT only) LCD Power Save (HR-TFT only) SYNCHRONOUS SERIAL PORT (SSP) SSP Serial Frame Output SSP Clock SSP Data Enable SSP Data Out SSP Data In PULSE WIDTH MODULATOR (PWM) PWM0 Output PWM0 Synchronizing Input PWM1 Output UART0 (U0) UART0 Received Serial Data Input UART0 Transmitted Serial Data Output UART0 InfraRed Receive UART0 InfraRed Transmit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Preliminary Data Sheet 8/21/02 5 LH79520 System-on-Chip Table 1. LH79520 Signal Descriptions (Cont'd) PIN NO. 160 159 169 167 153 155 156 159 160 164 165 166 139 140 141 142 146 147 148 152 129 130 131 132 133 134 135 137 116 117 118 119 121 122 123 124 102 104 105 106 109 110 111 112 61 62 63 65 66 67 99 101 SIGNAL NAME UARTRX1 UARTTX1 UARTRX2 UARTTX2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 TYPE UART1 (U1) Input Output Input Output UART1 Received Serial Data Input UART1 Transmitted Serial Data Output UART2 (U2) UART2 Received Serial Data Input UART2 Transmitted Serial Data Output 1 1 1 1 DESCRIPTION NOTES GENERAL PURPOSE INPUT/OUTPUT (GPIO) Input/Output General Purpose I/O Signals - Port A 1 Input/Output General Purpose I/O Signals - Port B 1 Input/Output General Purpose I/O Signals - Port C 1 Input/Output General Purpose I/O Signals - Port D 1 Input/Output General Purpose I/O Signals - Port E 1 Input/Output General Purpose I/O Signals - Port F. GPIO PF1 is only available when CLKINSEL is `0' (i.e. the external clock source is not being used). 1 6 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Table 1. LH79520 Signal Descriptions (Cont'd) PIN NO. 52 53 54 56 57 58 59 60 34 35 41 42 43 44 50 51 145 96 97 114 115 144 150 151 152 153 155 93 94 89 90 88 98 99 156 98 174 170 173 172 171 175 176 1 SIGNAL NAME PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CTOUT1B nRESETIN nRESETOUT INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 XTALIN XTALOUT XTAL32IN XTAL32OUT CLKINSEL CLKIN CLKEN CLKOUT UARTCLK nTRST TMS TCLK TDI TDO TEST1 TEST2 nTSTA TYPE DESCRIPTION NOTES Input/Output General Purpose I/O Signals - Port G 1 Input/Output General Purpose I/O Signals - Port H 1 COUNTER/TIMER (C/T) Output Input Output Input Input Input Input Input Input Input Input Input Output Input Output Input Input Output Output Input Input Input Input Input Output Input Input Input Counter/Timer Output Reset Input Reset Output External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input Crystal Input Crystal Output 32.768 kHz Crystal Oscillator Input 32.768 kHz Crystal Oscillator Output External Clock Select External Clock Input (if CLKINSEL = HIGH at reset) External Clock Enable (if CLKINSEL = LOW at reset, then this pin functions as PF1) Clock Out (selectable from the internal bus clock or 32.768) External UART Clock Input (with CLKSEL = LOW) TEST INTERFACE JTAG Test Reset Input JTAG Test Mode Select Input JTAG Test Clock Input JTAG Test Serial Data Input JTAG Test Data Serial Output Tie LOW for Normal Operation (has internal pull-down). JTAG Debug Enable: Tie LOW for Normal Operation; pull HIGH to enable JTAG Debugging (has internal pull-down). Tie HIGH for Normal Operation (has internal pull-up). 1 1 1 1 1 1 1, 3 1 1 1 1 1 1 RESET, CLOCK, AND POWER CONTROLLER (RCPC) Preliminary Data Sheet 8/21/02 7 LH79520 System-on-Chip Table 1. LH79520 Signal Descriptions (Cont'd) PIN NO. 40 75 113 136 154 45 120 138 158 8 18 28 49 64 85 100 125 143 161 13 23 33 55 70 80 103 128 149 168 91 92 SIGNAL NAME TYPE DESCRIPTION POWER AND GROUND (GND) NOTES VDDC Power Core Power Supply VSSC Ground Core GND VDD Power Input/Output Power Supply VSS Ground Input/Output GND VDDA VSSA Power Ground Analog Power Supply for PLLs and XTAL Oscillators Analog GND for PLLs and XTAL Oscillators NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded by `n' are Active LOW. 3. Immediately after reset, pin 144 can be programmed to function as INT5, DREQ1 or both. Software should avoid enabling both of these functions simultaneously. Pin 144 can also be programmed to function as nWAIT, rendering the INT5/DREQ1 choice unavailable. 8 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 NUMERICAL PIN LIST Table 2. LH79520 Numerical Pin List PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET nTSTA A25 A24 A23 A22 A21 A20 VDD A19 A18 A17 A16 VSS A15 A14 A13 A12 VDD A11 A10 A9 A8 VSS A7 A6 A5 A4 VDD A3 A2 A1 A0 VSS PH7 PH6 nBLE1 nBLE0 nOE nBLE3 nBLE2 TYPE5 Input Output Output Output Output Output Output Power Output Output Output Output Ground Output Output Output Output Power Output Output Output Output Ground Output Output Output Output Power Output Output Output Output Ground I/O I/O Output Output Output OUTPUT DRIVE7 None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA NOTES 1 Preliminary Data Sheet 8/21/02 9 LH79520 System-on-Chip Table 2. LH79520 Numerical Pin List (Cont'd) PIN NO. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET nWE VDDC PH5 PH4 PH3 PH2 VSSC nCS2 nCS1 nCS0 VDD PH1 PH0 PG7 PG6 PG5 VSS PG4 PG3 PG2 PG1 PG0 PF7 PF6 PF5 VDD PF4 PF3 PF2 D15 D14 VSS D13 D12 D11 D10 VDDC D9 D8 D18 D17 D16 D26 D25 D24 D23 D22 D21 D20 D19 D31 D30 D29 D28 D27 nCS6 nCS5 nCS4 nCS3 TYPE5 Output Power I/O I/O I/O I/O Ground Output Output Output Power I/O I/O I/O I/O I/O Ground I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O Ground I/O I/O I/O I/O Power I/O I/O OUTPUT DRIVE7 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA NOTES 10 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Table 2. LH79520 Numerical Pin List (Cont'd) PIN NO. 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET D7 D6 VSS D5 D4 D3 D2 VDD D1 D0 CLKINSEL XTAL32IN XTAL32OUT VDDA VSSA XTALIN XTALOUT VDDC nRESETIN nRESETOUT CLKIN PF1 VDD PF0 PE7 VSS PE6 PE5 PE4 nRAS nCAS PE3 PE2 PE1 PE0 VDDC INT7 INT6 PD7 LCDVD11 LCDVD10 LCDVD9 DQM3 DQM2 DQM1 DQM0 nDCS1 nDCS0 nSDWE SDCLK SDCKE UARTCLK CLKEN TYPE5 I/O I/O Ground I/O I/O I/O I/O Power I/O I/O Input Input Output Power Ground Input Output Power Input Output Input I/O Power I/O I/O Ground I/O I/O I/O Output Output I/O I/O I/O I/O Power I/O I/O I/O None None 4 mA None 2 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 1, 4 None None None 3 OUTPUT DRIVE7 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None None 3 2 NOTES Preliminary Data Sheet 8/21/02 11 LH79520 System-on-Chip Table 2. LH79520 Numerical Pin List (Cont'd) PIN NO. 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET PD6 PD5 PD4 VSSC PD3 PD2 PD1 PD0 VDD LCDVD1 LCDVD0 VSS PC7 PC6 PC5 PC4 PC3 PC2 PC1 VDDC PC0 VSSC PB7 PB6 PB5 PB4 VDD INT5/DREQ1 CTOUT1B PB3 PB2 PB1 VSS INT4 INT3 PB0 PA7 VDDC PA6 INT0 PWM0 PWMSYNC0 INT2 INT1 nWAIT DACK1 DREQ0 nDACK0 DEOT0 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDREV LCDDSPLEN I/O I/O I/O I/O Power Input Output I/O I/O I/O Ground I/O Input I/O I/O Power I/O LCDENAB LCDSPL LCDFP LCDVD17 LCDLP LCDVD16 LCDDCLK LCDDCLKIN LCDVDDEN LCDCLS LCDSPS LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD8 LCDVD7 LCDVD6 LCDPS TYPE5 I/O I/O I/O Ground I/O I/O I/O I/O Power Output Output Ground I/O I/O I/O I/O I/O I/O I/O Power I/O OUTPUT DRIVE7 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 2 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None None 4 mA 2 mA 4 mA 4 mA None 4 mA None 2 mA 2 mA None 2 mA 4 4 4 4 4 4 4, 6 NOTES 12 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Table 2. LH79520 Numerical Pin List (Cont'd) PIN NO. 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 FUNCTION AT FUNCTION 2 FUNCTION 3 RESET PA5 PWM1 VSSC PA4 PA3 VDD UARTIRTX0 UARTIRRX0 PA2 PA1 PA0 SSPTX VSS SSPRX TMS TDO TDI TCLK nTRST TEST1 TEST2 UARTRX2 UARTTX0 UARTRX0 SSPFRM SSPCLK SSPEN UARTTX2 UARTTX1 UARTRX1 CLKOUT DEOT1 TYPE5 I/O Output Ground I/O I/O Power Output Input I/O I/O I/O Output Ground Input Input Output Input Input Input Input Input OUTPUT DRIVE7 8 mA 4 mA None 4 mA 2 mA None 4 mA None 4 mA 4 mA 4 mA 4 mA None None None 4 mA None None None None None 1, 4 2 2 1, 4 4 1, 4 4 4 NOTES NOTES: 1. Input with internal pull-up. 2. Input with internal pull-down. 3. Output is for crystal oscilator only, no drive capability. 4. Input with Schmitt Trigger. 5. I/O = Input/Output. 6. Software should avoid enabling the INT5 and DREQ1 functions simultaneously. 7. Output Drive Values shown are MAX. See `DC Specifications'. Preliminary Data Sheet 8/21/02 13 LH79520 System-on-Chip Table 3. LCD Panel Data Signal Multiplexing LH79520 EXTERNAL PIN LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN7 MLSTN6 MLSTN5 MLSTN4 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 CLSTN7 CLSTN6 CLSTN5 CLSTN4 CLSTN3 CLSTN2 CLSTN1 CLSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 RED4 RED3 RED2 RED1 RED0 Intensity RED4 RED3 RED2 RED1 RED0 Intensity GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 MONO STN 4-BIT SINGLE PANEL DUAL PANEL MONO STN 8-BIT SINGLE PANEL DUAL PANEL COLOR STN SINGLE PANEL DUAL PANEL TFT 18 BIT BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 HR-TFT 18 BIT BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 NOTES: 1. The Intensity bit is identically generated for all three colors. 2. MUSTN = Monochrome Upper data bit for STN panel 3. MLSTN = Monochrome Lower data bit for STN panel 4. CUSTN = Color Upper data bit for STN panel 5. CLSTN = Color Lower data bit for STN panel 14 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 TOUCH SCREEN CONTR. CODEC IMAGER SSP DMA STN/ TFT/HR-TFT PWM PIO UART FLASH/ SRAM/ SDRAM LH79520 UART IR MEMORY CARD INTERFACE SH FLA D R CA 79520-6A Figure 3. LH79520 Application Diagram Example SYSTEM DESCRIPTIONS ARM720T Processor The LH79520 microcontroller features the ARM720T cached core with an Advanced High-Performance Bus (AHB) interface. The ARM720T features: * 32-bit ARM7TDMITM RISC Core * 8KB Cache * MMU (Windows CE enabled) The processor is a member of the ARM7T family of processors. For more information, see the ARM document, `ARM720T (Rev 3) Technical Reference Manual', available on Sharp's website at www.sharpsma.com. The LH79520 MMU provides a means to map Physical Memory (PA) addresses to virtual memory addresses. This allows physical memory, which is constrained by hardware to specific addresses, to be reorganized at addresses identified by the user. These user identified locations are called Virtual Addresses (VA). When the MMU is enabled, Code and Data must be built, loaded, and executed using Virtual Addresses which the MMU translates to Physical Addresses. In addition, the user may implement a memory protection scheme by using the features of the MMU. Address translation and memory protection services provided by the MMU are controlled by the user. The MMU is directly controlled through the System Control Coprocessor, Coprocessor 15 (CP15). The MMU is indirectly controlled by a Translation Table (TT) and Page Tables (PT) prepared by the user and established using a portion of physical memory dedicated by the user to storing the TT and PT's. Preliminary Data Sheet 8/21/02 15 LH79520 System-on-Chip Memory Architecture An integrated SDRAM Controller and Static Memory Controller provide a glueless interface to external SDRAM, Flash, SRAM, ROM, and burst ROM. Three remap options for the physical memory are selectable by software, as shown in Figures 4, 5, and 6. Memory is exclusively Little Endian. SDRAM CONTROLLER The SDRAM Controller provides the interface between the internal bus and external (off-chip) SDRAM memory devices (Figure 2). The SDRAM Controller provides the following features: * Two independently controlled chip selects. * Transfers data between the controller and SDRAM in quad-word bursts. * Supports both 32-bit and 16-bit SDRAM. * Supports 2K, 4K, and 8K row address memory parts, i.e. typical 256M, 128M, 64M, and 16M parts, with 8, 16, or 32 DQ bits per device. * Two reset domains allow SDRAM contents to be preserved over a soft reset. STATIC MEMORY CONTROLLER (SMC) The SMC provides the interface between the internal bus and external (off-chip) memory devices. The LH79520 boots from 16-bit memory. The SMC address space is divided into eight memory banks of 64MB each. The SMC supports: * Static Memory-mapped Devices including RAM, ROM, Flash, and Burst ROM * Asynchronous Operations: - Page Mode Reads for non-clocked memory - Burst Mode Reads for burst mode ROM * 8-, 16-, and 32-bit wide external memory data paths * Independent configuration for up to eight memory banks, each up to 64MB * Programmable Parameters: - WAIT States (up to 32) - Bus Turnaround Cycles (1 to 16) - Initial and Subsequent Burst Read WAIT State for Burst ROM Devices. The Static Memory Controller (SMC) also supports an nWAIT input that can be used by an external device to vary the wait time. 0xFFFFFFFF 0xFFFF0000 0xFFFC0000 ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS 0x20000000 EXTERNAL STATIC MEMORY 0x00000000 79520-5 0xFFFFFFFF 0xFFFF0000 0xFFFC0000 ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS RESERVED 0x80000000 INTERNAL STATIC MEMORY 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 SDRAM Figure 4. Memory Remap `00' and `11' 0xFFFFFFFF 0xFFFF0000 0xFFFC0000 ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS RESERVED 0x80000000 INTERNAL STATIC MEMORY 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 SDRAM 0x20000000 INTERNAL STATIC MEMORY 0x00000000 79520-4 Figure 5. Memory Remap `10' RESERVED 0x80000000 INTERNAL STATIC MEMORY 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 SDRAM 0x20000000 SDRAM 0x00000000 79520-3 DMA Controller The DMA Controller provides support for DMAcapable peripherals. The LCD controller uses its own DMA port, connecting directly to memory for retrieving display data. Figure 6. Memory Remap `01' 16 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 * Simultaneous servicing of up to 4 data streams * Three transfer modes are supported: - Memory to Memory - Peripheral to Memory - Memory to Peripheral * Identical source and destination capabilities * Transfer Size Programmable (Byte, Half-word, Word) * Burst Size Programmable * Address Increment or Address Freeze * Transfer Error indication for each stream via an interrupt * 16-word FIFO array with pack and unpack logic Handles all combinations of byte, half-word or word transfers from input to output. The two modes of the LCDICP peripheral are: * Bypass Mode (used for driving STN, CSTN, and TFT panels) * HR-TFT Mode Synchronous Serial Port (SSP) The SSP is a master-only interface for synchronous serial communication with slave peripheral devices that support protocols for Motorola SPI, National Semiconductor MICROWIRE, or Texas Instruments Synchronous Serial Interface. * Master-only operation * Programmable clock rate * Separate transmit FIFO and receive FIFO buffers, 16 bits wide, 8 locations deep * DMA for transmit and receive * Programmable interface protocols: Motorola SPI, National Semiconductor MICROWIRE, or Texas Instruments Synchronous Serial Port * Programmable data frame size from 4 to 16 bits * Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts * Available internal loopback test mode. Color LCD Controller (CLCDC) The CLCDC provides all the necessary control and drive signals to interface directly with a variety of color and monochrome LCD panels. * Supports single and dual scan color and monochrome Super Twisted Nematic (STN) displays with 4- or 8-bit interfaces * Supports Thin Film Transistor (TFT) color displays * Programmable resolution up to 800 x 600 - 800 x 600 (16-bit color can only be supported at 65 Hz refresh rates with 800 x 600 resolution). * 15 gray-level mono, 3,375 color STN, and 64 k color TFT support * 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN * 1-, 2-, 4-, or 8-BPP palettized color displays for color STN and TFT * True-color non-palettized, for color STN and TFT * Programmable timing for different display panels * 256-entry, 16-bit palette fast-access RAM * Frame, line and pixel clock signals * AC bias signal for STN or data enable signal for TFT panels * Patented grayscale algorithm * Interrupt Generation Events * Dual 16-deep programmable 32-bit wide FIFOs for buffering incoming data. Universal Asynchronous Receiver Transmitter (UART) The LH79520 incorporates three UARTs. * Programmable use of UART0 or IrDA SIR input/output * Separate 16-byte transmit and receive FIFOs to reduce CPU interrupts * Programmable FIFO disabling for 1-byte depth * Programmable baud rate generator * Independent masking of transmit FIFO, receive FIFO, receive timeout and modem status interrupts * False start bit detection * Line Break generation and detection * Fully-programmable serial interface characteristics: - 5-, 6-, 7-, or 8-bit data word length - Even-, odd- or no-parity bit generation and detection - 1 or 2 stop bit generation * IrDA SIR Encode/Decode block, providing: - Programmable use of IrDA SIR or UART0 input/output - Supports data rates up to 115.2 Kbps half-duplex - Programmable internal clock generator, allowing division of the Reference clock in increments of 1 to 512 for low-power mode bit durations. Liquid Crystal Display Interface Conversion Peripheral Interface (LCDICP) The LCDICP peripheral converts TFT signals from the Color LCD controller to provide control of an HRTFT display. The internal data coming into the interface converter is in TFT format. Bypass mode is provided if any other format is required. Preliminary Data Sheet 8/21/02 17 LH79520 System-on-Chip VARIATIONS FROM THE 16C550 UART The UART varies from the industry-standard 16C550 UART device in six ways: * Receive FIFO trigger levels are fixed at 8 bytes * Receive errors are stored in the FIFO, and do not generate an interrupt. * The internal register map address space and each register's bit function differ. The following 16C550 UART features are not supported: * 1.5 stop bits (1 or 2 stop bits only are supported) * The forcing stick parity function * Independent receive clock. - FIQ interrupt request - Non-vectored IRQ interrupt request (software to poll IRQ source) - Vectored IRQ interrupt request (up to 16 channels total) * The Watchdog timer can only generate FIQ interrupt requests * External interrupt inputs programmable - Edge triggered or level triggered - Rising edge/active HIGH or falling edge/active LOW The 28 interrupt channels are shown in Table 4. Table 4. Interrupt Channels CHANNEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27-29 30 31 INTERRUPT SOURCE External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 Spare Internal Interrupt 0 COMRX (used for debug) COMTX (used for debug) SSP RX time-out interrupt SSPRXTO CLCD Combined Interrupt SSP SSPTXINTR SSP SSPRXINTR SSP SSPRORINTR SSP SSPINTR Counter/Timer0 Counter/Timer1 Counter/Timer2 Counter/Timer3 UART ch0 Rx UART ch0 Tx UART ch0 UART ch1 UART ch2 DMA Combined Unused RTC_ALARM WDT Pulse Width Modulator (PWM) * Two independent output channels with separate input clocks * Up to 16-bit resolution * Programmable synchronous mode support - Allows external input to start PWM * Programmable pulse width (duty cycle), interval (frequency), and polarity - Static programming: PWM is stopped - Dynamic programming: PWM is running - Updates duty cycle, frequency, and polarity at the end of a PWM cycle - Wide programming range. Vectored Interrupt Controller The Vectored Interrupt Controller combines the interrupt request signals from 20 internal and eight external interrupt sources and applies them, after masking and prioritization, to the IRQ and FIQ interrupt inputs of the ARM7TDMI processor core. The Interrupt Controller incorporates a hardware interrupt vector logic with programmable priority for up to 16 interrupt sources. This logic reduces the interrupt response time for IRQ type interrupts compared to solutions using software polling to determine the highest priority interrupt source. This significantly improves the real-time capabilities of the LH79520 in embedded control applications. * 20 internal and eight external interrupt sources - Individually maskable - Status accessible for software polling * IRQ interrupt vector logic for up to 16 channels with programmable priorities * All of the interrupt channels, with the exception of the Watchdog Timer interrupt, can be programmed to generate: 18 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Reset, Clock, and Power Controller (RCPC) The RCPC generates the various clock signals for the operation of the LH79520 and provides for an orderly start-up after power-on and during a wake-up from one of the power saving operating modes. The RCPC allows the software to individually select the frequency of the various on-chip clock signals as required to operate the chip in the most power-efficient mode. It features: * 14.7456 MHz crystal oscillator and PLL for on-chip Clock generation * External Clock input if on-chip oscillator and PLL are not used * 32.768 kHz crystal oscillator generating 1 Hz clock for Real Time Clock * Individually controlled clocks for peripherals and CPU * Clock source for UARTs is selectable between 14.7456 MHz crystal oscillator and external clock source * Programmable clock prescalers for UARTs and PWMs * Five global power control modes are available: - Active - Standby - Sleep - Stop1 - Stop2 * CPU and Bus clock frequency can be changed on the fly * Selectable clock output * Hardware reset (nRESETIN) and software reset. Table 5. Clock and Enable States for Different Power Modes (Using On-chip Oscillator and PLL) FUNCTION 14.7456 MHz Oscillator PLL Peripheral Clock CPU Clock ACTIVE ON ON ON ON STANDBY ON ON ON OFF SLEEP ON ON OFF OFF STOP1 ON OFF OFF OFF STOP2 OFF OFF OFF OFF Preliminary Data Sheet 8/21/02 19 LH79520 System-on-Chip Real Time Clock The RTC can provide a basic alarm function or long time base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of RTC input. Counting in one-second intervals is achieved by the use of a 1 Hz clock input to the RTC. The features of the RTC are: * 32-bit up counter with programmable load * Programmable 32-bit match compare register * Software maskable interrupt when counter and compare registers are identical. RTC input clock sources: * PLL clock * 32.768 kHz clock * 1 Hz clock (default). Timer The LH79520 incorporates two Timer modules, each comprising two 16-bit independently programmable timers. This gives a total of four independent timers. * Each timer has two operating modes: - Free-running mode: After reaching 0x0000 the timer wraps around to 0xFFFF and generates an interrupt request. It continues to count down from 0xFFFF. - Periodic timer mode: After reaching 0x0000 the timer is automatically reloaded with its programmed value and generates an interrupt request. It continues to count down from the loaded value. * Each timer contains a programmable pre-scaler: - Bus clock divided by 1, 16, or 256 * Timers can be cascaded to achieve longer timing periods * Carry-out of higher-order timer provides clock signal for next lower order timer * Possible timing ranges: - 215 (single timer) - 231 (two timers cascaded) - 247 (three timers cascaded) - 263 (four timers cascaded) * Output signal of lowest order timer is externally available as CTOUT1B signal. Watchdog Timer The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer to be reset by software at regular intervals. Failure to reset the timer will cause a FIQ interrupt. Failure to service the FIQ interrupt will then generate a System Reset. The features of the Watchdog Timer are: * Driven by the bus clock * 16 programmable time-out periods: 216 through 231 clock cycles * Generates a system reset (resets LH79520) or a FIQ Interrupt whenever a time-out period is reached * Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes * Protection mechanism guards against interrupt-service failure: - The first WDT time-out triggers FIQ and asserts nWDFIQ status flag - If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a soft reset. Input/Output Configuration System The registers provided by the IOCON System allow the user to directly control the pin multiplexing of the device; by setting or clearing bits in a set of registers, the user can configure the LH79520 for peripheral devices. General Purpose Input/Output (GPIO) The LH79520 provides up to 64 bits of programmable input/output. These eight 8-bit ports are Ports A through H, and are multiplexed with other signals. * Individually programmable input/output pins * All I/O ports default to Input on power-up. 20 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER DC Core Supply Voltage DC I/O Supply Voltage DC Analog Supply Voltage Storage Temperature SYMBOL VDDC VDD VDDA TSTG RATING -0.3 to 2.4 -0.3 to 4.6 -0.3 to 2.4 -55 to +125 UNIT V V V C NOTE: These stress ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended Operating Conditions PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) Clock Frequency Commercial Operating Temperature MINIMUM TYPICAL 1.62 V 3.0 V 1.62 V 10 MHz 0C 25C 1.8 V 3.3 V 1.8 V MAXIMUM 1.98 V 3.6 V 1.98 V 77.4144 MHz +70C 2, 3, 4, 5 NOTES 1 1 NOTES: 1. Core Voltage (VDDC) must never exceed I/O Voltage (VDD). 2. Commercial Temperature Range. 3. VDDC = 1.62 V to 1.98 V. 4. VDD = 3.0 V to 3.6 V. 5. Using 14.7456 MHz Input Crystal and On-Chip PLL. Preliminary Data Sheet 8/21/02 21 LH79520 System-on-Chip DC/AC SPECIFICATIONS (COMMERCIAL) Unless otherwise noted, all data provided under commercial DC specifications are based on 0C to +70C, VDDC = 1.62 V to 1.98 V, VDD = 3.3 V to 3.6 V, VDDA = 1.62 V to 1.98 V. DC Specifications (Commercial) SYMBOL VIH VIL VHST PARAMETER CMOS and Schmitt trigger input HIGH voltage CMOS and Schmitt trigger input LOW voltage Schmitt trigger hysteresis CMOS output HIGH voltage VOH Output drive (2 mA type) Output drive (4 mA type) Output drive (8 mA type) CMOS output LOW voltage VOL Output drive (2 mA type) Output drive (4 mA type) Output drive (8 mA type) IIN IOZ IACTIVE ISLEEP ISTOP1 ISTOP2 ISTOP2 CIN COUT Input leakage current Output tri-state leakage current Active current Sleep current Stop1 current Stop2 current (RTC ON) Stop2 current (RTC OFF) Input Capacitance Output Capacitance 0.35 2.6 2.6 2.6 2.6 0.0 0.0 0.0 0.0 -10 -10 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 10 10 55 35 5.5 500 34 18 4 4 MIN. MAX. UNIT 2.0 5.5 0.8 V V V V V V V V V V V A A mA mA mA A A A pF pF 4 4 4 VIL to VIH IOH = -50 A IOH = -2 mA IOH = -4 mA IOH = -8 mA IOL = 50 A IOL = 2 mA IOL = 4 mA IOL = 8 mA VIN = VDD or GND VOUT = VDD or GND 2 2, 3 1 1 CONDITIONS NOTES ISTANDBY Standby current NOTES: 1. Table 2 details each pin's buffer type. 2. Running Typical Application over operating range. 3. Current measured with CPU stopped and all peripherals enabled. 4. Typical AC Test Conditions PARAMETER Supply Voltage (VDD) Core Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels RATING 3.0 to 3.6 1.8 VSS to 3.0 2 VDD/2 UNIT V V V ns V 22 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 AC Specifications (Commercial) All signals described in Table 6 relate to transitions after a reference clock signal. The illustration in Figure 7 represents all cases of these sets of measurement parameters. The reference clock signals in this design are: * HCLK, the System Bus clock * PCLK, the Peripheral Bus clock * SSPCLK, the Synchronous Serial Interface clock * UARTCLK, the UART Interface clock * LCDDCLK, the LCD Data clock from the LCD Controller * and SDCLK, the SDRAM clock. All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. See Figure 7. For outputs from the LH79520, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX are shown in Table 6. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid from the rising edge of the reference clock signal. Minimum requirements for tOHXXX are listed in Table 6. For Inputs, tISXXX (e.g. tISD) represents the amount of time the input signal must be valid before the rising edge of the clock signal. Minimum requirements for tISXXX are shown in Table 6. The signal tIHXXX (e.g. tIHD) represents the amount of time the output must be held valid from the rising edge of the reference clock signal. Minimum requirements are shown in Table 6. REFERENCE CLOCK tOVXXX tOHXXX OUTPUT SIGNAL (O) tISXXX tIHXXX INPUT SIGNAL (I) 79520-34 Figure 7. LH79520 Signal Timing Preliminary Data Sheet 8/21/02 23 LH79520 System-on-Chip Table 6. AC Signal Characteristics SIGNAL TYPE LOAD DRIVE SYMBOL MIN. MAX. DESCRIPTION ASYNCHRONOUS MEMORY INTERFACE SIGNALS tOVD Output 50 pF D[31:0] Input 8 mA tOHD tIDD tOVCS nCS6 - nCS0 Output 30 pF 8 mA 3 x tHCLK - 6 ns 2 x tHCLK - 18 ns 6 ns tHCLK + 6 ns Data Output Valid, following Address Valid Data Output Invalid, following Address Valid Data Input Valid, following Address Valid Chip Select Output Valid, following Address Valid; read cycle Chip Select Output Valid, following Address Valid; write cycle Chip Select Output Invalid, following Address Valid tHCLK + 10 ns 2 x tHCLK - 6 ns tHCLK + 10 ns 2 x tHCLK - 6 ns 10 ns 3 x tHCLK - 6 ns 2 x tHCLK - 18 ns Byte Lane Enable Valid, following Address Valid Byte Lane Enable Invalid, following Address Valid Write Enable Valid, following Address Valid Write Enable Invalid, following Address Valid Ouput Enable Valid, following Address Valid Ouput Enable Invalid, following Address Valid WAIT Input Valid, following Address Valid Address Valid Output Data Valid Output Data Hold Input Data Setup Input Data Hold 10.5 ns 2 ns 10.5 ns 2 ns 10.5 ns 2 ns 10.5 ns 2 ns 10.5 ns 2 ns 10.5 ns 2 ns 19.37 ns CAS Valid CAS Hold RAS Valid RAS Hold SDWE Write Enable Valid SDWE Write Enable Hold SDCKE Clock Enable Valid SDCKE Clock Enable Hold DQM Data Mask Valid DQM Data Mask Hold SDCS Data Mask Valid SDCS Data Mask Hold SDRAM Clock Period tOHCSW tOHCSR tOVBE 3 x tHCLK - 6 ns tHCLK + 10 ns nBLE[3:0] Output 30 pF 8 mA tOHBE tOVWE nWE Output 30 pF 8 mA tOHWE tOVOE nOE Output 30 pF 8 mA tOHOE nWAIT Input tISWAIT SYNCHRONOUS MEMORY INTERFACE SIGNALS A[25:0] Ouput 50 pF Output 50 pF D[31:0] Input nCAS nRAS nSDWE SDCKE DQM[3:0] nSDCS[1:0] SDCLK Output 50 pF Output 50 pF Output 30 pF Output 30 pF Output 30 pF Output 30 pF Output 30 pF 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA tOVA tOVD tOHD tISD tIDD tOVCA tOHCA tOVRA tOHRA tOVSDW tOHSDW tOVC0 tOHC0 tOVDQ tOHDQ tOVSC tOHSC tSDCLK 2 ns 5 ns 1.5 ns 10.5ns 11 ns 24 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Table 6. AC Signal Characteristics (Cont'd) SIGNAL TYPE LOAD DRIVE SYMBOL MIN. MAX. DESCRIPTION SYNCHRONOUS SERIAL PORT (SSP) SSPFRM Input tISSSPFRM tOVSSPENB 14 ns 14ns SSPFRM Input Setup, Referenced to SSPCLK tOVSSPENB Valid, Referenced to SSPCLK GBD SSPTX SSPRX INTR[5:0] Output 50 pF Input Input 2 mA tOVSSPOUT tISSSPIN 14 ns INTERRUPTS Note 3 14ns SSP Transmit Valid GBD SSP Receive Setup SSPENB Output 50 pF 2 mA NOTES: 1. Input times shown are minimum requirement for setup. 2. Output times shown are maximum requirement for output valid. 3. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode, and held Active for a minimum of 20 ns in Edge Sensitive Mode. 4. DACK0, nDACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced, for a minimum of 20 ns. Preliminary Data Sheet 8/21/02 25 LH79520 System-on-Chip EXTERNAL CLOCKS Table 7. External Clocks AC Specifications SYMBOL tCLKIN tCLKINH tCLKINL tSSPCLK tSSPCLKH tSSPCLKL tUCLK tUCLKH tUCLKL DESCRIPTION CLKIN Period CLKIN HIGH Time CLKIN LOW TIme SSPCLK Period SSPCLK HIGH Time SSPCLK LOW Time UCLK UCLK HIGH Time UCLK LOW Time MIN. 6.66 2.8 2.8 1 0.4 0.4 1 0.4 0.4 UNIT ns ns ns PCLK PCLK PCLK PCLK PCLK PCLK tUCLKH tUCLK tUCLKL 79520-58 tSSPCLK tSSPCLKH tSSPCLKL Figure 9. Synchronous Serial I/F Clocks AC Timing NOTE: PCLK is the period chosen for the internal peripheral clock domain. tCLKIN tCLKINL tCLKINH 79520-59 Figure 10. External UARTs/SIR Clock AC Timing 79520-57 Figure 8. External Clock AC Timing 26 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Static Memory Controller Waveforms Figure 11 shows the waveform and timing for an External Static Memory Write. Figure 12 shows the waveform and timing for an External Static Memory Read, with one Wait State. Figure 13 shows the waveform and timing for an External Static Memory Read, with two Wait States. The Static Memory Controller (SMC) supports an nWAIT input that can be used by an external device to extend the wait time during a memory access. The SMC samples nWAIT at the beginning of at the beginning of each system clock cycle. The system clock cycle in which the nCSx signal is asserted counts as the first wait state. See Figure 14. The SMC recognizes that nWAIT is active within 2 clock cycles after it has been asserted. To assure that the current access (read or write) will be extended by nWAIT, at least two wait states must be programmed for this bank of memory. If N wait states are programmed, then the Static Memory Controller (SMC) holds this state for N system clocks, or until the SMC detects that nWAIT is inactive, whichever occurs last. As the number of wait states programmed increases, the amount of delay before nWAIT must be asserted also increases. If only 2 wait states are programmed, then nWAIT must be asserted in the clock cycle immediately following the clock cycle during which the nCSx signal is asserted. Once the SMC detects that the external device has deactivated nWAIT, the SMC will complete its access in 3 system clock cycles. The formula for the allowable delay between asserting nCSx and asserting nWAIT is: tASSERT = (system clock period) x (Wait States - 1) (where Wait States is from 2 to 31.) HCLK A[25:0] ADDRESS tOVA D[31:0] tOVD DATA tOHA tOHD tOVD nCSx tOVCS nBE[3:0], nWE tOHCS tOVBE, tOVWE NOTE: All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. tOHBE, tOHWE 79520-30 Figure 11. External Static Memory Write Preliminary Data Sheet 8/21/02 27 LH79520 System-on-Chip DATA READ 1 WAIT STATE HCLK A[25:0] tOVA ADDRESS tOHA D[31:0] tISD DATA tIHD nCSx tOVCS tOHCS nOE tOVOE tOHOE NOTE: All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. 79520-31 Figure 12. External Static Memory Read, One Wait State DATA READ 2 WAIT STATES HCLK tOHA A[25:0] ADDRESS tIHD tOVA D[31:0] DATA tISD tOHCS nCSx tOHOE tOVCS nOE tOVOE NOTE: All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. 79520-32 Figure 13. External Static Memory Read, Two Wait States 28 8/21/02 Preliminary Data Sheet System-on-Chip Preliminary Data Sheet tASSERT tISWAIT 79520-108 HCLK A[23:0] D[15:0] Figure 14. External Static Memory Read, nWait Active 8/21/02 nCSx nWEN nWAIT nBLE[1:0] (See Note) nOE LH79520 NOTE: 00 if appropriate RBLE register = 1, 11 if RBLE = 0. 29 LH79520 System-on-Chip SDRAM Memory Controller Waveforms Figure 15 shows the waveform and timing for an SDRAM Burst Read (page already open). Figure 16 shows the waveform and timing for SDRAM to Activate a Bank and Write. tSDCLK SCLK tOHXXX SDRAMcmd READ tOVB tOVXXX A[15:0] tOVA D[31:0] NOTES: DATA n + 2 DATA n 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X). DATA n + 1 DATA n + 3 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is LOW. 5. SDCKE is HIGH. BANK, COLUMN tISD tIHD LH79520-35 Figure 15. SDRAM Burst Read tSDCLK SCLK tOVC0 SDCKE tOVXXX tOHXXX SDRAMcmd ACTIVE tOVA WRITE A[15:0] BANK, ROW tOVA D[31:0] tOVD NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X). 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is LOW. tOHD DATA BANK, COLUMN 79520-36 Figure 16. SDRAM Bank Activate and Write 30 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 External DMA Handshake Signal Timing DREQ TIMING Once asserted, DREQ0 or DREQ1 must not transition from LOW to HIGH again until after DACK0 or nDACK1 has been asserted. DACK/DEOT TIMING These timing diagrams indicate when DACK0, nDACK1, DEOT0 and DEOT1 occur in relation to an external bus access to/from the external peripheral that requested the DMA transfer. The top diagram shows the timing with relation to a single read or the last word of a burst read from the requesting peripheral. The bottom diagram shows the timing with relation to a single write or the last word of a burst write to the requesting peripheral. The timing of DACK/DEOT may become unpredictable when a Write to SDRAM occurs just prior to a single word Write to the requesting peripheral. If the write buffer is enabled for the SDRAM Controller, this can cause the DACK/DEOT to occur an indeterminate number of cycles prior to the actual Write to the requesting peripheral. DREQ MUST NOT TRANSITON DREQ MAY TRANSITON tDREQ0L, tDREQ1L DREQ0, DREQ1 DACK0 nDACK1 NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN. tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN. 79520-158 Figure 17. DREQ Timing Restrictions Preliminary Data Sheet 8/21/02 31 LH79520 System-on-Chip HCLK (See Note) A[23:0] ADDRESS D[31:0] DATA nCSx nWEN nBLE[1:0] nOE DACK0/ DEOT0/DEOT1 nDACK1 NOTE: * HCLK is an internal signal provided for reference only. 79520-156 Figure 18. Read, from Peripheral to Memory HCLK (See Note) A[23:0] ADDRESS D[15:0] DATA nCSx nWEN nBLE[1:0] nOE DACK0/ DEOT0/DEOT1 nDACK1 NOTE: * HCLK is an internal signal provided for reference only. 79520-157 Figure 19. Write, from Memory to Peripheral 32 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Reset, Clock, and Power Controller (RCPC) Waveforms Figure 20 shows the method the LH79520 uses when coming out of Reset or Power On. Figure 21 shows external reset timing, and Table 8 gives the timing parameters. Table 8. Reset AC Timing PARAMETER tOSC (32 kHz) tOSC (14 MHz) tRSTIW tRSTOV tRSTOH DESCRIPTION Oscillator stabilization time after Power Up (VDDC = VDDCMIN) Oscillator stabilization time after Power Up (VDDC = VDDCMIN) nRESETIN Pulse Width (once sampled LOW) nRESETIN LOW to nRESETOUT valid (once nRESETIN sampled LOW) nRESETOUT hold relative to nRESETIN HIGH 2 3.5 1 MIN. TYP. MAX. 550 2.5 UNIT ms ms HCLK HCLK HCLK NOTE: Values in this table are from characterization. VDDCmin VDDC XTAL tOSC nRESETI tRSTOH nRESETO 79520-37 Figure 20. PLL Start-up tRSTIW nRESETIN tRSTOV tRSTOH nRESETO 79520-60 Figure 21. External Reset Preliminary Data Sheet 8/21/02 33 LH79520 System-on-Chip DC/AC SPECIFICATIONS (INDUSTRIAL) Under development. Results pending characterization. 34 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 Printed Circuit Board Layout Practices LH79520 POWER SUPPLY DECOUPLING The LH79520 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power to the core logic. Each of the VDD and VDDC pins must be provided with a low impedance path to the corresponding board power supply. Likewise, the VSS and VSSC pins must be provided with a low impedance path to the board ground. Each power supply must be decoupled to ground using at least one 0.1 F high frequency capacitor located as close as possible to a VDDx, VSSx pin pair on each of the four sides of the chip. If room on the circuit board allows, add one 0.01 F high frequency capacitor near each VDDx, VSSx pair on the chip. To be effective, the capacitor leads and associated circuit board traces connecting to the chip VDDx, VSSx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. There must be one bulk 10 F capacitor for each power supply placed near one side of the chip. REQUIRED LH79520 PLL, VDDA, VSSA FILTER The VDDA pin supplies power to the chip PLL circuitry. VSSA is the ground return path for the PLL circuit. If the internal PLL circuit will be used, these pins must have a low-pass filter attached as shown in Figure 22. The power pin VDDA path must be a single wire from the IC package pin to the high frequency capacitor, then to the low frequency capacitor, and finally through the series resistor to the board power supply. The distance from the IC pin to the high frequency capacitor must be kept as short as possible. Similarly, the VSSA path is from the IC pin to the high frequency capacitor, then to the low frequency capacitor, keeping the distance from the IC pin to the high frequency cap as short as possible. CAUTION Note that the VSSA pin specifically does not have a connection to the circuit board ground. The LH79520 PLL circuit has an internal DC ground connection to VSS (GND), so the external VSSA pin must NOT be connected to the circuit board ground, but only to the filter components. OTHER CIRCUIT BOARD LAYOUT PRACTICES All output pins on the LH79520 have fast rise and fall times. Printed circuit trace interconnection length must therefore be reduced to minimize overshoot, undershoot and reflections caused by transmission line effects of these fast output switching times. This recommendation particularly applies to the address and data buses. When considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. Capacitance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. Attention to power supply decoupling and printed circuit board layout becomes more critical in systems with higher capacitive loads. As these capacitive loads increase, transient currents in the power supply and ground return paths also increase. Add pull-up resistors to all unused inputs unless an internal pull-down resistor has been specified; see Table 2. Consider all signals that are Inputs at Reset time. VDDC (SOURCE) VDDC LH79520 100 PIN 91 VDDA + 22 F 0.1 F PIN 92 VSSA 79520-64 Figure 22. VDDA, VSSA Filter Circuit Preliminary Data Sheet 8/21/02 35 LH79520 System-on-Chip PACKAGE SPECIFICATIONS 176LQFP (JEDEC MS-026) 22.0 (TYP.) 20.0 (TYP.) 0.10 1.00 REF. 1.00 REF. 20.0 (TYP.) 22.0 (TYP.) 0.08 1.40 NOM. DETAIL 0.40 (TYP.) 0.23 0.13 NOTES: 1. Dimensions in mm. 2. Refer to JEDEC MS-026 for tolerances. 0.15 0.05 176LQFP-JEDEC Figure 23. 176-pin LQFP 36 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 21.25 0.4 1.67 0.25 17.2 NOTE: Dimensions in mm. 79520-155 Figure 24. Recommended PCB Footprint Preliminary Data Sheet 8/21/02 19.58 22.92 17.2 37 LH79520 System-on-Chip CONTENT REVISIONS This document contains the following changes to content, causing it to differ from previous versions. Table 9. Record of Revisions DATE PAGE NO. 1 PARAGRAPH OR ILLUSTRATION Features DC Specifications (Commercial) Table 6 Table 8 Figure 20 SUMMARY OF CHANGES UART Data Rate changed to `Supports Data Rates up to 460.8 kb/s. Synchronous Serial Port line added: Supports Data Rates up to 1.8452 Mb/s. Line added: 5 V Tolerant Inputs. VIH (MAX.) now 5.5 V Under `Synchronous Memory Interface Signals': D[31:0] Input parameter tISD changed to 5 ns. Parameter tOSC expanded to include both the 14 MHz and the 32 kHz oscillators, with the requisite (MAX.) timings. Added a Shottky diode for fast risetime, plus an improved filter circuit on VDDA. 22 8-16-2002 24 31 34 38 8/21/02 Preliminary Data Sheet System-on-Chip LH79520 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com TAIWAN SINGAPORE KOREA SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328 SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855 SHARP Electronic Components (Korea) Corporation RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819 CHINA HONG KONG SHARP Microelectronics of China (Shanghai) Co., Ltd. 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp SHARP-ROXY (Hong Kong) Ltd. 3rd Business Division, 17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower C, Electronics Science & Technology Building Shen Nan Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735 (c)2001 by SHARP Corporation Reference Code SMA00067 |
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