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0.5 Amp Output Current IGBT Gate Drive Optocoupler Technical Data
HCPL-3150 (Single Channel) HCPL-315J (Dual Channel) Features
* 0.5 A Minimum Peak Output Current * 15 kV/s Minimum Common Mode Rejection (CMR) at VCM = 1500 V * 1.0 V Maximum Low Level Output Voltage (VOL) Eliminates Need for Negative Gate Drive * ICC = 5 mA Maximum Supply Current * Under Voltage Lock-Out Protection (UVLO) with Hysteresis * Wide Operating VCC Range: 15 to 30 Volts * 0.5 s Maximum Propagation Delay * +/- 0.35 s Maximum Delay Between Devices/Channels * Industrial Temperature Range: -40C to 100C * HCPL-315J: Channel One to Channel Two Output Isolation = 1500 Vrms/1 min. * Safety and Regulatory Approval: UL Recognized (UL1577) 2500 Vrms/1 min. (HCPL3150) 3750 Vrms/1 min. (HCPL-315J) pending VDE 0884 Approved VIORM = 630 Vpeak (HCPL-3150 Option 060 only) VIORM = 891 Vpeak (HCPL315J) pending CSA Certified
Description
The HCPL-315X consists of a LED optically coupled to an integrated circuit with a power output stage. This optocoupler is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to 1200 V/50 A. For IGBTs with higher ratings, the HCPL-3150/315J can be used to drive a discrete power stage which drives the IGBT gate.
N/C 1 2 3
SHIELD
Applications
* Isolated IGBT/MOSFET Gate Drive * AC and Brushless DC Motor Drives * Industrial Inverters * Switch Mode Power Supplies (SMPS) * Uninterruptable Power Supplies (UPS)
Functional Diagram
N/C 1 8 VCC VO VO VEE
16 VCC 15 VO 14 VEE
ANODE CATHODE
ANODE CATHODE N/C
2 3 4
7 6 5
ANODE CATHODE N/C
6 7 8
SHIELD
11 VCC 10 VO 9 VEE
SHIELD HCPL-3150
HCPL-315J
TRUTH TABLE VCC - VEE "Positive Going" (i.e., Turn-On) 0 - 30 V 0 - 11 V 11 - 13.5 V 13.5 - 30 V VCC - VEE "Negative-Going" (i.e., Turn-Off) 0 - 30 V 0 - 9.5 V 9.5 - 12 V 12 - 30 V
LED OFF ON ON ON
VO LOW LOW TRANSITION HIGH
A 0.1 F bypass capacitor must be connected between the VCC and VEE pins for each channel.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
2
Selection Guide: Invertor Gate Drive Optoisolators
Package Type Part Number Number of Channels VDE 0884 Approvals UL Approval Output Peak Current CMR (minimum) UVLO Fault Status HCPL-3150 1 8-Pin DIP (300 mil) HCPL-3120 HCPL-J312 1 1 HCPL-J314 1 Widebody (400 mil) HCNW-3120 1 VIORM 1414 Vpeak 5000 Vrms/1min. 2A Small Outline SO-16 HCPL-315J HCPL-316J HCPL-314J 2 1 2 VIORM 891 Vpeak 3750 Vrms/1 min. 2A
VIORM 630 Vpeak Option 060 2500 Vrms/1 min. 0.5A 2A 15 kV/s Yes
VIORM 891Vpeak 3750 Vrms/1 min. 2A 0.4A 10 kV/s No No
0.5A 15 kV/s Yes
0.4A 10 kV/s No No
Yes
Ordering Information
Specify Part Number followed by Option Number (if desired) Example HCPL-315Y#XXX No Option = Standard DIP package, 50 per tube. 060 = VDE 0884 VIORM = 630 Vpeak Option, 50 per tube. (HCPL-3150 only) 300 = Gull Wing Surface Mount Option, 50 per tube. (HCPL-3150 only) 500 = Tape and Reel Packaging Option. HCPL-3150; 1000 per reel. HCPL-315J; 850 per reel.. = Single Channel, 8-pin PDIP. J = Dual Channel, SO16.
Option data sheets available. Contact Agilent sales representative or authorized distributor.
Package Outline Drawings
Standard DIP Package
8 9.40 (0.370) 9.90 (0.390) 7 6 5
OPTION CODE* DATE CODE 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310)
0.20 (0.008) 0.33 (0.013)
A 3150 Z YYWW PIN ONE 1.19 (0.047) MAX. 1 2 3 4
5 TYP.
1.78 (0.070) MAX.
4.70 (0.185) MAX. PIN ONE 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1 PIN DIAGRAM VDD1 VDD2 8
DIMENSIONS 2 MILLIMETERS AND (INCHES). IN VIN+ VOUT+ 7 0.76 (0.030) 1.40 (0.055) 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) * MARKING CODE IN- VOUT- OPTION NUMBERS. 3 V LETTER FOR 6 "V" = OPTION 060. 4 GND1 GND2 NOT MARKED. OPTION NUMBERS 300 AND 5005
3
Package Outline Drawings
Gull-Wing Surface-Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
OPTION CODE*
1.016 (0.040) 1.194 (0.047)
A 3150 Z YYWW
4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)
MOLDED
1
2
3
4
1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.381 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
0.20 (0.008) 0.33 (0.013)
1.080 0.320 (0.043 0.013) 2.540 (0.100) BSC
0.635 0.130 (0.025 0.005)
0.635 0.25 (0.025 0.010) 12 NOM.
DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004)
*MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060. OPTION NUMBERS 300 AND 500 NOT MARKED.
16 - Lead Surface Mount
16 15 14
11 10
9
GND1
VCC1
VO1
10.36 0.20 (0.408 0.008)
GND2
(0.295 0.004) 7.49 0.10
HCPL-315J
VIN1
VIN2
NC
VCC2
VO2 V2
7
1
2
3
6
NC
8 (0.004 - 0.011) 0.10 - 0.30 STANDOFF
V1
(0.345 0.008) 8.76 0.20
VIEW FROM PIN 16 0 - 8 9 (0.025 MIN.) 0.64 (0.138 0.005) 3.51 0.13 (0.408 0.008) 10.36 0.20 (0.0091 - 0.0125) 0.23 - 0.32
VIEW FROM PIN 1
ALL LEADS TO BE COPLANAR (0.002 INCHES) 0.05 mm. (0.018) (0.050) 0.457 1.27 (0.406 0.007) 10.31 0.18 DIMENSIONS IN (INCHES) AND MILLIMETERS.
4
Reflow Temperature Profile
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 T = 145C, 1C/SEC T = 115C, 0.3C/SEC
Regulatory Information
The HCPL-3150 and HCPL-315J have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. VDE Approved under VDE 0884/06.92 with VIORM = 630 Vpeak (HCPL-3150#060). Certification for HCPL-315J is pending.
TEMPERATURE - C
T = 100C, 1.5C/SEC
1
2
3
4
5
6
7
8
9
10
11
12
TIME - MINUTES MAXIMUM SOLDER REFLOW THERMAL PROFILE (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
VDE 0884 Insulation Characteristics
Description Symbol HCPL-3150#060 Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 Vrms for rated mains voltage 300 Vrms I-IV for rated mains voltage 600 Vrms I-III Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage VIORM 630 Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1181 Partial discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, VPR 945 Partial discharge < 5 pC Highest Allowable Overvoltage* VIOTM 6000 (Transient Overvoltage tini = 10 sec) Safety-Limiting Values - Maximum Values Allowed in the Event of a Failure, Also See Figure 37, Thermal Derating Curve. Case Temperature TS 175 Input Current IS, INPUT 230 Output Power PS, OUTPUT 600 Insulation Resistance at TS, VIO = 500 V RS 109 HCPL-315J** Unit
I-IV I-III I-II 55/100/21 2 891
Vpeak
1670
Vpeak
1336 6000
Vpeak Vpeak
175 400 1200 109
C mA mW
**Approval Pending. *Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section, (VDE 0884) for a detailed description of Method a and Method b partial discharge test profiles. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
5
Insulation and Safety Related Specifications
Parameter Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(101) HCPL-3150 7.1 HCPL-315J 8.3 Units mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output erminals, shortest distance path along body. Through insulation distance conductor to conductor. DIN IEC 112/VDE 0303 Part 1
L(102)
7.4
8.3
mm
0.08
0.5 175
mm
CTI
175
Volts
IIIa
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.
Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current (<1 s pulse width, 300 pps) Reverse Input Voltage "High" Peak Output Current "Low" Peak Output Current Supply Voltage Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Symbol TS TA IF(AVG) IF(TRAN) Min. -55 -40 Max. 125 100 25 1.0 Units C C mA A Note
1, 16
VR 5 Volts IOH(PEAK) 0.6 A 2, 16 IOL(PEAK) 0.6 A 2, 16 (VCC - VEE) 0 35 Volts VO(PEAK) 0 VCC Volts PO 250 mW 3, 16 PT 295 mW 4, 16 260C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings Section
Recommended Operating Conditions
Parameter Power Supply Voltage Input Current (ON) Input Voltage (OFF) Operating Temperature Symbol (VCC - VEE) IF(ON) VF(OFF) TA Min. 15 7 -3.0 -40 Max. 30 16 0.8 100 Units Volts mA V C
6
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40 to 100C, I F(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V, VEE = Ground, each channel) unless otherwise specified.
Parameter High Level Symbol IOH IOL VOH VOL ICCH ICCL IFLH VFHL VF VF/TA 0.8 1.2 1.5 1.6 Temperature Coefficient of Forward Voltage Input Reverse Breakdown Voltage Input Capacitance UVLO Threshold UVLO Hysteresis -1.6 1.8 1.95 Min. 0.1 0.5 0.1 0.5 (VCC - 4) (VCC - 3) 0.4 2.5 2.7 2.2 2.6 1.0 5.0 5.0 5.0 6.4 V V HCPL-3150 HCPL-315J mV/C IF = 10 mA IF = 10 mA 16 V V mA mA mA 0.6 A Typ.* 0.4 Max. Units A Test Conditions VO = (VCC - 4 V) VO = (VCC - 15 V) VO = (VEE + 2.5 V) VO = (V EE + 15 V) IO = -100 mA IO = 100 mA Output Open, IF = 7 to 16 mA Output Open, VF = -3.0 to +0.8 V HCPL-3150 HCPL-315J IO = 0 mA, VO > 5 V 9, 15, 21 Fig. 2, 3, 17 5, 6, 18 1, 3, 19 4, 6, 20 7, 8 16 Note 5 2 5 2 6, 7
Output Current
Low Level
Output Current
High Level Output Voltage Low Level Output Voltage High Level Supply Current Low Level Supply Current Threshold Input Current Low to High Threshold Input Voltage High to Low Input Forward Voltage
BVR CIN VUVLO+ VUVLOUVLOHYS
5 3 70 11.0 9.5 12.3 10.7 1.6 13.5 12.0
V pF V V
HCPL-3150 HCPL-315J VO > 5 V, IF = 10 mA
IR = 10 A IR = 10 A 22, 36
f = 1 MHz, VF = 0 V
*All typical values at TA = 25C and VCC - V EE = 30 V, unless otherwise noted.
7
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V, VEE = Ground, each channel) unless otherwise specified. Parameter Propagation Delay Time to High Output Level Symbol tPLH Min. 0.10 Typ.* 0.30 Max. 0.50 Units s Test Conditions Rg = 47 , Cg = 3 nF, f = 10 kHz, Duty Cycle = 50% Fig. 10, 11, 12, 13, 14, 23 Note 14
Propagation Delay tPHL 0.10 Time to Low Output Level Pulse Width PWD Distortion Propagation Delay PDD -0.35 Difference Between (tPHL - tPLH ) Any Two Parts or Channels Rise Time tr Fall Time tf UVLO Turn On tUVLO ON Delay UVLO Turn Off tUVLO OFF Delay Output High Level |CM H| 15 Common Mode Transient Immunity Output Low Level |CML| 15 Common Mode Transient Immunity
0.3
0.50
s s s 34,35
0.3 0.35
15 10
0.1 0.1 0.8 0.6 30
s s s s kV/s
23 VO > 5 V, IF = 10 mA VO < 5 V, IF = 10 mA TA = 25C, IF = 10 to 16 mA, VCM = 1500 V, VCC = 30 V TA = 25C, VCM = 1500 V, VF = 0 V, VCC = 30 V 22
24
11, 12
30
kV/s
11, 13
8
Package Characteristics (each channel, unless otherwise specified)
Parameter Symbol Input-Output VISO Momentary Withstand Voltage** Output-Output VO-O Momentary Withstand Voltage** Resistance RI-O (Input - Output) Capacitance CI-O (Input - Output) LED-to-Case Thermal Resistance LED-to-Detector Thermal Resistance Detector-to-Case Thermal Resistance LC LD DC Device HCPL-3150 HCPL-315J HCPL-315J Min. 2500 3750 1500 Typ.* Max. Units Vrms Test Conditions RH < 50%, t = 1 min., TA = 25C RH < 50% t = 1 min., TA = 25C VI-O = 500 VDC f = 1 MHz Thermocouple located at center underside of package 28 18 Fig. Note 8, 9
Vrms
17
1012 HCPL-3150 HCPL-315J HCPL-3150 HCPL-3150 HCPL-3150 0.6 1.3 391 439 119
pF C/W C/W C/W
9
*All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted. **The Input-Output/Output-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an inputoutput/output-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes: 1. Derate linearly above 70C free-air temperature at a rate of 0.3 mA/C. 2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 0.5 A. See Applications section for additional details on limiting IOH peak. 3. Derate linearly above 70C free-air temperature at a rate of 4.8 mW/C. 4. Derate linearly above 70C free-air temperature at a rate of 5.4 mW/C. The maximum LED junction temperature should not exceed 125C. 5. Maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL1577, each HCPL-3150 optocoupler is proof tested by applying an insulation test voltage 3000 Vrms ( 5000 Vrms for the HCPL-315J) for 1 second (leakage detection current limit, I I-O 5 A). This test is performed before the 100% production test for partial discharge (method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. The difference between tPHL and tPLH between any two parts or channels under the same test condition. 11. Pins 1 and 4 (HCPL-3150) and pins 3 and 4 (HCPL-315J) need to be connected to LED common. 12. Common mode transient immunity in the high state is the maximum tolerable |dVCM /dt| of the common
13.
14. 15.
16. 17.
18.
mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15.0 V). Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). This load condition approximates the gate load of a 1200 V/25 A IGBT. Pulse Width Distortion (PWD) is defined as |tPHL-t PLH| for any given device. Each channel. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted together. See the thermal model for the HCPL-315J in the application section of this data sheet.
9
(VOH - VCC ) - HIGH OUTPUT VOLTAGE DROP - V
0 IOH - OUTPUT HIGH CURRENT - A IF = 7 to 16 mA IOUT = -100 mA VCC = 15 to 30 V VEE = 0 V
(VOH - VCC ) - OUTPUT HIGH VOLTAGE DROP - V
0.50 IF = 7 to 16 mA VOUT = VCC - 4 V VCC = 15 to 30 V VEE = 0 V
-1 100 C 25 C -40 C
-1
0.45
-2
0.40
-3
-2
0.35
-4 IF = 7 to 16 mA VCC = 15 to 30 V VEE = 0 V 0 0.2 0.4 0.6 0.8 1.0
-3
0.30 0.25 -40 -20
-5 -6
-4 -40 -20
0
20
40
60
80
100
0
20
40
60
80
100
TA - TEMPERATURE - C
TA - TEMPERATURE - C
IOH - OUTPUT HIGH CURRENT - A
Figure 1. VOH vs. Temperature.
Figure 2. IOH vs. Temperature.
Figure 3. VOH vs. I OH.
1.0
VOL - OUTPUT LOW VOLTAGE - V
1.0
IOL - OUTPUT LOW CURRENT - A
5
VOL - OUTPUT LOW VOLTAGE - V
0.8
VF(OFF) = -3.0 to 0.8 V IOUT = 100 mA VCC = 15 to 30 V VEE = 0 V
0.8
VF(OFF) = -3.0 to 0.8 V VCC = 15 to 30 V 4 VEE = 0 V 3
0.6
0.6
0.4
0.4 VF(OFF) = -3.0 to 0.8 V VOUT = 2.5 V VCC = 15 to 30 V VEE = 0 V 0 20 40 60 80 100
2
0.2 0 -40 -20
0.2
1 0
0
20
40
60
80
100
0 -40 -20
100 C 25 C -40 C 0 0.2 0.4 0.6 0.8 1.0 IOL - OUTPUT LOW CURRENT - A
TA - TEMPERATURE - C
TA - TEMPERATURE - C
Figure 4. VOL vs. Temperature.
Figure 5. IOL vs. Temperature.
Figure 6. VOL vs. I OL.
3.5
ICC - SUPPLY CURRENT - mA
3.5
IFLH - LOW TO HIGH CURRENT THRESHOLD - mA
5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN
ICC - SUPPLY CURRENT - mA
ICCH ICCL 3.0
ICCH ICCL 3.0
4
3
2.5
2.5
2
2.0
VCC = 30 V VEE = 0 V IF = 10 mA for ICCH IF = 0 mA for ICCL 0 20 40 60 80 100
2.0
IF = 10 mA for ICCH IF = 0 mA for ICCL TA = 25 C VEE = 0 V 15 20 25 30
1
1.5 -40 -20
1.5
0 -40 -20
0
20
40
60
80
100
TA - TEMPERATURE - C
VCC - SUPPLY VOLTAGE - V
TA - TEMPERATURE - C
Figure 7. ICC vs. Temperature.
Figure 8. ICC vs. VCC.
Figure 9. IFLH vs. Temperature.
10
500
Tp - PROPAGATION DELAY - ns Tp - PROPAGATION DELAY - ns
500
Tp - PROPAGATION DELAY - ns
500
400
IF = 10 mA TA = 25 C Rg = 47 Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz
TPLH TPHL
400
VCC = 30 V, VEE = 0 V Rg = 47 , Cg = 3 nF TA = 25 C DUTY CYCLE = 50% f = 10 kHz
400
IF(ON) = 10 mA IF(OFF) = 0 mA VCC = 30 V, VEE = 0 V Rg = 47 , Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz
300
300
300
200
200 TPLH TPHL 100 6 8 10 12 14 16
200 TPLH TPHL 100 -40 -20 0 20 40 60 80 100
100
15
20
25
30
VCC - SUPPLY VOLTAGE - V
IF - FORWARD LED CURRENT - mA
TA - TEMPERATURE - C
Figure 10. Propagation Delay vs. VCC.
Figure 11. Propagation Delay vs. IF.
Figure 12. Propagation Delay vs. Temperature.
500
Tp - PROPAGATION DELAY - ns Tp - PROPAGATION DELAY - ns
500
30
VO - OUTPUT VOLTAGE - V
100
400
VCC = 30 V, VEE = 0 V TA = 25 C IF = 10 mA Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz
400
VCC = 30 V, VEE = 0 V TA = 25 C IF = 10 mA Rg = 47 DUTY CYCLE = 50% f = 10 kHz
25 20 15 10 5 0
300
300
200 TPLH TPHL 100 0 50 100 150 200
200 TPLH TPHL 100 0 20 40 60 80
0
1
2
3
4
5
Rg - SERIES LOAD RESISTANCE -
Cg - LOAD CAPACITANCE - nF
IF - FORWARD LED CURRENT - mA
Figure 13. Propagation Delay vs. Rg.
Figure 14. Propagation Delay vs. Cg.
Figure 15. Transfer Characteristics.
1000
IF - FORWARD CURRENT - mA
TA = 25C IF VF - +
100 10 1.0 0.1 0.01
0.001 1.10
1.20
1.30
1.40
1.50
1.60
VF - FORWARD VOLTAGE - V
Figure 16. Input Current vs. Forward Voltage.
11
1
8 0.1 F
1 + -
8 0.1 F IOL + VCC = 15 - to 30 V 2.5 V + -
2 IF = 7 to 16 mA 3
7
4V + VCC = 15 - to 30 V
2
7
6 IOH
3
6
4
5
4
5
Figure 17. I OH Test Circuit.
Figure 18. I OL Test Circuit.
1
8 0.1 F VOH + VCC = 15 - to 30 V
1
8 0.1 F 100 mA + VCC = 15 - to 30 V
2 IF = 7 to 16 mA 3
7
2
7
6 100 mA
3
6
VOL
4
5
4
5
Figure 19. VOH Test Circuit.
Figure 20. VOL Test Circuit.
1
8 0.1 F
1
8 0.1 F
2 IF 3
7 VO > 5 V 6 + VCC = 15 - to 30 V IF = 10 mA
2
7 VO > 5 V + - VCC
3
6
4
5
4
5
Figure 21. I FLH Test Circuit.
Figure 22. UVLO Test Circuit.
12
1 IF = 7 to 16 mA + 10 KHz -
50% DUTY CYCLE
8 0.1 F VCC = 15 to 30 V IF tr tf 90% 50% VOUT 10% tPLH tPHL
500
2
7 VO
+ -
3
6
47 3 nF
4
5
Figure 23. tPLH, t PHL, t r, and tf Test Circuit and Waveforms.
VCM 1 IF A B 5V + - 3 6 2 7 VO + - VCC = 30 V VO SWITCH AT A: IF = 10 mA VO SWITCH AT B: IF = 0 mA + VCM = 1500 V
-
8 0.1 F 0V t
V t
=
VCM t
VOH
4
5
VOL
Figure 24. CMR Test Circuit and Waveforms.
Applications Information
Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-3150/315J has a very low maximum VOL specification of 1.0 V. The HCPL-3150/315J realizes this very low VOL by using a DMOS transistor with 4 (typical) on resistance in its pull down circuit. When the HCPL-3150/315J is in the low state, the IGBT gate is shorted to
the emitter by Rg + 4 . Minimizing Rg and the lead inductance from the HCPL-3150/ 315J to the IGBT gate and emitter (possibly by mounting the HCPL-3150/315J on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or
emitter traces close to the HCPL3150/315J input as this can result in unwanted coupling of transient signals into the HCPL-3150/315J and degrade performance. (If the IGBT drain must be routed near the HCPL-3150/315J input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3150/315J.)
+5 V 1 270 2
HCPL-3150 8 0.1 F 7 Rg Q1 3 6 + - VCC = 18 V
+ HVDC
CONTROL INPUT 74XXX OPEN COLLECTOR
3-PHASE AC
4
5 Q2
- HVDC
Figure 25a. Recommended LED Drive and Application Circuit.
13
+5 V CONTROL INPUT 74XX OPEN COLLECTOR 270 1
HCPL-315J 16 0.1 F 2 15 + -
FLOATING SUPPLY VCC = 18 V
+ HVDC
Rg 3 GND 1 14
3-PHASE AC
6 11 0.1 F 7 10 Rg + - VCC = 18 V
+5 V 270 CONTROL INPUT 74XX OPEN COLLECTOR GND 1
8
9
- HVDC
Figure 25b. Recommended LED Drive and Application Circuit (HCPL-315J).
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. Step 1: Calculate Rg Minimum From the I OL Peak Specification. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3150/315J. (VCC - VEE - VOL) Rg --------------- I OLPEAK (VCC - VEE - 1.7 V) = ---------------- I OLPEAK (15 V + 5 V - 1.7 V) = ------------------ 0.6 A = 30.5
The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 0.6 A (see Figure 6). At lower Rg values the voltage supplied by the HCPL-3150/315J is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used VEE in the previous equation is equal to zero volts. Step 2: Check the HCPL-3150/ 315J Power Dissipation and Increase Rg if Necessary. The HCPL-3150/315J total power dissipation (PT) is equal to the
sum of the emitter power (PE ) and the output power (PO): PT = PE + PO PE = IF * VF * Duty Cycle PO = PO(BIAS) + PO (SWITCHING) = ICC* (VCC - VEE) + ESW(R G, QG) * f
For the circuit in Figure 26 with IF (worst case) = 16 mA, Rg = 30.5 , Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and TA max = 90C: PE = 16 mA * 1.8 V * 0.8 = 23 mW PO = 4.25 mA * 20 V + 4.0 J* 20 kHz = 85 mW + 80 mW = 165 mW > 154 mW (PO(MAX) @ 90C = 250 mW-20C* 4.8 mW/C)
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+5 V 1 270 2
HCPL-3150 8 0.1 F 7 Rg Q1 3 6 - + 4 5 Q2 VEE = -5 V + - VCC = 15 V
+ HVDC
CONTROL INPUT 74XXX OPEN COLLECTOR
3-PHASE AC
- HVDC
Figure 26a. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.
+5 V 1 CONTROL INPUT 74XX OPEN COLLECTOR 270 2
HCPL-315J 16 0.1 F 15 + -
FLOATING SUPPLY VCC = 15 V
+ HVDC
Rg 3 GND 1 14 - + VEE = -5 V
3-PHASE AC
+5 V 270 CONTROL INPUT 74XX OPEN COLLECTOR GND 1
6
11 0.1 F + -
VCC = 15 V
7
10 Rg
8
9
- + VCC = -5 V
- HVDC
Figure 26b. HCPL-315J Typical Application Circuit with Negative IGBT Gate Drive.
PE Parameter IF VF Duty Cycle
Description LED Current LED On Voltage Maximum LED Duty Cycle
PO Parameter ICC VCC VEE ESW(Rg,Qg) f
Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated in the HCPL-3150/315J for each IGBT Switching Cycle (See Figure 27) Switching Frequency
15
The value of 4.25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at -40C) to ICC max at 90C (see Figure 7). Since PO for this case is greater than PO(MAX), Rg must be increased to reduce the HCPL3150 power dissipation. PO(SWITCHING MAX) = PO(MAX) - PO(BIAS) = 154 mW - 85 mW = 69 mW PO(SWITCHINGMAX) ESW(MAX) = --------------- f 69 mW = ------- = 3.45 J 20 kHz For Qg = 500 nC, from Figure 27, a value of ESW = 3.45 J gives a Rg = 41 .
board design and is, therefore, determined by the designer. The value of CA = 83C/W was obtained from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a single HCPL3150 soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a CAvalue of 83C/W. From the thermal mode in Figure 28a the LED and detector IC junction temperatures can be expressed as:
For example, given PE = 45 mW, PO = 250 mW, TA = 70C and CA = 83C/W:
TJE = PE* 313C/W + PD* 132C/W + TA = 45 mW* 313C/W + 250 mW * 132C/W + 70C = 117C TJD = PE* 132C/W + PD* 187C/W + TA = 45 mW* 132C/W + 250 mW * 187C/W + 70C = 123C
TJE and TJD should be limited to 125C based on the board layout and part placement (CA) specific to the application.
TJE = PE * (LC||(LD + DC) + CA) LC * DC + PD * + CA + TA LC + DC + LD
(----------------
LC
*
)
TJD = PE
(--------------- + ) + +
DC LC DC LD CA
Thermal Model (HCPL-3150)
The steady state thermal model for the HCPL-3150 is shown in Figure 28a. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through CA which raises the case temperature TC accordingly. The value of CA depends on the conditions of the
+ PD* (DC||(LD + LC) + CA) + TA Inserting the values for LC and DC shown in Figure 28 gives: TJE = PE * (230C/W + CA) + PD * (49C/W + CA) + TA TJD = PE * (49C/W + CA) + PD * (104C/W + CA) + TA
LD = 439C/W TJE LC = 391C/W TC CA = 83C/W* TJD DC = 119C/W
TA
TJE = LED junction temperature T JD = detector IC junction temperature T C = case temperature measured at the center of the package bottom LC = LED-to-case thermal resistance LD = LED-to-detector thermal resistance DC = detector-to-case thermal resistance CA = case-to-ambient thermal resistance CA will depend on the board design and the placement of the part.
Figure 28a. Thermal Model.
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Thermal Model DualChannel (SOIC-16) HCPL-315J Optoisolator
Definitions 1 , 2, 3, 4, 5, 6, 7, 8, 9, 10 : Thermal impedances between nodes as shown in Figure 28b. Ambient Temperature: Measured approximately 1.25 cm above the optocoupler with no forced air. Description This thermal model assumes that a 16-pin dual-channel (SOIC-16) optocoupler is soldered into an 8.5 cm x 8.1 cm printed circuit board (PCB). These optocouplers are hybrid devices with four die: two LEDs and two detectors. The temperature at the LED and the detector of the optocoupler can be calculated by using the equations below.
LED 1 2
1 3
LED 2
4
5
DETECTOR 1 7 8 10
DETECTOR 2 6
9
AMBIENT
Figure 28b. Thermal Impedance Model for HCPL-315J.
TE1A = A11PE1 + A12PE2+A13 PD1+A 14PD2 TE2A = A21PE1 + A22PE2+A23 PD1+A 24PD2 TD1A = A31PE1 + A32PE2+A33P D1+A 34PD2 TD2A = A41PE1 + A42PE2+A43P D1+A 44PD2 where:
PE1
PD1
PE2
PD2
TE1A = Temperature difference between ambient and LED 1 TE2A = Temperature difference between ambient and LED 2 TD1A = Temperature difference between ambient and detector 1 TD2A = Temperature difference between ambient and detector 2 PE1 = Power dissipation from LED 1; PE2 = Power dissipation from LED 2; PD1 = Power dissipation from detector 1; PD2 = Power dissipation from detector 2 Axy thermal coefficient (units in C/W) is a function of thermal impedances 1 through 10.
Thermal Coefficient Data (units in C/W)
Part Number HCPL-315J A 11, A22 198 A 12, A21 64 A 13, A31 62 A 24, A42 64 A 14, A41 83 A 23, A32 90 A 33, A44 137 A 34, A43 69
Note: Maximum junction temperature for above part: 125C.
17
Esw - ENERGY PER SWITCHING CYCLE - J
LED Drive Circuit Considerations for Ultra High CMR Performance
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The HCPL3150/315J improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. How ever, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 30. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 15 kV/s CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections.
7 Qg = 100 nC 6 5 4 3 2 1 0 0 20 40 60 80 100 Qg = 250 nC Qg = 500 nC VCC = 19 V VEE = -9 V
logic gate is less than VF(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which, like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state.
Rg - GATE RESISTANCE -
Figure 27. Energy Dissipated in the HCPL-3150 for Each IGBT Switching Cycle.
CMR with the LED On (CMRH)
A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum I FLH of 5 mA to achieve 15 kV/s CMR.
Under Voltage Lockout Feature
The HCPL-3150/315J contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3150/315J supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3150/315J output is in the high state and the supply voltage drops below the HCPL-3150/315J VUVLO- threshold (9.5 CMR with the LED Off (CMRL)
A high CMR LED drive circuit must keep the LED off (VF VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 31, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the
18
high state (assuming LED is "ON") with a typical delay, UVLO TURN On Delay, of 0.8 s.
IPM Dead Time and Propagation Delay Specifications
The HCPL-3150/315J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices from the highto the low-voltage motor rails.
To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 34. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 350 ns over the operating temperature range of -40C to 100C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 35. The maximum dead time for the HCPL-3150/315J is 700 ns (= 350 ns - (-350 ns)) over an operating temperature range of -40C to 100C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs.
1
CLEDP
8
1
CLEDO1 CLEDP
8
2
7
2
CLEDO2
7
3
CLEDN
6
3
CLEDN
6
4
5
4
SHIELD
5
Figure 29. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers.
Figure 30. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers.
+5 V
1
CLEDP
8 0.1 F 7
ILEDP
+ VSAT -
2
+ -
VCC = 18 V
3
CLEDN
6 Rg 5
***
4
SHIELD
***
* THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING -dVCM/dt.
+- VCM
Figure 31. Equivalent Circuit for Figure 25 During Common Mode Transient.
19
1 +5 V
CLEDP
8
1 +5 V
CLEDP
8
2
7
2
7
3 Q1 4
CLEDN ILEDN
6
3
CLEDN
6
SHIELD
5
4
SHIELD
5
Figure 32. Not Recommended Open Collector Drive Circuit.
Figure 33. Recommended LED Drive Circuit for Ultra-High CMR.
ILED1
ILED1
VOUT1
Q1 ON Q1 OFF Q2 ON
VOUT1
Q1 ON Q1 OFF Q2 ON
VOUT2 ILED2
Q2 OFF
VOUT2
Q2 OFF
tPHL MAX tPLH MIN PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
ILED2 tPHL MIN tPHL MAX tPLH
MIN
*PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
tPLH MAX (tPHL-tPLH) MAX = PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) - (tPHL MIN - tPLH MAX) = PDD* MAX - PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 34. Minimum LED Skew for Zero Dead Time.
Figure 35. Waveforms for Dead Time.
OUTPUT POWER - PS, INPUT CURRENT - IS
14
VO - OUTPUT VOLTAGE - V
800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 PS (mW) IS (mA)
12 10 8 6 4 2 0 (10.7, 0.1) 0 5 10 (12.3, 0.1) 15 20 (12.3, 10.8) (10.7, 9.2)
(VCC - VEE ) - SUPPLY VOLTAGE - V
TS - CASE TEMPERATURE - C
Figure 36. Under Voltage Lock Out.
Figure 37a. HCPL-3150: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884.
1400 PSI OUTPUT 1200
PSI - POWER - mW
PSI INPUT
1000 800 600 400 200 0 0 25 50 75 100 125 150 175 200
TS - CASE TEMPERATURE - C
Figure 37b. HCPL-315J: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884.
www.semiconductor.agilent.com Data subject to change. Copyright (c) 1999 Agilent Technologies Obsoletes 5965-4780E 5966-2495E (11/99)

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