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TDA7429S TDA7429T
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
3 STEREO/4 STEREO INPUTS INPUT ATTENUATION CONTROL IN 0.5dB STEP TREBLE MIDDLE AND BASS CONTROL THREE SURROUND MODES ARE AVAILABLE: - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES FOUR SPEAKERS ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7429 is volume tone (bass middle and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems. PIN CONNECTION (TQFP44)
SDIP42
TQFP44
ORDERING NUMBERS: TDA7429S TDA7429T
It reproduces surround sound by using programmable phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
R_IN4
R_IN3
R_IN2 35
44 LP1 HP1 HP2. REAROUT REARIN VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI 1 2 3 4 5 6 7 8 9 10 11 12 BASS_RO
43
42
41 40
39
38
37
36
34 33 32 31 30 29 28 27 26 25 24 23 MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 L_IN4 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND
13 BASS_RI
14 MIDDLE_LO
15 16 MIDDLE_RO MIDDLE_LI
17 MIDDLE_RI
18 TREBLE_R
19 TREBLE_L
20 AGND
21 SDA
22 SCL
R_IN1
D96AU532
CREF
PS1
PS2
PS3
PS4
VS
LP
July 1999
1/20
TDA7429S - TDA7429T
PIN CONNECTION (SDIP42)
PS4 PS3 PS2 PS1 LP LP1 HP1 HP2 REAROUT REARIN VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
D97AU623
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VS CREF R_IN3 R_IN2 R_IN1 MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND SCL SDA AGND TREBLE_L TREBLE_R MIDDLE_RI
TEST CIRCUIT (TDA7429S)
2.2F 2.2F 2.2F 0.47F BASSO_R 22nF PS4 22nF 1 14 VAR_R 13 BASSO_L 12 VAR_L 11 REAROUT 9 REARIN 10 R_IN3 40 0.47F R_IN2 39 38 36 2 4.7nF PS2 35 L_IN1 0.47F R_IN1
PS3
MONITOR_L 0.47F
3
100nF
PS1
4
34
L_IN2
0.47F
0.47F 33 L_IN3
1.2nF
LP
5
5.6nF
LP1
6 42
5.6nF TREBLE_R 5.6nF 23
VS 10F 22F 100nF
TREBLE_L 24 41 CREF
100nF MONITOR_R 22nF 37
220nF 100nF
MIDDLE_LO
15 19 16
BASS_LO 100nF
18nF MIDDLE_LI 2.7K 22nF 21 18nF MIDDLE_RO 22 32 31 30 29 R_OUT 28 DIG_GND 27 SCL 26 SDA 25 AGND HP2 8 HP1 680nF 7 20
BASS_LI 100nF
5.6K
17
BASS_RO
100nF 18 BASS_RI 5.6K
MIDDLE_RI 2.7K
AUXOUT_L AUXOUT_R L_OUT
D97AU626
2/20
TDA7429S - TDA7429T
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz Treble Control (2db step) -14 -14 -14 -79 100 Middle Control (2db step) Bass Control (2dB step) Balance Control Mute Attenuation 1dB step (LCH, RCH) Parameter Min. 7 2 0.01 106 90 +14 +14 +14 0 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB
TEST CIRCUIT (TDA7429T)
2.2F
2.2F
2.2F 0.47F 0.47F R-IN3 37 36 0.47F R-IN2 35 34 32 R-IN1 0.47F
BASSO-R 22nF PS4 9 40
VAR-R 8
BASSO-L 7
VAR-L 6
REAROUT 4
REARIN 5
R-IN4
22nF
PS3
41
MONITOR_L L-IN1 0.47F
4.7nF
PS2
42
31
100nF
PS1
43
30
L-IN2
0.47F
1.2nF
LP
44
29
L-IN3
0.47F
5.6nF
LP1
1
28 39
L-IN4 VS
0.47F
5.6nF
TREBLE-R
18
5.6nF
TDA7429
38
10F 22F
100nF
TREBLE-L
19
CREF
100nF MONITOR_R 22nF 33
220nF 100nF 10 BASS-LO 100nF 11 BASS-LI 100nF
MIDDLE-LO
14
18nF MIDDLE-LI 22nF MIDDLE-RO 16 15
2.7K
5.6K
12
BASS-RO
18nF
100nF 17 27 AUXOUT-L 26 AUXOUT-R 25 L-OUT 24 R-OUT 23 DIG-GND 22 SCL 21 SDA 20 AGND HP2 3 HP1 680nF 2 13 BASS-RI
2.7K
MIDDLE-RI
5.6K
D96AU533
3/20
MIDDLE-LI
MONITOR L HP2 43 RPS1 FIX RPS2 RPS3 RPS4 RM RB 30K 42 41 40 19 15 14 11 10 7 6
LP1
HP1
PS1
PS2
PS3
PS4
TREBLE-L
MIDDLE-LO
AGND
CREF
REARIN
REAROUT
MIDDLE-RI
MIDDLE-RO
2.2F 5.6nF
18nF 2.7K
22nF
100nF 5.6K
100nF
THE SWITCHES POSITION MATCHES THE RESET CONDITION
BASS-RO
22F
1.2nF
BASS-RI
4/20
100nF 2.2F 4.7nF 22nF 22nF 5.6nF 2.7K 18nF 100nF 5.6K 22nF 100nF BASS-LI BASS-LO BASSO-L VAR-L 27 OFF R5 R6 + + MOVIE/ MUSIC OFF MOVIE/SIM BASS MIXING AMP TREBLE MIDDLE 3BAND 22 21 I2C BUS DECODER + LATCHES 23 SIM MUSIC MUTE SURR REAR SURR REC ATT VAR 79dB CONTROL 79dB CONTROL + FIX SPKR ATT MUTE PS1 90Hz PS2 4KHz PS3 400Hz PS4 400Hz AUXOUT-L 25 L-OUT + L-R SCL SDA DIG GND LPF 9KHz SURR EFFECT CONTROL MIXING AMP TREBLE MIDDLE BASS FIX FIX VAR 3BAND REAR Vref 50K 44 LP TREBLE-R 4 5 18 17 RM 16 13 SURR RB 12 MUTE 79dB CONTROL BASSO-R 9 8 VAR-R
D96AU513
TDA7429S - TDA7429T
5.6nF
680nF
0.47F
31
32
31.5dB 1 control
2
3
BLOCK DIAGRAM (TDA7429T)
L-IN1
50K
0.47F
30
RLP1 RHP1
L-IN2
50K
0.47F
29
L-IN3
50K
0.47F
28
L-IN4
50K
+
0.47F
34
R-IN1
50K
0.47F
35
R-IN2
50K
0.47F
+ -
SPKR ATT
36 OFF
24
R-OUT MUTE REC ATT 79dB CONTROL
R-IN3
50K
0.47F
37
R-IN4 SUPPLY
26 30K
AUXOUT-R
50K
31.5dB control 20 38
33
39
MONITOR R
VS
2.2F
5.6nF
MIDDLE_LI MIDDLE_LO
680nF 2.2F BASS_LI 16 RB FIX 30K 15 12 11 BASS_LO BASSO_L VAR_L
100nF
4.7nF
22nF
22nF
5.6nF
2.7K 18nF 100nF
5.6K 22nF 100nF
MONITOR_L HP2 8 RPS1 RPS2 RPS3 RPS4 RM 4 3 2 1 24 20 19 PS1 PS2 PS3 PS4 TREBLE_L
LP1
HP1
BLOCK DIAGRAM (TDA7429S)
0.47F
36
35
31.5dB control
6
7
L_IN1
50K 32 OFF R5 R6 + + + I2 C BUS DECODER + LATCHES L-R MOVIE/ MUSIC OFF MOVIE/SIM MIXING AMP TREBLE MIDDLE BASS 3BAND SIM MUTE MUSIC SURR REAR SURR REC ATT VAR 79dB CONTROL 79dB CONTROL + FIX SPKR ATT MUTE
0.47F PS1 90Hz PS2 4KHz PS3 400Hz PS4 400Hz
34
RLP1 RHP1 AUXOUT_L
L_IN2
50K
0.47F
33
L_IN3
50K
30
L_OUT
+
27 26 28
SCL SDA DIG GND
0.47F LPF 9KHz SURR EFFECT CONTROL MIXING AMP TREBLE MIDDLE BASS
38
R_IN1
FIX
FIX VAR 3BAND + -
50K
0.47F
SPKR ATT
39 OFF REAR SURR 50K 5 LP REAROUT 22F 1.2nF 2.2F 5.6nF REARIN TREBLE_R 9 10 23 22 RM 21 18 RB 17 MUTE 79dB CONTROL BASSO_R BASS_RI MIDDLE_RI MIDDLE_RO BASS_RO 2.2F 18nF 2.7K 22nF 100nF 5.6K 100nF 14 13 VAR_R 30K
29
R_OUT MUTE REC ATT 79dB CONTROL 31
R_IN2
50K
0.47F
40 SUPPLY Vref
R_IN3
AUXOUT_R
50K
31.5dB control 25 41
37
42
MONITOR_R AGND CREF
VS
D97AU624A
THE SWITCHES POSITION MATCHES THE RESET CONDITION
TDA7429S - TDA7429T
5/20
TDA7429S - TDA7429T
THERMAL DATA
Symbol R th j-pins Thermal Resistance Junction-pins Description Ma x. Value 85 Unit C/W
ABSOLUTE MAXIMUM RATINGS
Symbol VS T amb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 11 -10 to 85 -55 to +150 Unit V C C
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, Vin = 1Vrms; RG = 600, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection LCH / RCH out, Mode = OFF 7 10 60 9 18 80 10.2 26 V mA dB
INPUT STAGE
R IN V CL C RANGE AVMIN AVMAX ASTEP Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution -1 31 THD = 0.3% 35 2 50 2.5 31.5 0 31.5 0.5 1 32 1 65 K Vrms dB dB dB dB
BASS CONTROL
Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +11.5 1 32 +14.0 2 44 +16.0 3 56 dB dB K
MIDDLE CONTROL
Gm M STEP RM Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +11.5 1 17.5 +14.0 2 25 +16.0 3 32.5 dB dB K
TREBLE CONTROL
Gt TSTEP Control Range Step Resolution Max. Boost/cut +13.0 1 +14.0 2 +15.0 3 dB dB
EFFECT CONTROL
C RANGE SSTEP Control Range Step Resolution - 21 0.5 1 -6 1.5 dB dB
SURROUND SOUND MATRIX PHASE
R PS10 R PS11 R PS12 R PS13 R PS20 6/20 Phase Shifter 1: D1 = 0, D0 = 0 Phase Shifter 1: D1 = 0, D0 = 1 Phase Shifter 1: D1 = 1, D0 = 0 Phase Shifter 1: D1 = 1, D0 = 1 Phase Shifter 2: D3 = 0, D2 = 0 8.3 10 12.6 26.4 4 11.8 14.1 17.9 37.3 5.6 15.2 18.3 23.3 48.85 7.2 K K K K K
TDA7429S - TDA7429T
ELECTRICAL CHARACTERISTICS (continued) SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
Symbol R PS21 R PS22 R PS23 R PS30 R PS31 R PS32 R PS33 R PS40 R PS41 R PS42 R PS43 GOFF Parameter Phase Shifter 2: D3 = 0, D2 = 1 Phase Shifter 2: D3 = 1, D2 = 0 Phase Shifter 2: D3 = 1, D2 = 1 Phase Shifter 3: D5 = 0, D4 = 0 Phase Shifter 3: D5 = 0, D4 = 1 Phase Shifter 3: D5 = 1, D4 = 0 Phase Shifter 3: D5 = 1, D4 = 1 Phase Shifter 4: D7 = 0, D6 = 0 Phase Shifter 4: D7 = 0, D6 = 1 Phase Shifter 4: D7 = 1, D6 = 0 Phase Shifter 4: D7 = 1, D6 = 1 In-phase Gain (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout Lin Lout Mode OFF, Input signal of 1kHz, 1.4 Vp-p R in Rout, Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in Rout, Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout), (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Lou t Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Lou t Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Lou t Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin R out Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin R out Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Rout 7 42 7 Test Condition Min. 4.8 6 12.9 8.5 10.2 12.7 27.4 8.5 10.2 12.7 27.4 -1 Typ. 6.8 8.4 18.3 12.1 14.5 18.1 39.1 12.1 14.5 18.1 39.1 0 Max. 8.7 10.9 23.7 15.6 18.7 23.3 50.75 15.6 18.7 23.3 50.75 1 Unit K K K K K K K K K K K dB
D GOFF
LR In-phase Gain Difference (OFF) In-phase Gain (Movie)
-1
0
1
dB
GMOV
8
dB
DGMOV
LR In-phase Gain Difference (Movie) In-phase Gain (Music)
0
dB
GMUS
7
dB
D GMUS
LR In-phase Gain Difference (Music) Simulated L Output 1
0
dB
LMON1
4.5
dB
LMON2
Simulated L Output 2
-4.0
dB
LMON3
Simulated L Output 3
7.0
dB
R MON1
Simulated R Output 1
- 4.5
dB
R MON2
Simulated R Output 2
3.8
dB
R MON3
Simulated R Output 3
- 20
dB
RLP1 R HPI RLPF
Low Pass Filter Resistance High Pass Filter Resistance LP Pin Impedance
10 60 10
13 78 13
K K K
7/20
TDA7429S - TDA7429T
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SPEAKER & AUX ATTENUATORS
Crange SSTEP EA VDC AMUTE RVEA Control Range Step Resolution Attenuation set error DC Steps Output Mute Condition Input Impedance Av = 0 to -20dB Av = -20 to -79dB adjacent att. steps -0.5 -1.5 -3 -3 +70 21 79 1 0 0 0 100 30 39 1.5 1.5 2 3 dB dB dB dB mV dB K Vrms Vrms Vrms mVrms Vrms 0.1 % dB Vrms 85 V
AUDIO OUTPUTS
NO(OFF) NO(MOV) NO(MUS) N O(MON) d SC VOCL ROUT VOUT Output Noise (OFF) Output Noise (Movie) Output Noise (Music) Output Noise (Simulated) Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Output Mute, Flat BW = 20Hz to 20KHz Mode =Movie , BW = 20Hz to 20KHz Mode = Music , BW = 20Hz to 20KHz, Mode = Simulated, BW = 20Hz to 20KHz Av = 0 ; Vin = 1Vrms 70 2 25 4 5 30 30 30 0.01 90 2.5 50 3.8
MONITOR OUTPUTS
d SC VOCL ROUT VOUT Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Av = 0 ; Vin = 1Vrms 70 2 25 0.01 90 2.5 50 4.5 85 0.1 % dB Vrms V
BUS INPUTS
V IL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V A V
8/20
TDA7429S - TDA7429T
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7429 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
9/20
TDA7429S - TDA7429T
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7429 address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB B
SUBADDRESS LSB DATA ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D95AU226A
ACK = Achnowledge S = Start P = Stop A = Address B = Auto Increment
EXAMPLES No Incremental Bus The TDA7429 receives a start condition, the cor-
rect chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 0 X
SUBADDRESS LSB X X D3 D2 D1 D0 ACK MSB
DATA LSB DATA ACK P
D95AU306
Incremental Bus The TDA7429 receive s a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas
SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored. The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 1 X
SUBADDRESS LSB X X D3 D2 D1 D0 ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D95AU307
10/20
TDA7429S - TDA7429T
DATA BYTES Address = 80(HEX) FUNCTION SELECTION: The first byte (subaddress)
MSB D7 B B B B B B B B B B D6 X X X X X X X X X X D5 X X X X X X X X X X D4 X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 0 1 INPUT ATTENUATION SURROUND & OUT & EFFECT CONTROL PHASE RESISTOR BASS & NATURAL BASE MIDDLE & TREBLE SPEAKER ATTENUATION "L" SPEAKER ATTENUATION "R" AUX ATTENUATION "L" AUX ATTENUATION"R" INPUT MULTIPLEXER, & AUX OUT SUBADDRESS
B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 INPUT ATTENUATION SELECTION
MSB D7 X X X X X X X X X X X X X X X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 INPUT ATTENUATION 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS 0 -4 -8 -12 -16 -20 -24 -28
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
INPUT ATTENUATION = 0 -31.5dB
D7 X X D6 0 1 D5 D4 D3 D2 D1 D0 REAR SWITCH REARIN, REAROUT PIN ACTIVE NO REARIN, REAROUT PIN 11/20
TDA7429S - TDA7429T
SURROUND SELECTION
MSB D7 X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D6 D5 D4 D3 D2 D1 0 0 1 1 LSB D0 0 1 0 1 SURROUND MODE SIMULATED MUSIC OFF MOVIE OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21
0 1
PHASE RESISTOR SELECTION
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 LSB D0 0 1 0 1 SURROUND PHASE RESISTOR PHASE SHIFT 1 (K) 12 14 18 37 PHASE SHIFT 2 (K) 6 7 8 18 PHASE SHIFT 3 (K) 12 14 18 39 PHASE SHIFT 4 (K) 12 14 18 39
0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 1 0 1
12/20
TDA7429S - TDA7429T
BASS SELECTION
MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
SPEAKER/AUX ATT. R & L SELECTION
MSB D7 X X X X X X X X X X X X X X X X X X X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER/AUX ATT 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE
0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 X
0 1 0 1 0 1 0 1 0 1 X X
X = INDIFFERENT 0,1 SPEAKER/AUX ATTENUATION = 0dB -79dB
13/20
TDA7429S - TDA7429T
MIDDLE & TREBLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 MIDDLE 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 TREBLE 2 dB STEPS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
14/20
TDA7429S - TDA7429T
INPUT/RECOUT L & R SELECTION
MSB D7 X X X X X X X X X X X X 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 D6 D5 D4 D3 D2 0 0 1 1 D1 0 1 0 1 LSB D0 0 0 0 0 0 0 0 0 0 0 0 0 INPUT MULTIPLEXER IN2 IN3 IN4 IN1 AUX OUT "L" VER 1 (3BAND) VER 2 (SURR) VER 3 (REAR) FIX AUX OUT "R" VER 1 (3BAND) VER 2 (SURR) VER 3 (REAR) FIX
POWER ON RESET
BASS & MIDDLE TREBLE SURROUND & OUT CONTROL+ EFFECT CONTROL SPEAKER/AUX ATTENUATION L &R INPUT ATTENUATION + REAR SWITCH NATURAL BASE INPUT 2dB 0dB OFF + FIX + MAX ATTENUATION MUTE MAX ATTENUATION + ON OFF IN1
PIN: TREBLE-L, TREBLE-R
VS 20A
PIN: VOUT REF
VS 20A
25K
GND
GND
D95AU233A
10K
D95AU309
GND
15/20
TDA7429S - TDA7429T
PIN: HP1 PIN: HP2
LP1
VS 10K
VS 20A 5.5K
60K GND
D94AU198
60K GND
D94AU199
HP2
HP1
5.5K
PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4,
PIN: VAR-L, VAR-R,
VS 20A
VS 20A
SW
50K GND
30K
D94AU200
VREF
GND Vref
D95AU227
PIN: CREF
PIN: LP1
VS 20K 42K 20A
VS 20A
20K
GND
10K
D95AU336
GND
HP1
D94AU211
16/20
TDA7429S - TDA7429T
PIN: SCL, SDA PIN: PS1, PS2, PS3, PS4, LP
VS
20A
20A
GND
D94AU205
GND
D95AU308
PIN: REARIN
PIN: L-OUT, R-OUT, MONITOR-L, MONITOR-R REAROUT, BASSO-L, BASSO-R, AUXOUT_L, AUXOUT_R
VS 20A
VS 20A
SW
50K GND Vref
D95AU229
GND
D95AU230
PIN: BASS-LI,BASS-RI, MIDDLE-LI, MIDDLE-RI,
PIN: BASS-LO,BASS-RO,MIDDLE-LO,MIDDLE-RO,
VS 20A
VS 20A
(*)
GND BASS-LO
45K : Bass or 25K : MIDDLE
D95AU231A
GND BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI (*) 45K : Bass 25K : MIDDLE
D95AU232
BASS-RO,MIDDLE-LO,MIDDLE-RO
17/20
TDA7429S - TDA7429T
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 1.40 0.37 mm TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030 0.055 0.014 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10)
0(min.), 3.5(typ.), 7(max.)
D D1 A1
33 34 23 22
0.10mm .004 Seating Plane
A A2
E1
B
44 1 11
12
E
B
e
C
L
K
TQFP4410
18/20
TDA7429S - TDA7429T
DIM. MIN. A A1 A2 B B1 c D E E1 e e1 e2 e3 L 2.54 3.30 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70 13.72 1.778 15.24 18.54 1.52 3.56 0.10 0.130 3.81 0.46 1.02 0.25 36.83 4.57 0.56 1.14 0.38 37.08 16.00 14.48 mm TYP. MAX. 5.08 0.020 0.120 0.150 0.180 MIN. inch TYP. MAX. 0.20
OUTLINE AND MECHANICAL DATA
0.0149 0.0181 0.0220 0.035 0.040 0.045
0.0090 0.0098 0.0150 1.440 0.60 0.50 0.540 0.070 0.60 0.730 0.060 0.140 1.450 1.460 0.629 0.570
SDIP42 (0.600")
E E1
A1
A2
B
B1
e
L
A
e1 e2
D c E 42 22
.015 0,38 Gage Plane
1
21
SDIP42
e3 e2
19/20
TDA7429S - TDA7429T
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
20/20

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