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PRELIMINARY
CYD04S72V CYD09S72V CYD18S72V
FLEx72TM 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
Features
* True dual-ported memory cells that allow simultaneous access of the same memory location * Synchronous pipelined operation * Family of 4-Mbit, 9-Mbit and 18-Mbit devices * Pipelined output mode allows fast operation * 0.18-micron CMOS for optimum speed and power * High-speed clock to data access * 3.3V low power -- Active as low as 225 mA (typ) * * * * * * * -- Standby as low as 55 mA (typ) Mailbox function for message passing Global master reset Separate byte enables on both ports Commercial and industrial temperature ranges IEEE 1149.1-compatible JTAG boundary scan 484-ball FBGA (1 mm pitch) Counter wrap around control -- Internal mask register controls counter wrap-around -- Counter-interrupt flags to indicate wrap-around -- Memory block retransmit operation * Counter readback on address lines * Mask register readback on address lines * Dual Chip Enables on both ports for easy depth expansion * Seamless Migration to Next Generation Dual Port Family
Functional Description
The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow). The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The CYD18S72V device have limited features. Please see "Address Counter and Mask Register Operations[16]" on page 6 for details. Seamless Migration to Next Generation Dual Port Family Cypress offers a migration path for all devices to the next-generation devices in the Dual-Port family with a compatible footprint. Please contact Cypress Sales for more details
Table 1. Product Selection Guide Density Part Number Max. Speed (MHz) Max. Access Time - clock to Data (ns) Typical operating current (mA) Package 4-Mbit (64K x 72) CYD04S72V 167 4.0 225 484-ball FBGA 23mm x 23mm 9-Mbit (128K x 72) CYD09S72V 167 4.0 270 484-ball FBGA 23mm x 23mm 18-Mbit (256K x 72) CYD18S72V 133 5.0 410 484-ball FBGA 23mm x 23mm
Cypress Semiconductor Corporation Document #: 38-06069 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised June 23, 2004
PRELIMINARY
.
CYD04S72V CYD09S72V CYD18S72V
Logic Block Diagram[1]
FTSELL PORTST[1:0]L CONFIG Block CONFIG Block PORTST[1:0]R FTSELR
DQ[71:0]L BE [7:0]L CE0L CE1L OEL R/WL
IO Control
IO Control
DQ [71:0]R BE [7:0]R CE0R CE1R OER R/WR
Dual Ported Array
BUSYL A [17:0]L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL WRPL
Arbitration Logic
BUSYR A [17:0]R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR WRPR
Address & Counter Logic
Address & Counter Logic
Mailboxes INTL INTR JTAG
TRST TMS TDI TDO TCK
READYL LowSPDL
RESET LOGIC
MRST READYR LowSPDR
Note: 1. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
Document #: 38-06069 Rev. *D
Page 2 of 26
PRELIMINARY
Pin Configuration 484-ball BGA Top View CYD04S72V / CYD09S72V / CYD18S72V
1 A
NC DQ6 3L DQ6 5L DQ6 7L
CYD04S72V CYD09S72V CYD18S72V
2
DQ6 1L DQ6 2L DQ6 4L DQ6 6L
3
DQ5 9L DQ6 0L VSS VSS
4
DQ5 7L DQ5 8L VSS VSS
5
DQ5 4L DQ5 5L DQ5 6L VSS
6
DQ5 1L DQ5 2L DQ5 3L
[2, 5]
7
DQ4 8L DQ4 9L DQ5 0L
[2, 5]
8
DQ4 5L DQ4 6L DQ4 7L REV L[2,4]
9
DQ4 2L DQ4 3L DQ4 4L LOW SPD L[2,4] VDDI OL VDDI OL VSS
10
DQ3 9L DQ4 0L DQ4 1L POR TST D0L
[2,4]
11
DQ3 6L DQ3 7L DQ3 8L
[2, 5]
12
DQ3 6R DQ3 7R DQ3 8R BUS YL
[2, 5]
13
DQ3 9R DQ4 0R DQ4 1R CNTI NTL
[10]
14
DQ4 2R DQ4 3R DQ4 4R POR TST D1L
[2, 5]
15
DQ4 5R DQ4 6R DQ4 7R REV R[2,4]
16
DQ4 8R DQ4 9R DQ5 0R
[2, 5]
17
DQ5 1R DQ5 2R DQ5 3R
[2, 5]
18
DQ5 4R DQ5 5R DQ5 6R VSS
19
DQ5 7R DQ5 8R VSS VSS
20
DQ5 9R DQ6 0R VSS VSS
21
DQ6 1R DQ6 2R DQ6 4R DQ6 6R
22
NC DQ6 3R DQ6 5R DQ6 7R
B C
NC
NC
NC
NC
NC
D E F G
A2L A3L A5L DQ6 9L DQ7 1L A0L DQ6 8L DQ7 0L A1L VDD IOL CE1 L[8] RET L[2,3] WRP L[2,3] REA DYL
[2, 5]
VSS
VSS
VDD IOL VDD IOL VDD IOL VDD IOL VDD IOL VCO RE VCO RE VCO RE VCO RE VDD IOL VDD IOL VDD IOL VDD IOL VDD IOL NC
VDD IOL VDD IOL VRE FL
[2, 4]
VDD IOL VDD IOL VSS
VDDI OL VCO RE VSS
VTT L VCO RE VSS
VTT L VCO RE VSS
VTTL
VDDI OR VDDI OR VSS
VDD IOR VDD IOR VSS
VDD IOR VDD IOR VRE FR
[2, 4]
VDD IOR VDD IOR VDD IOR VDD IOR VDD IOR VCO RE VCO RE VCO RE VCO RE VDD IOR VDD IOR VDD IOR VDD IOR VDD IOR NC
NC
VSS
VDD IOR CE1 R[8] RET R[2,3] WRP R[2,3] REA DYR
[2, 5]
DQ6 8R DQ7 0R A1R
DQ6 9R DQ7 1R A0R
CE0 L [9] BE4 L BE5 L BE6 L BE7 L OEL BE3 L BE2 L BE1 L BE0 L INTL
VDD IOL VDD IOL VDD IOL VDD IOL VTT L VTT L VTT L VDD IOL VDD IOL VDD IOL VDD IOL VDD IOL NC
VCO RE VSS
VDD IOR VDD IOR VDD IOR VDD IOR VDD IOR VTT L VTT L VTT L VDD IOR VDD IOR VDD IOR VDD IOR TRS T[2, 5] VSS
CE0 R [9] BE4 R BE5 R BE6 R BE7 R OER BE3 R BE2 R BE1 R BE0 R INTR
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
A3R A5R
A2R A4R
H
A4L
J
A6L A7L A9L A11L A13L A15L
NC CL REV L [2,4] ADS L [9] CNT/ MSK L[8] CNT ENL
[9]
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
NC CR REV R[2,4] ADS R [9] CNT/ MSK R[8] CNT ENR
[9]
A7R A9R A11 R A13 R A15 R A17 R
[7]
A6R A8R A10 R A12 R A14 R A16 R
[6]
K
A8L
L
A10L
M
A12L
N
A14L
P
A16L
[6]
A17L
[7]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R
A18L
[2,5]
NC
T U V
DQ3 5L DQ3 3L DQ3 1L DQ3 4L DQ3 2L DQ3 0L
CNT RST L [8] R/W L FTS ELL
[2,3]
VRE FL
[2, 4]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VRE FR
[2, 4]
CNT RST R[8] R/W R FTS ELR
[2,3]
NC
A18 R
[2,5]
REV L [2,4] VDD IOL MRS T
VDD IOL VDD IOL NC
VDD IOL VDD IOL REV L[2,4]
VDDI OL VDDI OL POR TST D1R
[2, 5]
VCO RE VTTL
VCO RE VTT L BUS YR
[2, 5]
VCO RE VTT L NC
VCO RE VDDI OR POR TST D0R
[2,4]
VDDI OR VDDI OR LOW SPD R[2,4] DQ8 R DQ7 R DQ6 R
VDD IOR VDD IOR REV R[2,4]
VDD IOR VDD IOR NC
REV R[2,4] VDD IOR TDI
DQ3 4R DQ3 2R DQ3 0R
DQ3 5R DQ3 3R DQ3 1R
VSS
VSS
[2, 5]
[2, 5]
CNTI NTR
[10]
[2, 5]
[2, 5]
[2, 5]
TDO
W Y A A A B 2. 3. 4. 5. 6. 7. 8. 9. 10.
DQ2 9L DQ2 7L NC DQ2 8L DQ2 6L DQ2 5L VSS DQ2 4L DQ2 3L VSS DQ2 2L DQ2 1L DQ2 0L DQ1 9L DQ1 8L DQ1 7L DQ1 6L DQ1 5L DQ1 4L DQ1 3L DQ1 2L DQ1 1L DQ1 0L DQ9 L
DQ8 L DQ7 L DQ6 L
DQ5 L DQ4 L DQ3 L
DQ2 L DQ1 L DQ0 L
DQ2 R DQ1 R DQ0 R
DQ5 R DQ4 R DQ3 R
DQ1 1R DQ1 0R DQ9 R
DQ1 4R DQ1 3R DQ1 2R
DQ1 7R DQ1 6R DQ1 5R
DQ2 0R DQ1 9R DQ1 8R
TMS DQ2 2R DQ2 1R
TCK DQ2 4R DQ2 3R
DQ2 8R DQ2 6R DQ2 5R
DQ2 9R DQ2 7R NC
This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales. Leave this ball unconnected. For more information about this feature, contact Cypress Sales. Leave this ball unconnected for a 64K x 72 configuration. Leave this ball unconnected for 128K x 72 and 64K x72 configurations. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO. These balls are not applicable for CYD18S72V device. They need to be tied to VSS. These balls are not applicable for CYD18S72V device. They need to be no connected.
Document #: 38-06069 Rev. *D
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PRELIMINARY
Pin Definitions
Left Port A0L-A17L BE0L-BE7L BUSYL[2,5] CL CE0L[9] CE1L[8] DQ0L-DQ71L OEL Right Port A0R-A17R BE0R-BE7R BUSYR[2,5] CR CE0R[9] CE1R[8] DQ0R-DQ71R OER Address Inputs. Description
CYD04S72V CYD09S72V CYD18S72V
Byte Enable Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. Port Busy Output. When the collision is detected, a BUSY is asserted. Input Clock Signal. Active Low Chip Enable Input. Active High Chip Enable Input. Data Bus Input/Output. Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD disables the port DLL.
INTL
INTR
LowSPDL[2,4]
LowSPDR[2,4]
PORTSTD[1:0]L[2,4,5] PORTSTD[1:0]R[2,4,5] Port Address/Control/Data I/O Standard Select Input. R/WL READYL[2,5] CNT/MSKL[8] ADSL[9] CNTENL[9] CNTRSTL[8] CNTINTL[10] WRPL[2,3] RETL[2,3] FTSELL[2,3] VREFL[2,5] VDDIOL REV[2,4]L MRST TRST[2,5] TMS R/WR READYR[2,5] CNT/MSKR[8] ADSR[9] CNTENR[9] CNTRSTR[8] CNTINTR[10] WRPR[2,3] RETR[2,3] FTSELR[2,3] VREFR[2,5] VDDIOR REV[2,4]R Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. Port Ready Output. This signal will be asserted when a port is ready for normal operation. Port Counter/Mask Select Input. Counter control input. Port Counter Address Load Strobe Input. Counter control input. Port Counter Enable Input. Counter control input. Port Counter Reset Input. Counter control input. Port Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all "1s". Port Counter Wrap Input. After the burst counter reaches the maximum count, if WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be loaded with the value stored in the mirror register. Port Counter Retransmit Input. Counter control input. Flow-Through Select. Use this pin to select Flow-Through mode. When is de-asserted, the device is in pipelined mode. Port External High-Speed IO Reference Input. Port IO Power Supply. Reserved pins for future features. Master Reset Input. MRST is an asynchronous input signal and affects both ports. A master reset operation is required at power-up. JTAG Reset Input. JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK.
Document #: 38-06069 Rev. *D
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PRELIMINARY
Pin Definitions (continued)
Left Port TDI TCK TDO VSS VCORE VTTL Master Reset The FLEx72 family devices undergo a complete reset by taking the MRST input LOW. MRST input can switch asynchronously to the clocks. MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). MRST also forces the mailbox interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. MRST must be performed on the FLEx72 family devices after power-up. Mailbox Interrupts The upper two memory locations may be used for message passing and permit communications between ports. Table 2 shows the interrupt operation for both ports using 18Mbit device as an example. The highest memory location, 3FFFF is the mailbox for the right port and 3FFFE is the mailbox for the left port. Table 2.shows that in order to set the INTR flag, a Table 2. Interrupt Operation Example [1, 11, 12, 13] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X H CEL L X X L A0L-17L 3FFFF X X 3FFFE INTL X X L H R/WR X H L X X L L X Right Port CER Right Port Description
CYD04S72V CYD09S72V CYD18S72V
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. JTAG Test Clock Input. JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Ground Inputs. Core Power Supply. LVTTL Power Supply. write operation by the left port to address 3FFFF will assert INTR LOW. At least one byte has to be active for a write to generate an interrupt. A valid Read of the 3FFFF location by the right port will reset INTR HIGH. At least one byte has to be active in order for a read to reset the interrupt. When one port writes to the other port's mailbox, the INT of the port that the mailbox belongs to is asserted LOW. The INT is reset when the owner (port) of the mailbox reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). Each port can read the other port's mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open.
A0R-17R X 3FFFF 3FFFE X
INTR L H X X
Note: 11. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge. 12. OE is "Don't Care" for mailbox operation. 13. At least one of BE0 or BE7 must be LOW.
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PRELIMINARY
Table 3. Address Counter and Counter Mask Register Control Operation (Any Port) [14,15 ] CLK X MRST L H H H H H H H H H CNT/MSK CNTRST ADS CNTEN X H H H H H L L L L X L H H H H L H H H X X L L H H X L L H X X L H L H X L H X Operation Master Reset Counter Reset Counter Load
CYD04S72V CYD09S72V CYD18S72V
Description Reset address counter to all 0s and mask register to all 1s. Reset counter unmasked portion to all 0s. Load counter with external address value presented on address lines.
Counter Readback Read out counter internal value on address lines. Counter Increment Internally increment address counter value. Counter Hold Mask Reset Mask Load Mask Readback Reserved Constantly hold the address value for multiple clock cycles. Reset mask register to all 1s. Load mask register with value presented on the address lines. Read out mask register value on address lines. Operation undefined
Note: 14. X" = "Don't Care," "H" = HIGH, "L" = LOW. 15. Counter operation and mask register operation is independent of chip enables.
Address Counter and Mask Register Operations[16] This section describes the features only apply to 4Mbit and 9Mbit devices, not to 18Mbit device. Each port have a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register. The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more "0s" in the most significant bits define the masked region, one or more "1s" in the least significant bits define the unmasked region. Bit 0 may also be "0," masking the least significant counter bit and causing the counter to increment by two instead of one. The mirror register is used to reload the counter register on increment operations (see "retransmit," below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load, and Counter Reset operations, and by the MRST. Table 3 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port's CLK. All these counter and mask operations are independent of the port's chip enable inputs (CE0 and CE1)
Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port's burst counter is loaded when the port's address strobe (ADS) and CNTEN signals are LOW. When the port's CNTEN is asserted and the ADS is deasserted, the address counter will increment on each LOW to HIGH transition of that port's clock signal. This will Read/Write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap. Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to "0." All masked bits remain unchanged. A Mask Reset followed by a Counter Reset will reset the counter and mirror registers to 00000, as will master reset (MRST). Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a "1" for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are "1," the next increment
Document #: 38-06069 Rev. *D
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PRELIMINARY
will wrap the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being "1s," a counter interrupt flag (CNTINT) is asserted. The next Increment will return the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[17] An increment that results in one or more of the unmasked bits of the counter being "0" will de-assert the counter interrupt flag. The example in Figure 2 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit "0" as the LSB and bit "16" as the MSB. The maximum value the mask register can be loaded with is 1FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address will start at address 8h. The counter will increment its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value. Counter Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Counter Interrupt The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all "1s." It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST. Counter Readback Operation The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address will be valid tCA2 after the next rising edge of the port's clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Retransmit
CYD04S72V CYD09S72V CYD18S72V
Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal "mirror register" is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this "mirror register." If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the "mirror register." Thus, the repeated access of the same data is allowed without the need for any external logic. Mask Reset Operation The mask register is reset to all "1s," which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all "1s." Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n - 1 or 2n - 2. From the most significant bit to the least significant bit, permitted values have zero or more "0s," one or more "1s," or one "0." Thus 1FFFF, 003FE, and 00001 are permitted values, but 1F0FF, 003FC, and 00000 are not. Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address will be valid tCM2 after the next rising edge of the port's clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is "0," the counter increments by two. This may be used to connect the x72 devices as a 144-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 144-bit data in even memory locations, and the other half in odd memory locations.
Notes: 16. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF. The CYD18S72V has 18 address bits and a maximum address value of 3FFFF. 17. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
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PRELIMINARY
CYD04S72V CYD09S72V CYD18S72V
CNT/MSK CNTEN ADS CNTRST MRST Decode Logic
Bidirectional Address Lines
Mask Register Counter/ Address Register
Address Decode
RAM Array
CLK
From Address Lines
17 Mirror
Load/Increment Counter To Readback and Address Decode
1 From Mask Register 17 Increment Logic Wrap 0
1 0
17
From Mask From Counter
17 17
17 Bit 0 +1 1 +2 0 1 0 17 To Counter Wrap Detect Wrap
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
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PRELIMINARY
Example: Load Counter-Mask Register = 3F CNTINT H 00 216 215 Masked Address Load Address Counter = 8 H XX 216 215 Max Address Register Max + 1 Address Register L XX 216 215 H XX 216 215 Xs Xs Xs 0s 011 1 1 1 1
CYD04S72V CYD09S72V CYD18S72V
26 25 24 23 22 21 20 Unmasked Address X00 1 0 0 0
Mask Register bit-0
26 25 24 23 22 21 20 X11 1 11 1
Address Counter bit-0
26 25 24 23 22 21 20 X0 0 1 00 0
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 18]
IEEE 1149.1 Serial Boundary Scan (JTAG)[19]
The FLEx72 incorporates an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the FLEx72 family and may be performed while the device is operating. An MRST must be performed on the FLEx72 after power-up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain will output the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device will output a 11010101. This extra bit will cause some testers to report an erroneous failure for the FLEx72 in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state.
Boundary Scan Hierarchy for FLEx72 Family Internally, the CYD04S72V and CYD09S72V have two DIEs while CYD18S72V have four DIEs. Each DIE contains all the circuitry required to support boundary scan testing. The circuitry includes the TAP, TAP controller, instruction register, and data registers. The circuity and operation of the DIE boundary scan are described in detail below. The scan chain of each DIE is connected serially to form the scan chain of the FLEx72 family as shown in Figure 3. TMS and TCK are connected in parallel to each DIE to drive all 4 TAP controllers in unison. In many cases, each DIE will be supplied with the same instruction. In other cases, it might be useful to supply different instructions to each DIE. One example would be testing the device ID of one DIE while bypassing the others. Each pin of FLEx72 family is typically connected to multiple DIEs. For connectivity testing with the EXTEST instruction, it is desirable to check the internal connections between DIEs as well as the external connections to the package. This can be accomplished by merging the netlist of the devices with the netlist of the user's circuit board. To facilitate boundary scan testing of the devices, Cypress provides the BSDL file for each DIE, the internal netlist of the device, and a description of the device scan chain. The user can use these materials to easily integrate the devices into the board's boundary scan environment. Further information can be found in the Cypress application note Using JTAG Boundary Scan For System In a Package (SIP) Dual-Port SRAMs.
Notes: 18. The "X" in this diagram represents the counter upper bits. 19. Boundary scan is IEEE 1149.1-compatible. See "Performing a Pause/Restart" for deviation from strict 1149.1 compliance.
Document #: 38-06069 Rev. *D
Page 9 of 26
PRELIMINARY
18 Mbit
TDO D2 TDI TDO D4 TDI TDO
CYD04S72V CYD09S72V CYD18S72V
4 Mbit/9 Mbit
TDO TDO D2 TDI
TDO D1 TDI TDI
TDO D3 TDI TDI
TDO D1 TDI
Figure 3. Scan Chain Table 4. Identification Register Definitions Instruction Field Revision Number(31:28) Cypress Device(27:12) Value 0h C002h C001h Cypress JDEC ID(11:1) ID Register Presence (0) Table 5. Scan Registers Sizes Register Name Instruction Bypass Identification Boundary Scan Table 6. Instruction Identification Codes Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP SAMPLE/PRELOAD NBSRST RESERVED 1111 1011 0111 0100 1000 1100 All other codes Code 0000 Description Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all FLEx72 output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. Captures the input/output ring contents. Places BSR between TDI and TDO. Resets the non-boundary scan logic. Places BYR between TDI and TDO. Other combinations are reserved. Do not use other than the above. Bit Size 4 1 32 n [20] 034h 1 Description Reserved for version number Defines Cypress DIE number for CYD18S72V and CYD09S72V. Defines Cypress DIE number for CYD04S72V Allows unique identification of FLEx72 family device vendor Indicates the presence of an ID register
Note: 20. See details in the device BSDL files
Document #: 38-06069 Rev. *D
Page 10 of 26
PRELIMINARY
Maximum Ratings [21]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................-55C to + 125C Supply Voltage to Ground Potential .............. -0.5V to + 4.6V DC Voltage Applied to Outputs in High-Z State..........................-0.5V to VDD + 0.5V
CYD04S72V CYD09S72V CYD18S72V
DC Input Voltage .............................. -0.5V to VDD + 0.5V[22] Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2000V (JEDEC JESD22-A114-2000B) Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial Industrial
Ambient Temperature
0C to +70C -40C to +85C
VDD
3.3V 165 mV 3.3V 165 mV
VCORE
1.8V 100 mV 1.8V 100mV
Electrical Characteristics Over the Operating Range
-167 Parameter
VOH VOL VIH VIL IOZ IIX1 IIX2 ICC
-133 Max. Min.
2.4 0.4 0.4 2.0 0.8 0.8 -10 -10 -0.1 225 410 10 10 1.0 300 580 115 -10 -10 -0.1 10 10 1.0 2.0
-100 Max. Min.
2.4 0.4
Description
Part No.
Min.
2.4
Typ.
Typ.
Typ
Max
Unit
V V V
Output HIGH Voltage (VDD = Min., IOH= -4.0 mA) Output LOW Voltage (VDD = Min., IOL= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Input Leakage Current Except TDI, TMS, MRST Input Leakage Current TDI, TMS, MRST Operating Current (VDD = Max.,IOUT = 0 mA), Outputs Disabled Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER VDD - 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX Operating Current (VDDIO = Max,Iout=0mA,f=0) Outputs Disabled CYD04S72V CYD09S72V CYD18S72V CYD04S72V CYD09S72V CYD04S72V CYD09S72V CYD04S72V CYD09S72V CYD04S72V CYD09S72V CYD18S72V
2.0 -10 -10 -0.1 225
0.8 10 10 1.0
V A A mA mA
300
315
450
mA mA
ISB1 ISB2 ISB3 ISB4 ISB5 ICORE
90
115
90
160
210
160
210
mA
55
75
55
75
mA
160
210
160
210
mA
75
75
mA
Core Operating Current for (VDD = Max.,IOUT = 0 mA), Outputs Disabled
0
0
0
0
0
0
mA
Capacitance [23]
Part#
CYD04S72V CYD09S72V CYD18S72V
Parameter
CIN COUT CIN COUT
Description
Input Capacitance Output Capacitance Input Capacitance Output Capacitance
Test Conditions
TA = 25C, f = 1 MHz, VDD = 3.3V
Max.
20 10[24] 40 20
Unit
pF pF pF pF
Note: 21. The voltage on any input or I/O pin can not exceed the power pin during power-up. 22. Pulse width < 20 ns. 23. COUT also references CI/O
Document #: 38-06069 Rev. *D
Page 11 of 26
PRELIMINARY
AC Test Load and Waveforms
3.3V Z0 = 50 OUTPUT C = 10 pF VTH = 1.5V OUTPUT C = 5 pF R = 50
CYD04S72V CYD09S72V CYD18S72V
R1 = 590
R2 = 435
(a) Normal Load (Load 1)
3.0V ALL INPUT PULSES Vss < 2 ns
(b) Three-state Delay (Load 2)
90% 10%
90% 10% < 2 ns
Switching Characteristics Over the Operating Range
-167 CYD04S72V CYD09S72V Parameter fMAX2 tCYC2 tCH2 tCL2 tR[25] tF[25] tSA tHA tSB tHB tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST Description Maximum Operating Frequency Clock Cycle Time Clock HIGH Time Clock LOW Time Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Byte Select Set-up Time Byte Select Hold Time Chip Enable Set-up Time Chip Enable Hold Time R/W Set-up Time R/W Hold Time Input Data Set-up Time Input Data Hold Time ADS Set-up Time ADS Hold Time CNTEN Set-up Time CNTEN Hold Time CNTRST Set-up Time 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 6.0 2.7 2.7 2.0 2.0 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 Min. Max. 167 7.5 3.0 3.0 2.0 2.0 2.2 1.0 2.2 1.0 NA NA 2.2 1.0 2.2 1.0 NA NA NA NA NA CYD04S72V CYD09S72V Min. Max. 133 7.5 3.4 3.4 2.0 2.0 2.7 1.0 2.7 1.0 NA NA 2.7 1.0 2.7 1.0 NA NA NA NA NA -133 CYD18S72V Min. Max 133 10 4.5 4.5 3.0 3.0 -100 CYD18S72V Min. Max 100 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Document #: 38-06069 Rev. *D
Page 12 of 26
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
-167 CYD04S72V CYD09S72V Parameter tHRST tSCM tHCM tOE tOLZ
[26, 27] [26, 27]
CYD04S72V CYD09S72V CYD18S72V
-133 CYD04S72V CYD09S72V Min. 0.6 2.5 0.6 4.0 4.4 0 4.0 4.0 4.0 4.0 0 4.4 4.4 4.4 4.4 1.0 4.0 4.0 6.7 6.7 5.0 5.0 0 1.0 0.5 0.5 0.5 0.5 6.0 5.0 6.0 5.0 4.4 4.4 7.5 7.5 5.7 5.7 1.0 0 1.0 0.5 0.5 NA NA 5.7 5.0 6.0 5.0 10.0 10.0 10.0 NA 4.7 4.7 7.5 7.5 NA NA 0 0 5.5 5.0 NA NA 1.0 0 1.0 0.5 0.5 NA NA 8.0 5.0 8.5 5.0 Max. CYD18S72V Min. NA NA NA 5.5 0 0 Max
-100 CYD18S72V Min. NA NA NA 5.5 5.5 5.2 NA NA Max Unit ns ns
Description CNTRST Hold Time CNT/MSK Set-up Time CNT/MSK Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid Clock to Counter Address Valid Clock to Mask Register Readback Valid Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Clock to INT Set Time Clock to INT Reset Time Clock to CNTINT Set Time Clock to CNTINT Reset time Clock to Clock Skew Master Reset Pulse Width Master Reset Set-up Time Master Reset Recovery Time Master Reset to Outputs Inactive Master Reset to Counter Interrupt Flag Reset Time
Min. 0.6 2.3 0.6 0 0
Max.
ns ns
ns ns ns ns ns ns 5.0 5.0 10 10 NA NA ns ns ns ns ns ns ns cycles ns cycles 10.0 NA ns ns
tOHZ tCD2 tCA2 tCM2 tDC
1.0 0 1.0 0.5 0.5 0.5 0.5 5.2 5.0 6.0 5.0 10.0 10.0
tCKHZ[26, 27] tCKLZ[26, 27] tSINT tRINT tSCINT tRCINT tCCS tRS tRSS tRSR tRSF tRSCNTINT
Port to Port Delays Master Reset Timing
Notes: 24. Except INT and CNTINT which are 20pF 25. Except JTAG signal (tr and tf < 10ns max) 26. This parameter is guaranteed by design, but is not production tested 27. Test conditions used are Load 2
Document #: 38-06069 Rev. *D
Page 13 of 26
PRELIMINARY
JTAG Timing Characteristics
CYD04S72V CYD09S72V CYD18S72V
CYD04S72V CYD09S72V CYD18S72V -167/-133/-100 Parameter fJTAG tTCYC tTH tTL tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX TCK Clock Cycle Time TCK Clock HIGH Time TCK Clock LOW Time TMS Set-up to TCK Clock Rise TMS Hold After TCK Clock Rise TDI Set-up to TCK Clock Rise TDI Hold After TCK Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 Description Maximum JTAG TAP Controller Frequency 100 40 40 10 10 10 10 30 Min. Max. 10 Unit MHz ns ns ns ns ns ns ns ns ns
Switching Waveforms
tTH Test Clock TCK Test Mode Select TMS tTDIS Test Data-In TDI Test Data-Out TDO tTDIH tTL
tTMSS
tTCYC tTMSH
tTDOX tTDOV
Document #: 38-06069 Rev. *D
Page 14 of 26
PRELIMINARY
Switching Waveforms (continued)
Master Reset
MRST ALL ADDRESS/ DATA LINES ALL OTHER INPUTS TMS CNTINT INT TDO tRSF tRSS tRSR ACTIVE tRS
CYD04S72V CYD09S72V CYD18S72V
INACTIVE
Read Cycle[11, 28, 29, 30, 31]
tCH2 CLK tCYC2 tCL2
CE tSC tSB BE0-BE7 tHC tHB tSC tHC
R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE
tOE Notes: 28. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 29. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 30. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 31. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
An+2 tDC Qn+1 tOHZ
An+3
Qn+2 tOLZ
Document #: 38-06069 Rev. *D
Page 15 of 26
PRELIMINARY
Switching Waveforms (continued)
Bank Select Read[32, 33]
tCH2 CLK tSA ADDRESS(B1) tSC CE(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 Q2 tCKHZ tSC Q0 tDC A2 tHC tHC tCD2 Q1 tDC A3 A4 tCKLZ tCKHZ tCD2 A0 tHC tHA A1 A2 A3 A4 tCYC2 tCL2
CYD04S72V CYD09S72V CYD18S72V
A5
tCKHZ Q3
A5
tCD2 Q4 tCKLZ
Read-to-Write-to-Read (OE = LOW)[31, 34, 35, 36, 37]
tCH2 tCYC2tCL2 CLK
CE tSC tHC
tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ tDC tHW An+1 An+2
tHW
An+2
An+2 tSD tHD
An+3
tCKHZ
Dn+2
DATAOUT
NO OPERATION
WRITE
Notes: 32. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx72 device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 33. ADS = CNTEN= BE0 - BE7 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH. 34. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 35. During "No Operation," data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 36. CE0 = OE = BE0 - BE7 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 37. CE0 = BE0 - BE7 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06069 Rev. *D
Page 16 of 26
PRELIMINARY
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[31, 34, 36, 37]
tCH2 CLK tCYC2 tCL2
CYD04S72V CYD09S72V CYD18S72V
CE tSC tHC tSW tHW
R/W
tSW An tSA
tHW An+1 tHA tCD2 An+2 tSD tHD Dn+2 Dn+3 tCD2 Qn tOHZ Qn+4 An+3 An+4 An+5
ADDRESS DATAIN
DATAOUT
OE READ WRITE READ
Read with Address Counter
tCH2 CLK tSA ADDRESS tSAD ADS An
Advance[36]
tCYC2 tCL2
tHA
tHAD tSAD tHAD
CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC tCD2 Qn READ WITH COUNTER tSCN Qn+1 COUNTER HOLD tHCN Qn+2 READ WITH COUNTER Qn+3
Document #: 38-06069 Rev. *D
Page 17 of 26
PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance [37]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
CYD04S72V CYD09S72V CYD18S72V
INTERNAL ADDRESS tSAD ADS tHAD
An
An+1
An+2
An+3
An+4
CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4
WRITE COUNTER HOLD
WRITE WITH COUNTER
Document #: 38-06069 Rev. *D
Page 18 of 26
PRELIMINARY
Switching Waveforms (continued)
Counter Reset [38, 39]
tCYC2 tCH2 tCL2 CLK tSA ADDRESS INTERNAL ADDRESS An Ax tSW R/W tHW 0 1 An tHA Am
CYD04S72V CYD09S72V CYD18S72V
Ap Ap
Am
ADS
CNTEN tSRST tHRST CNTRST tSD DATAIN tHD
D0
tCD2 Q0 tCKLZ READ ADDRESS 0
tCD2 Q1 Qn
[51] DATAOUT
COUNTER RESET
WRITE ADDRESS 0
READ ADDRESS 1
READ ADDRESS An
READ ADDRESS Am
Notes: 38. CE0 = BE0 - BE7= LOW; CE1 = MRST = CNT/MSK = HIGH. 39. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Document #: 38-06069 Rev. *D
Page 19 of 26
PRELIMINARY
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[40, 41, 42, 43]
tCYC2 tCH2 tCL2 CLK tSA tHA EXTERNAL ADDRESS A0-A17 INTERNAL ADDRESS tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-2 Qx-1 tCKHZ Qn tCKLZ Qn+1 Qn+2 An tCA2 or tCM2 An*
CYD04S72V CYD09S72V CYD18S72V
An
An+1
An+2
An+3
An+4
Qn+3
LOAD EXTERNAL ADDRESS
READBACK COUNTER INTERNAL ADDRESS
INCREMENT
Notes: 40. CE0 = OE = BE0 - BE7 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 41. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle. 42. Address in input mode. Host can drive address bus after tCKHZ. 43. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06069 Rev. *D
Page 20 of 26
PRELIMINARY
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[44, 45, 46]
tCH2 CLKL tSA L_PORT ADDRESS tSW R/WL tCKHZ tSD Dn tCYC2 tCL2 tCH2 tSA An tHA tCCS tHD An tHW tHA tCYC2 tCL2
CYD04S72V CYD09S72V CYD18S72V
L_PORT
DATAIN
tCKLZ
CLKR R_PORT ADDRESS
R/WR tCD2
R_PORT
DATAOUT tDC
Qn
Notes: 44. CE0 = OE = ADS = CNTEN = BE0 - BE7 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 45. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out. 46. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document #: 38-06069 Rev. *D
Page 21 of 26
PRELIMINARY
Switching Waveforms (continued)
Counter Interrupt and Retransmit[47, 48, 49, 50, 51]
tCH2 CLK tSCM CNT/MSK tHCM tCYC2 tCL2
CYD04S72V CYD09S72V CYD18S72V
ADS
CNTEN
COUNTER INTERNAL ADDRESS CNTINT
1FFFC
1FFFD
1FFFE tSCINT
1FFFF tRCINT
Last_Loaded
Last_Loaded +1
Notes: 47. CE0 = OE = BE0 - BE7 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 48. CNTINT is always driven. 49. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 50. The mask register assumed to have the value of 1FFFFh. 51. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06069 Rev. *D
Page 22 of 26
PRELIMINARY
Mailbox Interrupt Timing[52,53,54,55,56]
tCYC2 tCL2
CYD04S72V CYD09S72V CYD18S72V
tCH2 CLKL
tSA L_PORT ADDRESS INTR tCYC2 tCL2
tHA An tSINT tRINT An+1 An+2 An+3
3FFFF
tCH2 CLKR
tSA R_PORT ADDRESS Am
tHA Am+1 3FFFF Am+3 Am+4
Table 7. Read / Write and Enable Operation (Any Port) [1,14,57,58,59] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs DQ0 - DQ71 High-Z High-Z DIN DOUT High-Z Operation Deselected Deselected Write Read Outputs Disabled
Notes: 52. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 53. Address "1FFFF" is the mailbox location for R_Port. 54. L_Port is configured for Write operation, and R_Port is configured for Read operation. 55. At least one byte enable (B0 - B3) is required to be active during interrupt operations. 56. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. 57. OE is an asynchronous input signal. 58. When CE changes state, deselection and Read happen after one cycle of latency. 59. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document #: 38-06069 Rev. *D
Page 23 of 26
PRELIMINARY
Ordering Information
256K x 72 (18Mb) 3.3V Synchronous CYD18S72V Dual-Port SRAM Speed (MHz) 133 100 Ordering Code CYD18S72V-133BBC CYD18S72V-100BBC CYD18S72V-100BBI Package Name BB484 BB484 BB484 Package Type
CYD04S72V CYD09S72V CYD18S72V
Operating Range
484-ball Grid Array Commercial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Commercial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Industrial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Commercial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Commercial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Industrial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Commercial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Commercial 23mm x 23mm with 1.0mm pitch (FBGA) 484-ball Grid Array Industrial 23mm x 23mm with 1.0mm pitch (FBGA)
128K x 72 (9Mb) 3.3V Synchronous CYD09S72V Dual-Port SRAM 167 133 CYD09S72V-167BBC CYD09S72V-133BBC CYD09S72V-133BBI BB484 BB484 BB484
64K x 72 (4Mb) 3.3 Synchronous CYD04S72V Dual-Port SRAM 167 133 CYD04S72V-167BBC CYD04S72V-133BBC CYD04S72V-133BBI BB484 BB484 BB484
Document #: 38-06069 Rev. *D
Page 24 of 26
PRELIMINARY
Package Diagram
484-ball FBGA (23 mm x 23 mm x 1.9 mm) BB484
CYD04S72V CYD09S72V CYD18S72V
51-85124-*D
FLEx72 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06069 Rev. *D
Page 25 of 26
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: FLEx72TM 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Document Number: 38-06069 REV. ** *A ECN NO. 125859 128707 Issue Date 06/17/03 08/01/03 Orig. of Change SPN SPN Description of Change New Data Sheet
CYD04S72V CYD09S72V CYD18S72V
Added -133 speed bin Updated spec values for ICC, tHA, tHB, tHW, tHD Added new parameter ICC1 Added bank select read and read to write to read (OE=low) timing diagrams Updated spec values for tOE, tOHZ, tCH2, tCL2, tHA, tHB, tHW, tHD, ICC, ISB5, tSA, tSB,tSW,tSD, tCD2 Updated read to write (OE=low) timing diagram Updated Master Reset values for tRS, tRSR, tRSF Updated pinout Updated VCORE voltage range Updated Package Diagram Updated tCD2 value on first page Removed Preliminary Status Added 4M and 9M x72 devices into the datasheet with updated pinout, pin description table, power table, and timing table. Changed the title and Added back Preliminary status to reflect the addition of 4M and 9M devices. Removed FLEX72-E word from the document. Added counter related functions for 4M and 9M. Removed standard JTAG description. Updated block diagram. Updated pinout with FTSEL and one more PORTSTD pins per port. Updated tRSF of CYD18S72V value.
*B
128997
09/18/03
SPN
*C
129936
09/30/03
SPN
*D
233830
See ECN
WWZ
Document #: 38-06069 Rev. *D
Page 26 of 26

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Price & Availability of CYD09S72V

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