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| MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7532 Group is the 8-bit microcomputer based on the 740 family core technology. The 7532 Group has a USB, 8-bit timers, and an A-D converter, and is useful for an input device for personal computer peripherals. * * * * * * * * Serial I/O1 ................................ used only for Low Speed in USB (USB/UART) Serial I/O2 ...................................................................... 8-bit 1 (Clock-synchronized) A-D converter ................................................ 10-bit 8 channels Clock generating circuit ............................................. Built-in type (connect to external ceramic resonator or quartz-crystal oscillator ) FEATURES * Basic machine-language instructions ....................................... 69 * The minimum instruction execution time .......................... 0.34 s (at 6 MHz oscillation frequency for the shortest instruction) * Memory size ................................................................................. * * * ROM ............................................... 8K to 16K bytes RAM .............................................. 256 to 384 bytes Programmable I/O ports ...................................... 28 (36-pin type) ............................................................................ 24 (32-pin type) Interrupts .................................................... 13 sources, 8 vectors Timers ............................................................................ 8-bit 3 Watchdog timer ............................................................ 16-bit 1 Power source voltage At 6 MHz XIN oscillation frequency at ceramic resonator ................................................................................... 4.1 to 5.5 V Power dissipation ............................................ 30 mW (standard) Operating temperature range ................................... -20 to 85 C APPLICATION Input device for personal computer peripherals PIN CONFIGURATION (TOP VIEW) P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 P11/TXD/D+ P10/RXD/DP07 P06 P05 P04 P03 P02 P01 P00 USBVREFOUT P37/INT0 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Package type: 36P2R-A M37532M4-XXXFP M37532E8FP Fig. 1 Pin configuration of M37532M4-XXXFP,M37532E8FP MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) 23 20 24 22 19 18 P07 P10/RXD/DP11/TXD/D+ P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1 21 17 P06 P05 P04 P03 P02 P01 P00 USBVREFOUT 25 26 27 28 29 30 31 32 3 4 5 6 7 1 2 8 16 15 14 M37532M4-XXXGP 13 12 11 10 9 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN Fig. 2 Pin configuration of M37532M4-XXXGP 2 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC Outline 32P6B-A MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) P14/CNTR0 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 NC NC VREF RESET CNVSS Vcc XIN XOUT VSS 1 2 3 4 5 6 7 42 41 40 39 38 37 36 8 9 10 11 12 13 14 15 16 17 18 19 20 21 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P13/SDATA P12/SCLK P11/TXD/D+ P10/RXD/DP07 P06 P05 P04 P03 P02 P01 P00 USBVREFOUT P37/INT0 NC P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Outline 42S1M M37532RSS Fig. 3 Pin configuration of M37532RSS 3 12 25 24 23 22 21 20 19 11 10 9 8 7 6 5 4 26 3 2 1 36 35 34 33 32 31 30 29 28 27 VREF MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wake up 4 Reset input VSS VCC 15 13 14 18 FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R) Clock input RESET CNVSS Clock output XIN XOUT FUNCTIONAL BLOCK Fig. 4 Functional block diagram CPU 16 17 Clock generating circuit RAM ROM X Prescaler 12 (8) Prescaler X (8) S CNTR0 A Timer 1 (8) Timer 2 (8) Timer X (8) Y PC H PS PCL Watchdog timer Reset 0 A-D converter (10) SI/O1(8) USB(LS) SI/O2(8) USBVREFOUT INT0 P3(7) P2(8) P1(5) P0(8) FUNCTIONAL BLOCK DIAGRAM (Package: 32P6B-A) Reset input VSS VCC 8 6 7 11 Clock input RESET CNVSS Clock output XIN XOUT 5 4 3 2 1 32 31 16 15 14 13 12 17 30 29 28 27 26 25 24 23 22 21 20 19 18 VREF I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wake up Fig. 5 Functional block diagram CPU 9 10 Clock generating circuit RAM ROM X Prescaler 12 (8) Prescaler X (8) S CNTR0 A Timer 1 (8) Timer 2 (8) Timer X (8) Y PC H PS PCL Watchdog timer Reset 0 A-D converter (10) SI/O1(8) USB(LS) SI/O2(8) USBVREFOUT P3(5) P2(6) P1(5) P0(8) 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 5 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description Pin Vcc, Vss VREF USBVREFOUT CNVss RESET XIN XOUT P00-P07 Name Power source Analog reference voltage USB reference voltage output CNVss Reset input Clock input Clock output I/O port P0 Function *Apply voltage of 4.1 to 5.5 V to Vcc, and 0 V to Vss. *Reference voltage input pin for A-D converter *Output pin for pulling up a D- line with 1.5 k external resistor *Chip operating mode control pin, which is always connected to Vss. *Reset input pin for active "L" *Input and output pins for main clock generating circuit *Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *8-bit I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *Whether a built-in pull-up resistor is to be used or not can be determined by program. P10/RxD/DP11/TxD/D+ P12/SCLK P13/SDATA P14/CNTR0 I/O port P1 *5-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *CMOS/TTL level can be switched for P10, P12, P13. *When using the USB function, input level of ports P10 and P11 becomes USB input level, and output level of them becomes USB output level. P20/AN0- P27/AN7 I/O port P2 *8-bit I/O port having almost the same function as P0 *CMOS compatible input level *CMOS 3-state output structure P30-P35 I/O port P3 *7-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level (CMOS/TTL level can be switched for P37). *CMOS 3-state output structure *P30 to P35 can output a large current for driving LED. *Whether a built-in pull-up resistor is to be used or not can be determined by program. *Input pins for A-D converter *Timer X function pin *Serial I/O1 function pin *Serial I/O2 function pin *Key-input (key-on wake up interrupt input) pins Function expect a port function P37/INT0 *Interrupt input pins 6 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 7532 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU . Memory size ROM/PROM size .................................................. 8 K to 16 K bytes RAM size ................................................................256 to 384 bytes Package 36P2R-A ..................................... 0.8 mm-pitch plastic molded SOP 32P6B-A .................................... 0.8 mm-pitch plastic molded LQFP 42SIM ...................................... 42 pin shrink ceramic PIGGY BACK ROM size (Byte) 16K M37532E8 8K M37532M4 0 128 256 384 RAM size (Byte) Fig. 6 Memory expansion plan Currently supported products are listed below. Table 2 List of supported products Product M37532M4-XXXFP M37532M4-XXXGP M37532E8FP M37532RSS (P) ROM size (bytes) ROM size for User () 8192 (8062) 8192 (8062) 16384 (16254) RAM size (bytes) 256 256 384 384 Package 36P2R-A 32P6B-A 36P2R-A 42S1M Remarks Mask ROM version Mask ROM version One Time PROM version (blank) Emulator MCU 7 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 7532 Group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the 740 Family Software Manual for details on each instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions cannot be used. 2. The MUL and DIV instructions cannot be used. 3. The WIT instruction can be used. 4. The STP instruction can be used. [CPU Mode Register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. b7 b0 CPU mode register (CPUM: address 003B 16) Processor mode bits b1 b0 0 0 Single-chip mode 01 10 Not available 11 Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns "0" when read) (Do not write "1" to these bits ) Main clock division ratio selection bits b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f() = f(XIN) (Double-speed mode) Fig. 7 Structure of CPU mode register Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method. After releasing reset Start with a built-in ring oscillator (Note) Wait until establish ceramic oscillator clock. Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Switch to other mode except a ring oscillator (Select one of 1/1, 1/2, and 1/8) Main routine Note. After releasing reset the operation starts by starting a ring oscillator automatically. Do not use a ring oscillator at ordinary operation. Fig. 8 Switching method of CPU mode register 8 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 000016 SFR area 004016 010016 Zero page RAM RAM area RAM capacity (bytes) address XXXX16 XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area (128 bytes) 256 384 013F16 01BF16 ZZZZ16 ROM ROM area ROM capacity (bytes) address YYYY16 address ZZZZ16 FF0016 8192 16384 E00016 C00016 E08016 C08016 FFEC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page Fig. 9 Memory map diagram 9 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 USB interrupt control register (USBICON) USB transmit data byte number set register 0 (EP0BYTE) USB transmit data byte number set register 1 (EP1BYTE) USBPID control register 0 (EP0PID) USBPID control register 1 (EP1PID) USB address register (USBA) USB sequence bit initialization register (INISQ1) USB control register (USBCON) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) A-D control register (ADCON) A-D conversion register (low-order) (ADL) A-D conversion register (high-order) (ADH) Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit/Receive buffer register (TB/RB) USB status register (USBSTS)/UART status register (UARTSTS) 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) USB data toggle synchronization register ( TRSYNC) USB interrupt source discrimination register 1 (USBIR1) USB interrupt source discrimination register 2 (USBIR2) Interrupt control register 1 (ICON1) Fig. 10 Memory map of special function register (SFR) 10 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. [Pull-up control] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. [Port P1P3 control] P1P3C By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, and P37 by program. Then, set "1" to each bit 6 of the port P3 direction register and port P3 register. b7 b0 Pull-up control register (PULL: address 0016 16) P00 pull-up control bit P01 pull-up control bit P02, P03 pull-up control bit P04 - P07 pull-up control bit P30 - P33 pull-up control bit P34 pull-up control bit P35 pull-up control bit P37 pull-up control bit Note : Pins set to output ports are disconnected from pull-up control. Fig. 11 Structure of pull-up control register 0: Pull-up off 1: Pull-up on Initial value: FF16 b7 b0 Port P1P3 control register (P1P3C: address 0017 16) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level Not used (Do not write "1" to this bit) P10,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used Fig. 12 Structure of port P1P3 control register 11 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 3 I/O port function table Pin Name Input/output P00-P07 P10/RxD/DP11/TxD/D+ P12/SCLK P13/SDATA P14/CNTR0 P20/AN0- P27/AN7 P30-P35 P37/INT0 Note: Port P37 is CMOS/TTL level. I/O port P2 I/O port P3 I/O port P0 I/O port P1 I/O individual bits I/O format *CMOS compatible input level *CMOS 3-state output *USB input/output level when selecting USB function *CMOS compatible input level *CMOS 3-state output (Note) Non-port function Key input interrupt Serial I/O1 function input/output Serial I/O2 function input/output Timer X function input/output A-D conversion input Related SFRs Pull-up control register Serial I/O1 control register Serial I/O2 control register Timer X mode register A-D control register Diagram No. (1) (2) (3) (4) (5) (6) (7) (8) External interrupt input Interrupt edge selection register (9) 12 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Port P0 Pull-up control Direction register (2) Port P10 Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Receive enable bit Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Direction register Data bus Port latch Data bus Port latch P10,P12,P13 input level selection bit To key input interrupt generating circuit Serial I/O1 input (3) Port P11 P-channel output disable bit Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Transmit enable bit Direction register Data bus Port latch + D- input D- output USB output enable (internal signal) USB differential input Serial I/O1 output D+ input D+ output USB output enable (internal signal) (4) Port P12 SCLK pin selection bit Direction register (5) Port P13 Signals during the SDATA output action SDATA pin selection bit Direction register Data bus Port latch Data bus P10,P12,P13 input level selection bit Serial I/O2 clock output Serial I/O2 clock input Serial I/O2 clock output Port latch SDATA pin selection bit P10,P12,P13 input level selection bit Serial I/O2 clock input P10, P12, P13 input levels are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 13 Block diagram of ports (1) 13 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (6) Port P14 Direction register (7) Ports P20 - P27 (32-pin version: Ports P20 - P25) Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output CNTR0 interrupt input A-D conversion input Analog input pin selection bit (8) Ports P30 - P35 (32-pin version: Ports P30 - P34) Pull-up control Direction register (9) Port P37 (only for 36-pin version) Pull-up control Direction register Data bus Port latch Data bus Port latch P37/INT0 input level selection bit INT interrupt input P37 input level is switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 14 Block diagram of ports (2) 14 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupts Interrupts occur by 13 different sources : 3 external sources, 9 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. It becomes usable by switching CNTR0 and AD interrupt sources with bit 7 of the interrupt edge selection register, timer 2 and serial I/ O2 interrupt sources with bit 6, and timer X and key-on wake-up interrupt sources with bit 5. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Table 4 Interrupt vector address and priority Interrupt source Reset (Note 2) UART receive USB IN token UART transmit USB SETUP/OUT token Reset/Suspend/Resume Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. Notes on use When the active edge of an external interrupt (INT0, CNTR0) is set, the interrupt request bit may be set. Therefore, please take following sequence: 1. Disable the external interrupt which is selected. 2. Change the active edge in interrupt edge selection register. (in case of CNTR0: Timer X mode register) 3. Clear the set interrupt request bit to "0". 4. Enable the external interrupt which is selected. Vector addresses (Note 1) Priority 1 2 3 High-order Low-order Interrupt request generating conditions At reset input At completion of UART data receive At detection of IN token At completion of UART transmit shift or when transmit buffer is empty At detection of SETUP/OUT token or At detection of Reset/ Suspend/ Resume Remarks Non-maskable Valid in UART mode Valid in USB mode Valid in UART mode Valid in USB mode External interrupt (active edge selectable) External interrupt (valid at falling) STP release timer underflow FFFD16 FFFB16 FFF916 FFFC16 FFFA16 FFF816 INT0 Timer X Key-on wake-up Timer 1 Timer 2 Serial I/O2 CNTR0 A-D conversion BRK instruction 4 5 FFF716 FFF516 FFF616 FFF416 At detection of either rising or falling edge of INT0 input At timer X underflow At falling of conjunction of input logical level for port P0 (at input) 6 7 8 FFF316 FFF116 FFEF16 FFF216 FFF016 FFEE16 At timer 1 underflow At timer 2 underflow At completion of transmit/receive shift At detection of either rising or falling edge of CNTR0 input At completion of A-D conversion External interrupt (active edge selectable) Non-maskable software interrupt At BRK instruction execution 9 FFED16 FFEC16 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 15 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 15 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns "0" when read) (Do not write "1" to these bits) Timer X or key-on wake up interrupt selection bit 0 : Timer X 1 : Key-on wake up Timer 2 or serial I/O2 interrupt selection bit 0 : Timer 2 1 : Serial I/O2 CNTR0 or AD converter interrupt selection bit 0 : CNTR0 1 : AD converter b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) UART receive/USB IN token interrupt request bit UART transmit/USB SETUP/OUT token/ reset/Suspend/Resume interrupt request bit INT0 interrupt request bit Timer X or key-on wake up interrupt request bit Timer 1 interrupt request bit Timer 2 or serial I/O2 interrupt request bit CNTR0 or AD converter interrupt request bit 0 : No interrupt request issued Not used (returns "0" when read) 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) UART receive/USB IN token interrupt enable bit UART transmit/USB SETUP/OUT token/ reset/Suspend/Resume interrupt enable bit INT0 interrupt enable bit Timer X or key-on wake up interrupt enable bit Timer 1 interrupt enable bit Timer 2 or serial I/O2 interrupt enable bit CNTR0 or AD converter interrupt enable bit Not used (returns "0" when read) 0 : Interrupts disabled (Do not write "1" to this bit) 1 : Interrupts enabled Fig. 16 Structure of Interrupt-related registers 16 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying "L" level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports. Port PXx "L" level output PULL register bit 3 = "0" * P07 output ** Port P07 latch Falling edge detection Port P07 Direction register = "1" Key input interrupt request PULL register bit 3 = "0" * P06 output ** Port P06 latch Port P06 Direction register = "1" Falling edge detection PULL register bit 3 = "0" * P05 output ** Port P05 latch Port P05 Direction register = "1" Falling edge detection PULL register bit 3 = "0" * P04 output ** Port P04 latch Port P04 Direction register = "1" Falling edge detection PULL register bit 2 = "1" * P03 input ** Port P03 latch Port P03 Direction register = "0" Falling edge detection Port P0 Input read circuit PULL register bit 2 = "1" * P02 input ** Port P02 latch Port P02 Direction register = "0" Falling edge detection PULL register bit 1 = "1" * P01 input ** Port P01 latch Port P01 Direction register = "0" Falling edge detection PULL register bit 0 = "1" * P00 input ** Port P00 latch Port P00 Direction register = "0" Falling edge detection * P-channel transistor for pull-up ** CMOS output buffer Fig. 17 Connection example when using key input interrupt and port P0 block diagram 17 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timers The 7532 Group has 3 timers: timer X, timer 1 and timer 2. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches "0", an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to "1". b7 b0 Timer X mode register (TM : Address 002B16) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop Not used (return "0" when read) qTimer 1, Timer 2 Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always count the prescaler output and periodically sets the interrupt request bit. qTimer X Timer X can be selected in one of 4 operating modes by setting the timer X mode register. * Timer Mode The timer counts the signal selected by the timer X count source selection bit. * Pulse Output Mode The timer counts the signal selected by the timer X count source selection bit, and outputs a signal whose polarity is inverted each time the timer value reaches "0", from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the output of the CNTR0 pin is started with an "H" output. At "1", this output is started with an "L" output. When using a timer in this mode, set the port P14 direction register to output mode. * Event Counter Mode The operation in the event counter mode is the same as that in the timer mode except that the timer counts the input signal from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the timer counts the rising edge of the CNTR0 pin. When this bit is "1", the timer counts the falling edge of the CNTR0 pin. * Pulse Width Measurement Mode When the CNTR0 active edge switch bit is "0", the timer counts the signal selected by the timer X count source selection bit while the CNTR0 pin is "H". When this bit is "1", the timer counts the signal while the CNTR0 pin is "L". In any mode, the timer count can be stopped by setting the timer X count stop bit to "1". Each time the timer overflows, the interrupt request bit is set. Fig. 18 Structure of timer X mode register b7 b0 Timer count source set register (TCSS : Address 002E16) Timer X count source selection bit (Note) 0 : f(XIN)/16 1 : f(XIN)/2 Not used (return "0" when read) Note : To switch the timer X count source selection bit , stop the timer X count operation. Fig. 19 Timer count source set register 18 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data bus f(XIN)/16 f(XIN)/2 Timer X count source selection bit CNTR0 active edge switch bit "0" Prescaler X latch (8) Pulse width measurement mode Timer mode pulse output mode Prescaler X (8) Event counter mode Timer X count stop bit Timer X latch (8) Timer X (8) To timer X interrupt request bit To CNTR0 interrupt request bit P14/CNTR0 "1" CNTR0 active edge switch bit "1" Q Q "0" Port P14 latch Port P14 direction register Pulse output mode Toggle flip-flop R T Timer X latch write Pulse output mode Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) f(XIN)/16 Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 20 Block diagram of timer X, timer 1 and timer 2 19 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O qSerial I/O1 * Asynchronous serial I/O (UART) mode Serial I/O1 can be used as an asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation when serial I/O1 is in operation. Eight serial data transfer formats can be selected, and the transfer formats to be used by a transmitter and a receiver must be identical. Each of the transmit and receive shift registers has a buffer register Data bus Address (001816) OE Receive Buffer Register (the same address on memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the respective buffer registers. These buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession. By selecting "1" for continuous transmit valid bit (bit 2 of SIO1CON), continuous transmission of the same data is made possible. This can be used as a simplified PWM. Serial I/O1 control register Address (001A16) Receive buffer full flag (RBF) Receive interrupt request (RI) Character length selection bit P10/RXD ST Detector 7-bit 8-bit PE FE SP Detector Receive Shift Register 1/16 UART Control Register Address (001B16) Clock Control Circuit BRG count source selection bit XIN 1/4 Division ratio 1/(n+1) Baud Rate Generator Address (001C16) ST/SP/PA Generator 1/16 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) P11/TXD Character length selection bit Transmit Shift Register Transmit Buffer Register Continuous transmit valid bit Data bus Address (001816) Transmit buffer empty flag (TBE) Serial I/O1 status register Address (001916) Fig. 21 Block diagram of UART serial I/O Transmit/Receive Clock Transmit Buffer Register Write Signal TBE=0 TSC=0 TBE=1 Serial Output TXD ST D0 TBE=0 TBE=1 D1 SP ST D0 D1 TSC=1* SP Receive Buffer Register Read Signal 1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit * Generated at second bit in 2-stop -bit mode RBF=0 RBF=1 Serial Input RXD ST D0 D1 SP ST D0 D1 RBF=1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0. Fig. 22 Operation of UART serial I/O function 20 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Serial I/O1 control register] SIO1CON The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART control register] UARTCON The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P11/TxD pin. [UART status register] UARTSTS The read-only UART status register consists of seven flags (bits 0 to 6) which indicate the operating status of the UART function and various errors. This register functions as the UART status register (UARTSTS) when selecting the UART. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the UART status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 mode selection bits MOD1 and MOD0 (bit 7 and 6 of the Serial I/O1 control register ) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "8116" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the continuous transmit valid bit (bit 2) becomes "1". [Transmit/Receive buffer register] TB/RB The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7-bit, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator] BRG The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Transmit/Receive Clock Transmit Buffer Register Write Signal TBE=0 TSC=0 TBE=1 Serial Output TXD ST D0 D1 SP ST D0 D1 SP ST 1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit Notes 1 : When the serial I/O1 mode selection bits (b7, b6) is "10", the transmit enable bit is "1", and continuous transmit valid bit is "1", writing on the transmit buffer initiates continuous transmission of the same data. 2 : Select 0 for continuous transmit valid bit to stop continuous transmission. The TXD pin will stop at high level after completing transmission of 1 byte. 3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after completing transmission of 1 byte. Fig. 23 Continuous transmission operation of UART serial I/O 21 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER * Universal serial bus (USB) mode By setting bits 7 and 6 of the serial I/O1 control register (address 001A16) to "11", the USB mode is selected. This mode conforms to "Low Speed device" of USB Specification 1.0. In this mode serial I/O1 interrupt have 5 sources; USB in and out token receive, USB reset, suspend, and resume. The USB status/UART status register functions as the USB status register (USBSTS).There is the USBVREFOUT pin for the USB reference voltage output, and a D-line with 1.5 k external resistor can be pull up. USB mode block and USB transceiver block show in figures 24 and 25. Data bus 1.5 MHz XIN 6 MHz Address 001816 Receive buffer register RxRDY Digital PLL NRZI, bit stuffing decoder Receive shift register BSTFE SYNC decoder EOP Differential input and Single end input Bus state detection PID decoder Reset interrupt request PIDE RxPID OPID P10/DP11/D+ Suspend interrupt request USB transceiver Resume interrupt request Address comparative unit USBA Token interrupt request End pointer decoder Output data and I/O control CRC check RxEP CRCE NRZI, bit stuffing encoder USB transmit unit EOP generating unit CRC encoder Transmit shift register SYNC, PID generating unit Transmit buffer register Address 001816 Data bus TxRDY EP0BYTE EP1BYTE EP0PID EP1PID Fig. 24 USB mode block diagram Serial I/O1 control register MOD0 MOD1 USB control register USBVREFOUT output valid flag (initial value "0") Output enable signal Voltage input Output amplifier USBVREFOUT USB reference power source voltage Voltage input Internal D- output signal Internal D+ output signal Suspend OE (internal signal) D+/Doutput amplifier DD+ Signal for function stop Output enable signal + Differential input Single end input Single end input Fig. 25 USB transceiver block diagram 22 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Transmit buffer register (TB: address 001816) After setting data to address 001816, a content of the transmit buffer register transfers to the transmit shift register automatically. CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b7 b0 Receive buffer register (RB: address 001816) By reading data from address 001816, a content of the receive buffer register can be read out. CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear b7 b0 USB status register (USBSTS: address 001916) Transmit buffer empty flag 0: Buffer full 1: Buffer empty EOP detection flag 0: Not detected 1: Detect False EOP error flag 0: No error 1: False EOP error CRC error flag 0: No error 1: CRC error PID error flag 0: No error 1: PID error Bit stuffing error flag 0: No error 1: Bit stuffing error Summing error flag 0: No error 1: Summing error Receive buffer full flag 0: Buffer empty 1: Buffer full CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set Fig. 26 Structure of serial I/O1-related registers (1) 23 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 USB data toggle synchronization register (TRSYNC: address 001D16) Not used (return "1" when read) Sequence bit toggle flag 0: No toggle 1: Sequence toggle b7 b0 CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set USB interrupt source discrimination register 1 (USBIR1: address 001E16) Not used (return "1" when read) Endpoint determination flag 0: Endpoint 0 interrupt 1: Endpoint 1 interrupt b7 b0 CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear USB interrupt source discrimination register 2 (USBIR2: address 001F16) Not used (return "1" when read) Suspend request flag 0: No request 1: Suspend request USB reset request flag 0: No request 1: Reset request Not used (return "1" when read) Token PID determination flag 0: SETUP interrupt 1: OUT interrupt Token interrupt flag 0: No request 1: Token request b7 b0 CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear USB interrupt control register (USBICON: address 002016) Not used (return "1" when read) Endpoint 1 enable 0: Endpoint 1 invalid 1: Endpoint 1 valid USB reset interrupt enable 0: USB reset invalid 1: USB reset valid Resume interrupt enable 0: Resume invalid 1: Resume valid Token interrupt enable 0: Token invalid 1: Token valid USB enable flag 0: USB invalid 1: USB valid CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used Fig. 27 Structure of serial I/O1-related registers (2) 24 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 USB transmit data byte number set register 0 (EP0BYTE: address 002116) Set a number of data byte for transmitting with endpoint 0. CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used Not used (return "0" when read) b7 b0 USB transmit data byte number set register 1 (EP1BYTE: address 002216) Set a number of data byte for transmitting with endpoint 1. CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used Not used (return "0" when read) b7 b0 USB PID control register 0 (EP0PID: address 002316) Not used (return "1" when read) Endpoint 0 enable flag 0: Endpoint 0 invalid 1: Endpoint 0 valid Endpoint 0 PID selection flag 1xxx: IN token interrupt of DATA0/1 is valid 01xx: STALL handshake is valid for IN token 00xx: NACK handshake is valid for IN token xxx1: STALL handshake is valid for OUT token xx10: ACK handshake is valid for OUT token xx00: NACK handshake is valid for OUT token x: any data CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b4, b5, b6 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b7 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Clear b7 b0 USB PID control register 1 (EP1PID: address 002416) Not used (return "1" when read) Endpoint 1 PID selection flag 1x: IN token interrupt of DATA0/1 is valid 01: STALL handshake is valid for IN token 00: NACK handshake is valid for IN token x: any data b6 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b7 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Clear b7 b0 USB address register (USBA: address 002516) Set an address allocated by the USB host. CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used Not used (returns "1" when read) Fig. 28 Structure of serial I/O1-related registers (3) 25 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 USB sequence bit initialization register (INISQ1: address 002616) A sequence bit of endpoint 1 is initialized. CPU read: Disabled CPU write: Dummy Hardware read: Not used Hardware write: Not used b7 b0 USB control register (USBCON: address 002716) Not used (return "1" when read) USBVREFOUT output valid flag 0: Output off 1: Output on Remote wake up request flag 0: No request 1: Remote wake up request CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used CPU read: Disabled CPU write: Set Hardware read: Used Hardware write: Clear b7 b0 UART status register (UARTSTS: address 001916) Transmit buffer empty flag 0: Buffer full 1: Buffer empty Receive buffer full flag 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag 0: No error 1: Overrun error Parity error flag 0: No error 1: Parity error Framing error flag 0: No error 1: Framing error Summing error flag 0: No error 1: Summing error Not used (returns "1" when read) CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set b7 b0 Baud rate generator (BRG: address 001C16) This register is valid only when selecting the UART mode. A baud rate value is set. CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used Fig. 29 Structure of serial I/O1-related registers (4) 26 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 UART control register (UARTCON: address 001B16) Character length selection bit 0: 8 bits 1: 7 bits Parity enable bit 0: Parity checking disabled 1: Parity checking enabled Parity selection bit 0: Even parity 1: Odd parity Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits P-channel output disable bit 0: CMOS output 1: N-channel open-drain output Not used (returns "1" when read) CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b7 b0 Serial I/O1 control register (SIO1CON: address 001A16) BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 Not used (returns "1" when read) Continuous transmit valid bit 0: Continuous transmit invalid 1: Continuous transmit valid Transmit interrupt source selection bit 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit 0: Transmit disabled 1: Transmit enabled Receive enable bit 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bits 00: I/O port 01: Not available 10: UART mode 11: USB mode Fig. 30 Structure of serial I/O1-related registers (5) CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used 27 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note on using USB mode Handling of SE0 signal in program (at receiving) 7532 group has the border line to detect as USB RESET or EOP (End of Packet) on the width of SE0 (Single Ended 0). A response apposite to a state of the device is expected. The name of the following short words which is used in table 5 shows as follow. *TKNE: Token interrupt enable (bit 6 of address 2016) *RSME: Resume interrupt enable (bit 5 of address 2016) *RSTE: USB reset interrupt enable (bit 4 of address 2016) *Spec: A response of the device requested by USB Specification 1.0 *SIE: Hardware operation in 7532 group *F/W: Recommendation process in the program *FEOPE: False EOP error flag (bit 2 of address 1916) *RxPID: Token interrupt flag (bit 7 of address 1F16) Table 5 Relation of the width of SE0 and the state of the device State of device End of Token in transaction End of data or handshake in transaction TKNE = 1 TKNE = 0 RSME = 0 RSME = 0 RSTE =1 RSTE = 0 or 1 Ignore Not detected as EOP(in case of no detection EOP, SIE returns idle state as time out. FEOPE flag is set.) Not acknowledge EOP Token interrupt request Token interrupt processing execute EOP or Reset may determine as EOP and Reset interrupt RxPID = 1> Token interrupt processing RxPID = 0> Reset interrupt processing Reset Reset interrupt request Reset processing Ignore Not detected as EOP(in case of no detection EOP, SIE returns idle state as timeup. FEOPE flag is set.) Wait for the next EOP flag EOP Set EOP flag After checking the set of EOP flag, go to the next processing EOP or Reset may determine as EOP and Reset interrupt Continue the processing in case of no interrupt request Reset processing in case of interrupt request Reset Reset interrupt request Reset processing F/W Reset interrupt processing Resume interrupt processing Idle state TKNE = X Width of SE0 RSME = 0 RSTE =1 Spec 0 sec. 0.5 sec. Ignore Keep counting suspend timer SIE Suspend state TKNE = 0 RSME = 1 RSTE = 0 Spec Reset or resume F/W Spec 0.5 sec. 2.5 sec. F/W Spec SIE 2.5 sec. 2.67 sec. F/W SIE Not acknowledge Keep alive Initialize suspend timer count value Not acknowledge SIE Keep alive or Reset may determine as keep alive and Reset interrupt Keep alive in case of no interrupt request Reset processing in case of interrupt request Reset Reset interrupt request Reset processing Reset interrupt request Spec 2.67 sec. SIE F/W 28 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER qSerial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control various serial I/O functions. * For receiving, set "0" to bit 3. * When receiving, bit 7 is cleared by writing dummy data to serial I/ O2 register after shift is completed. * Bit 7 is set earlier a half cycle of shift clock than completion of shift operation. Accordingly, when checking shift completion by using this bit, the setting is as follows: (1) check that this bit is set to "1", (2) wait a half cycle of shift clock, (3) read/write to serial I/O2 register. b7 b0 Serial I/O2 control register (SIO2CON: address 003016) Internal synchronous clock selection bits 000 : f(XIN)/8 001 : f(XIN)/16 010 : f(XIN)/32 011 : f(XIN)/64 110 : f(XIN)/128 111 : f(XIN)/256 SDATA pin selection bit (Note) 0 : I/O port/SDATA input 1 : SDATA output Not used (returns "0" when read) Transfer direction selection bit 0 : LSB first 1 : MSB first SCLK pin selection bit 0 : External clock (SCLK is an input) 1 : Internal clock (SCLK is an output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed Note : When using it as an SDATA input, set the port P13 direction register to "0". Fig. 31 Structure of serial I/O2 control registers Data bus 1/8 1/16 Divider 1/32 1/64 1/128 1/256 XIN SCLK pin selection bit "1" "0" Internal synchronous clock selection bits SCLK SCLK pin selection bit "0" P12/SCLK "1" P12 latch Serial I/O counter 2 (3) Serial I/O2 interrupt request SDATA pin selection bit "0" P13/SDATA "1" P13 latch SDATA pin selection bit Serial I/O shift register 2 (8) Fig. 32 Block diagram of serial I/O2 29 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 operation By writing to the serial I/O2 register(address 003116) the serial I/O2 counter is set to "7". After writing, the SDATA pin outputs data every time the transfer clock shifts from a high to a low level. And, as the transfer clock shifts from a low to a high, the SDATA pin reads data, and at the same time the contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. * Serial I/O2 counter is cleared to "0". * Transfer clock stops at an "H" level. * Interrupt request bit is set. * Shift completion flag is set. Also, the SDATA pin is in a high impedance state after the data transfer is complete (refer to figure 33). When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the SDATA pin is not in a high impedance state on the completion of data transfer. Synchronous clock Transfer clock Serial I/O2 register write signal (Note) SDATA at serial I/O2 output transmit SDATA at serial I/O2 input receive D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 interrupt request bit set Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA pin is set to the input mode, the SDATA pin is in a high impedance state after the data transfer is completed. Fig. 33 Serial I/O2 timing (LSB first) 30 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D Converter The functional blocks of the A-D converter are described below. [A-D conversion register] AD The A-D conversion register is a read-only register that stores the result of A-D conversion. Do not read out this register during an A-D conversion. [A-D control register] ADCON The A-D control register controls the A-D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during A-D conversion, and changes to "1" at completion of A-D conversion. A-D conversion is started by setting this bit to "0". [Comparison voltage generator] The comparison voltage generator divides the voltage between VSS and VREF by 1024 by a resistor ladder, and outputs the divided voltages. Since the generator is disconnected from VREF pin and VSS pin, current is not flowing into the resistor ladder. [Channel Selector] The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A-D conversion register. When A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A-D conversion. b7 b0 A-D control register (ADCON : address 003416) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 111 : P27/AN7 Not used (returns "0" when read) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read) Fig. 34 Structure of A-D control register Read 8-bit (Read only address 003516) b7 (Address 003516) b9 b8 b7 b6 b5 b4 b3 b0 b2 Read 10-bit (read in order address 003616, 003516) b7 (Address 003616) b7 (Address 003516) b7 b6 b5 b4 b3 b2 b1 b9 b0 b8 b0 b0 High-order 6-bit of address 003616 returns "0" when read. Fig. 35 Structure of A-D conversion register Data bus b7 A-D control register (Address 0034 16) 3 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 A-D control circuit Channel selector b0 A-D interrupt request A-D conversion register (high-order) Comparator (Address 0036 16) (Address 0035 16) A-D conversion register (low-order) 10 Resistor ladder VREF Fig. 36 Block diagram of A-D converter VSS 31 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 003916), the watchdog timer H is set to "FF16" and the watchdog timer L is set to "FF16". Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is "0", the count source becomes a watchdog timer L underflow signal. The detection time is 174.763 ms at f(XIN)=6 MHz. When this bit is "1", the count source becomes f(XIN)/16. In this case, the detection time is 683 s at f(XIN)=6 MHz. This bit is cleared to "0" after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address 003916). When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to "1", it cannot be changed to "0" by program. This bit is cleared to "0" after reset. Data bus Write "FF16" to the watchdog timer control register Watchdog timer L (8) 1/16 Write "FF16" to the watchdog timer control register "0" "1" Watchdog timer H (8) XIN Watchdog timer H count source selection bit STP Instruction Disable Bit STP Instruction Reset circuit Internal reset RESET Fig. 37 Block diagram of watchdog timer b7 b0 Watchdog timer control register(address 0039 16) WDTCON Watchdog timer H (read-only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 Fig. 38 Structure of watchdog timer control register 32 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Circuit ______ Poweron Power source voltage 0V Reset input voltage 0V (Note) The microcomputer is put into a reset status by holding the RESET pin at the "L" level for 15 s or more when the power source voltage is 4.1 to 5.5 V and XIN is in stable oscillation. ______ After that, this reset status is released by returning the RESET pin to the "H" level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address. Note that the reset input voltage should be 0.82 V or less when the power source voltage passes 4.1 V. RESET VCC 0.2 VCC Note : Reset release voltage Vcc = 4.1 V RESET VCC Power source voltage detection circuit Fig. 39 Example of reset circuit Clock from built-in ring oscillator RESET RESETOUT SYNC Address Data ? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD ADH,ADL ADH Reset address from the vector table 8-13 clock cycles Notes 1 : A built-in ring oscillator applies about 250 kHz frequency as clock at average of Vcc = 5 V. 2 : The mark "?" means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET Fig. 40 Timing diagram at reset 33 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Pull-up control register (6) Transmit/Receive buffer register (7) USB status/UART status register (8) Serial I/O1 control register (9) UART control register (10) USB data toggle synchronization register (11) USB interrupt source discrimination register 1 (12) USB interrupt source discrimination register 2 (13) USB interrupt control register (14) USB transmit data byte number set register 0 (15) USB transmit data byte number set register 1 (16) USBPID control register 0 (17) USBPID control register 1 (18) USB address register (19) USB sequence bit initialization register (20) USB control register (21) Prescaler 12 (22) Timer 1 (23) Timer 2 (24) Timer X mode register (25) Prescaler X (26) Timer X (27) Timer count source set register (28) Serial I/O2 control register (29) A-D control register (30) MISRG (31) Watchdog timer control register (32) Interrupt edge selection register (33) CPU mode register (34) Interrupt request register 1 (35) Interrupt control register 1 (36) Processor status register (37) Program counter 000116 000316 000516 000716 001616 001816 001916 001A16 001B16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 003016 003416 003816 003916 003A16 003B16 003C16 003E16 (PS) (PCH) (PCL) X 1 0 0 0 1 1 0 1 0 0 0 0 0 1 X Register contents 0016 X X 0 0 0 0 0 0016 0016 FF16 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0216 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0016 0016 0 0 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 FF16 0116 0016 0016 FF16 FF16 0016 0016 1016 0016 0 1 1 1 1 1 1 0016 0 0 0 0 0 0 0 0016 0016 X X X X 1 X X Contents of address FFFD16 Contents of address FFFC16 Note X : Undefined Fig. 41 Internal status of microcomputer at reset 34 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. XIN XOUT qOscillation control * Stop mode When the STP instruction is executed, the internal clock stops at an "H" level and the XIN oscillator stops. At this time, timer 1 is set to "0116" and prescaler 12 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 12 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 12. When an external interrupt is accepted, oscillation is restarted but the internal clock remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. ______ So apply an "L" level to the RESET pin while oscillation becomes stable. * Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. When the STP status is released, prescaler 12 and timer 1 will start counting clock which is XIN divided by 16, so set the timer 1 interrupt enable bit to "0" before the STP instruction is executed. Note For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 12 after fully appreciating the oscillation stabilization time of the oscillator to be used. * Clock mode Operation is started by a built-in ring oscillator after releasing reset. A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the CPU mode register after releasing it. CIN COUT Fig. 42 External circuit of ceramic resonator XIN XOUT Open External oscillation circuit VCC VSS Fig. 43 External clock input circuit b7 b0 MISRG(Address 003816) Oscillation stabilization time set bit after release of the STP instruction 0: Set "0116" in timer1, and "FF16" in prescaler 12 automatically 1: Not set automatically Reserved bits (return "0" when read) (Do not write "1" to these bits) Not used (return "0" when read) Fig. 44 Structure of MISRG 35 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XIN Rf XOUT Rd Main clock division ratio selection bit Middle-speed, High-speed, double -speed mode 1/2 Ring oscillator mode 1/4 1/2 Prescaler 12 Timer 1 Main clock division ratio selection bit Middle-speed mode High-speed mode Double-speed mode Ring oscillator (Note) Timing (Internal clock) 1/8 Ring oscillator mode QS R STP instruction WIT instruction S R Q Q S R STP instruction Reset Interrupt disable flag l Interrupt request Note: Ring oscillator is used only for starting. Fig. 45 Block diagram of system clock generating circuit (for ceramic resonator) 36 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. NOTES ON USE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. Handling of USBVREFOUT Pin In order to prevent the instability of the USBVREFOUT output due to external noise, connect a capacitor as bypass capacitor between USBVREFOUT pin and GND pin (VSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor, a ceramic or electrolytic capacitor of 0.1 F is recommended. Decimal Calculations * For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor. Timers * When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When a count source of timer X is switched, stop a count of timer X. Ports * The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. * Set "1" to each bit 6 of the port P3 direction register and the port P3 register. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500kHz or more during A-D conversion. Do not execute the STP instruction during A-D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. 37 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 6 Special programming adapter Package Name of Programming Adapter 36P2R-A PCA7535FP The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 46 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150 C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 46 Programming and testing of One Time PROM version 38 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 7 Absolute maximum ratings Parameter Symbol VCC VI VI VI VO Pd Topr Tstg Power source voltage Input voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature P00-P07, P10-P14, P20-P27, P30- P35, P37, VREF ____________ Conditions Ratings -0.3 to 7.0 -0.3 to VCC + 0.3 Unit V V V V V mW C C RESET, XIN CNVSS (Note 1) P00-P07, P10-P14, P20-P27, P30- P35, P37, XOUT, USBVREFOUT All voltages are based on VSS. Output transistors are cut off. -0.3 to VCC + 0.3 -0.3 to 13 -0.3 to VCC + 0.3 Ta = 25C 300 (Note 2) -20 to 85 -40 to 125 Notes 1: It is a rating only for the One Time PROM version. Connect to VSS for the Mask ROM version. 2: 200 mW for 32-pin version. 39 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Recommended Operating Conditions Table 8 Recommended operating conditions (VCC = 4.1 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VSS VREF VIH VIH VIH VIH VIL VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Power source voltage Power source voltage Analog reference voltage "H" input voltage "H" input voltage (TTL input level selected) "H" input voltage "H" input voltage "L" input voltage "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage "L" input voltage "H" total peak output current (Note 1) "L" total peak output current (Note 1) "L" total peak output current (Note 1) "H" total average output current (Note 1) "L" total average output current (Note 1) "L" total average output current (Note 1) "H" peak output current (Note 2) "L" peak output current (Note 2) "L" peak output current (Note 2) "H" average output current (Note 3) "L" average output current (Note 3) "L" average output current (Note 3) Internal clock oscillation frequency (Note 4) at ceramic oscillation or external clock input P00-P07, P10-P14, P20-P27, P30-P35, P37 P10, P12, P13, P37 ____________ Parameter f(XIN) = 6 MHz Limits Min. 4.1 2.0 0.8 VCC 2.0 0.8 VCC 2.0 0 0 0 0 0 Typ. 5.0 0 VCC VCC VCC VCC 3.6 0.3 VCC 0.8 0.2 VCC 0.8 0.16VCC -80 80 60 -40 40 30 -10 10 30 -5 5 15 6 Max. 5.5 Unit V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz RESET, XIN D+, DP00-P07, P10-P14, P20-P27, P30-P35, P37 P10, P12, P13, P37 ____________ RESET, CNVSS D+, DXIN P00-P07, P10-P14, P20-P27, P30-P35, P37 P00-P07, P10-P14, P20-P27, P37 P30-P35 P00-P07, P10-P14, P20-P27, P30-P35, P37 P00-P07, P10-P14, P20-P27, P37 P30-P35 P00-P07, P10-P14, P20-P27, P30-P35, P37 P00-P07, P10-P14, P20-P27, P37 P30-P35 P00-P07, P10-P14, P20-P27, P30-P35, P37 P00-P07, P10-P14, P20-P27, P37 P30-P35 VCC = 4.1 to 5.5 V Double-speed mode Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50 %. 40 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Electrical Characteristics Table 9 Electrical characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P35, P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.1 to 5.5 V IOH = -1.0 mA VCC = 4.1 to 5.5 V VOH "H" output voltage D+, DVCC = 4.40 to 5.25 V Pull-down through 15k 5% for D+, DPull-up through 1.5k 5% by USBVREFOUT for D- (Ta = 0 to 70 C) IOL = 5 mA VCC = 4.1 to 5.5 V IOL = 1.5 mA VCC = 4.1 to 5.5 V VOL "L" output voltage D+, DVCC = 4.40 to 5.25 V Pull-down through 15k 5% for D+, DPull-up through 1.5k 5% by USBVREFOUT for D- (Ta = 0 to 70 C) IOL = 15 mA VCC = 4.1 to 5.5 V IOL = 1.5 mA VCC = 4.1 to 5.5 V VT+-VT- VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis Hysteresis Hysteresis Hysteresis "H" input current D+, D- CNTR0, INT0 (Note 2), P00-P07(Note 3) RXD, SCLK, SDATA (Note 2) RESET P00-P07, P10-P14, P20-P27, P30-P35, P37 RESET XIN P00-P07, P10-P14, P20-P27, P30-P35, P37 RESET, CNVSS XIN P00-P07, P30-P35, P37 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors"on") -4 -0.2 -0.5 4 -5.0 0.15 0.4 0.5 0.5 5.0 Limits Min. VCC-1.5 VCC-1.0 2.8 3.6 Typ. Max. Unit V V V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 1.5 0.3 0.3 V V V VOL "L" output voltage P30-P35 2.0 0.3 V V V V V V A A A A A A mA IIH IIH IIL "H" input current "H" input current "L" input current 5.0 IIL IIL IIL "L" input current "L" input current "L" input current -5.0 When clock stopped VRAM RAM hold voltage 2.0 V 5.5 Note 1: P11 is measured when the P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD, SCLK, SDATA, and INT0 have hysteresises only when bits 0 and 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake-up. 41 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 10 Electrical characteristics (2) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ICC Parameter Power source current Test conditions Double-speed mode, f(XIN) = 6 MHz Output transistors "off" f(XIN) = 6 MHz (in WIT state) Output transistors "off" Increment when A-D conversion is executed f(XIN) = 6 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors "off" VCC = 4.40 to 5.25 V Oscillation stopped in USB mode USB (SUSPEND), (pull-up resistor output not included) (Fig. 47) Ta = 25 C Ta = 85 C Ta = 0 to 70 C Limits Min. Typ. 6 1.6 0.8 0.1 1.0 10 300 Max. 10 3.2 Unit mA mA mA A A A A-D Converter Characteristics Table 11 A-D Converter characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- -- VOT VFST tCONV RLADDER IVREF Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current A-D port input current VREF = 5.0 V VREF = 3.0 V II(AD) 50 30 55 150 70 200 120 5.0 VCC = 4.1 to 5.5 V Ta = 25 C VCC = 4.1 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 5.12 V 0 5105 5 5115 Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 20 5125 122 Unit Bits LSB LSB mV mV tc(XIN) k A A VCC ICC VCC USBVREFOUT 1.5 k D15 k VSS IOUT Rating value = ICC - IOUT Fig. 47 Power source current measurement circuit in USB mode at oscillation stop 42 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing Requirements Table 12 Timing requirements (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ____________ Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0 input "H" pulse width CNTR0, INT0 input "L" pulse width Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Limits Min. 15 166 70 70 200 80 80 1000 400 400 200 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SDATA) th(SCLK-SDATA) Switching Characteristics Table 13 Switching characteristics (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SDATA) tv(SCLK-SDATA) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) tr(D+), tr(D-) tf(D+), tf(D-) Parameter Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note) CMOS output falling time (Note) USB output rising time, CL = 350 pF, Ta = 0 to 70 C USB output falling time, CL = 350 pF, Ta = 0 to 70 C 100 100 10 10 200 200 0 30 30 30 30 300 300 Limits Min. tC(SCLK)/2-30 tC(SCLK)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns Notes: XOUT pin is excluded. Measured output pin 100 pF CMOS output Fig. 48 Output switching characteristics measurement circuit 43 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0 0.8VCC tWH(INT) tWL(INT) 0.2VCC INT0 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(SCLK) tf tWL(SCLK) 0.2VCC tsu(SDATA-SCLK) tr 0.8VCC tWH(SCLK) SCLK th(SCLK-SDATA) SDATA(at receive) td(SCLK-SDATA) 0.8VCC 0.2VCC tv(SCLK-SDATA) SDATA(at transmit) tf tr 0.1V0H 0.9V0H D+, DFig. 49 Timing chart 44 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MARK SPECIFICATION FORM 36P2R-A (36-PIN SHRINK SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 36 19 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 1 18 B. Customer's Parts Number + Mitsubishi catalog name 36 19 Mitsubishi lot number (6-digit or 7-digit) 1 18 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 11 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required . , C. Special Mark Required 36 19 1 18 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required 3 : The standard Mitsubishi font is used for all characters except for a logo. 45 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 32P6B-A (32-PIN LQFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 24 25 17 16 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (4-digit or 5-digit) 32 1 8 9 B. Customer's Parts Number + Mitsubishi catalog name 17 16 24 25 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 7 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c),. (periods), (commas) are usable. , 32 1 8 9 46 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 36P2R-A EIAJ Package Code SSOP36-P-450-0.80 JEDEC Code - Weight(g) 0.53 Lead Material Alloy 42 Plastic 36pin 450mil SSOP e 36 19 b2 HE E F e1 Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.5 0.4 0.35 0.2 0.15 0.13 15.2 15.0 14.8 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - 0.15 - - 0 - 10 - 0.5 - - 11.43 - - - 1.27 1 18 A D A2 A1 L1 e y b A A1 A2 b c D E e HE L L1 y b2 e1 I2 Detail F L c I2 47 MITSUBISHI MICROCOMPUTERS 7532 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 32P6B-A EIAJ Package Code LQFP32-P-77-0.80 JEDEC Code - Weight(g) Lead Material Alloy 42 Plastic 32pin 7!7mm body LQFP MD 32 25 b2 HD D e I2 1 24 Recommended Mount Pad E HE Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME 8 17 9 16 A L1 e F b A1 y L Detail F Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.3 0.35 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.1 - - 0 10 - 0.5 - - 1.0 - - - - 7.4 - - 7.4 A2 Keep safety first in your circuit designs! * Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials * * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. * * * * (c) 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Jul. 1999. Specifications subject to change without notice. 48 c ME REVISION DESCRIPTION LIST Rev. No. 1.0 1.1 First Edition Revision Description 7532 Group DATA SHEET Rev. date 970822 981218 All pages; "PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change." eliminated. Page 4; Page 5; Fig. 3; "Under development" eliminated. Central Processing Unit (CPU); The name of manual, 740 Family Software Manual, is revised. Fig. 4; The bit name is revised. Bits 6 and 7 explanations of CPU mode register are revised. Fig. 5; Explanation is added. Page 6; Page 7 Page 8 Special page; Some words are corrected. Fig. 7 ; Some register names are revised. [Direction register] PiD; The sentence is revised. Pins set to output are floating. Fig. 9; The Figure title is revised. Page 12; Interrupts; Explanation is revised. The period is added. Interrupt operation; The order of operation is revised. Table 4: Remarks is revised. Some words are corrected. Page 17; Serial I/O; Some words and the pin name position are revised. Page 18; The register name is revised. [UART status register] UARTSTS Fig. 20; Some words are corrected. Page 21 to Page 24; Some words are corrected. Page 26; Serial I/O2; Some words are corrected. Fig. 29; Explanation is revised. Page 28; [A-D conversion register]AD; The sentence is revised.Do not read out during an A-D conversion. Page 29; Fig. 35; The sentence is revised.read-only for high-order 6-bit Page 30; Fig. 37; The period is added. Page 32; * Wait mode; The sentence is revised. When the STP status is released, prescaler 12 and timer 1 will start counting clock which is XIN divided by 16,..... Page 34; One Time PROM Version; The sentences are revised. To improve the noise reduction, connect a track between CNMSS pin and VSS pin... The mask ROM version track of CNVSS pin has no operational interference... Page 36; Absolute Maximum Ratings; Parameter of input voltage is revised. Note is revised. Page 37; Recommended operating conditions; Limits of "H" input voltage is revised. (1/2) REVISION DESCRIPTION LIST Rev. No. 1.1 Page 38; Electrical characteristics; Test conditions of VOH and VOL are revised. Some of VOL are eliminated partly. Hysteresis is added. Revision Description 7532 Group DATA SHEET Rev. date 981218 Page 39; Electrical characteristics; Test condition is added. A-D Converter Characteristics; Some of VOT and VFST are eliminated partly. Page 40; Switching characteristics; Title and Table title are revised. Limits of tC(XIN), tWH(XIN), tWL(XIN). Figure is added. 2.0 2.1 Most of the contents (Functional Description, Electrical characteristics, and so on) are updated. 990723 Page 2; Fig. 2 Pin configuration of M37532M4-XXXGP; Pin functions revised. Pin 26: P10/RxD/D- (correct) Pin 27: P11/TxD/D+ (correct) 2.2 Updated as follows: *Page 1; Power dissipation to 30 mW *Page 9; Fig. 9; Start address of Interrupt vector area to FFEC16 *Page 42, Table 11; Parameter to Linearity error from former Absolute accuracy 2.3 Page 30; Fig.33 Note revised Page 33; Description revised; RESET "L" pulse width 2 s 15 s Page 42, Table 11 Linearity error; "excluding quantization error" deleted Page 43; Table 12 tw(RESET) revised; 2 15 000614 991110 991015 (2/2) |
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