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EL4581
Data Sheet August 16, 2002 FN7172
Sync Separator, 50% Slice, S-H, Filter
The EL4581 extracts timing information from standard negative going video sync found in NTSC, PAL, and SECAM broadcast systems. It can also be used in non standard formats and with computer graphics systems at higher scan rates, by adjusting a single external resistor. When the input does not have correct serration pulses in the vertical interval, a default vertical output is produced. Outputs are composite sync, vertical sync, burst/back porch output, and odd/even output. The later operates only in interlaced scan formats. The EL4581 provides a reliable method of determining correct sync slide level by setting it to the mid-point between sync tip and blanking level at the back porch. This 50% level is determined by two internal self timing sample and hold circuits that track sync tip and back porch levels. This also provides a degree of hum and noise rejection to the input signal, and compensates for varying input levels of 0.5P-P to 2.0VP-P. A built in linear phase, third order, low pass filter attenuates the chroma signal in color systems to prevent incorrectly set color burst from disturbing the 50% sync slide. This device may be used to replace the industry standard LM1881, offering improved performance and reduced power consumption. The EL4581 video sync separator is manufactured using Elantec's high performance analog CMOS process.
Features
* NTSC, PAL and SECAM sync separation * Single supply, +5V * Precision 50% slicing, internal caps * Built-in color burst filter * Decodes non-standard verticals * Pin compatible with LM1881 * Low power * Typically 1.5mA supply current * Resistor programmable scan rate * Few external components * Available in 8-pin PDIP and SO packages
Applications
* Video special effects * Video test equipment * Video distribution * Displays * Imaging * Video data capture * Video triggers
Ordering Information
PART NUMBER EL4581CN EL4581CS TEMP. RANGE -40C to +85C -40C to +85C PACKAGE 8-Pin PDIP 8-Pin SO PKG. NO. MDP0031 MDP0027
Pinout
EL4581 (8-Pin SO, DIP) TOP VIEW
COMPOSITE SYNC OUT COMPOSITE VIDEO IN VERTICAL SYNC OUT GND
1 2 3 4
8 7 6 5
VDD 5V ODD/EVEN OUTPUT RSET BURST/BACK PORCH OUTPUT
Demo Board
A dedicated demo board is not available. However, this device can be placed on the EL4584/5 Demo Board.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303. Manufactured under License, U.S. Patents 5,486,869; 5,754,250.
1
EL4581
Absolute Maximum Ratings (TA = 25 C)
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER IDD Clamp Voltage Discharge Current Clamp Charge Current Ref Voltage VOL Output Low Voltage VOH Output High Voltage
Unless otherwise state VDD = 5V, TA = 25C, RSET = 680k. DESCRIPTION TEMP 25C 25C 25C 25C 25C 25C 25C 25C 4 2.4 MIN 0.75 1.3 6 2 1.5 TYP 1.7 1.5 10 3 1.8 2.1 800 MAX 3 1.9 20 UNIT mA V A mA V mV V V
VDD = 5V (Note 1) Pin 2, Unloaded Pin 2 = 2V Pin 2, VIN = 1V Pin 6, VDD = 5V (Note 2) IOL = 1.6mA IOH = -40A IOH = -1.6mA
NOTES: 1. No video signal, outputs unloaded. 2. Tested for VDD 5V 5% which guarantees timing of output pulses over this range.
Dynamic Specifications
PARAMETER Vertical Sync Width, tVS Burst/Back Porch Width, tB Vertical Sync Default Delay tVSD Filter Attenuation Composite Sync Prop Delay Input Dynamic Range Slice Level
VDD = 5V, IVpk-pk video, TA = 25C, CL = 15pF, IOH = -1.6mA, IOL = 1.6mA. Signal voltages are peak to peak. DESCRIPTION (Note 1) (Note 1) TEMP 25C 25C 25C FIN = 3.4MHz (Note 2) VIN- Composite Sync (Note 1) p-p NTSC Signal (Note 3) Input Voltage = 1VP-P (Note 4) 25C 25C 25C 25C Full 0.5 40% 40% 50% 50% MIN 190 2.5 40 TYP 230 3.5 55 24 260 400 2 60% 60% MAX 300 4.5 70 UNIT s s s dB ns V
NOTES: 1. C/S, Vertical and Burst outputs are all active low - VOH = 2.4V, VOL = 0.8V. 2. Attenuation is a function of RSET (PIN6). 3. Typical min. is 0.3VP-P. 4. Refers to threshold level of sync. tip to back porch amplitude.
2
EL4581
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME Composite Sync Out Composite Video in Vertical Sync Out GND Burst/Back Porch Output RSET (Note 1) Odd/Even Output VDD 5V FUNCTION Composite sync pulse output. Sync pulses start on a falling edge and end on a rising edge. AC coupled composite video input. Sync tip must be at the lowest potential (Positive picture phase). Vertical sync pulse output. The falling edge of Vert Sync is the start of the vertical period. Supply ground. Burst/Back porch output. Low during burst portion of composite video. An external resistor to ground sets all internal timing. 681k, 1% resistor will provide correct timing for NTSC signals. Odd/Even field output. Low during odd fields, high during even fields. Transitions occur at start of Vert Sync pulse. Positive supply. (5V)
NOTE 1. RSET must be a 1% resistor.
3
EL4581 Typical Performance Curves
RSET vs Horizontal Frequency Back Porch Clamp On Time vs RSET Vertical Pulse Width vs RSET
Vertical Default Delay Time vs RSET
Vertical Pulse Width vs Temperature
Supply Current vs Temperature
Input Signal = 300mVP-P EL4581 Filter Characteristic Constant Delay 240ns
1.8 1.6 Power Dissipation (W)
Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
2 1.8 1.6 Power Dissipation (W)
Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board
1.4 1.25W 1.2 1 781mW 0.8 0.6 0.4 0.2 0 0 25
1.471W
PDIP8 JA=100C/W
1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.136
PDIP8 JA=85C/W
SO8 JA=160C/W 50 75 85 100 125 150
SO8 JA=110C/W
0
25
50
75 85 100
125
150
Ambient Temperature (C)
Ambient Temperature (C)
4
EL4581 Timing Diagrams
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).
FIGURE 1.
5
EL4581 Timing Diagrams
(Continued)
FIGURE 2.
6
EL4581 Timing Diagrams
(Continued)
FIGURE 3.
FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL
7
EL4581 Description of Operation
A simplified block schematic is shown in Figure 2. The following description is intended to provide the user with sufficient information to be able to understand the effects that the external components and signal conditions have on the outputs of the integrated circuit. The video signal is AC coupled to pin 2 via the capacitor C1, nominally 0.1F. The clamp circuit A1 will prevent the input signal on pin 2 going any more negative than 1.5V, the value of reference voltage VR1. Thus the sync tip, the most negative part of the video waveform, will be clamped at 1.5V. The current source I1, nominally 10A, charges the coupling capacitor during the remaining portion of the H line, approximately 58s for a 15.75kHz timebase. From I * t = C * V, the video time-constant can be calculated. It is important to note that the charge taken from the capacitor during video must be replaced during the sync tip time, which is much shorter, (ratio of x 12.5). The corresponding current to restore the charge during sync will therefore be an order of magnitude higher, and any resistance in series with CI will cause sync tip crushing. For this reason, the internal series resistance has been minimized and external high resistance values in series with the input coupling capacitor should be avoided. The user can exercise some control over the value of the input time constant by introducing an external pull-up resistance from pin 2 to the 5V supply. The maximum voltage across the resistance will be VDD less 1.5V, for black level. For a net discharge current greater than zero, the resistance should be greater than 450k. This will have the effect of increasing the time constant and reducing the degree of picture tilt. The current source I1 directly tracks reference current ITR and thus increases with scan rate adjustment, as explained later. The signal is processed through an active 3 pole filter (F1) designed for minimum ripple with constant phase delay. The filter attenuates the color burst by 24dB and eliminates fast transient spikes without sync crushing. An external filter is not necessary. The filter also amplifies the video signal by 6dB to improve the detection accuracy. Note that the filter cut-off frequency is a function of RSET through IOT and is proportional to IOT. Internal reference voltages (block VREF) with high immunity to supply voltage variation are derived on the chip. Reference VR4 with op-amp A2 forces pin 6 to a reference voltage of 1.7V nominal. Consequently, it can be seen that the external resistance RSET will determine the value of the reference current ITR. The internal resistance R3 is only about 6k, much less than RSET. All the internal timing functions on the chip are referenced to ITR and have excellent supply voltage rejection. Comparator C2 on the input to the sample and hold block (S/H) compares the leading and trailing edges of the sync. pulse with a threshold voltage VR2 which is referenced at a fixed level above the clamp voltage VR1. The output of C2 initiates the timing one-shots for gating the sample and hold circuits. The sample of the sync tip is delayed by 0.8s to enable the actual sample of 2s to be taken on the optimum section of the sync. pulse tip. The acquisition time of the circuit is about three horizontal lines. The double poly CMOS technology enables long time constants to be achieved with small high quality on-chip capacitors. The back porch voltage is similarly derived from the trailing edge of sync, which also serves to cut off the tip sample if the gate time exceeds the tip period. Note that the sample and hold gating times will track RSET through IOT. The 50% level of the sync tip is derived, through the resistor divider R1 and R2, from the sample and held voltages VTIP and VBP, and applied to the plus input of comparator C1. This comparator has built in hysteresis to avoid false triggering. The output of C2 is a digital 5V signal which feeds the C/S output buffer B1 and the other internal circuit blocks, the vertical, back porch and odd/even functions. The vertical circuit senses the C/S edges and initiates an integrator which is reset by the shorter horizontal sync pulses but times out the longer vertical sync. pulse widths. The internal timing circuits are referenced to IOT and VR3, the time-out period being inversely proportional to the timing current. The vertical output pulse is started on the first serration pulse in the vertical interval and is then self-timed out. In the absence of a serration pulse, an internal timer will default the start of vertical. The back porch is triggered from the sync tip trailing edge and initiates a one-shot pulse. The period of this pulse is again a function of IOT and will therefore track the scan rate set by RSET. The odd/even circuit (O/E) comprises of flip flops which track the relationship of the horizontal pulses to the leading edge of the vertical output, and will switch on every field at the start of vertical. Pin 7 is high during the odd field. Loss of video signal can be detected by monitoring the C/S output. The 50% level of the previous video signal will remain held on the S/H capacitors after the input video signal has gone and the input on pin 2 has defaulted to the clamp voltage. Consequently the C/S output will remain low longer than the normal vertical pulse period. An external timing circuit could be used to detect this condition.
8
EL4581 Block Diagram
*Note: RSET must be a 1% resistor.
FIGURE 5. STANDARD (NTSC INPUT) H. SYNC DETAIL
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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