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ST72F324L, ST72324BL 3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE Memories - 8 to 32K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and InCircuit Programming for HDFlash devices - 384 to 1K bytes RAM - HDFlash endurance: 100 cycles, data retention: 20 years at 55C Clock, Reset And Supply Management - Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock - PLL for 2x frequency multiplication - Four Power Saving Modes: Halt, Active-Halt, Wait and Slow Interrupt Management - Nested interrupt controller - 10 interrupt vectors plus TRAP and RESET - 9/6 external interrupt lines (on 4 vectors) Up to 32 I/O Ports - 32/24 multifunctional bidirectional I/O lines - 22/17 alternate function lines - 12/10 high sink outputs 4 Timers - Main Clock Controller with: Real time base, Beep and Clock-out capabilities - Configurable watchdog timer - 16-bit Timer A with: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes - 16-bit Timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes TQFP44 10 x 10 TQFP32 7x7 SDIP32 400 mil 2 Communication Interfaces - SPI synchronous serial interface - SCI asynchronous serial interface 1 Analog Peripheral - 10-bit ADC with up to 12 input ports Instruction Set - 8-bit Data Manipulation - 63 Basic Instructions - 17 main Addressing Modes - 8 x 8 Unsigned Multiply Instruction Development Tools - Full hardware/software development package - In-Circuit Testing capability ST72324BL(J/K)4 ROM 16K Device Summary Features Program memory bytes RAM (stack) - bytes Voltage Range Temp. Range Packages ST72F324L(J/K)6 Flash 32K 1024 (256) ST72F324L(J/K)4 Flash 16K 512 (256) ST72F324L(J/K)2 Flash 8K ST72324BL(J/K)2 ROM 8K 384 (256) 384 (256) 512 (256) 2.85 to 3.6V up to -40C to +85C TQFP44 10x10, SDIP32, TQFP32 7x7 Rev. 3 January 2005 1/151 1 Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 4.3 4.4 4.5 4.6 4.7 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 5.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 24 24 25 25 6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 7.3 7.4 7.5 7.6 7.7 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 32 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 8.3 8.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 39 39 8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151. ... 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/151 2 Table of Contents 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 39 39 42 9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 9.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 45 46 48 48 48 48 48 50 50 50 50 50 51 51 51 53 53 53 53 65 65 65 66 73 73 73 73 77 78 80 80 81 84 84 84 3/151 1 Table of Contents 10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 100 101 101 101 102 104 104 105 105 105 105 105 106 106 107 12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 110 110 110 110 111 111 111 112 112 113 115 115 116 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.5.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 151 12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4/151 1 Table of Contents 12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 122 123 124 12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 130 12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 133 135 136 136 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 139 14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 141 14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.1.1 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 15.1.4 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5 ADC Conversion Spurious Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.6 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 148 148 148 148 149 149 15.2.1 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.3 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.3.1 Timer A Restrictions in Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.3.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.3.3 39-Pulse ICC Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 150 ... 5/151 1 ST72F324L, ST72324BL 1 INTRODUCTION The ST72F324L and ST72324BL devices are members of the ST7 microcontroller family designed for the 3V operating range. They can be grouped as follows: - The 32-pin devices are designed for mid-range applications - The 44-pin devices target the same range of applications requiring more than 24 I/O ports. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc- tion set and are available with FLASH or ROM program memory. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. Figure 1. Device Block Diagram 8-BIT CORE ALU RESET VPP VSS VDD CONTROL RAM (384 - 2048 Bytes) PROGRAM MEMORY (8K - 60K Bytes) WATCHDOG OSC1 OSC2 OSC ADDRESS AND DATA BUS MCC/RTC/BEEP PORT A PORT F PF7:6,4,2:0 (6 bits on J devices) (5 bits on K devices) TIMER A BEEP PORT E PE1:0 (2 bits) SCI PA7:3 (5 bits on J devices) (4 bits on K devices) PORT B PB4:0 (5 bits on J devices) (3 bits on K devices) PORT C TIMER B PORT D PC7:0 (8 bits) PD5:0 (6 bits on J devices) (2 bits on K devices) VAREF VSSA SPI 10-BIT ADC 6/151 3 ST72F324L, ST72324BL 2 PIN DESCRIPTION Figure 2. 44-Pin TQFP Package Pinouts RDI / PE1 PB0 PB1 PB2 PB3 (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 ei0 ei2 4 30 5 29 ei3 6 28 7 27 8 26 9 25 ei1 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 AIN5 / PD5 VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 VDD_0 VSS_0 PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12 eix associated external interrupt vector 7/151 ST72F324L, ST72324BL PIN DESCRIPTION (Cont'd) Figure 3. 32-Pin SDIP Package Pinout (HS) PB4 AIN0 / PD0 AIN1 / PD1 VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ICCDATA/ MISO / PC4 AIN14 / MOSI / PC5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei3 32 ei2 31 30 29 28 PB3 PB0 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) PA6 (HS) PA4 (HS) PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK (HS) 8mA high sink capability eix associated external interrupt vector ei1 27 26 25 24 23 22 21 20 ei0 19 18 17 Figure 4. 32-Pin TQFP 7x7 Package Pinout VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 32 31 30 29 28 27 26 25 24 1 ei3 ei2 23 2 22 3 ei1 21 4 20 5 19 6 18 7 ei0 17 8 9 10 11 12 13 14 15 16 AIN13 / OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ICCDATA / MISO / PC4 AIN14 / MOSI / PC5 ICCCLK / SCK / PC6 AIN15 / SS / PC7 (HS) PA3 PD1 / AIN1 PD0 / AIN0 PB4 (HS) PB3 PB0 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) PA6 (HS) PA4 (HS) (HS) 8mA high sink capability eix associated external interrupt vector 8/151 1 ST72F324L, ST72324BL PIN DESCRIPTION (Cont'd) For more details, refer to "ELECTRICAL CHARACTERISTICS" on page 110 Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: C = CMOS CT= CMOS with input trigger Output level: HS = high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog ports - Output: OD = open drain 2), PP = push-pull Refer to "I/O PORTS" on page 39 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description Pin n TQFP44 TQFP32 Type SDIP32 Pin Name Level Output Input Port Input float wpu ana int Main Output function (after reset) OD X X X X X X X X X X X X X PP X X X X X X X Port B4 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 ADC Analog Input 5 Alternate Function 6 30 1 7 31 2 8 32 3 9 10 11 12 13 1 14 2 15 3 16 4 17 18 5 19 6 8 9 4 5 6 7 PB4 (HS) PD0/AIN0 PD1/AIN1 PD2/AIN2 PD3/AIN3 PD4/AIN4 PD5/AIN5 VAREF VSSA PF0/MCO/AIN8 PF1 (HS)/BEEP PF2 (HS) PF4/OCMP1_A/ AIN10 PF6 (HS)/ICAP1_A PF7 (HS)/ EXTCLK_A VDD_0 VSS_0 PC0/OCMP2_B/ AIN12 PC1/OCMP1_B/ AIN13 I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT S S I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT S S I/O CT HS X X X X X X X ei3 X X X X X X Analog Reference Voltage for ADC Analog Ground Voltage X HS HS X X X HS HS X X X X X ei1 ei1 ei1 X X X X X X X X X X X X X X Port F0 Port F1 Port F2 Port F4 Port F6 Port F7 Timer A OutADC Analog put ComInput 10 pare 1 Timer A Input Capture 1 Timer A External Clock Source Main clock out (fOSC/2) ADC Analog Input 8 Beep signal output 20 7 10 21 22 23 8 11 Digital Main Supply Voltage Digital Ground Voltage X X X X X Port C0 Timer B OutADC Analog put ComInput 12 pare 2 Timer B OutADC Analog put ComInput 13 pare 1 24 9 12 I/O CT X X X X X Port C1 9/151 1 ST72F324L, ST72324BL Pin n TQFP44 TQFP32 Type SDIP32 Pin Name Level Output Input Port Input float wpu ana int OD 25 10 13 PC2 (HS)/ICAP2_B 26 11 14 PC3 (HS)/ICAP1_B 27 12 15 PC4/MISO/ICCDATA I/O CT I/O CT I/O CT HS HS X X X X X X X X X PP Main function Output (after reset) X X X Port C2 Port C3 Port C4 Alternate Function Timer B Input Capture 2 Timer B Input Capture 1 SPI Master In / Slave Out Data SPI Master Out / Slave In Data SPI Serial Clock SPI Slave Select (active low) ICC Data Input ADC Analog Input 14 ICC Clock Output ADC Analog Input 15 28 13 16 PC5/MOSI/AIN14 29 14 17 PC6/SCK/ICCCLK 30 15 18 PC7/SS/AIN15 31 16 19 PA3 (HS) 32 33 35 VDD_1 VSS_1 PA5 (HS) I/O CT I/O CT I/O CT I/O CT S S I/O CT I/O CT I/O CT I/O CT HS HS HS HS HS X X X X X X X ei0 X X X X X X X Port C5 Port C6 Port C7 Port A3 X X X Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X T T X X Port A4 Port A5 Port A6 1) Port A7 1) Must be tied low. In the flash programming mode, this pin acts as the programming voltage input VPP. See Section 12.9.2 for more details. High voltage must not be applied to ROM devices. Top priority non maskable interrupt. Digital Ground Voltage Resonator oscillator inverter output External clock input or Resonator oscillator inverter input Digital Main Supply Voltage X X X X X X X X ei2 ei2 ei2 ei2 X X X X X X X X X X X X Port E0 Port E1 Port B0 Port B1 Port B2 Port B3 SCI Transmit Data Out SCI Receive Data In 34 17 20 PA4 (HS) 36 18 21 PA6 (HS) 37 19 22 PA7 (HS) 38 20 23 VPP /ICCSEL I 39 21 24 RESET 40 22 25 VSS_2 41 23 26 OSC2 42 24 27 OSC1 43 25 28 VDD_2 44 26 29 PE0/TDO 1 27 30 PE1/RDI 2 28 31 PB0 3 4 PB1 PB2 I/O CT S O I S I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT 5 29 32 PB3 Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD 10/151 1 ST72F324L, ST72324BL are not implemented). See See "I/O PORTS" on page 39. and Section 12.8 I/O PORT PIN CHARACTERISTICS for more details. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details. 4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 11/151 1 ST72F324L, ST72324BL 3 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. Figure 5. Memory Map The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device. 0000h 007Fh 0080h HW Registers (see Table 2) 0080h Short Addressing RAM (zero page) 00FFh 0100h RAM (1024, 512 or 384 Bytes) 087Fh 0880h 256 Bytes Stack 01FFh 0200h Reserved 7FFFh 8000h 16-bit Addressing RAM 027Fh or 047Fh 8000h C000h E000h Program Memory (32K, 16K or 8K) FFDFh FFE0h FFFFh 32 KBytes 16 KBytes 8 Kbytes Interrupt & Reset Vectors (see Table 8) FFFFh 12/151 1 ST72F324L, ST72324BL Table 2. Hardware Register Map Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h to 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh to 0030h MCC MCCSR MCCBCR FLASH WATCHDOG SPIDR SPICR SPICSR ISPR0 ISPR1 ISPR2 ISPR3 EICR FCSR WDGCR Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDADR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Port F Option Register Reset Status 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W2) R/W2) R/W R/W R/W Port A 2) Port B 2) Port C Port D 2) Port E 2) Port F 2) Reserved Area (15 Bytes) SPI SPI Data I/O Register SPI Control Register SPI Control/Status Register Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register Flash Control/Status Register Watchdog Control Register Reserved Area (1 Byte) Main Clock Control / Status Register Main Clock Controller: Beep Control Register xxh 0xh 00h FFh FFh FFh FFh 00h 00h 7Fh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ITC 00h 00h R/W R/W Reserved Area (3 Bytes) 13/151 1 ST72F324L, ST72324BL Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h to 006Fh 0070h 0071h 0072h 0073h 007Fh Block Register Label TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Register Name Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register3)4) Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register3) Timer A Input Capture 2 Low Register3) Timer A Output Compare 2 High Register4) Timer A Output Compare 2 Low Register4) Reserved Area (1 Byte) Reset Status 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h Remarks R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W TIMER A TIMER B TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00h x000 0000h 00h 00h --00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W SCI Reserved Area (24 Bytes) ADC ADCCSR ADCDRH ADCDRL Control/Status Register Data High Register Data Low Register Reserved Area (13 Bytes) 00h 00h 00h R/W Read Only Read Only Legend: x=undefined, R/W=read/write 14/151 1 ST72F324L, ST72324BL Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. The Timer A Input Capture 2 pin is not available (not bonded). - In Flash devices: The TAIC2HR and TAIC2LR registers are not present. Bit 4 of the TACSR register (ICF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used. 4. The Timer A Output Compare 2 pin is not available (not bonded). - In ROM devices: The TAOC2HR and TAOC2LR Registers can be used in PWM mode or for timebase generation. - In Flash devices: The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values. Bit 3 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used. Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in the ST72F324L but are present in the emulator. For compatibility with the emulator, it is recommended to perform a dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags. 15/151 1 ST72F324L, ST72324BL 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 3. Sectors available in Flash devices Flash Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2 Three Flash programming modes: - Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. - ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. - IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection against piracy Register Access Security System (RASS) to prevent accidental programming or erasing 4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Figure 6. Memory Map and Sector Address 4K 1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh 4.3.1 Read-out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased. Read-out protection selection depends on the device type: - In Flash devices it is enabled and removed through the FMP_R bit in the option byte. - In ROM devices it is enabled by mask option specified in the Option List. 8K 10K 16K 24K 32K 48K 60K FLASH MEMORY SIZE SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0 16/151 1 ST72F324L, ST72324BL FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC Interface ICC needs a minimum of 5 and up to 6 pins to be connected to the programming tool (see Figure 7). These pins are: - RESET: device reset - VSS: device power supply ground Figure 7. Typical ICC Interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) (See Note 4) 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O ICC CONNECTOR HE10 CONNECTOR TYPE - - - - ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source - VDD: application board power supply (optional, see Figure 7, Note 3) ST7 Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man- agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. External clock ICC entry mode is mandatory in this device. Pin 9 must be connected to the OSC1 or OSCIN pin of the ST7 and OSC2 must be grounded. ICCSEL/VPP ICCDATA RESET ICCCLK OSC2 OSC1 VDD VSS 17/151 1 ST72F324L, ST72324BL FLASH PROGRAM MEMORY (Cont'd) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool using 36-pulse mode. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description. 4.6 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 0 0 This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations. Table 4. Flash Control/Status Register Address and Reset Value Address (Hex.) 0029h Register Label FCSR Reset Value 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 18/151 1 ST72F324L, ST72324BL 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES 5.3 CPU REGISTERS The 6 CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts Figure 8. CPU Registers 7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR 19/151 1 ST72F324L, ST72324BL CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx 7 1 1 I1 H I0 N Z Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority. Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1 0 C The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details. 20/151 1 ST72F324L, ST72324BL CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh 15 0 7 SP7 SP6 SP5 SP4 SP3 SP2 SP1 8 0 0 0 0 0 0 1 0 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 9. Stack Manipulation Example CALL Subroutine @ 0100h Interrupt Event PUSH Y The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. POP Y IRET RET or RSP SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP Stack Higher Address = 01FFh Stack Lower Address = 0100h 21/151 1 ST72F324L, ST72324BL 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10. For more details, refer to dedicated parametric section. Main features Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) Reset Sequence Manager (RSM) Multi-Oscillator Clock Management (MO) - 5 Crystal/Ceramic resonator oscillators - 1 Internal RC oscillator 6.1 PHASE LOCKED LOOP If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required. See Section 6.1 on page 22. Caution: The PLL must not be used with the internal RC oscillator. Figure 10. Clock, Reset and Supply Block Diagram PLL Block OSC2 OSC1 MULTIOSCILLATOR (MO) fOSC PLL x 2 /2 0 1 fOSC2 MAIN CLOCK CONTROLLER WITH REALTIME CLOCK (MCC/RTC) fCPU PLL OPTION BIT RESET SEQUENCE RESET MANAGER (RSM) WATCHDOG TIMER (WDG) 22/151 1 ST72F324L, ST72324BL 6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by three different source types coming from the multioscillator block: an external source 4 crystal or ceramic resonator oscillators an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 5. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page 139 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Table 5. ST7 Clock Sources Hardware Configuration External Clock ST7 OSC1 OSC2 EXTERNAL SOURCE Crystal/Ceramic Resonators ST7 OSC1 OSC2 CL1 LOAD CAPACITORS CL2 Internal RC Oscillator ST7 OSC1 OSC2 23/151 1 ST72F324L, ST72324BL 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes two RESET sources as shown in Figure 12: External RESET source pulse Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: Active Phase depending on the RESET source 256 or 4096 CPU clock cycle delay (selected by option byte) RESET vector fetch The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.3.3 External Power-On RESET To start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Watchdog RESET Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. RESET Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR Figure 12. Reset Block Diagram VDD RON RESET Filter INTERNAL RESET PULSE GENERATOR WATCHDOG RESET 24/151 1 ST72F324L, ST72324BL 7 INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: - Up to 4 software programmable nesting levels - Up to 16 interrupt vectors fixed by hardware - 2 non maskable events: RESET, TRAP This interrupt management is based on: - Bit 5 and bit 3 of the CPU CC register (I1:0), - Interrupt software priority registers (ISPRx), - Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 6). The processing flow is shown in Figure 13 Figure 13. Interrupt Processing Flowchart RESET PENDING INTERRUPT N Y TRAP Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y When an interrupt request has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 6. Interrupt Software Priority Levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1 High FETCH NEXT INSTRUCTION THE INTERRUPT STAYS PENDING Y "IRET" N RESTORE PC, X, A, CC FROM STACK EXECUTE INSTRUCTION STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR 25/151 1 ST72F324L, ST72324BL INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: - the highest software priority interrupt is serviced, - if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 14 describes this decision process. Figure 14. Priority Decision Process PENDING INTERRUPTS vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode. TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 13. RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details. Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed. Same SOFTWARE PRIORITY Different HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET and TRAP can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 13). After stacking the PC, X, A and CC registers (except for RESET), the corresponding 26/151 1 ST72F324L, ST72324BL INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 14. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 15. Concurrent Interrupt Management TRAP SOFTWARE PRIORITY LEVEL IT2 IT1 IT4 IT3 IT0 I1 I0 7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 15 and Figure 16 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 16. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure. HARDWARE PRIORITY TRAP IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1 3 3 3 3 3 3 3/0 10 11 11 11 11 11 11 11 / 10 Figure 16. Nested Interrupt Management TRAP SOFTWARE PRIORITY LEVEL IT0 IT2 IT1 IT4 IT3 I1 I0 HARDWARE PRIORITY TRAP IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2 3 3 2 1 3 3 3/0 10 11 11 00 01 11 11 11 / 10 27/151 USED STACK = 20 BYTES USED STACK = 10 BYTES 1 ST72F324L, ST72324BL INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh) 7 1 1 I1 H I0 N Z 0 C ISPR0 INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh) 7 I1_3 I1_7 I0_3 I0_7 I1_2 I1_6 I0_2 I0_6 I1_1 I1_5 I0_1 I0_5 I0_9 I1_0 I1_4 I1_8 0 I0_0 I0_4 I0_8 Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority. Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1 ISPR1 ISPR2 ISPR3 I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1 I1_13 I0_13 I1_12 I0_12 High These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TRAP and RESET events can interrupt a level 3 program. These four registers contain the interrupt software priority of each interrupt vector. - Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table. Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits - Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. - Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x). 28/151 1 ST72F324L, ST72324BL INTERRUPTS (Cont'd) Table 7. Dedicated Interrupt Instruction Set Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 (level 3) Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. 29/151 1 ST72F324L, ST72324BL INTERRUPTS (Cont'd) Table 8. Interrupt Mapping Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 SPI TIMER A TIMER B SCI MCC/RTC ei0 ei1 ei2 ei3 Reset Software interrupt Not used Main clock controller time base interrupt External interrupt port A3..0 External interrupt port F2..0 External interrupt port B3..0 External interrupt port B7..4 Not used SPI peripheral interrupts TIMER A peripheral interrupts TIMER B peripheral interrupts SCI Peripheral interrupts SPICSR TASR TBSR SCISR Lower Priority yes no no no yes1) no no no N/A MCCSR Higher Priority no yes yes yes yes yes yes1) yes1) yes 1) N Description Register Label Priority Order Exit from HALT yes no Exit from Active HALT yes no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h N/A yes1) Notes: 1. Valid for ROM devices. For Flash devices only a RESET or MCC/RTC interrupt can be used to wakeup from Active Halt mode. 7.6 EXTERNAL INTERRUPTS 7.6.1 I/O Port Interrupt Sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 17). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. 30/151 1 ST72F324L, ST72324BL Figure 17. External Interrupt Control bits PORT A3 INTERRUPT PAOR.3 PADDR.3 PA3 EICR IS20 IS21 ei0 INTERRUPT SOURCE SENSITIVITY CONTROL IPA BIT PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2 EICR IS20 IS21 PF2 PF1 PF0 SENSITIVITY CONTROL ei1 INTERRUPT SOURCE PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3 EICR IS10 IS11 PB3 PB2 PB1 PB0 SENSITIVITY CONTROL ei2 INTERRUPT SOURCE IPB BIT PORT B [7:4] INTERRUPTS PBOR.7 PBDDR.7 PB7 EICR IS10 IS11 PB7 PB6 PB5 PB4 SENSITIVITY CONTROL ei3 INTERRUPT SOURCE 31/151 1 ST72F324L, ST72324BL INTERRUPTS (Cont'd) 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 IPB IS21 IS20 IPA 0 0 0 Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: - ei0 (port A3..0) Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0) External Interrupt Sensitivity IS11 IS10 IPB bit =0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only IPB bit =1 Rising edge & high level Falling edge only Rising edge only 0 1 1 1 0 1 External Interrupt Sensitivity IS21 IS20 IPA bit =0 0 0 Falling edge & low level Rising edge only Falling edge only IPA bit =1 Rising edge & high level Falling edge only Rising edge only Rising and falling edge Rising and falling edge - ei1 (port F2..0) IS21 IS20 0 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge - ei3 (port B7..4) IS11 IS10 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge 0 1 1 These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 2 = IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion Bits 1:0 = Reserved, must always be kept cleared. These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = IPB Interrupt polarity for port B This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion 32/151 1 ST72F324L, ST72324BL INTERRUPTS (Cont'd) Table 9. Nested Interrupts Register Map and Reset Values Address (Hex.) 0024h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR Reset Value 7 ei1 I1_3 1 SPI 0025h I1_7 1 I1_11 1 I0_7 1 I0_11 1 I1_6 1 SCI 0026h I1_10 1 I0_10 1 I0_6 1 I0_3 1 I1_2 1 6 5 ei0 I0_2 1 I1_1 1 ei3 I1_5 I0_5 1 1 TIMER B I1_9 I0_9 1 1 I1_13 1 IS20 0 I0_13 1 IPA 0 4 3 MCC I0_1 1 1 ei2 I1_4 I0_4 1 1 TIMER A I1_8 I0_8 1 1 I1_12 1 0 I0_12 1 0 1 2 1 0 0027h 0028h 1 IS11 0 1 IS10 0 1 IPB 0 1 IS21 0 33/151 1 ST72F324L, ST72324BL 8 POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 18. Power Saving Mode Transitions High fOSC2/2 fOSC2/4 fOSC2 8.2 SLOW MODE This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode. Figure 19. SLOW Mode Clock Transitions RUN SLOW MCCSR WAIT SLOW WAIT ACTIVE HALT HALT Low POWER CONSUMPTION fCPU fOSC2 CP1:0 SMS 00 01 NEW SLOW FREQUENCY REQUEST NORMAL RUN MODE REQUEST 34/151 1 ST72F324L, ST72324BL POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 20. Figure 20. WAIT Mode Flow-chart OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON OFF 10 WFI INSTRUCTION N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 10 Y 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 1) FETCH RESET VECTOR OR SERVICE INTERRUPT Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 35/151 1 ST72F324L, ST72324BL POWER SAVING MODES (Cont'd) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register). MCCSR OIE bit 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode pending on option byte). Otherwise, the ST7 enters HALT mode for the remaining tDELAY period. Figure 21. ACTIVE-HALT Timing Overview RUN ACTIVE 256 OR 4096 CPU HALT CYCLE DELAY 1) RESET OR INTERRUPT RUN HALT INSTRUCTION [MCCSR.OIE=1] FETCH VECTOR Figure 22. ACTIVE-HALT Mode Flow-chart 8.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 10.2 on page 50 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 8, "Interrupt Mapping," on page 30) or a RESET. When exiting ACTIVEHALT mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 22). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. CAUTION: When exiting ACTIVE-HALT mode following an interrupt, OIE bit of MCCSR register must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay deHALT INSTRUCTION (MCCSR.OIE=1) OSCILLATOR PERIPHERALS 2) CPU I[1:0] BITS N N ON OFF OFF 10 RESET Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON XX 4) 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX 4) FETCH RESET VECTOR OR SERVICE INTERRUPT Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 8, "Interrupt Mapping," on page 30 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped. 36/151 1 ST72F324L, ST72324BL POWER SAVING MODES (Cont'd) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2 on page 50 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 8, "Interrupt Mapping," on page 30) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24). When entering HALT mode, the I[1:0] bits in the CC register are forced to `10b'to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 14.1 on page 139 for more details). Figure 23. HALT Timing Overview RUN HALT 256 OR 4096 CPU CYCLE DELAY RESET OR INTERRUPT FETCH VECTOR FETCH RESET VECTOR OR SERVICE INTERRUPT RUN Figure 24. HALT Mode Flow-chart HALT INSTRUCTION (MCCSR.OIE=0) ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I[1:0] BITS 10 0 WATCHDOG DISABLE N RESET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS OFF CPU ON I[1:0] BITS XX 4) 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 4) HALT INSTRUCTION [MCCSR.OIE=0] Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 8, "Interrupt Mapping," on page 30 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 37/151 1 ST72F324L, ST72324BL POWER SAVING MODES (Cont'd) 8.4.2.1 Halt Mode Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 38/151 1 ST72F324L, ST72324BL 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 25 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status: DR 0 1 Push-pull VSS VDD Open-drain Vss Floating 9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. 39/151 1 ST72F324L, ST72324BL I/O PORTS (Cont'd) Figure 25. I/O Port General Block Diagram REGISTER ACCESS ALTERNATE OUTPUT 1 0 ALTERNATE ENABLE DR VDD P-BUFFER (see table below) PULL-UP (see table below) VDD DDR PULL-UP CONDITION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD OR EXTERNAL INTERRUPT SOURCE (eix) Table 10. I/O Port Mode Options Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS Output Legend: NI - not implemented Off - implemented not activated On - implemented and activated 40/151 DATA BUS DR SEL 1 0 ALTERNATE INPUT NI (see note) Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress. 1 ST72F324L, ST72324BL I/O PORTS (Cont'd) Table 11. I/O Port Configurations Hardware Configuration NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS DR REGISTER W DATA BUS R INPUT 1) ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS OPEN-DRAIN OUTPUT 2) VDD RPU DR REGISTER ACCESS PAD DR REGISTER R/W DATA BUS ALTERNATE ENABLE ALTERNATE OUTPUT PUSH-PULL OUTPUT 2) NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU DR REGISTER ACCESS PAD DR REGISTER R/W DATA BUS ALTERNATE ENABLE ALTERNATE OUTPUT Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. 41/151 1 ST72F324L, ST72324BL I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 26 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 26. Interrupt I/O Port State Transitions 01 INPUT floating/pull-up interrupt 00 INPUT floating (reset state) 10 OUTPUT open-drain 11 OUTPUT push-pull XX = DDR, OR 9.4 LOW POWER MODES Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode. 9.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction). Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx ORx Exit from Wait Yes Exit from Halt Yes 42/151 1 ST72F324L, ST72324BL I/O PORTS (Cont'd) 9.5.1 I/O Port Implementation The I/O port register configurations are summarised as follows. Standard Ports PA5:4, PC7:0, PD5:0, PE1:0, PF7:6, 4 MODE floating input pull-up input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1 PA3, PB3, PF2 (without pull-up) MODE floating input floating interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1 True Open Drain Ports PA7:6 MODE floating input open drain (high sink ports) DDR 0 1 Interrupt Ports PB4, PB2:0, PF1:0 (with pull-up) MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1 Table 12. Port Configuration Port Pin name PA7:6 PA5:4 PA3 PB3 PB4, PB2:0 PC7:0 PD5:0 PE1:0 PF7:6, 4 PF2 PF1:0 Input OR = 0 floating floating floating floating floating floating floating floating floating floating floating pull-up floating interrupt floating interrupt pull-up interrupt pull-up pull-up pull-up pull-up floating interrupt pull-up interrupt Output OR = 1 OR = 0 OR = 1 true open-drain open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull Port A Port B Port C Port D Port E Port F 43/151 1 ST72F324L, ST72324BL I/O PORTS (Cont'd) Table 13. I/O Port Register Map and Reset Values Address (Hex.) Register Label 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Reset Value of all I/O port registers 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR 000Ah PDDDR 000Bh PDOR 000Ch PEDR 000Dh PEDDR 000Eh PEOR 000Fh PFDR 0010h PFDDR 0011h PFOR MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB 44/151 1 ST72F324L, ST72324BL 10 ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 10.1.2 Main Features Programmable free-running downcounter Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte 10.1.3 Functional Description The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h: - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 28. Approximate Timeout Duration). The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 29). Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. Figure 27. Watchdog Block Diagram RESET fOSC2 MCC/RTC WATCHDOG CONTROL REGISTER (WDGCR) DIV 64 WDGA T6 T5 T4 T3 T2 T1 T0 6-BIT DOWNCOUNTER (CNT) 12-BIT MCC RTC COUNTER MSB 11 65 LSB 0 TB[1:0] bits (MCCSR Register) WDG PRESCALER DIV 4 45/151 1 ST72F324L, ST72324BL WATCHDOG TIMER (Cont'd) 10.1.4 How to Program the Watchdog Timeout Figure 28 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If Figure 28. Approximate Timeout Duration 3F 38 30 more precision is needed, use the formulae in Figure 29. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset. CNT Value (hex.) 28 20 18 10 08 00 1.5 18 34 50 65 82 98 114 128 Watchdog timeout (ms) @ 8 MHz. fOSC2 46/151 1 ST72F324L, ST72324BL WATCHDOG TIMER (Cont'd) Figure 29. Exact Timeout Duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2=8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register TB1 Bit TB0 Bit (MCCSR Reg.) (MCCSR Reg.) 0 0 0 1 1 0 1 1 Selected MCCSR Timebase 2ms 4ms 10ms 25ms MSB 4 8 20 49 LSB 59 53 35 54 To calculate the minimum Watchdog Timeout (tmin): IF CNT < MSB ------------4 THEN t min = t min0 + 16384 x CNT x t osc2 x t osc2 ELSE t min = t min0 + 16384 x CNT - 4CNT + ( 192 + LSB ) x 64 x 4CNT ------------------------------ MSB MSB To calculate the maximum Watchdog Timeout (tmax): IF CNT MSB ------------4 THEN t max = t max0 + 16384 x CNT x t osc2 ELSE t max = t max0 + 16384 x CNT - 4CNT + ( 192 + LSB ) x 64 x 4CNT ------------------------------ MSB MSB x t osc2 Note: In the above formulae, division results must be rounded down to the next integer value. Example: With 2ms timeout selected in MCCSR register Value of T[5:0] Bits in WDGCR Register (Hex.) 00 3F Min. Watchdog Timeout (ms) tmin 1.496 128 Max. Watchdog Timeout (ms) tmax 2.048 128.552 47/151 1 ST72F324L, ST72324BL WATCHDOG TIMER (Cont'd) 10.1.5 Low Power Modes Mode SLOW WAIT Description No effect on Watchdog. No effect on Watchdog. OIE bit in MCCSR register WDGHALT bit in Option Byte No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.1.7 below. A reset is generated. No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks. 0 0 HALT 0 1 1 x 10.1.6 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description. 10.1.7 Using Halt Mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. 10.1.8 Interrupts None. 10.1.9 Register Description CONTROL REGISTER (WDGCR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA T6 T5 T4 T3 T2 T1 0 T0 Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB). These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). 48/151 1 ST72F324L, ST72324BL Table 14. Watchdog Timer Register Map and Reset Values Address (Hex.) 002Ah Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1 49/151 1 ST72F324L, ST72324BL 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three different functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 10.2.1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See Section 8.2 SLOW MODE for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS. 10.2.2 Clock-out Capability The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC2 clock to drive external devices. It is controlled by the MCO bit in the MCCSR register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode. 10.2.3 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC2 are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 8.4 ACTIVE-HALT AND HALT MODES for more details. 10.2.4 Beeper The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the BEEP pin (I/O port alternate function). Figure 30. Main Clock Controller (MCC/RTC) Block Diagram BC1 BC0 MCCBCR BEEP BEEP SIGNAL SELECTION MCO DIV 64 12-BIT MCC RTC COUNTER TO WATCHDOG TIMER MCO CP1 CP0 SMS TB1 TB0 OIE MCCSR fOSC2 DIV 2, 4, 8, 16 OIF MCC/RTC INTERRUPT 1 0 fCPU CPU CLOCK TO CPU AND PERIPHERALS 50/151 1 ST72F324L, ST72324BL MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) 10.2.5 Low Power Modes Bit 6:5 = CP[1:0] CPU clock prescaler Mode Description These bits select the CPU clock prescaler which is No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is WAIT MCC/RTC interrupt cause the device to exit conditioned by the setting of the SMS bit. These from WAIT mode. two bits are set and cleared by software ACTIVEHALT No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability. fCPU in SLOW mode fOSC2 / 2 fOSC2 / 4 fOSC2 / 8 fOSC2 / 16 CP1 0 0 1 1 CP0 0 1 0 1 HALT 10.2.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction). Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Yes Exit from Halt No 1) Bit 4 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2 1: Slow mode. fCPU is given by CP1, CP0 See Section 8.2 SLOW MODE and Section 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) for more details. Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software. Time Base Counter Prescaler f OSC2 =4MHz fOSC2=8MHz 16000 4ms 8ms 20ms 50ms 2ms 4ms 10ms 25ms 32000 80000 200000 TB1 0 0 1 1 TB0 0 1 0 1 Note: The MCC/RTC interrupt wakes up the MCU from ACTIVE-HALT mode, not from HALT mode. 10.2.7 Register Description MCC CONTROL/STATUS REGISTER (MCCSR) Read/Write Reset Value: 0000 0000 (00h) 7 MCO CP1 CP0 SMS TB1 TB0 OIE 0 OIF A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode. Bit 7 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode. 51/151 1 ST72F324L, ST72324BL MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) MCC BEEP CONTROL REGISTER (MCCBCR) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software Read/Write reading the MCCSR register. It indicates when set Reset Value: 0000 0000 (00h) that the main oscillator has reached the selected elapsed time (TB1:0). 7 0 0: Timeout not reached 1: Timeout reached 0 0 0 0 0 0 BC1 BC0 CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid Bit 7:2 = Reserved, must be kept cleared. unintentionally clearing the OIF bit. Bit 1:0 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability. BC1 0 0 1 1 BC0 0 1 0 1 ~2-KHz ~1-KHz ~500-Hz Beep mode with fOSC2=8MHz Off Output Beep signal ~50% duty cycle The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption. Table 15. Main Clock Controller Register Map and Reset Values Address (Hex.) 002Ch 002Dh Register Label MCCSR Reset Value MCCBCR Reset Value 7 MCO 0 0 6 CP1 0 0 5 CP0 0 0 4 SMS 0 0 3 TB1 0 0 2 TB0 0 0 1 OIE 0 BC1 0 0 OIF 0 BC0 0 52/151 1 ST72F324L, ST72324BL 10.3 16-BIT TIMER 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 10.3.2 Main Features Programmable prescaler: fCPU divided by 2, 4 or 8. Overflow status flag and maskable interrupt External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge 1 or 2 Output Compare functions each with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt 1 or 2 Input Capture functions each with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt Pulse width modulation mode (PWM) One pulse mode Reduced Power Mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 31. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 10.3.3 Functional Description 10.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 16 Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency. Caution: In Flash devices, Timer A functionality has the following restrictions: - TAOC2HR and TAOC2LR registers are write only - Input Capture 2 is not implemented - The corresponding interrupts cannot be used (ICF2, OCF2 forced by hardware to zero) 53/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) Figure 31. Timer Block Diagram ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8-bit buffer EXEDG 16 1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 16 INPUT CAPTURE REGISTER 2 16 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8 8 high OUTPUT COMPARE CIRCUIT 6 EDGE DETECT CIRCUIT1 ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin LATCH1 ICF1 OCF1 TOF ICF2 OCF2 TIMD OCMP1 pin OCMP2 pin 0 0 LATCH2 (Control/Status Register) CSR ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG (Control Register 1) CR1 (Control Register 2) CR2 (See note) TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table) 54/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte Other instructions Read At t0 +t LS Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Returns the buffered LS Byte value at t0 LS Byte is buffered Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 10.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. 55/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) Figure 32. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003 Figure 33. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001 Figure 34. Counter Timing Diagram, internal clock divided by 8 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. 56/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) 10.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see figure 5). ICiR MS Byte ICiHR LS Byte ICiLR ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 16 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pullup without interrupt if this configuration is available). When an input capture occurs: - ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 36). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One pulse Mode and PWM mode only Input Capture 2 can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh). 7. In Flash devices, the ICAP2 registers (TAIC2HR, TAIC2LR) are not available on Timer A. The corresponding interrupts cannot be used (ICF2 is forced by hardware to 0). 57/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) Figure 35. Input Capture Block Diagram ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE (Control Register 1) CR1 IEDG1 (Status Register) SR IC2R Register IC1R Register ICF1 ICF2 0 0 0 16-BIT 16-BIT FREE RUNNING COUNTER (Control Register 2) CR2 CC1 CC0 IEDG2 Figure 36. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The rising edge is the active edge. FF03 FF01 FF02 FF03 58/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) 10.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. OCiR MS Byte OCiHR LS Byte OCiLR - The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR = Where: t * fCPU PRESC t fCPU = Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16 Clock Control Bits) If the timer clock is an external clock, the formula is: These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 16 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set. OCiR = t * fEXT Where: t fEXT = Output compare period (in seconds) = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit). 59/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 38 on page 61). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 39 on page 61). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. 6. In Flash devices, the TAOC2HR, TAOC2LR registers are "write only" in Timer A. The corresponding event cannot be generated (OCF2 is forced by hardware to 0). Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both one pulse mode and PWM mode. Figure 37. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1E OC2E CC1 CC0 (Control Register 2) CR2 (Control Register 1) CR1 OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1 OCMP1 Pin OCMP2 Pin OC1R Register OCF1 OCF2 0 0 0 Latch 2 OC2R Register (Status Register) SR 60/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) Figure 38. Output Compare Timing Diagram, fTIMER =fCPU/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 Figure 39. Output Compare Timing Diagram, fTIMER =fCPU/4 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 61/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) 10.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 16 Clock Control Bits). One pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: t * fCPU -5 OCiR Value = PRESC Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 16 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) = External timer clock frequency (in hertz) fEXT When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 40). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. 6. In Flash devices, Timer A OCF2 bit is forced by hardware to 0. OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. 62/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) Figure 40. One Pulse Mode Timing Example IC1R COUNTER ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 01F8 FFFC FFFD FFFE 01F8 2ED0 2ED1 2ED2 2ED3 2ED3 FFFC FFFD compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 41. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2 2ED0 2ED1 2ED2 34E2 FFFC OLVL1 OLVL2 compare2 compare1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 63/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) 10.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). Procedure To use pulse width modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 16 Clock Control Bits). Pulse Width Modulation cycle When Counter = OC1R If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: t * fCPU - 5 OCiR Value = PRESC Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) = External timer clock frequency (in hertz) fEXT The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 41) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 6. In Flash devices, the TAOC2HR, TAOC2LR registers in Timer A are "write only". A read operation returns an undefined value. 7. In Flash devices, the ICAP2 registers (TAIC2HR, TAIC2LR) are not available in Timer A. The ICF2 bit is forced by hardware to 0. OCMP1 = OLVL1 When Counter = OC2R OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set 64/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) 10.3.4 Low Power Modes Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. HALT 10.3.5 Interrupts Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2* OCF1 OCF2* TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). * In Flash devices, the ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no interrupt event for these flags. 10.3.6 Summary of Timer modes MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode PWM Mode Input Capture 1 Yes Yes No No TIMER RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes4) Yes2)5) 5) Yes Yes Yes4) Not No Partially 2) Recommended1)5) Not No No Recommended3)5) 1) See note 4 in Section 10.3.3.5 One Pulse Mode 2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode 3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode 4) In Flash devices, the TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event cannot be generated, OCF2 is forced by hardware to 0. 5) In Flash devices, Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0. 65/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) 10.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) 7 0 Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. 66/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 0 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 16. Clock Control Bits Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1 Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Note: In Flash devices, this bit is not available for Timer A. It must be kept at its reset value. Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. 67/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) CONTROL/STATUS REGISTER (CSR) Read Only (except bit 2 R/W) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 0 Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Note: In Flash devices, this bit is not available for Timer A and is forced by hardware to 0. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Note: In Flash devices, this bit is not available for Timer A and is forced by hardware to 0. Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled Bits 1:0 = Reserved, must be kept cleared. 68/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB 0 LSB OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB 0 LSB INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 MSB 0 LSB OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 MSB 0 LSB 69/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB 0 LSB COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB 0 LSB Note: In Flash devices, the Timer A OC2HR register is write-only. OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 MSB 0 COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit. 7 MSB 0 LSB LSB Note: In Flash devices, the Timer A OC2LR register is write-only. 70/151 1 ST72F324L, ST72324BL ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB 0 LSB INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). 7 MSB 0 LSB ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. 7 MSB 0 LSB Note: In Flash devices, this register is not implemented for Timer A. INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event). 7 MSB 0 LSB Note: In Flash devices, this register is not implemented for Timer A. 71/151 1 ST72F324L, ST72324BL 16-BIT TIMER (Cont'd) Table 17. 16-Bit Timer Register Map and Reset Values Address (Hex.) Timer A: 32 Timer B: 42 Timer A: 31 Timer B: 41 Timer A: 33 Timer B: 43 Timer A: 34 Timer B: 44 Timer A: 35 Timer B: 45 Timer A: 36 Timer B: 46 Timer A: 37 Timer B: 47 Timer A: 3E3 Timer B: 4E Timer A: 3F3 Timer B: 4F Timer A: 38 Timer B: 48 Timer A: 39 Timer B: 49 Timer A: 3A Timer B: 4A Timer A: 3B Timer B: 4B Timer A: 3C4 Timer B: 4C Timer A: 3D4 Timer B: 4D 1 2 3 Register Label CR1 Reset Value CR2 Reset Value CSR Reset Value IC1HR Reset Value IC1LR Reset Value OC1HR Reset Value OC1LR Reset Value OC2HR Reset Value OC2LR Reset Value CHR Reset Value CLR Reset Value ACHR Reset Value ACLR Reset Value IC2HR Reset Value IC2LR Reset Value 7 ICIE 0 OC1E 0 ICF1 x MSB x MSB x MSB 1 MSB 0 MSB 1 MSB 0 MSB 1 MSB 1 MSB 1 MSB 1 MSB x MSB x 6 OCIE 0 OC2E1 0 OCF1 x x x 0 0 0 0 1 1 1 1 x x 5 TOIE 0 OPM 0 TOF x x x 0 0 0 0 1 1 1 1 x x 4 FOLV21 0 PWM 0 ICF22 x x x 0 0 0 0 1 1 1 1 x x 3 FOLV1 0 CC1 0 OCF22 x x x 0 0 0 0 1 1 1 1 x x 2 OLVL2 0 CC0 0 TIMD 0 x x 0 0 0 0 1 1 1 1 x x 1 IEDG1 0 IEDG21 0 x x x 0 0 0 0 1 0 1 0 x x 0 OLVL1 0 EXEDG 0 x LSB x LSB x LSB 0 LSB 0 LSB 0 LSB 0 LSB 1 LSB 0 LSB 1 LSB 0 LSB x LSB x In Flash devices, these bits are not used in Timer A and must be kept cleared. In Flash devices, these bits are forced by hardware to 0 in Timer A In Flash devices, the TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values In Flash devices, the TAIC2HR and TAIC2LR registers are not present. 4 72/151 1 ST72F324L, ST72324BL 10.4 SERIAL PERIPHERAL INTERFACE (SPI) 10.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system. 10.4.2 Main Features Full duplex synchronous transfers (on 3 lines) Simplex synchronous transfers (on 2 lines) Master or slave operation Six master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) SS Management by software or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.4.3 General Description Figure 42 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: - SPI Control Register (SPICR) - SPI Control/Status Register (SPICSR) - SPI Data Register (SPIDR) The SPI is connected to external devices through 3 pins: - MISO: Master In / Slave Out data - MOSI: Master Out / Slave In data - SCK: Serial Clock out by SPI masters and input by SPI slaves - SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU. Figure 42. Serial Peripheral Interface Block Diagram Data/Address Bus SPIDR Read Read Buffer Interrupt request MOSI MISO 8-Bit Shift Register 7 SPIF WCOL OVR MODF 0 SPICSR SOD SSM 0 SSI SOD bit Write SS SPI STATE CONTROL 7 SPIE 1 0 SCK SPICR 0 SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 MASTER CONTROL SERIAL CLOCK GENERATOR SS 73/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 43. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device reFigure 43. Single Master/ Single Slave Application sponds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 46) but master and slave must be programmed with the same timing mode. MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit 8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER MOSI MOSI SPI CLOCK GENERATOR SCK SS +5V SCK SS Not used if SS is managed by software 74/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 45) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: - SS internal must be held high continuously In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 44): If CPHA=1 (data latched on 2nd clock edge): - SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the in the SPICSR register) If CPHA=0 (data latched on 1st clock edge): - SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 10.4.5.3). Figure 44. Generic SS Timing Diagram MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Byte 1 Byte 2 Byte 3 Figure 45. Hardware/Software Slave Select Management SSM bit SSI bit SS external pin 1 0 SS internal 75/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit ) may be not taken into account): 1. Write to the SPICR register: - Select the clock frequency by configuring the SPR[2:0] bits. - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 46 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: - Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: - Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). The transmit sequence begins when software writes a byte in the SPIDR register. 10.4.3.4 Master Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 10.4.3.5 Slave Mode Operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 46). Note: The slave must have the same CPOL and CPHA settings as the master. - Manage the SS pin as described in Section 10.4.3.2 and Figure 44. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. 10.4.3.6 Slave Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 10.4.5.2). 76/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 46). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 46. Data Clock Timing Diagram Figure 46, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. CPHA =1 SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit CPHA =0 SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. 77/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.5 Error Flags 10.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: - The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. 10.4.5.2 Overrun Condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs: - The OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. 10.4.5.3 Write Collision Error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Section 10.4.3.2 Slave Select Management. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 47). Figure 47. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR RESULT 2nd Step Read SPIDR SPIF =0 WCOL=0 Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Read SPICSR RESULT Read SPIDR WCOL=0 Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit 78/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 48). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission. For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Figure 48. Single Master / Multiple Slave Configuration SS SCK Slave MCU MOSI MISO SCK Slave MCU SS SCK Slave MCU SS SCK Slave MCU SS MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK Master MCU 5V SS Ports 79/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.6 Low Power Modes Mode WAIT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the device. HALT Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selection is configured as external (see Section 10.4.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode. 10.4.7 Interrupts Interrupt Event Event Flag SPIF MODF OVR SPIE Enable Control Bit Exit from Wait Yes Yes Yes Exit from Halt Yes No No 10.4.6.1 Using the SPI to wakeup the MCU from Halt mode In slave configuration, the SPI is able to wakeup the ST7 device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. SPI End of Transfer Event Master Mode Fault Event Overrun Error Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in 80/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 0 SPR0 Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1, MODF=1 or OVR=1 in the SPICSR register Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 10.4.5.1 Master Mode Fault (MODF)). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 18 SPI Master mode SCK Frequency. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. Bit 4 = MSTR Master Mode. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 10.4.5.1 Master Mode Fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 18. SPI Master mode SCK Frequency Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1 81/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF SOD SSM 0 SSI Bit 3 = Reserved, must be kept cleared. Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 10.4.3.2 Slave Select Management. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0: Slave selected 1: Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined 7 0 D6 D5 D4 D3 D2 D1 D0 Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 47). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 10.4.5.2). An interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 10.4.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected D7 The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 42). 82/151 1 ST72F324L, ST72324BL SERIAL PERIPHERAL INTERFACE (Cont'd) Table 19. SPI Register Map and Reset Values Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPICSR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x SSI 0 x SPE 0 WCOL 0 x SPR2 0 OR 0 x MSTR 0 MODF 0 x CPOL x 0 x CPHA x SOD 0 x SPR1 x SSM 0 83/151 1 ST72F324L, ST72324BL 10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 10.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 10.5.2 Main Features Full duplex, asynchronous communications NRZ standard format (Mark/Space) Dual baud rate generator systems Independently programmable transmit and receive baud rates up to 500K baud. Programmable data word length (8 or 9 bits) Receive buffer full, Transmit buffer empty and End of Transmission flags Two receiver wake-up modes: - Address bit (MSB) - Idle line Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver Four error detection flags: - Overrun error - Noise error - Frame error - Parity error Five interrupt sources with flags: - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error detected Parity control: - Transmits parity bit - Checks parity of received data byte Reduced power consumption mode 10.5.3 General Description The interface is externally connected to another device by two pins (see Figure 50): - TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. - RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as frames comprising: - An Idle Line prior to transmission or reception - A start bit - A data word (8 or 9 bits) least significant bit first - A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: - A conventional type for commonly-used baud rates, - An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. 84/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 49. SCI Block Diagram Write Read (DATA REGISTER) DR Transmit Data Register (TDR) TDO Transmit Shift Register RDI Received Data Register (RDR) Received Shift Register CR1 R8 T8 SCID M WAKE PCE PS PIE TRANSMIT CONTROL WAKE UP UNIT RECEIVER CONTROL RECEIVER CLOCK CR2 TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE SR SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE fCPU CONTROL /16 /PR BRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR 85/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 49. It contains 6 dedicated registers: - Two control registers (SCICR1 & SCICR2) - A status register (SCISR) - A baud rate register (SCIBRR) - An extended prescaler receiver register (SCIERPR) - An extended prescaler transmitter register (SCIETPR) Refer to the register descriptions in Section 10.5.7for the definitions of each bit. 10.5.4.1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 49). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of "1"s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving "0"s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra "1" bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator. Figure 50. Word Length Programming 9-bit Word length (M bit is set) Data Frame Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8 Next Data Frame Next Stop Start Bit Bit Start Bit Idle Frame Break Frame Extra '1' Start Bit 8-bit Word length (M bit is reset) Data Frame Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Possible Parity Bit Bit7 Stop Bit Next Data Frame Next Start Bit Start Bit Extra Start Bit '1' Idle Frame Break Frame 86/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.5.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 49). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the SCIBRR and the SCIETPR registers. - Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. - Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: - The TDR register is empty. - The data transfer is beginning. - The next data can be written in the SCIDR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 50). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR. 87/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.5.4.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 49). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the SCIBRR and the SCIERPR registers. - Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: - The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. - The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SPI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared. When a overrun error occurs: - The OR bit is set. - The RDR content will not be lost. - The shift register will be overwritten. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise Error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame: - The NF flag is set at the rising edge of the RDRF bit. - Data is transferred from the Shift register to the SCIDR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. See also Section 10.5.4.10. 88/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 51. SCI Baud Rate and Extended Prescaler Block Diagram TRANSMITTER CLOCK EXTENDED PRESCALER TRANSMITTER RATE CONTROL SCIETPR EXTENDED TRANSMITTER PRESCALER REGISTER SCIERPR EXTENDED RECEIVER PRESCALER REGISTER RECEIVER CLOCK EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER fCPU TRANSMITTER RATE CONTROL /16 /PR SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR 89/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) Framing Error A framing error is detected when: - The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. - A break is received. When the framing error is detected: - the FE bit is set by hardware - Data is transferred from the Shift register to the SCIDR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. 10.5.4.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU (16*PR)*TR Rx = fCPU (16*PR)*RR Note: the extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows: fCPU fCPU Rx = Tx = 16*ERPR*(PR*RR) 16*ETPR*(PR*TR) with: ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,.. 255 (see SCIERPR register) 10.5.4.6 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the following two ways: - by Idle Line detection if the WAKE bit is reset, - by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a "1" as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode. with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If fCPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud. Note: the baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. 10.5.4.5 Extended Baud Rate Generation The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility. The extended baud rate generator block diagram is described in the Figure 51. The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register. 90/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.5.4.7 Parity Control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 20. Table 20. Frame Formats M bit 0 0 1 1 PCE bit 0 1 0 1 SCI frame | SB | 8 bit data | STB | | SB | 7-bit data | PB | STB | | SB | 9-bit data | STB | | SB | 8-bit data PB | STB | Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit Even parity: the parity bit is calculated to obtain an even number of "1s" inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity: the parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of "1s" if even parity is selected (PS=0) or an odd number of "1s" if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. 10.5.4.8 SCI Clock Tolerance During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be "1", but the Noise Flag bit is be set because the three samples values are not the same. Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples will be at 28s, 32s & 36s respectively (the first sample starting ideally at 0s). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4us. This means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchronization with the internal sampling clock). 91/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.5.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: - DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). - DQUANT: Error due to the baud rate quantisation of the receiver. - DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. - DTCL: Deviation due to the transmission line (generally due to the transceivers) All the deviations of the system should be added and compared to the SCI clock tolerance: DTRA + DQUANT + DREC + DTCL < 3.75% 10.5.4.10 Noise Error Causes See also description of Noise error in Section 10.5.4.3. Start bit The noise flag (NF) is set during start bit reception if one of the following conditions occurs: 1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a "1". 2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a "1". Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set. Data Bits The noise flag (NF) is set during normal data bit reception if the following condition occurs: - During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set. Figure 52. Bit Sampling in Reception Mode RDI LINE sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 One bit time 7/16 92/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.5.5 Low Power Modes Mode WAIT Description No effect on SCI. SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Interrupt Event Enable Exit Event Control from Flag Bit Wait TIE TCIE RIE ILIE PIE Yes Yes Yes Yes Yes Yes Exit from Halt No No No No No No HALT 10.5.6 Interrupts The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control Bit is set and the inter- Transmit Data Register TDRE Empty Transmission ComTC plete Received Data Ready RDRF to be Read Overrun Error Detected OR Idle Line Detected IDLE Parity Error PE rupt mask in the CC register is reset (RIM instruction). 93/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.5.7 Register Description Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line ocSTATUS REGISTER (SCISR) curs). Read Only Reset Value: 1100 0000 (C0h) Bit 3 = OR Overrun error. 7 0 This bit is set by hardware when the word currently being received in the shift register is ready to be TDRE TC RDRF IDLE OR NF FE PE transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an Bit 7 = TDRE Transmit data register empty. access to the SCISR register followed by a read to This bit is set by hardware when the content of the the SCIDR register). TDR register has been transferred into the shift 0: No Overrun error register. An interrupt is generated if the TIE bit=1 1: Overrun error is detected in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register folNote: When this bit is set RDR register content will lowed by a write to the SCIDR register). not be lost but the shift register will be overwritten. 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Bit 2 = NF Noise flag. Note: Data will not be transferred to the shift regThis bit is set by hardware when noise is detected ister unless the TDRE bit is cleared. on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). Bit 6 = TC Transmission complete. 0: No noise is detected This bit is set by hardware when transmission of a 1: Noise is detected frame containing Data is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it apcleared by a software sequence (an access to the pears at the same time as the RDRF bit which itSCISR register followed by a write to the SCIDR self generates an interrupt. register). 0: Transmission is not complete 1: Transmission is complete Bit 1 = FE Framing error. This bit is set by hardware when a de-synchronizaNote: TC is not set after the transmission of a Pretion, excessive noise or a break character is deamble or a Break. tected. It is cleared by a software sequence (an access to the SCISR register followed by a read to Bit 5 = RDRF Received data ready flag. the SCIDR register). This bit is set by hardware when the content of the 0: No Framing error is detected RDR register has been transferred to the SCIDR 1: Framing error or break character is detected register. An interrupt is generated if RIE=1 in the Note: This bit does not generate interrupt as it apSCICR2 register. It is cleared by a software sepears at the same time as the RDRF bit which itquence (an access to the SCISR register followed self generates an interrupt. If the word currently by a read to the SCIDR register). being transferred causes both frame error and 0: Data is not received overrun error, it will be transferred and only the OR 1: Received data is ready to be read bit will be set. Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected Bit 0 = PE Parity error. This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register. 0: No parity error 1: Parity error 94/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) CONTROL REGISTER 1 (SCICR1) Read/Write Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is Reset Value: x000 0000 (x0h) set or cleared by software. 0: Idle Line 7 0 1: Address Mark R8 T8 SCID M WAKE PCE PS PIE Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception). Bit 2 = PCE Parity control enable. This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled Bit 1 = PS Parity selection. This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity Bit 0 = PIE Parity interrupt enable. This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled. 95/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) CONTROL REGISTER 2 (SCICR2) Notes: Read/Write - During transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble (idle line) Reset Value: 0000 0000 (00h) after the current word. 7 0 - When TE is set there is a 1 bit-time delay before the transmission starts. TIE TCIE RIE ILIE TE RE RWU SBK Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 2 = RE Receiver enable. 1: An SCI interrupt is generated whenever This bit enables the receiver. It is set and cleared TDRE=1 in the SCISR register by software. 0: Receiver is disabled Bit 6 = TCIE Transmission complete interrupt ena1: Receiver is enabled and begins searching for a ble start bit This bit is set and cleared by software. 0: Interrupt is inhibited Bit 1 = RWU Receiver wake-up. 1: An SCI interrupt is generated whenever TC=1 in This bit determines if the SCI is in mute mode or the SCISR register not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is Bit 5 = RIE Receiver interrupt enable. recognized. This bit is set and cleared by software. 0: Receiver in Active mode 0: Interrupt is inhibited 1: Receiver in Mute mode 1: An SCI interrupt is generated whenever OR=1 Note: Before selecting Mute mode (setting the or RDRF=1 in the SCISR register RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with Bit 4 = ILIE Idle line interrupt enable. wakeup by idle line detection. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 0 = SBK Send break. 1: An SCI interrupt is generated whenever IDLE=1 This bit set is used to send break characters. It is in the SCISR register. set and cleared by software. Bit 3 = TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to "1" and then to "0", the transmitter will send a BREAK word at the end of the current word. 96/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to. 7 DR7 DR6 DR5 DR4 DR3 DR2 DR1 Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode. TR dividing factor 1 2 4 8 16 32 64 128 SCT2 0 0 0 0 1 1 1 1 SCT1 0 0 1 1 0 0 1 1 SCT0 0 1 0 1 0 1 0 1 0 DR0 The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 49). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 49). BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) 7 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. RR Dividing factor 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1 0 SCR1 SCR0 Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: PR Prescaling factor 1 3 4 13 SCP1 0 0 1 1 SCP0 0 1 0 1 97/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATIONS INTERFACE (Cont'd) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate division factor for the receive circuit. 7 0 EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate division factor for the transmit circuit. 7 ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2 0 ETPR ETPR 1 0 ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0 Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 51) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. Table 21. Baudrate Selection Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 51) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. Conditions Symbol Parameter fCPU Accuracy vs. Standard Prescaler Conventional Mode TR (or RR)=128, PR=13 TR (or RR)= 32, PR=13 TR (or RR)= 16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 16, PR= 3 TR (or RR)= 2, PR=13 TR (or RR)= 1, PR=13 Extended Mode ETPR (or ERPR) = 35, TR (or RR)= 1, PR=1 Standard Baud Rate Unit ~0.16% fTx fRx Communication frequency 8MHz 300 ~300.48 1200 ~1201.92 2400 ~2403.84 4800 ~4807.69 9600 ~9615.38 10400 ~10416.67 19200 ~19230.77 38400 ~38461.54 14400 ~14285.71 Hz ~0.79% 98/151 1 ST72F324L, ST72324BL SERIAL COMMUNICATION INTERFACE (Cont'd) Table 22. SCI Register Map and Reset Values Address (Hex.) 0050h 0051h 0052h 0053h 0054h 0055h 0057h Register Label SCISR Reset Value SCIDR Reset Value SCIBRR Reset Value SCICR1 Reset Value SCICR2 Reset Value SCIERPR Reset Value SCIPETPR Reset Value 7 TDRE 1 MSB x SCP1 0 R8 x TIE 0 MSB 0 MSB 0 6 TC 1 x SCP0 0 T8 0 TCIE 0 0 0 5 RDRF 0 x SCT2 0 SCID 0 RIE 0 0 0 4 IDLE 0 x SCT1 0 M 0 ILIE 0 0 0 3 OR 0 x SCT0 0 WAKE 0 TE 0 0 0 2 NF 0 x SCR2 0 PCE 0 RE 0 0 0 1 FE 0 x SCR1 0 PS 0 RWU 0 0 0 0 PE 0 LSB x SCR0 0 PIE 0 SBK 0 LSB 0 LSB 0 99/151 1 ST72F324L, ST72324BL 10.6 10-BIT A/D CONVERTER (ADC) 10.6.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register. Figure 53. ADC Block Diagram fCPU DIV 4 DIV 2 0 1 10.6.2 Main Features 10-bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register (DR) which contains the results Conversion complete status flag On/off bit (to reduce consumption) The block diagram is shown in Figure 53. fADC EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR 4 AIN0 AIN1 ANALOG MUX AINx ANALOG TO DIGITAL CONVERTER ADCDRH D9 D8 D7 D6 D5 D4 D3 D2 ADCDRL 0 0 0 0 0 0 D1 D0 100/151 1 ST72F324L, ST72324BL 10-BIT A/D CONVERTER (ADC) (Cont'd) 10.6.3 Functional Description The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 10.6.3.1 A/D Converter Configuration The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: - Select the CS[3:0] bits to assign the analog channel to convert. 10.6.3.2 Starting the Conversion In the ADCCSR register: - Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: - The EOC bit is set by hardware. - The result is in the ADCDR registers. A read to the ADCDRH resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll the EOC bit 2. Read the ADCDRL register 3. Read the ADCDRH register. This clears EOC automatically. Note: The data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result. To read only 8 bits, perform the following steps: 1. Poll the EOC bit 2. Read the ADCDRH register. This clears EOC automatically. 10.6.3.3 Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel. 10.6.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed. Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed. HALT 10.6.5 Interrupts None. 101/151 1 ST72F324L, ST72324BL 10-BIT A/D CONVERTER (ADC) (Cont'd) 10.6.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 CH2 CH1 Bit 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. Channel Pin* 0 CH0 CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection This bit is set and cleared by software. 0: fADC = fCPU/4 1: fADC = fCPU/2 Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: Disable ADC and stop conversion 1: Enable ADC and start conversion Bit 4 = Reserved. Must be kept cleared. AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 *The number of channels is device dependent. Refer to the device pinout description. DATA REGISTER (ADCDRH) Read Only Reset Value: 0000 0000 (00h) 7 D9 D8 D7 D6 D5 D4 D3 0 D2 Bit 7:0 = D[9:2] MSB of Converted Analog Value DATA REGISTER (ADCDRL) Read Only Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 D1 0 D0 Bit 7:2 = Reserved. Forced by hardware to 0. Bit 1:0 = D[1:0] LSB of Converted Analog Value 102/151 1 ST72F324L, ST72324BL 10-BIT A/D CONVERTER (Cont'd) Table 23. ADC Register Map and Reset Values Address (Hex.) 0070h 0071h 0072h Register Label ADCCSR Reset Value ADCDRH Reset Value ADCDRL Reset Value 7 EOC 0 D9 0 0 6 SPEED 0 D8 0 0 5 ADON 0 D7 0 0 4 3 CH3 0 D5 0 0 2 CH2 0 D4 0 0 1 CH1 0 D3 0 D1 0 0 CH0 0 D2 0 D0 0 0 D6 0 0 103/151 1 ST72F324L, ST72324BL 11 INSTRUCTION SET 11.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do Table 24. CPU Addressing Mode Overview Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip Syntax so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Destination Pointer Address (Hex.) Pointer Size (Hex.) Length (Bytes) +0 +1 00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word +1 +2 +0 +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3 104/151 1 ST72F324L, ST72324BL INSTRUCTION SET OVERVIEW (Cont'd) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles 11.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 11.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 11.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function 105/151 1 ST72F324L, ST72324BL INSTRUCTION SET OVERVIEW (Cont'd) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 25. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function 11.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. Available Relative Direct/Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative The relative addressing mode consists of two submodes: Relative (Direct) The offset is following the opcode. Relative (Indirect) The offset is defined in memory, which address follows the opcode. Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine 106/151 1 ST72F324L, ST72324BL INSTRUCTION SET OVERVIEW (Cont'd) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 107/151 1 ST72F324L, ST72324BL INSTRUCTION SET OVERVIEW (Cont'd) Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. INT pin = 1 Jump if ext. INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I1:0 = 11 Jump if I1:0 <> 11 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) jrf * (ext. INT pin high) (ext. INT pin low) H=1? H=0? I1:0 = 11 ? I1:0 <> 11 ? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Pop CC, A, X, PC inc X jp [TBL.w] reg, M tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 1 I1 H 0 I0 N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst Src M M M M I1 H H H I0 N N N N N Z Z Z Z Z C C C 108/151 1 ST72F324L, ST72324BL INSTRUCTION SET OVERVIEW (Cont'd) Mnemo JRULE LD MUL NEG NOP OR POP PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Substract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I1:0 = 10 (level 0) C <= A <= C C => A => C S = Max allowed A=A-M-C C=1 I1:0 = 11 (level 3) C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A=A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt 1 1 1 0 N Z reg, M reg, M reg, M reg, M A reg, M M 1 1 N N 0 N N N N Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 1 0 N N Z Z C C A=A+M pop reg pop CC push Y C=0 A reg CC M M M M reg, CC 0 I1 H I0 N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src I1 H I0 N Z C 109/151 1 ST72F324L, ST72324BL 12 ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. By default, MCU characteristics are specified for 2.85 to 3.6V VDD. 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 12.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD=3V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 12.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 54. Figure 54. Pin loading conditions ST7 PIN CL 12.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 55. Figure 55. Pin input voltage ST7 PIN VIN 110/151 1 ST72F324L, ST72324BL 12.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi12.2.1 Voltage Characteristics Symbol VDD - VSS VPP - VSS VIN 1) & 2) |VDDx| and |VSSx| |VSSA - VSSx| VESD(HBM) VESD(MM) Supply voltage Programming Voltage Input Voltage on true open drain pin Input voltage on any other pin Variations between different digital power pins Variations between digital and analog ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Ratings tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Maximum value 6.5 13 VSS-0.3 to 5.5 VSS-0.3 to VDD+0.3 50 50 Unit V mV see Section 12.7.3.1 on page 123 12.2.2 Current Characteristics Symbol IVDD IVSS Ratings Total current into VDD power lines (source) 3) Total current out of VSS ground lines (sink) for 3) 32-pin devices 44-pin devices 32-pin devices 44-pin devices Maximum value 75 150 75 150 25 50 - 25 5 2 +5 5 5 25 mA Unit mA mA Output current sunk by any standard I/O and control pin IIO Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on VPP pin Injected current on RESET pin when not driven low internally Injected current on flash device pin PB0 Injected current on OSC1 and OSC2 pins Injected current on any other pin IINJ(PIN) 2) 5) & 6) IINJ(PIN) 2) & 4) Total injected current (sum of all I/O and control pins) 5) Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN 1 ST72F324L, ST72324BL 12.2.3 Thermal Characteristics Symbol TSTG TJ Ratings Storage temperature range Value -65 to +150 Unit C Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS) 12.3 OPERATING CONDITIONS Symbol fCPU Parameter Internal clock frequency Operating Voltage (ROM versions) VDD Operating Voltage (Flash versions) VPP = 11.4 to 12.6V (for Write/ Erase operation) 1 Suffix Version TA Ambient temperature range 5 Suffix Version 6 Suffix Version Conditions ADC not used fADC max = 1 MHz. Min 0 0 2.85 2.85 0 -10 -40 Max 8 4 3.6 3.6 70 85 85 C Unit MHz V V Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device. Figure 56. fCPU Max Versus VDD fCPU [MHz] 8 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 6 ADC NOT OPERATIONAL IN THIS AREA 4 2 1 0 3.3 2.85 3.0 SUPPLY VOLTAGE [V] 3.6 FUNCTIONALITY GUARANTEED IN THESE AREAS 112/151 1 ST72F324L, ST72324BL 12.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped). 12.4.1 CURRENT CONSUMPTION Symbol Parameter Conditions Flash Devices Typ 0.9 1.4 2.5 4.7 350 400 500 700 0.7 1.0 1.8 3.2 330 370 440 570 <1 fOSC = 16 MHz 350 Max 1) ROM Devices Typ 0.23 0.45 0.88 1.8 15 40 80 170 0.12 0.22 0.42 0.83 10 20 50 100 <1 45 Max 1) 0.5 1.0 2.0 4.0 45 90 180 350 0.25 0.5 1 2 31 63 125 250 10 100 Unit fOSC=2MHz, fCPU=1MHz Supply current in RUN mode fOSC=4MHz, fCPU=2MHz 2) fOSC=8MHz, fCPU=4MHz fOSC=16MHz, fCPU=8MHz Supply current in SLOW mode 2) fOSC=2MHz, fCPU=62.5kHz fOSC=4MHz, fCPU=125kHz fOSC=8MHz, fCPU=250kHz fOSC=16MHz, fCPU=500kHz fOSC=2MHz, fCPU=1MHz fOSC=4MHz, fCPU=2MHz fOSC=8MHz, fCPU=4MHz fOSC=16MHz, fCPU=8MHz fOSC=2MHz, fCPU=62.5kHz fOSC=4MHz, fCPU=125kHz fOSC=8MHz, fCPU=250kHz fOSC=16MHz, fCPU=500kHz 1.35 2.1 3.8 7.0 500 600 750 1000 1.0 1.5 2.7 4.8 500 550 650 900 10 Not guaranteed mA A IDD Supply current in WAIT mode 2) mA Supply current in SLOW WAIT mode 2) Supply current in HALT mode 3) Supply current in ACTIVEHALT mode 4) A A A Notes: 1. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Measurements are done in the following conditions: - Progam executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is 50%. - All I/O pins in input mode with a static value at VDD or VSS (no load) - All peripherals in reset state. - Clock input (OSC1) driven by external square wave. - In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32. To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the peripheral power consumption (Section 12.4.3). 3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load). Data based on characterization results, tested in production at VDD max. and fCPU max. 4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave. To obtain the total current consumption of the device, add the clock source consumption (Section 12.5.3). 113/151 1 ST72F324L, ST72324BL SUPPLY CURRENT CHARACTERISTICS (Cont'd) 12.4.1.1 Power Consumption vs fCPU: ROM Devices Figure 57. Typical IDD in RUN mode 3000 2500 2000 Figure 59. Typical IDD WAIT mode 8MHz 4MHz 2MHz 1MHz 8MHz 4MHz 2MHz 1MHz Idd (A) 1400 1200 1000 800 600 400 Idd (A) 1500 1000 500 0 2.6 2.8 3 3.2 3.4 3.6 200 0 2.6 2.8 3 3.2 3.4 3.6 Vdd (V) Vdd (V) Figure 58. Typical IDD SLOW mode 250 200 Figure 60. Typical IDD SLOW-WAITmode 140 500kHz 250kHz 125kHz 62.5kHz 120 100 500kHz 250kHz 125kHz 62.5kHz Idd (A) 2.6 2.8 3 3.2 3.4 3.6 Idd (A) 150 100 50 80 60 40 20 0 0 2.6 2.8 3 3.2 3.4 3.6 Vdd (V) Vdd (V) 114/151 1 ST72F324L, ST72324BL SUPPLY CURRENT CHARACTERISTICS (Cont'd) 12.4.2 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode). Symbol Parameter Conditions Typ 625 see Section 12.5.3 on page 117 180 A A Max 1) Unit IDD(RCINT) Supply current of internal RC oscillator IDD(RES) IDD(PLL) Supply current of resonator oscillator 2) & 3) PLL supply current Notes: 1. Data based on characterization results, not tested in production. 2. Data based on characterization results done with the external components specified in Section 12.5.3 , not tested in production. 3. As the oscillator is based on a current source, the consumption does not depend on the voltage. 12.4.3 On-Chip Peripherals TA = 25C fCPU=4MHz. Symbol IDD(TIM) IDD(SPI) IDD(ADC) SPI supply current 2) ADC supply current when converting 3) Parameter 16-bit Timer supply current 1) Conditions VDD=3.3V Typ 20 250 300 Unit A Notes: 1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer. 2. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption. 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. 115/151 1 ST72F324L, ST72324BL 12.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA. 12.5.1 General Timings Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10 2) Conditions fCPU=8MHz fCPU=8MHz Min 2 250 10 1.25 Typ 1) 3 375 Max 12 1500 22 2.75 Unit tCPU ns tCPU s 12.5.2 External Clock Source Symbol VOSC1H VOSC1L tw(OSC1H) tw(OSC1L) tr(OSC1) tf(OSC1) IL Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 3) OSC1 rise or fall time 3) OSC1 Input leakage current VSSVINVDD see Figure 61 Conditions Min 0.9xVDD VSS 5 ns 15 1 A Typ Max VDD 0.1xVDD Unit V Figure 61. Typical Application with an External Clock Source 90% VOSC1H 10% VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L) OSC2 Not connected internally fOSC EXTERNAL CLOCK SOURCE OSC1 IL ST72XXX Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production. 116/151 1 ST72F324L, ST72324BL CLOCK AND TIMING CHARACTERISTICS (Cont'd) 12.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as Symbol fOSC RF CL1 CL2 Parameter Oscillator Frequency 1) Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS) Parameter close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). Conditions Min 1 >2 >4 >8 20 22 22 18 15 Typ 80 160 310 610 Max 2 4 8 16 56 46 33 33 Max 150 250 460 910 Unit MHz k pF LP: Low power oscillator MP: Medium power oscillator MS: Medium speed oscillator HS: High speed oscillator RS=200 RS=200 RS=200 RS=100 LP osc. (1-2 MHz) MP osc. (2-4 MHz) MS osc. (4-8 MHz) HS osc. (8-16 MHz) Conditions VIN=VSS LP osc. (1-2 MHz) MP osc. (2-4 MHz) MS osc. (4-8 MHz) HS osc. (8-16 MHz) Symbol i2 Unit A OSC2 driving current Figure 62. Typical Application with a Crystal or Ceramic Resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS i2 fOSC OSC1 CL1 RESONATOR CL2 OSC2 RF ST72XXX Notes: 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details. 117/151 1 ST72F324L, ST72324BL CLOCK CHARACTERISTICS (Cont'd) 12.5.4 RC Oscillators Symbol fOSC (RCINT) Parameter Internal RC oscillator frequency Conditions TA=25C, VDD=3V Min 2 Typ 3.5 Max 5.6 Unit MHz Note 1: To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitors between VDD and VSS as shown in Figure 80 Note 2: fCPU = fOSC(RCINT)/2. The PLL must be disabled if the internal RC clock source is used. 118/151 1 ST72F324L, ST72324BL CLOCK CHARACTERISTICS (Cont'd) 12.5.5 PLL Characteristics Symbol VDD(PLL) fOSC fCPU/fCPU Parameter PLL Operating Range PLL input frequency range Instantaneous PLL jitter 1) fOSC = 4 MHz. (fCPU=8MHz.) Conditions Min 2.85 2 3.5 Typ Max 3.6 4 5.5 Unit V MHz % Note: 1. Instantaneous PLL jitter is the absolute maximum deviation on a single clock period. Data characterized, not tested in production. Figure 63. PLL Clock Jitter vs. Application Signal frequency1 0.8 0.7 0.6 +/-Jitter (%) 0.5 0.4 0.3 0.2 0.1 0 2000 1000 500 250 125 Application Signal Frequency (KHz) FLASH DEVICES ROM DEVICES PLL clock jitter may cause application errors if high frequency signals are input or output by the application (e.g. high speed serial I/O or sampling of high frequency signals). Using the PLL increases clock jitter, however this is a periodic effect which is absorbed over several CPU cycles. The lower the frequency of the application signal, the less the impact. Figure 63 shows the effect of jitter (with and without PLL) on application signals in the range 125kHz to 2MHz. At frequencies of less than 125kHz, the jitter is negligible. Note 1: Measurement conditions: fCPU = 4MHz, TA= 25C 119/151 1 ST72F324L, ST72324BL 12.6 MEMORY CHARACTERISTICS 12.6.1 RAM and Hardware Registers Symbol VRM Parameter Data retention mode 1) Conditions HALT mode (or RESET) Min 1.6 Typ Max Unit V 12.6.2 FLASH Memory DUAL VOLTAGE HDFLASH MEMORY Symbol Parameter fCPU VPP IDD IPP tVPP tRET NRW TPROG TERASE Operating frequency Programming voltage 3) Supply current4) VPP current4) Internal VPP stabilization time Data retention Write erase cycles Programming or erasing temperature range Conditions Read mode Write / Erase mode 2.85V VDD 3.6V Write / Erase Read (VPP=12V) Write / Erase TA=55C TA=25C Min 2) 0 1 11.4 Typ Max 2) 8 8 12.6 200 30 10 20 100 -40 25 85 Unit MHz V A A mA s years cycles C <10 Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Not tested in production. 2. Data based on characterization results, not tested in production. 3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons. 4. Data based on simulation results, not tested in production. 120/151 1 ST72F324L, ST72324BL 12.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 12.7.1.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical applicaSymbol VFESD VFFTB Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Conditions Level/Class Flash 3B 4A ROM 4B 4A VDD=3.3V, TA=+25C, fOSC=8MHz conforms to IEC 1000-4-2 Fast transient voltage burst limits to be VDD=3.3V, TA=+25C, fOSC=8MHz applied through 100pF on VDD and VDD conforms to IEC 1000-4-4 pins to induce a functional disturbance 121/151 1 ST72F324L, ST72324BL 12.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin. Symbol Parameter Conditions Monitored Frequency Band 0.1MHz to 30MHz Max vs. [fOSC/fCPU] 8/4MHz 14 18 16 3.0 8 16 8 2.5 16/8MHz 15 23 22 3.5 4 20 14 3.0 dBV dBV Unit SEMI Peak level Flash device: VDD=3.3V, 30MHz to 130MHz TA=+25C, TQFP44 package 130MHz to 1GHz conforming to SAE J 1752/3 SAE EMI Level ROM device: VDD=3.3V, 30MHz to 130MHz TA=+25C, TQFP44 package 130MHz to 1GHz conforming to SAE J 1752/3 SAE EMI Level 0.1MHz to 30MHz SEMI Peak level Notes: 1. Data based on characterization results, not tested in production. 122/151 1 ST72F324L, ST72324BL EMC CHARACTERISTICS (Cont'd) 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. 12.7.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. Absolute Maximum Ratings Symbol VESD(HBM) VESD(MM) Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) TA=+25C TA=+25C Conditions Maximum value 1) Unit 2000 V 200 Notes: 1. Data based on characterization results, not tested in production. 12.7.3.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Electrical Sensitivities Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Conditions TA=+25C TA=+85C VDD=5.5V, fOSC=4MHz, TA=+25C Class 1) A A A Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 123/151 1 ST72F324L, ST72324BL 12.8 I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol VIL VIH Vhys Parameter Input low level voltage 1) Conditions Min 0.7xVDD Typ Max 0.3xVDD Unit V V Input high level voltage 1) Schmitt trigger voltage hysteresis 2) 0.8 0 +4 4 25 1 4) Injected Current on flash device pin IINJ(PIN)3) PB0 Injected Current on other I/O pins Total injected current (sum of all I/O VDD=3V IINJ(PIN)3) and control pins) Ilkg IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Input leakage current Static current consumption Weak pull-up equivalent resistor 5) I/O pin capacitance Output high to low level fall time 1) External interrupt pulse time 6) CL=50pF Output low to high level rise time 1) Between 10% and 90% VSS VIN VDD Floating input mode VIN=VSS VDD=3V mA mA 200 110 180 5 25 25 1 250 A k pF ns tCPU Notes: 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN VDD 10k Figure 65. Typical IPU vs. VDD with VIN=VSS 90 80 70 Ta=1 40C Ta=9 5C Ta=2 5C Ta=-45 C ST72XXX UNUSED I/O PORT Ipu(uA ) 60 50 40 30 10k UNUSED I/O PORT 20 10 ST72XXX 0 2 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6 124/151 1 ST72F324L, ST72324BL I/O PORT PIN CHARACTERISTICS (Cont'd) 12.8.2 Output Driving Current Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 66 and Figure 69) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 67 and Figure 70) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 68 and Figure 71 ) VDD=3V Conditions IIO=+2mA Min Typ. 0.3 Max. 0.7 Unit VOL 1) IIO=+10mA 0.3 0.7 V VOH 2) IIO=-2mA VDD-0.9 2.6 Figure 66. Typical VOL at VDD=3V (std. ports) Figure 68. Typical VOH at VDD=3V 3.1 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 Ta=90C Ta=25C Ta=-45C VOH (V) 3.0 2.9 2.8 2.7 2.6 2.5 2.4 VOL (V) Ta=90C Ta=25C Ta=-45C 1 2 2.3 2.2 2 1 0 lIO (mA) lIO(mA) Figure 67. Typ. VOL at VDD=3V (high-sink ports) 0.50 0.40 Ta=90C Ta=25C Ta=-45C VOL (V) 0.30 0.20 0.10 0.00 0 1 2 3 4 5 6 7 8 lIO (mA) Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH. 125/151 1 ST72F324L, ST72324BL I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 69. Typical VOL vs. VDD (std. ports) 0.6 0.5 Figure 70. Typical VOL vs. VDD (high-sink ports) 0.6 0.5 Ta=125C Ta=25C Ta=125C Ta=25C Vol(V) at Iio=2mA Vol(V) at lio=8mA Ta=-45C 0.4 0.3 0.2 0.1 0.0 2.6 2.8 3 3.2 3.4 3.6 Ta=-45C 0.4 0.3 0.2 0.1 0.0 2.6 2.8 3 3.2 3.4 3.6 Vdd (V) Vdd (V) Figure 71. Typical VOH vs. VDD 3.5 Voh(V) at lio=-2mA) 3.0 2.5 Ta=125C 2.0 Ta=25C Ta=-45C 1.5 2.6 2.8 3 3.2 3.4 3.6 Vdd (V) 126/151 1 ST72F324L, ST72324BL 12.9 CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol VIL VIH Vhys VOL IIO RON th(RSTL)in tg(RSTL)in Parameter Input low level voltage 1) Input high level voltage 1) Schmitt trigger voltage hysteresis 2) Output low level voltage 1) Conditions Flash versions ROM versions Flash versions ROM versions IIO=+2mA Min Typ Max 0.16xVDD 0.3xVDD Unit 0.85xVDD 0.7xVDD 2.5 0.3 2 0.7 V V mA Output current on RESET pin when driven low internally Weak pull-up equivalent resistor External reset pulse hold time Filtered glitch duration 5) 4) VDD=3V Internal reset sources 50 13 2.5 82 30 200 150 721) k s s ns tw(RSTL)out Generated reset pulse duration Figure 72. Typical Application with RESET pin 6)7)8) Recommended VDD VDD VDD ST72XXX USER EXTERNAL RESET CIRCUIT 5) 0.01F 4.7k RON Filter INTERNAL RESET 0.01F PULSE GENERATOR WATCHDOG RESET Required Notes: 1. Data guaranteed by design, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below th(RSTL)in can be ignored. 5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments. 6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (watchdog). 7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 12.9.1 . Otherwise the reset will not be taken into account internally. 8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current source on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for IINJ(RESET) in Section 12.2.2 on page 111. 127/151 1 ST72F324L, ST72324BL CONTROL PIN CHARACTERISTICS (Cont'd) 12.9.2 ICCSEL/VPP Pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol VIL VIH IL Parameter Input low level voltage 1) Input high level voltage 1) Input leakage current Conditions FLASH versions ROM versions FLASH versions ROM versions VIN=VSS Min VSS VSS VDD-0.1 0.7xVDD Max 0.2 0.3xVDD 12.6 VDD 1 A V Unit Figure 73. Two typical Applications with ICCSEL/VPP Pin 2) ICCSEL/VPP PROGRAMMING TOOL 10k VPP ST72XXX ST72XXX Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. 2. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS. 128/151 1 ST72F324L, ST72324BL 12.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). 12.10.1 16-Bit Timer Symbol Parameter Conditions Min 1 2 fCPU=8MHz 250 0 0 fCPU/4 fCPU/4 16 Typ Max Unit tCPU tCPU ns MHz MHz bit tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fEXT fPWM Timer external clock frequency PWM repetition rate ResPWM PWM resolution 129/151 1 ST72F324L, ST72324BL 12.11 COMMUNICATION INTERFACE CHARACTERISTICS 12.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter Master SPI clock frequency fCPU=8MHz Slave fCPU=8MHz SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge) 0 0.25 0.25 tCPU Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Conditions Min fCPU/128 0.0625 0 Max fCPU/4 2 fCPU/2 4 Unit MHz see I/O port pin description 120 120 100 90 100 100 100 100 0 120 240 90 ns Figure 74. SPI Slave Timing Diagram with CPHA=0 3) SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) LSB OUT tc(SCK) th(SS) tdis(SO) see note 2 see note 2 MSB OUT BIT6 OUT tsu(SI) th(SI) MOSI INPUT MSB IN BIT1 IN LSB IN Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 130/151 1 ST72F324L, ST72324BL COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 75. SPI Slave Timing Diagram with CPHA=11) SS INPUT tsu(SS) SCK INPUT CPHA=1 CPOL=0 CPHA=1 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) LSB OUT tc(SCK) th(SS) tdis(SO) MISO OUTPUT see note 2 HZ MSB OUT BIT6 OUT see note 2 tsu(SI) th(SI) MOSI INPUT MSB IN BIT1 IN LSB IN Figure 76. SPI Master Timing Diagram 1) SS INPUT tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK) MSB IN BIT6 IN LSB IN th(MO) MOSI OUTPUT see note 2 MSB OUT BIT6 OUT LSB OUT see note 2 Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. 131/151 1 ST72F324L, ST72324BL 12.12 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol fADC VAREF VAIN Parameter ADC clock frequency Analog reference voltage 1) Conditions Min 0.4 VDD VSSA Typ Max 1 VDD VAREF 1 Unit MHz V A A k pF Hz pF s 1/fADC Conversion voltage range 2) Positive input leakage current for analog -40CTA85C range input ROM devices: negative input leakage current on analog pins 5) External input impedance External capacitor on analog input Variation freq. of analog input signal Internal sample and hold capacitor Conversion time (Sample+Hold) fCPU=4MHz, SPEED=0 fADC=1MHz - No of sample capacitor loading cycles - No. of Hold conversion cycles VIN 5 6 see Figure 77 and Figure 782)3)4) RAIN CAIN fAIN CADC tADC tADC 12 15 4 11 Figure 77. RAIN max. vs fADC with CAIN=0pF3) 45 40 Figure 78. Recommended CAIN & RAIN values.4) 1000 Cain 10 nF 100 Max. R AIN (Kohm) Max. R AIN (Kohm) 35 30 25 20 15 10 5 0 0 10 30 70 Cain 22 nF Cain 47 nF 1 MHz 10 1 0.1 0.01 0.1 1 10 CPARASITIC (pF) fAIN(KHz) Notes: 1. When VAREF and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS. 2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 3. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and decreased to allow the use of a larger serial resistor (RAIN). 5.The analog inputs of ROM devices are designed to be negative current tolerant. On Flash devices, injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 12.8 does not affect the ADC accuracy. 132/151 1 ST72F324L, ST72324BL ADC CHARACTERISTICS (Cont'd) Figure 79. Typical A/D Converter Application VDD VT 0.6V ST72XXX 2k(max) RAIN VAIN CAIN AINx 10-Bit A/D Conversion CADC 12pF VT 0.6V IL 1A 12.12.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate VAREF and VSSA analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion. In some packages, VAREF and VSSA pins are not available (refer to Section 2 on page 7). In this case the analog supply and reference pads are internally bonded to the VDD and VSS pins. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see Section 12.12.2 General PCB Design Guidelines). 12.12.2 General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. - Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. - Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1F and optionally, if needed 10pF capacitors as close as possible to the ST7 power supply pins and a 1 to 10F capacitor close to the power source (see Figure 80). - The analog and digital power supplies should be connected in a star nework. Do not use a resistor, as VAREF is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. - Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted. 133/151 1 ST72F324L, ST72324BL Figure 80. Power Supply Filtering ST72XXX 1 to 10F ST7 DIGITAL NOISE FILTERING 0.1F VSS VDD VDD POWER SUPPLY SOURCE EXTERNAL NOISE FILTERING 0.1F VAREF VSSA 134/151 1 ST72F324L, ST72324BL 10-BIT ADC CHARACTERISTICS (Cont'd) 12.12.3 ADC Accuracy Conditions: VDD=3V 1) Symbol |ET| |EO| |EG| |ED| |EL| Parameter Total unadjusted error 1) Offset error 1) Conditions Flash Devices Typ 4 3 0.5 Max2) 6 5 4.5 4.5 4.5 ROM Devices Typ 2.6 1.3 1 1.6 1.7 Max 4 2.6 2.8 Unit Gain Error 1) Differential linearity error 1) Integral linearity error 1) CPU in run mode @ fADC 1 MHz. CPU in run mode @ fADC 1 MHz. LSB 1.5 1.5 3.5 2.5 Notes: 1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion being performed on another analog input. The effect of negative injection current on robust pins is specified in Section 12.12. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 12.8 does not affect the ADC accuracy. 2. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40C to 85C ( 3 distribution limits). Figure 81. ADC Accuracy Characteristics Digital Result ADCDR 1023 1022 1021 1LSB IDEAL V -V AREF SSA = -------------------------------------------EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 1024 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Vin (LSBIDEAL) 5 6 7 1021 1022 1023 1024 VAREF 135/151 1 ST72F324L, ST72324BL 13 PACKAGE CHARACTERISTICS 13.1 PACKAGE MECHANICAL DATA Figure 82. 44-Pin Thin Quad Flat Package mm Min 0.05 1.35 0.30 0.09 12.00 10.00 12.00 10.00 0.80 0 0.45 3.5 0.60 1.00 44 7 0 1.40 0.37 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006 D D1 A1 b A A2 Dim. A A1 A2 b C D 1.45 0.053 0.055 0.057 0.45 0.012 0.015 0.018 0.20 0.004 0.000 0.008 0.472 0.394 0.472 0.394 0.031 3.5 0.039 7 0.75 0.018 0.024 0.030 E1 E e D1 E E1 e L L1 L1 L h c Number of Pins N Figure 83. 32-Pin Thin Quad Flat Package Dim. D D1 A A2 A1 mm Min 0.05 1.35 0.30 0.09 9.00 7.00 9.00 7.00 0.80 0 0.45 3.5 0.60 1.00 32 7 0 1.40 0.37 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006 A A1 A2 b C D D1 E E1 e L h 1.45 0.053 0.055 0.057 0.45 0.012 0.015 0.018 0.20 0.004 0.354 0.276 0.354 0.276 0.031 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008 e E1 E b L1 L c L1 N Number of Pins 136/151 1 ST72F324L, ST72324BL PACKAGE MECHANICAL DATA (Cont'd) Figure 84. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width mm Min 3.56 0.51 3.05 0.36 0.76 0.20 27.43 7.62 8.89 1.78 10.16 12.70 1.40 2.54 3.05 Number of Pins N 32 3.56 0.46 1.02 0.25 Typ 3.76 Max Min 0.020 4.57 0.120 0.140 0.180 0.58 0.014 0.018 0.023 1.40 0.030 0.040 0.055 0.36 0.008 0.010 0.014 28.45 1.080 1.100 1.120 9.40 0.300 0.350 0.370 0.070 0.400 0.500 0.055 inches Typ Max 5.08 0.140 0.148 0.200 Dim. E eC A A2 A A1 A2 b E1 eA eB A1 L C b1 C D E E1 e eA eB eC L b2 D b e 9.91 10.41 11.05 0.390 0.410 0.435 3.81 0.100 0.120 0.150 13.2 THERMAL CHARACTERISTICS Symbol Ratings Package thermal resistance (junction to ambient) TQFP44 10x10 TQFP32 7x7 SDIP32 200mil Power dissipation 1) Maximum junction temperature 2) Value 52 70 50 500 150 Unit RthJA PD TJmax C/W mW C Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA. 137/151 1 ST72F324L, ST72324BL 13.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines. Figure 85. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 Temp. [C] 100 50 0 20 40 60 80 100 120 140 160 PREHEATING PHASE Time [sec] 80C 5 sec SOLDERING PHASE COOLING PHASE (ROOM TEMPERATURE) Figure 86. Recommended Reflow Soldering Oven Profile (MID JEDEC) 250 200 150 Temp. [C] 100 50 0 100 200 300 400 ramp up 2C/sec for 50sec ramp down natural 2C/sec max 90 sec at 125C 150 sec above 183C Tmax=235+/-5C for 25 sec Time [sec] Recommended glue for SMD plastic packages dedicated to molding compound with silicone: Heraeus: PD945, PD955 Loctite: 3615, 3298 138/151 1 ST72F324L, ST72324BL 14 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (ROM). ST72324BL devices are ROM versions. ST72P324L devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory-programmed HDFlash 14.1 FLASH OPTION BYTES STATIC OPTION BYTE 0 7 Reserved WDG HALT SW CSS 1 1 VD 0 1 Reserved 0 FMP_R 7 RSTC PKG1 OSCTYPE 1 1 0 0 2 1 OSCRANGE 1 1 0 1 STATIC OPTION BYTE 1 0 PLLOFF 1 139/151 devices. FLASH devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. Default 1 1 1 1 1 1 1 1 The option bytes allows the hardware configuration of the microcontroller to be selected. They have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. To program directly the FLASH devices using ICP, FLASH devices are shipped to customers with the internal RC clock source. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). OPTION BYTE 0 OPT7= WDG HALT Watchdog reset on HALT This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode OPT6= WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) OPT5 = CSS Clock security system on/off Reserved in current silicon revision, must be kept at default value. OPT4:3= VD[1:0] Voltage detection Reserved, must be kept at default value. OPT2:1 = Reserved, must be kept at default value. OPT0= FMP_R Flash memory read-out protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected causes the whole user memory to be erased first, and the device can be reprogrammed. Refer to Section 7.3.1 on page 37 and the ST7 Flash Programming Reference Manual for more details. 0: Read-out protection enabled 1: Read-out protection disabled 1 ST72F324L, ST72324BL DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) OPTION BYTE 1 OPT7= PKG1 Pin package selection bit This option bit selects the package. Version J K Selected Package TQFP44 TQFP32 / SDIP32 PKG1 1 0 LP MP MS HS Typ. Freq. Range 2 1~2MHz 2~4MHz 4~8MHz 8~16MHz 0 0 0 0 1 0 0 1 1 0 0 1 0 1 these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. Otherwise, these bits are used to select the normal operating frequency range. OSCRANGE Note: On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. OPT6 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles applied during the RESET phase and when exiting HALT mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: Reset phase with 4096 CPU cycles 1: Reset phase with 256 CPU cycles OPT5:4 = OSCTYPE[1:0] Oscillator Type These option bits select the ST7 main clock source type. OSCTYPE Clock Source 1 Resonator Oscillator Reserved Internal RC Oscillator External Source 0 0 1 1 0 0 1 0 1 OPT0 = PLL OFF PLL activation This option bit activates the PLL which allows multiplication by two of the main input clock frequency. The PLL is guaranteed only with an input frequency between 2 and 4MHz. 0: PLL x2 enabled 1: PLL x2 disabled Caution: the PLL can be enabled only if the "OSC RANGE" (OPT3:1) bits are configured to "MP 2~4MHz". Otherwise, the device functionality is not guaranteed. Caution: The PLL must not be used with the internal RC oscillator. CAUTION: In Flash devices, External Clock Source is not supported if the PLL is enabled. OPT3:1 = OSCRANGE[2:0] Oscillator range When the resonator oscillator type is selected, 140/151 1 ST72F324L, ST72324BL DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE ROM devices can be ordered in any combination of memory size and temperature range with the types given in Figure 87 and by completing the option list on the next page. Flash devices are available only in the types listed in Table 26. ROM customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. Figure 87. ROM Factory Coded Device Types DEVICE PACKAGE VERSION / XXX Code name (defined by STMicroelectronics) 1= Standard 0 to +70 C 5= Standard -10 to +85 C 6= Standard -40 to +85 C A= Automotive -40 to +85 C T= Plastic Thin Quad Flat Pack B= Plastic Dual in Line ST72324BLJ4, ST72324BLJ2 ST72324BLK4, ST72324BLK2 Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Caution: The Readout Protection binary value is inverted between ROM and FLASH products. The option byte checksum will differ between ROM and FLASH. 141/151 1 ST72F324L, ST72324BL DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) Table 26. Orderable Flash Device Types Part Number ST72F324LK6TA ST72F324LJ6TA ST72F324LK2T6 ST72F324LK4T6 ST72F324LK6T6 ST72F324LK2T5 ST72F324LK4T5 ST72F324LK6T5 ST72F324LK6B5 ST72F324LJ2T6 ST72F324LJ4T6 ST72F324LJ6T6 ST72F324LJ2T5 ST72F324LJ4T5 ST72F324LJ6T5 TQFP44 Standard SDIP32 TQFP32 Version Package TQFP32 TQFP44 Flash Memory (KBytes) 32 32 8 16 32 8 16 32 32 8 16 32 8 16 32 -10C +85C -40C +85C -10C +85C -40C +85C Temp. Range Automotive -40C +85C 142/151 1 ST72F324L, ST72324BL DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) ST72324BL MICROCONTROLLER OPTION LIST (Last update: January 2005) ................................... ................................... ................................... Contact: ................................... Phone No: ................................... Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . . . . . . *The ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): --------------------------------------------------------------------|| || ROM DEVICE: 16K --------------------------------------------------------------------TQFP32: TQFP44 : --------------------------------DIE FORM: --------------------------------32-pin: 44-pin: [ ] ST72324BLK4T [ ] ST72324BLJ4T --------------------------------------|| 16K --------------------------------------| [] | [] | | | | ------------------------------------8K ------------------------------------Customer: Address: [ ] ST72324BLK2T [ ] ST72324BLJ2T -------------------------------------|| 8K --------------------------------------| [] | [] Conditioning (check only one option) -------------------------------------------------------------------|| Packaged Product -------------------------------------------------------------------[ ] Tape & Reel [ ] Tray | | | | ----------------------------------------------------Die Product (dice tested at 25C only) ----------------------------------------------------[ ] Tape & Reel [ ] Inked wafer [ ] Sawn wafer on sticky foil [ ] Waffle pack Power Supply Range: [ ] 2.85 to 3.6V Version/Temp. Range (do not check for die product). Please refer to datasheet for specific sales conditions: -----------------------------------------------------------------------|| Automotive || Standard Temp. Range -----------------------------------------------------------------------[] | | 0C to +70C [] | | -10C to +85C [] | [] | -40C to +85C Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (TQFP32 7 char., other pkg. 10 char. max) Authorized characters are letters, digits, '.', '-', '/' and spaces only. Clock Source Selection: [ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] Internal RC: [ ] External Clock PLL Reset Delay Watchdog Selection: Watchdog Reset on Halt: Readout Protection (Note 1): Date Signature [ ] Disabled [ ] Enabled [ ] 256 Cycles [ ] 4096 Cycles [ ] Software Activation [ ] Hardware Activation [ ] Reset [ ] No Reset [ ] Disabled [ ] Enabled ................................... ................................... Note1: The Readout Protection binary value is inverted between ROM and FLASH products. The option byte checksum will differ between ROM and FLASH. Note 2: LVD is not available and this option is disabled by ST at ROM code entry. Please download the latest version of this option list from: http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list 143/151 1 ST72F324L, ST72324BL DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) 14.2.1 Version-Specific Sales Conditions To satisfy the different customer requirements and to ensure that ST Standard Microcontrollers will consistently meet or exceed the expectations of each Market Segment, the Codification System for Standard Microcontrollers clearly distinguishes products intended for use in automotive environments, from products intended for use in non-automotive environments. It is the responsibility of the Customer to select the appropriate product for his application. 14.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: http//:mcu.st.com. Tools from these manufacturers include C compliers, emulators and gang programmers. Emulators Two types of emulators are available from ST for the ST72 family: ST7 DVP3 entry-level emulator offers a flexible and modular debugging and programming solution. SDIP42 & SDIP32 probes/adapters are included, other packages need a specific connection kit (refer to Table 27) ST7 EMU3 high-end emulator is delivered with everything (probes, TEB, adapters etc.) needed to start emulating the ST72. To configure it to Table 27. STMicroelectronics Development Tools Emulation Supported Products ST72F324LK, ST72324BLK, ST72F324LJ, ST72324BLJ, ST7 DVP3 Series Emulator Connection kit ST7MDT20-T32/ DVP ST7MDT20-T44/ DVP ST7 EMU3 series Emulator Active Probe & T.E.B. ICC Socket Board Programming emulate other ST7 subfamily devices, the active probe for the ST7EMU3 can be changed and the ST7EMU3 probe is designed for easy interchange of TEBs (Target Emulation Board). See Table 27. In-circuit Debugging Kit Two configurations are available from ST: STXF521-IND/USB: Low-cost In-Circuit Debugging kit from Softec Microsystems. Includes STX-InDART/USB board (USB port) and a specific demo board for ST72521 (TQFP64) STxF-INDART Flash Programming tools ST7-STICK ST7 In-circuit Communication Kit, a complete software/hardware package for programming ST7 Flash devices. It connects to a host PC parallel port and to the target board or socket board via ST7 ICC connector. ICC Socket Boards provide an easy to use and flexible means of programming ST7 Flash devices. They can be connected to any tool that supports the ST7 ICC interface, such as ST7 EMU3, ST7-DVP3, inDART, ST7-STICK, or many third-party development tools. Evaluation board ST7232x-EVAL evaluation board, with ICC connector for programming capability. Provides direct connection to ST7-DVP3 emulator. Supplied with daughter boards (core module) for ST72F321, ST72F324 & ST72F521 (the ST72F321 & ST72F324 chips are not included) ST7MDT20-DVP3 ST7MDT20JEMU3 ST7MDT20J-TEB ST7SB20J/xx1 Note 1: Add suffix /EU, /UK, /US for the power supply of your region. 144/151 1 ST72F324L, ST72324BL 14.3.1 Socket and Emulator Adapter Information For information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in Table 28. Note: Before designing the board layout, it is recommended to check the overall dimensions of the Note: 1. Flash Programming interface for FLASH devices. Table 28. Suggested List of Socket Types Device TQFP32 7 X 7 TQFP44 10 X10 socket as they may be greater than the dimensions of the device. For footprint and other mechanical information about these sockets and adapters, refer to the manufacturer's datasheet (www.yamaichi.de for TQFP44 10 x 10 and www.ironwoodelectronics.com for TQFP32 7 x 7). Socket (supplied with ST7MDT20J-EMU3) IRONWOOD SF-QFE32SA-L-01 YAMAICHI IC149-044-*52-*5 Emulator Adapter (supplied with ST7MDT20J-EMU3) IRONWOOD SK-UGA06/32A-01 YAMAICHI ICP-044-5 145/151 1 ST72F324L, ST72324BL 14.4 ST7 APPLICATION NOTES Table 29. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 IC COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF IC BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1445 EMULATED 16 BIT SLAVE SPI AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK REFERENCE NOTE PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1150 BENCHMARK ST72 VS PC16 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 PRODUCT OPTIMIZATION AN 982 USING ST7 WITH CERAMIC RESONATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLAAN1530 TOR AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS PROGRAMMING AND TOOLS 146/151 1 ST72F324L, ST72324BL Table 29. ST7 Application Notes IDENTIFICATION DESCRIPTION AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT SYSTEM OPTIMIZATION AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS 147/151 1 ST72F324L, ST72324BL 15 KNOWN LIMITATIONS 15.1 ALL FLASH AND ROM DEVICES 15.1.1 Safe Connection of OSC1/OSC2 Pins The OSC1 and/or OSC2 pins must not be left unconnected otherwise the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. Refer to Section 6.2 on page 23. 15.1.2 Unexpected Reset Fetch If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the RESET vector address to the CPU. Workaround To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction. 15.1.3 Clearing active interrupts outside interrupt routine When an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. Note: clearing the related interrupt mask will not generate an unwanted reset Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: - The interrupt flag is cleared within its own interrupt routine - The interrupt flag is cleared within any interrupt routine - The interrupt flag is cleared in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following sequence: Perform SIM and RIM operation before and after resetting an active interrupt request. Example: SIM reset interrupt flag RIM Nested interrupt context: The symptom does not occur when the interrupts are handled normally, i.e. when: - The interrupt flag is cleared within its own interrupt routine - The interrupt flag is cleared within any interrupt routine with higher or identical priority level - The interrupt flag is cleared in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following sequence: PUSH CC SIM reset interrupt flag POP CC 15.1.4 16-bit Timer PWM Mode In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on the OLVL1 and OLVL2 settings. 15.1.5 ADC Conversion Spurious Results Spurious conversions occur with a rate lower than 50 per million. Such conversions happen when the measured voltage is just between 2 consecutive digital values. Workaround A software filter should be implemented to remove erratic conversion results whenever they may cause unwanted consequences. In order to have the accuracy specified in the datasheet, the first conversion after a ADC switch-on has to be ignored. 148/151 1 ST72F324L, ST72324BL 15.1.6 SCI Wrong Break duration Description A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: - 20 bits instead of 10 bits if M=0 - 22 bits instead of 11 bits if M=1. In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than expected. Occurrence The occurrence of the problem is random and proportional to the baudrate. With a transmit frequency of 19200 baud (fCPU=8MHz and SCIBRR=0xC9), the wrong break duration occurrence is around 1%. Workaround If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. This can be ensured by temporarily disabling interrupts. The exact sequence is: - Disable interrupts - Reset and Set TE (IDLE request) - Set and Reset SBK (Break Request) - Re-enable interrupts 15.2 ROM DEVICES ONLY 15.2.1 I/O Port A and F Configuration When using an external quartz crystal or ceramic resonator, the fOSC2 clock may be disturbed because the device goes into reserved mode controlled by Port A and F. This happens with either one of the following configurations: PA3=0, PF4=1, PF1=0 when the PLL option is disabled and PF0 is toggling PA3=0, PF4=1, PF1=0, PF0=1 when the PLL option is enabled This is detailed in the following table: PLL PA3 PF4 PF1 PF0 Clock Disturbance Max. 2 clock cycles TogOFF 0 1 0 lost at each rising or gling falling edge of PF0 Max. 1 clock cycle ON 0 1 0 1 lost out of every 16 As a consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. Workaround: To avoid this occurring, it is recommended to connect one of these pins to GND (PF4 or PF0) or VDD (PA3 or PF1). 15.3 FLASH DEVICES ONLY 15.3.1 Timer A Restrictions in Flash Devices In Flash devices, Timer A functionality has the following restrictions: - TAOC2HR and TAOC2LR registers are write only - Input Capture 2 is not implemented - The corresponding interrupts cannot be used (ICF2, OCF2 forced by hardware to zero) 15.3.2 External clock source with PLL External clock source is not supported with the PLL enabled. 15.3.3 39-Pulse ICC Entry Mode ICC mode entry using ST7 application clock (39 pulses) is not supported. External clock mode must be used (36 pulses). Refer to the ST7 Flash Programming Reference Manual. 149/151 1 ST72F324L, ST72324BL 16 REVISION HISTORY Table 30. Revision History Date 01-Oct-2003 Revision 1.0 Description of Changes First release. Changed Flash & ROM voltage range 2.85 to 3.6V in Section 12.3 on page 112 Changed OSC1 high & low level in Section 12.5.1 on page 116 Updated "EMC CHARACTERISTICS" on page 121 01-Jan-2004 1.1 Changed I/O Port: VOL/VOH values in Section 12.8.2 on page 125. Changed Reset pin: tw(RSTL)out & VOL in Section 12.9.1 on page 127. Changed ADC Varef & Ilkg in Section 12.12 on page 132 and ADC accuracy Section 12.12.3 on page 135. Removed SDIP42 package Max. values TBD in Section 12.12.3 on page 135 01-Feb-2004 1.2 Removed 10pf cap. in Figure 80 on page 134 Added Section 15.1.5 on page 148 Revision number incremented from 1.2 to 3 due to Internal Document Management System change Modified I/O VIL in Section 12.8 on page 124 14-Jan-2004 3 Modified RON in Section 12.9.1 on page 127 Added Clearing active interrupts in Section 15.1.3 on page 148 Modified Figure 7 and note 4 in "FLASH PROGRAM MEMORY" on page 16 Added limitation on ICC entry mode with 39 pulses to "KNOWN LIMITATIONS" on page 148 150/151 1 ST72F324L, ST72324BL Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 151/151 1 |
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